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STAP16DPS05
Low voltage 16-bit constant current LED sink driver with output error
detection and auto power-saving for automotive applications
Datasheet - production data
Description
+76623
H[SRVHGSDG
The STAP16DPS05 is a monolithic, low voltage,
low current power 16-bit shift register designed for
LED panel displays. The device contains a 16-bit
serial-in, parallel-out shift register that feeds a 16bit D-type storage register. In the output stage,
sixteen regulated current sources are designed to
provide 5-100 mA constant current to drive the
LEDs.
The STAP16DPS05 features the open and short
LED detections on the outputs.The
Features
STAP16DPS05 ensures the backward
compatibility with the STP16C/L596. The
• AECQ100 qualification
detection circuit checks 3 different conditions,
• Low voltage power supply down to 3 V
which can occur on the output line: short to GND,
• 16 constant current output channels
short to VO or open line. The data detection
results
are loaded in the shift register and shifted
• Adjustable output current through external
out
via
the serial line output. The detection
resistor
functionality is implemented without increasing
• Short and open output error detection
the pin number. Through a secondary function of
• Serial data IN/parallel data OUT
the output enable and latch pin (DM1 and DM2
respectively), a dedicated logic sequence allows
• 3.3 V micro driver-able
the device to enter or leave detection mode.
• Output current: 5-100 mA
Through an external resistor, users can adjust the
• Auto power-saving
output current of the STAP16DPS05, thus
controlling the light intensity of the LEDs. In
• Max. clock frequency: 30 MHz
addition, the user can adjust the intensity of the
• 20 V current generator rated voltage
brightness of the LEDs from 0% to 100% through
• Power supply voltage: from 3 V to 5.5 V
the OE/DM2 pin. The STAP16DPS05 guarantees
a 20 V output driving capability, allowing users to
• Thermal shutdown for overtemperature
connect more LEDs in series. The high clock
protection
frequency, 30 MHz, also satisfies the system
• ESD protection 2.0 kV HBM
requirement of high volume data transmission.
The 3.3 V of voltage supply is very useful for
Applications
applications that interface any microcontroller
from 3.3 V micro. Compared with a standard
• Dashboard and infotainment backlighting
TSSOP package, the TSSOP exposed pad
• Exterior/interior lighting
increases the capability of heat dissipation by a
factor of 2.5.
• DTRLs
Table 1. Device summary
Order code
Package
Packing
STAP16DPS05XTTR
HTSSOP24 (exposed pad)
2500 parts per reel
November 2015
This is information on a product in full production.
DocID024315 Rev 6
1/34
www.st.com
Contents
STAP16DPS05
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
2
3
Pin connections and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7
Detection mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8
9
2/34
7.1
Phase one: “entering in detection mode“ . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2
Phase two: “error detection” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3
Phase three: “resuming to normal mode” . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.4
Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.5
Auto power-saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.1
TSSOP24 exposed pad package information . . . . . . . . . . . . . . . . . . . . . 29
8.2
TSSOP24 exposed pad packing information . . . . . . . . . . . . . . . . . . . . . . 31
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DocID024315 Rev 6
STAP16DPS05
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical current accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output current-REXT resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ISET vs. dropout voltage (Vdrop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Entering in detection truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
IODEC average value at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
IODEC average value at 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TSSOP24 exposed pad mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
TSSOP24 exposed pad tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DocID024315 Rev 6
3/34
34
List of figures
STAP16DPS05
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
4/34
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OE/DM2 terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
LE/DM1 terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CLK, SDI terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SDO terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock, serial-in, serial-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock, serial-in, latch, enable, outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output current-REXT resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ISET vs. dropout voltage (Vdrop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
IDD ON/OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Entering in detection timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Detection diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Timing example for open and/or short detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Resuming to normal mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Detection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Error detection sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Error detection typical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Auto power-saving feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Delay LE-OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Auto power-saving behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
TSSOP24 exposed pad package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TSSOP24 exposed pad tape and reel outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DocID024315 Rev 6
STAP16DPS05
1
Summary description
Summary description
Table 2. Typical current accuracy
Current accuracy
Output voltage
≥ 1.3 V
1.1
Between bits
Between ICs
±1.5%
±5%
Output current
VDD
Temperature
20 to 100 mA
3.3 V to 5 V
25 °C
Pin connections and description
Figure 1. Pin connections
Note:
The exposed pad is electrically connected to a metal layer electrically isolated or connected
to ground.
Table 3. Pin description
Pin n°
Symbol
Name and function
1
GND
Ground terminal
2
SDI
Serial data input terminal
3
CLK
Clock input terminal
4
LE/DM1
Latch input terminal - detect mode 1 (see operation principle)
5-20
OUT-15
Output terminal
21
OE/DM2
Input terminal of output enable (active low) - detect mode 1 (see
operation principle)
22
SDO
23
R-EXT
24
VDD
Serial data out terminal
Input terminal of an external resistor for constant current programing
Supply voltage terminal
DocID024315 Rev 6
5/34
34
Electrical ratings
STAP16DPS05
2
Electrical ratings
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
.
Table 4. Absolute maximum ratings
Symbol
2.2
Parameter
Value
Unit
VDD
Supply voltage
0 to 7
V
VO
Output voltage
-0.5 to 20
V
IO
Output current
100
mA
VI
Input voltage
-0.4 to VDD
V
1600
mA
50
MHz
IGND
GND terminal current
fCLK
Clock frequency
TOPR
Operating temperature range
-40 to +150
°C
TSTG
Storage temperature range
-55 to +150
°C
Thermal data
Table 5. Thermal data
Symbol
Rth(JA)
Parameter
Thermal resistance junction-ambient (1)
TSSOP24 (2)
exposed pad
1. According to JEDEC standard 51-7B.
2. The exposed pad should be soldered to the PCB in order to derive the thermal benefits.
6/34
DocID024315 Rev 6
Value
Unit
37.5
°C/W
STAP16DPS05
2.3
Electrical ratings
Recommended operating conditions
Table 6. Recommended operating conditions
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
3.0
-
5.5
V
-
20
V
-
100
mA
VDD
Supply voltage
VO
Output voltage
IO
Output current
OUTn
IOH
Output current
Serial-OUT
-
+1
mA
IOL
Output current
Serial-OUT
-
-1
mA
VIH
Input voltage
0.7 VDD
-
VDD+0.3
V
VIL
Input voltage
-0.3
-
0.3 VDD
V
5
twLAT
LE/DM1 pulse width
6
-
ns
twCLK
CLK pulse width
8
-
ns
twEN
OE/DM2 pulse width
100
-
ns
10
-
ns
5
-
ns
10
-
ns
VDD = 3.0 V to 5.0 V
tSETUP(D) Setup time for DATA
tHOLD(D) Hold time for DATA
tSETUP(L) Setup time for LATCH
fCLK
Clock frequency
Cascade operation
(1)
-
30
MHz
1. If the device is connected in cascade, it may not be possible to achieve the maximum data transfer. Please
consider the timings carefully.
DocID024315 Rev 6
7/34
34
Electrical characteristics
3
STAP16DPS05
Electrical characteristics
VDD = 5V, Tj = -40 °C to 125 °C, unless otherwise specified.
Table 7. Electrical characteristics
Symbol
Parameter
VIH
Input voltage high level
0.7·VDD
VDD
VIL
Input voltage
low level
GND
0.3·VDD
VOL
VOH
IOH
∆IOL1
∆IOL2
∆IOL3
∆IOL4
Test conditions
Serial data output voltage
(SDO)
IOL = + 1 mA
Output leakage current
Current accuracy channelto-channel (1) (2)
Current accuracy device-todevice (1)
Min.
Typ.
Max.
0.03
0.4
Vo =19 V, Outn = OFF
0.5
2
VDD = 3.3 V, VO = 0.4 V,
Rext = 980 Ω
±1.5
±5
VDD = 3.3 V, VO = 1.3 V,
Rext = 200 Ω
±1.2
±4
IOH = - 1 mA
±6
VDD = 3.3 V, VO = 1.3 V,
Rext = 200 Ω
±6
150
300
600
RIN(down)
Pull-down resistor for LE pin
100
200
400
Rext = 980 Ω, OE = low,
OUT0 to OUT7 = OFF
200
300
Rext = 980 Ω, OE = high,
OUT0 to OUT7 = ON
5
8
IDD(OFF2)
Rext = 200 Ω, OE = high,
OUT0 to OUT15 = ON
13
20
IDD(ON1)
Rext = 980 Ω, OE = low,
OUT0 to OUT15 = ON
6
8
Rext = 200 Ω, OE = low,
OUT0 to OUT15 = ON
13
20
kΩ
IDD(AutoOff)
Supply current (OFF)
Supply current (ON)
IDD(ON2)
Thermal shutdown (3)
2. DIOL+ = ((IOLmax - IOLmean)/ IOLmean)*100, DIOL - = ((IOLmin - IOLmean)/ IOLmean)*100, where IOLmean =
(IOLout1+IOLout2+…+IOLout16) / 16.
3. Not tested, guaranteed by design.
DocID024315 Rev 6
µA
mA
170
1. Test performed with all outputs turned on, but only one output loaded at a time.
8/34
µA
%
VDD = 3.3 V, VO = 0.4 V,
Rext = 980 Ω
Pull-up resistor for OE pin
Tsd
V
VDD-0.4
RIN(up)
IDD(OFF1)
Unit
°C
STAP16DPS05
3.1
Electrical characteristics
Switching characteristics
VDD = 5 V, Tj = 25 °C, unless otherwise specified.
Table 8. Switching characteristics
Symbol
Parameter
Test conditions
fclk
Clock frequency
Cascade operation
tPLH1
tPLH2
tPLH3
tPLH
tPHL1
tPHL2
tPHL3
tPHL
CLK-OUTn
LE\DM1 = H
OE\DM2 = L
LE\DM1-OUTn
OE\DM2 = L
OE\DM2-OUTn
LE\DM1 = H
Propagation
delay time
(“L” to “H”)
CLK-OUTn
LE\DM1 = H
OE\DM2 = L
OE\DM2-OUTn
LE\DM1 = H
Min.
Typ.
Max.
Unit
30
MHz
VDD= 3.3 V
40
45
VDD = 5 V
20
45
VDD = 3.3 V
51
80
VDD = 5 V
32
50
VDD = 3.3 V
50
80
VDD = 5 V
30
50
VDD = 3.3 V
22
35
VDD = 5 V
15
25
VDD = 3.3 V
15
25
VDD = 5 V
12
20
VDD = 3.3 V
13
25
VDD = 5 V
10
15
VDD = 3.3 V
12
20
VDD = 5 V
10
15
VDD = 3.3 V
25
40
VDD = 5 V
18
25
ns
CLK - SDO
LE\DM1-OUTn
OE\DM2 = L
(1)(2)
Propagation
delay time
(“H” to “L”)
VIH = VDD
VIL = GND
CL = 10 pF
Io = 20 mA
VL = 3 V
Rext = 1 KΩ
RL = 60 Ω
CLK - SDO
ns
ns
ns
ns
ns
ns
ns
Output rise time
10~90 % of voltage
waveform
VDD = 3.3 V
35
55
tON
VDD = 5 V
10
20
Output fall time
90~10 % of voltage
waveform
VDD = 3.3 V
4
10
tOFF
VDD = 5 V
3
8
ns
ns
tr
CLK rise time(3)
5
tf
CLK fall time(3)
5
µs
1. All table limits are guaranteed by design.
2. Not tested in production.
3. If devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer
between two cascaded devices.
DocID024315 Rev 6
9/34
34
Equivalent circuit and outputs
4
STAP16DPS05
Equivalent circuit and outputs
Figure 2. OE/DM2 terminal
Figure 3. LE/DM1 terminal
Figure 4. CLK, SDI terminal
10/34
DocID024315 Rev 6
STAP16DPS05
Equivalent circuit and outputs
Figure 5. SDO terminal
Figure 6. Block diagram
-
DocID024315 Rev 6
11/34
34
Timing diagrams
5
STAP16DPS05
Timing diagrams
Table 9. Truth table
Clock
Note:
LE/DM1
OE/DM2
Serial-in
OUT0............. OUT7................ OUT15
SDO
H
L
Dn
Dn..... Dn - 7..... Dn -15
Dn - 15
L
L
Dn + 1
No change
Dn - 14
H
L
Dn + 2
Dn + 2..... Dn - 5..... Dn -13
Dn - 13
X
L
Dn + 3
Dn + 2..... Dn - 5..... Dn -13
Dn - 13
X
H
Dn + 3
OFF
Dn - 13
OUTn = ON when Dn = H OUTn = OFF when Dn = L.
Figure 7. Timing diagram
Note:
12/34
Latch and output enable are level-sensitive and they are not synchronized with rising or
falling edge of CLK signal. When LE/DM1 terminal is low level, the latch circuits hold the
previous set of data. When LE/DM1 terminal is high level, the latch circuits refresh new set
of data from SDI chain. When OE/DM2 terminal is at low level, the output terminals - Out0 to
Out15 respond to data in the latch circuits, either '1' ON or '0' OFF. When OE/DM2 terminal
is at high level, all output terminals are switched OFF.
DocID024315 Rev 6
STAP16DPS05
Timing diagrams
Figure 8. Clock, serial-in, serial-out
DocID024315 Rev 6
13/34
34
Timing diagrams
STAP16DPS05
Figure 9. Clock, serial-in, latch, enable, outputs
LE/DM1
OE/DM2
OUTn
Figure 10. Outputs
OUTn
14/34
DocID024315 Rev 6
STAP16DPS05
Typical characteristics
Figure 11. Output current-REXT resistor
4500
4000
3500
Rext (Ohm)
6
Typical characteristics
3000
2500
2000
1500
1000
500
0
0
10
20
30
40
50
60
70
80
Iset (mA)
AM13674V1
Table 10. Output current-REXT resistor
REXT(Ω)
Output current (mA)
976
20
780
25
652
30
560
35
488
40
433
45
389
50
354
55
325
60
300
65
278
70
259
75
241
80
229
85
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34
Typical characteristics
STAP16DPS05
Conditions:
–
Temperature = 25 °C, VDD = 3.3 V; 5.0 V, ISET = 3 mA; 5 mA; 10 mA; 20 mA; 50
mA; 80 mA.
Vdrop (mV)
Figure 12. ISET vs. dropout voltage (Vdrop)
800
700
600
500
400
300
200
100
0
Avg @ 3.0V
Avg @ 5.0V
0
20
40
60
80
Iset mA)
AM13675V1
Table 11. ISET vs. dropout voltage (Vdrop)
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Iout (mA)
Avg @ 3.0 V
Avg @ 5.0 V
3
19.33
22.66
5
36.67
40.33
10
77.33
80
20
158.67
157.33
50
406
406
80
692
668
DocID024315 Rev 6
STAP16DPS05
Typical characteristics
Figure 13. IDD ON/OFF
14
12
Idd (mA)
10
8
IddON Avg @ 5.5V
IddON Avg @ 3.6V
6
IddOFF Avg @ 5.5V
4
IddOFF Avg @ 3.6V
2
0
0
10
20
30
40 50
Iset (mA)
60
DocID024315 Rev 6
70
80
90
AM13676V1
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Detection mode functionality
STAP16DPS05
7
Detection mode functionality
7.1
Phase one: “entering in detection mode“
From the “normal mode” condition the device can switch to the “error mode” by a logic
sequence on the OE/DM2 and LE/DM1 pins as shown in the following table and diagram:
Table 12. Entering in detection truth table
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
H
L
Figure 14. Entering in detection timing diagram
AM13677V1
After these five CLK cycles the device goes into the “error detection mode” and at the 6th
rising edge of CLK the SDI data are ready for sampling.
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STAP16DPS05
7.2
Detection mode functionality
Phase two: “error detection”
The 16 data bits must be set to “1” in order to set ON all the outputs during the detection.
The data are latched by LE/DM1 and after that the outputs are ready for the detection
process. When the microcontroller switches the OE/DM2 to LOW, the device drives the
LEDs in order to analyze if an OPEN or SHORT condition has occurred.
Figure 15. Detection diagram
The LED status is detected at least in 1 microsecond (minimum) and after this time the
microcontroller sets OE/DM2 in high state and the output data detection result goes to the
microprocessor via SDO.
Detection mode and normal mode both use the same data format. As soon as all the
detection data bits are available on the serial line, the device may go back to normal mode
of operation. To re-detect the status, the device must go back in normal mode and re-enter
error detection mode.
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34
Detection mode functionality
STAP16DPS05
Figure 16. Timing example for open and/or short detection
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STAP16DPS05
7.3
Detection mode functionality
Phase three: “resuming to normal mode”
The sequence for re-entering in normal mode is shown in the following table and diagram:
Figure 17. Resuming to normal mode timing diagram
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
L
L
Note:
For proper device operation the “entering in detection” sequence must be followed by a
“resume mode” sequence, it is not possible to insert consecutive equal sequences.
7.4
Error detection conditions
VDD = 3.3 to 5 V temperature range -40 to 125 °C
Table 13. Detection conditions
Configuration
Note:
Detection mode
Detection results
SW-1 or SW-3b
Open line or output
No error
==> IODEC ≤ 0.5 x IO
==> IODEC ≥ 0.5 x IO
short to GND detected
detected
SW-2 or SW-3a
Short on LED or short
==> VO ≥ 2.4 V
to V-LED detected
No error
==> VO ≤ 2.2 V
detected
Where: IO = the output current programmed by the REXT, IODEC = the detected output
current in detection mode.
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34
Detection mode functionality
STAP16DPS05
Figure 18. Detection circuit
STAP16DPS05
16
AM13669v1
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STAP16DPS05
Detection mode functionality
Figure 19. Error detection sequence
During the error
detection are
necessary at least
2 CLK signal plus
oneat the end
16 CLK pulse are required to
load the data setting 1 into
shift register
LE/DM1 and OE/DM2
Key Sequence
necessary to Enter
in EDM
Every CLK pulse shows the results of
single Output results:Out15;14; 13 etc. etc
After OE/DM2 signal turn High the
SDO pin show the results of
Error Detection (Open or
Short in this case)
The LE/DM1 pulse
latch the data
loaded during the
previous state
The OE/DM2 Pulse put
the device from
EDM to Normal
Mode
Typical schematic used to perform the error detection:
Figure 20. Error detection typical schematic
Vled
Vdd
IDEC
Out
Iset
Rload
REXT
DUT
GND
AM13678v1
IODEC can be measured as follows:
IODEC = (Vled-Vload) / Rload
Table 14 and Table 15 show respectively the IODEC average value at 3.3 V and 5.0 V.
The IODEC is the current value recognized by the device output open error detection.
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34
Detection mode functionality
STAP16DPS05
Table 14. IODEC average value at 3.3 V
Vdd (V)
3.3
Iset (mA)
REXT (Ω)
Iout AVG (mA)
5
4270
2.097
10
2056
6.79
20
1006
10.46
50
382
26.92
80
251
35.03
Table 15. IODEC average value at 5 V
Vdd (V)
5
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Iset (mA)
REXT (Ω)
Iout AVG (mA)
5
4270
1.98
10
2056
6.09
20
1006
9.67
50
382
25.54
80
251
38.9
DocID024315 Rev 6
STAP16DPS05
7.5
Detection mode functionality
Auto power-saving
The auto power-saving feature minimizes the quiescent current if no active data is detected
on the latches and auto powers-up the device as the first active data is latched.
Figure 21. Auto power-saving feature
AM13679v1
Conditions:
–
Temp. = 25 °C, VDD = 3.3 V, Vin = VDD, VLed = 3.0 V, Iset = 20 mA
–
Ch1 (yellow) = IDD, Ch2 (blue) = SDI, Ch3 (purple) = LE/DM1, Ch4 (green) = CLK
Idd consumption:
–
Idd (normal operation) = 5.15 mA
–
Idd (shutdown condition) = 163 µA
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Detection mode functionality
STAP16DPS05
Figure 22. Delay LE-OUT
AM13680v1
After 16 clock cycles without data change, the auto power-saving mode starts as expected.
Delay TLE-OUT = 1.053 µs
Conditions:
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–
Temp. = 25 °C, VDD = 3.3 V, Vin = VDD, VLed = 3.0 V, Iset = 20 mA
–
Ch1 (yellow) = CLK, Ch2 (blue) = SDI, Ch3 (purple) = LE/DM1, Ch4 (green) =
IOUT
DocID024315 Rev 6
STAP16DPS05
Detection mode functionality
Figure 23. Auto power-saving behavior
AM13681v1
Note:
When the device goes from auto power-saving to normal operating condition, the first output
switching ON shows the TON condition as seen in the plot above.
Temp. = 25°C, VDD = 3.3 V, Vin = VDD, VLed = 3.0 V, Iset = 20 mA
Ch1 (yellow) = IDD, Ch2 (blue) = SDI, Ch3 (purple) = LE/DM1, Ch4 (green) = CLK.
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34
Package information
8
STAP16DPS05
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
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STAP16DPS05
8.1
Package information
TSSOP24 exposed pad package information
Figure 24. TSSOP24 exposed pad package outline
7100778_D
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Package information
STAP16DPS05
Table 16. TSSOP24 exposed pad mechanical data
mm
Symbol
Min.
Max.
A
1.20
A1
0.15
A2
0.80
b
0.19
0.30
c
0.09
0.20
D
7.70
7.80
7.90
D1
4.80
5.00
5.2
E
6.20
6.40
6.60
E1
4.30
4.40
4.50
E2
3.00
3.20
3.40
e
L
k
1.00
1.05
0.65
0.45
L1
0.60
0.75
1.00
0
aaa
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Typ.
8
0.10
DocID024315 Rev 6
STAP16DPS05
8.2
Package information
TSSOP24 exposed pad packing information
Figure 25. TSSOP24 exposed pad tape and reel outline
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34
Package information
STAP16DPS05
Table 17. TSSOP24 exposed pad tape and reel mechanical data
mm
Dim.
Min.
A
Max.
330
C
12.8
D
20.2
N
60
T
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Typ.
13.2
22.4
Ao
6.8
7
Bo
8.2
8.4
Ko
1.7
1.9
Po
3.9
4.1
P
11.9
12.1
DocID024315 Rev 6
STAP16DPS05
9
Revision history
Revision history
Table 18. Document revision history
Date
Revision
Changes
21-May-2013
1
Initial release.
01-Jul-2013
2
Added footnote in Table 8: Switching characteristics.
11-Oct-2013
3
Modified TOPR value in Table 4: Absolute maximum ratings.
10-Mar-2014
4
Modified footnote 1 in Table 8: Switching characteristics.
Added footnote 2 in Table 8: Switching characteristics.
Updated Table 3: Pin description.
05-Jun-2014
5
Updated Table 16: TSSOP24 exposed pad mechanical data.
Minor text changes.
10-Nov-2015
6
Updated features in cover page.
Minor text changes.
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STAP16DPS05
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