cd00222052

AN2870
Application note
L6585DE combo IC
Introduction
The modern requirements for fluorescent lamp electronics ballast concerns both efficiency
of the drivers and safety aspects.
The L6585DE offers the designer a high performance PFC stage, high capability half bridge
high voltage drivers, a fully programmable control and an enhanced set of protections.
Figure 1.
March 2009
Typical electronic ballast block diagram
Rev 1
1/41
www.st.com
Contents
AN2870
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
Typical configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2
Lamp requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
L6585DE combo IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Device blocks description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
Start-up and shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2
PFC section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3
4
5
2/41
3.2.1
Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.2
Multiplier block and THD optimizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.3
Current comparator and choke saturation detection . . . . . . . . . . . . . . . 11
3.2.4
Zero current detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.5
Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.6
PFC protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ballast controller section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.1
Oscillator and timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.2
Overcurrent control and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.3
End of life detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.4
Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Designing with L6585DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1
PFC stage design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2
Ballast stage design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3
PCB hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
AN2870
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 15.
Figure 16.
Figure 17.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Typical electronic ballast block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Start-up and shut-down waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PFC section block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PFCCS pin waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Protections block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Oscillator and starting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Current control sequence during ignition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
HBCS thresholds summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Window comparator for rectifying effect detection (Cblock to GND). . . . . . . . . . . . . . . . . . 17
Window comparator for rectifying effect detection (lamp to GND) . . . . . . . . . . . . . . . . . . . 19
Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PFC MOSFET losses (example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Multiplier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
(A) voltage frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
(B) current frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Oscillator characteristic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
(A) k parameter versus Cosc (pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
(B) e parameter versus Cosc (pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
EOL - Cblock to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
EOL - lamp to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Current consumption vs PFC frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3/41
Introduction
AN2870
1
Introduction
1.1
Typical configuration
Typical fluorescent lamp electronic ballasts are composed by (Figure 1):
1.2
●
An input PFC section, if input power is greater than 25 W, usually a TM PFC converter,
that generates a DC output voltage and absorbs power from mains with very high
Power Factor (typically 0.95 or grater) and very low THD (mandatory less than 10%).
●
A high frequency half bridge driver, fed by the PFC output, with internal or external
oscillator, a timer and various protections in order to drive correctly the lamp, to avoid to
deliver an excessive power to the lamp and to detect any malfunction of the lamp
(broken lamp, broken cathode or lamp absence)
●
An output resonant stage, realized by reactive components (capacitors and inductors),
that, together with the half bridge driver, optimizes the power delivered to the lamp (one
or more) during all working conditions (preheating, ignition and run mode).
Lamp requirements
Fluorescent lamp, during its normal operation, has to be supplied by means of alternative
and controlled current. In order to reduce the size of the ballast and increase the light
efficiency of the lamp a frequency greater than 20 kHz is typically used. A half bridge quasi
resonant inverter (series-parallel converter Figure 1) is used to obtain sinusoidal current into
the lamp and to reduce the power dissipation of the half bridge switches, in fact zero voltage
switching is achieved.
Lamp current and lamp voltage during normal operation are reported in lamp documentation
and are to be considered as design specification. Moreover, a well preheated lamp ignites at
a lower voltage; this implies a longer lamp life and a greater number of ignitions. The
efficiency of the preheating is mainly related with the total energy delivered to the cathode
(reported on lamp documentation), and then it depends on the time available for this
operation: keeping constant the preheating energy, longer is the preheating time, smaller is
the instantaneous power delivered to the cathode. During the preheating operation the
voltage across the lamp must be kept below a specified value in order to avoid unwanted
ignitions (when these happen, the lamp experiences multiple re-strike and dissipates large
amounts of power).
There are many ways to deliver power to the cathode, but the most used are two:
4/41
1.
Current controlled preheating: the cathodes are interposed between the choke and the
resonant capacitor so they experience the same current of the resonant LC circuitry. An
efficient preheating is obtained controlling this current and the time of preheating. The
advantages of this method are the cheapness and easiness of design; it has also some
disadvantages, namely the difficulty of keeping low the lamp voltage during preheating
and the fact that during steady state the cathode experiences the sum of the lamp
current and of the resonant capacitor current.
2.
Voltage controlled preheating: the current into the cathodes is generated by auxiliary
windings coupled with ballast choke or driven by an auxiliary oscillator. This implies
that, in any case, the design of the preheating circuitry is somewhat independent from
the design of the LC circuitry, even if it requires a lot of external components. This
method is then more efficient, but is cheaper and more difficult to design.
AN2870
Introduction
After a good preheating, the voltage across the lamp is suddenly increased in order to
generate a strike inside the tube and ignite the lamp. This phase should last between 10 ms
and 100 ms.
The strike voltage depends on various parameters, many of which cannot be exactly
evaluated: preheating energy, remaining lamp life, number and efficiency of the past
ignitions. An insufficient preheating causes greater ignition voltage and a subsequent stress
of the cathodes that lose small amounts of material that darken the region of the tube near
to the cathode itself (sputtering).
Lamp ageing is related with the symmetrical or, more often, asymmetrical increasing of the
cathodes resistance. A symmetrically aged lamp absorbs more power causing hard
switching and over-current. Asymmetrically aged lamps experience a current that is more
intense in one direction than in the other. This implies that the current flowing into the lamp
has positive or negative mean value (DC component). This effect can be detected
measuring the mean values of the lamp voltage that should be zero in normal lamps. The
worst case of rectifying effect causes the current flowing only in one direction: the voltage
across the resonant capacitor can reach very high values and heavy hard switching is
detected.
When symmetrical or asymmetrical ageing of the lamp reaches a value indicated in
international norms, the lamp reaches its end of life (EOL).
5/41
L6585DE combo IC
2
AN2870
L6585DE combo IC
The L6585DE embeds both a PFC converter and a ballast regulator in a single SO20
package. It is intended to design complete high power electronic ballasts with a single chip.
●
The most significant features of the L6585DE concern the following points:
●
Transition mode PFC converter with over voltage and over current protection.
●
Half-bridge controller with High voltage driver (600 Vdc) and integrated bootstrap
diode.
●
3% precise, fully programmable oscillator.
●
Flexibility in programming preheating time and ignition time.
●
Configurable EOL detection and over current protection.
●
Hard switching detection.
The PFC section achieves current mode control operating in Transition Mode. The multiplier,
together with the internal THD optimizer, reduces input current distortion, and allows
reaching very high performances also in wide-range-mains operation and large load range.
The PFC output voltage is controlled by means of a voltage-mode error amplifier and a
precise internal voltage reference.
A static and dynamic OVP protects the IC from excessive output voltage and an over current
protection turns off the PFC gate driver in case of PFC choke saturation.
The PFC driver is able to provide 300 mA (source) and 600 mA (sink).
The half bridge section is driven by a current controlled oscillator (CCO) and the internal
control logic.
The steady state frequency, the preheating frequency, the pre-heating time, the over-current
protection time and the ignition time are independently set by means of six external
components (resistors and capacitors).
An over-current protection limits the voltage across the HBCS pin acting directly on the CCO
realizing a precise closed loop control. This control lasts for a time set by the Tch pin and,
after that, if the fault condition is still present, the IC is stopped in low consumption mode.
The HBCS voltage amplitude depends on actual operating mode, then this protection can
detect either a broken lamp during ignition (in this case the current regulation implies the
lamp voltage regulation) or the symmetrical ageing of the lamp during run mode.
An internal window comparator can be simply configured setting the window amplitude or
the comparator reference in order to detect the EOL status. The programmability of
comparator reference makes the L6585DE compliant with either “lamp-to-ground” (fixed
reference) or “block capacitor-to ground” (tracking with CTR) configurations.
The drivers of the half-bridge provide 290 mA source and 480 mA sink.
6/41
AN2870
L6585DE combo IC
Figure 2.
Block diagram
7/41
Device blocks description
3
Device blocks description
3.1
Start-up and shut-down
AN2870
During start-up the chip is supplied through a resistive path from the rectified AC Mains
voltage whereas, during normal operation, a self-supply source is recommended: a charge
pump, an auxiliary winding coupled either with PFC choke or resonant choke, or an auxiliary
converter.
As the voltage at Vcc pin reaches the turn-on threshold (VccON, Figure 3-A), the chip is
enabled and (unless a lamp absence is detected) the Half-Bridge and the PFC sections
start at the same time (independently):
●
The PFC section, as the synchronization signal at pin ZCD is not yet generated by the
external ZCD circuit, is forced to switch by internal starter (fstarter = 6 kHz (typ)) for the
first few switching cycles, until the control loop operates correctly at a frequency higher
than fstarter.
●
The oscillator starts switching at a preheating frequency set by values of COSC, RRUN
and RPRE.
At shut-down (Figure 3-B), when the VCC decreases below the UVLO threshold (either in
case of mains removal or in case of fault):
8/41
●
All drivers are off;
●
EOI pin is discharged (the internal switch is on);
●
RF reference is disabled;
●
Tch is discharged.
AN2870
Device blocks description
Figure 3.
Start-up and shut-down waveforms
A) Start-up
B) Shut down
9/41
Device blocks description
3.2
PFC section
3.2.1
Error amplifier
AN2870
The error amplifier (E/A, Figure 4) is used to close the output voltage control loop. Its non
inverting input is connected to a precise voltage reference (2.52 V), the inverting input and
the output are externally available (pin 10 –INV; pin 9 – COMP).
The compensation network, placed between pins INV and COMP, is needed to reject the
mains ripple.
The E/A output dynamic is internally clamped: it can swing between 2.25 V and 4.2 V in
order to speed up the recovery after the E/A saturates low due to an over-voltage (static
OVP) or saturates high because of an over-current.
Figure 4.
3.2.2
PFC section block
Multiplier block and THD optimizer
The multiplier (Figure 4) gives the sinusoidal voltage reference to the current sense in order
to absorb from the mains a sinusoidal current. This current will be function of both input
voltage and load current then this block has two inputs: the first one (Pin MULT – 8) takes a
partition of the instantaneous rectified line voltage and the second one (Pin COMP – 9) is
the output of the E/A.
An internal voltage clamp (1 V) sets the maximum allowed voltage of the multiplier output,
then it act as PFC current limiter.
When the rectified input voltage reaches 0 V the boost inductor cannot store enough energy
to discharge the input capacitor: this event increases the THD. In order to avoid this
additional distortion, a THD optimizer block is placed between the output of the multiplier
and the current sense comparator.
The characteristic curves of the multiplier block are reported in Figure 14.
10/41
AN2870
3.2.3
Device blocks description
Current comparator and choke saturation detection
The current comparator senses the voltage across the current sense resistor (Rpfccs) and,
by comparing it with the programming signal delivered by the multiplier, determines the
exact time when the external MOSFET has to be switched off.
When PFC MOSFET is turned on, parasitic drain capacitances are discharged and an
intense current spike can be seen by PFCCS (Figure 5). In past solutions, an RC filter
between sense resistor and current sense input was commonly used to reject these spikes,
but it introduced a delay between the instant the current crosses the threshold and the
actual activation of internal comparator. This delay may cause the inductor saturation, then
an over dimensioned inductor had to be used. In L6585DE, an internal leading edge
blanking structure (LEB) masks the first 200 ns of the PFC gate at the time current spikes
occurs; the filter is no longer necessary and the inductor can be smaller and lighter. On the
other hand this LEB limits the maximum available “ON time”.
Moreover, the device is provided with a second comparator on the PFC current sense pin
that turns off immediately the PFC MOSFET if the voltage on the pin, normally limited within
1.0 V, exceeds 1.7 V. A current peak limiting control is therefore achieved avoiding MOSFET
overheating in case of boost inductor’s hard saturation. In this case the current up-slope
becomes so large (50-100 times steeper) that during the current sense propagation delay
the current may reach abnormally high values.
Figure 5.
PFCCS pin waveforms
11/41
Device blocks description
3.2.4
AN2870
Zero current detection
The zero current detection (ZCD) block switches on the external PFC MOSFET as the
current through the boost inductor has gone to zero. This feature allows TM operation.
When the circuit is running, the signal for ZCD is obtained with an auxiliary winding coupled
with the boost inductor. A Schmidt trigger prevents false activations and an internal clamp
limits the voltage across the pin during normal operation in 0 V-5 V range. As at start-up no
signal is coming from the ZCD, an internal starter is needed in order to turn on the external
MOSFET and to arm the ZCD trigger.
The repetition rate of the starter is ≅ 6 kHz and this maximum frequency must be taken into
account at design time.
3.2.5
Driver
A totem pole buffer, with 300 mA source and 600 mA sink capability, allows driving an
external MOSFET. A pull-down circuit holds the output low when the device is in UVLO
conditions, to ensure that the external MOSFET cannot be turned on accidentally.
3.2.6
PFC protections
The device is provided with a double over-voltage protection (OVP).
The first over voltage protection, also called dynamic OVP, is activated immediately when
CTR pin (pin 7) goes above 3.4 V. The maximum voltage allowed for the output voltage
(VOVP) is defined by a resistive divider connected between output voltage and CTR pin.
In case of over voltage, the output of the E/A will tend to saturate low with a long constant
time, because of the bandwidth of this stage (typ. 10 Hz).
If the over-voltage lasts so long that the output of E/A goes below 2.25 V, the PF gate driver
is stopped and Tch timer is started. If E/A output voltage doesn’t return above 2.25 V after
the timer finishes its count, the IC is stopped in latch condition. This protection prevents
damages due to the connection to an excessive input voltage.
An intense high voltage (e.g. a surge) may break the upper resistors (one or more than one)
of the voltage dividers connected to input voltage (MULT biasing) or to output voltage (INV
and CTR biasing). Losing of the bias on pin INV implies losing of the control of the loop: in
fact E/A output saturates high and causes an increased output voltage, eventually not seen
by OVP because of failure on CTR voltage divider. The feedback disconnection protection
prevents this failure stopping the PF gate if INV voltage falls below 1.2 V and CTR pin goes
above 3.4 V. CTR pin can be also used to disable the IC pulling its voltage below 0.8 V.
Figure 6.
12/41
Protections block diagram
AN2870
Device blocks description
3.3
Ballast controller section
3.3.1
Oscillator and timer
The half bridge driver oscillation is regulated by a current controlled oscillator (CCO): it
needs a capacitor connected to OSC pin (pin 1) and uses the current flowing outside RF pin
(pin 2) as reference.
The RF pin has a 2 V precise voltage reference that let the designer fix the run mode
frequency simply connecting a resistor between RF pin and GND (Rrun).
The EOI pin (pin 3) is driven by the internal logic in order to set the frequency during the
preheating and to control the lamp current during an over-current event in the half bridge.
Preheating frequency is set by the parallel of Rrun and a resistor (Rpre) placed between RF
and EOI: in fact during the preheating the EOI pin is pulled to GND.
TCH pin is connected to the parallel of a resistor (RD) and a capacitor (CD) and is used in
order to define the preheating time and the protection time; its cycle (Tch cycle) is
composed by the following steps:
1.
A 31 μA current generator charges the CD causing TCH voltage to rise linearly,
2.
When TCH voltage reaches 4.63 V, the TCH pin is left in high impedance status and CD
is discharged by RD,
3.
When TCH voltage reaches 1.5 V the cycle finishes and an internal resistor pulls down
the TCH pin to GND.
Figure 7.
Oscillator and starting sequence
13/41
Device blocks description
3.3.2
AN2870
Overcurrent control and protections
Limiting the current flowing into the half bridge:
●
The lamp voltage during the ignition phase is limited
●
The power of the lamp during run mode is limited
Ignition phase: (see Figure 8) if the VHBCS high threshold (HBCSH = 1.6 V) is crossed
(because the lamp doesn’t ignite), the following actions are taken by L6585DE:
1.
A current, whose amplitude is proportional to the time the VHBCS is above threshold, is
sunk from EOI and consequently from RF pin. This results in a frequency increase that
reduces the resonant network current and therefore the lamp voltage.
2.
A reduced time is calculated by Tch pin:
a)
The 31µA generator charges CD to 4.63 V
b)
Instead of leaving CD to be discharged by RD, a 26 µA current generator discharge
quickly CD to 1.5 V (S4 on)
c)
The pull down switch S3 completes the reduced cycle
The reduced Tch cycle depends only on CD value and is equal to:
Equation 1
⎛ 4.63
4.63 − 1.5 ⎞⎟
TTch,reduced = CD ⎜
≅ 269740 ⋅ CD
+
⎜I
ITch,snk ⎟⎠
⎝ Tch,source
At the end of the Tch cycle, during the first subsequent low side on time, the HBCS voltage
is checked: if VHBCS is higher than a threshold (HBCSH,test) the IC is stopped in latched
condition, otherwise EOI pin is released in high impedance status. When EOI voltage
reaches 1.9 V the IC enters the run mode.
The sense resistor value defines the maximum current that can flow during ignition and then
the maximum allowed lamp voltage.
The linear growth of the lamp voltage, thanks to the exponential decrease of the operating
frequency during ignition allows a better control of the voltage thanks to a lower dV/dFsw.
In case of choke saturation the intense current results in very high VHBCS. The 2.75
threshold triggers this event and stops immediately the IC.
Run mode: During this phase, current control similar to the one present during ignition is
available in case of an over-current due to symmetrical ageing of the lamp. It follows the
same rules, but the threshold is equal to 1.05 V instead of 1.6 V.
Also during run mode the saturation protection is active: in case of choke saturation due to
lamp breaking, lamp removal and capacitive mode where VHBCS experiences a spike whose
amplitude is higher than 1.6 V and whose duration is longer than 300 ns. This kind of event
causes the IC turn-off in latched condition.
The lamp ageing causes the shift of peak of the resonance curve towards the run frequency.
This results in hard switching behavior: the half bridge doesn’t work at ZVS and spikes
appears at HBCS pin. These spikes have very high amplitude (up to 8 V) and short duration
(30 ns-50 ns).
14/41
AN2870
Device blocks description
During hard switching the power dissipation of half bridge MOSFETs increases rapidly.
L6585DE detects these pulses and shuts down the half bridge after 350 (typ) subsequent
pulses.
The hard switching detection structure is masked during preheating and ignition: in fact
during this phase the frequency changes cause hard switching that is unavoidable but is not
dangerous.
In Figure 9 a summary of the protection thresholds is reported:
Figure 8.
Current control sequence during ignition
Figure 9.
HBCS thresholds summary
15/41
Device blocks description
3.3.3
AN2870
End of life detection
When the lamp becomes older and approaches its end of life, its equivalent resistance
increases symmetrically or asymmetrically.
In symmetrical ageing a modification of the frequency response of the resonance network
can be seen and, consequently, an increasing of lamp current and the appearance of hard
switching events: in fact the resonance frequency is now closer to operating frequency.
In asymmetrical ageing the current flowing in one direction is greater than the current
flowing in the other; this means that lamp voltage and current waveforms have no longer
zero mean value. A window comparator measures the variation of the DC component of the
lamp voltage that can be either positive or negative. The reference and the amplitude of this
comparator can be set choosing the value of a resistor connected between EOLP pin and
GND accordingly with the following table.
Table 1.
Comparator amplitude
EOLP resistor
Symbol
Reference
Half–window amplitude
REOLP > 620 kΩ
RFH
Fixed 2.5 V
± 720 mV
220 kΩ < REOLP < 270 kΩ
RTL
Tracking with CTR
- 240 mV / + 250 mV
75 kΩ < REOLP < 91 kΩ
RFL
Fixed 2.5 V
± 240 mV
22 kΩ < REOLP < 27 kΩ
RTL
Tracking with CTR
- 150 mV / + 160 mV
This comparator can be used in both the two most used ballast configurations: Blocking
capacitor to ground and lamp to ground.
Block capacitor to ground (Figure 10): During normal operation the DC mean value
across Cblock is equal to the half of the output voltage of the PFC. A resistive divider is
placed across the block capacitor to sense its DC voltage: the asymmetric effect appears as
a shifting of this DC value.
Any voltage ripple or disturbance across the output voltage is present also on Blocking
Capacitor and may alter the correct detection of a lamp at the end of its life.
In order to reject all this disturbances, the reference of the window comparator is connected
to CTR pin (Tracking reference configurations): in fact this pin is connected directly to the
output voltage and experiences the same ripple voltage. The rejection of the PFC output
voltage low frequency ripple allows using a smaller bulk capacitance.
16/41
AN2870
Device blocks description
Figure 10. Window comparator for rectifying effect detection (Cblock to GND)
17/41
Device blocks description
AN2870
Lamp to ground (Figure 11): the resistive divider senses the voltage across the lamp. As
the L6585DE doesn’t have a negative rail, it is necessary to shift the external signal; this can
be done (for example) using two Zener diodes connected back-to-back between the EOL
pin and the centre of the resistive divider.
The Zener voltages should differ by an amount as close as possible to the double of the
internal reference to have a symmetrical detection, in fact:
Let be VUP and VDOWN the maximum allowed values of the DC component of the Lamp
Voltage divided by the divider factor KD, W the window amplitude, VZ the Zener voltage of a
Zener and VF the forward voltage of the Zener (@ 5.5 μA)
●
VUP = VLAMP,MAX/KD = VREF + W/2 + VZ1 + VF
●
VDOWN = VLAMP,MIN/KD = VREF – W/2 – VZ2 – VF
It must be:
●
VUP = - VDOWN
therefore:
●
2 VREF = VZ2 − VZ1
The biasing current available at pin EOL is equal to 5.5 μA then the VZ1 Voltage should be
greater than 8 V in order to have a more precise EOL threshold.
In this case the window comparator can be referenced to the 2.5 V internal reference as
external disturbances don’t influence the lamp voltage mean value (Fixed reference
configurations).
In the Figure 11 is shown the case of asymmetric rectification with positive shifting.
To avoid an immediate intervention of the EOL protection, a filtering is introduced: as soon
as the voltage at pin EOL goes outside the window of the comparator a Tch cycle is started.
The IC is stopped if, at the end of the Tch cycle, the EOL voltage is again outside the limits.
18/41
AN2870
Device blocks description
Figure 11. Window comparator for rectifying effect detection (lamp to GND)
3.3.4
Shutdown
A second comparator, with a threshold equal to 0.8 V, has been introduced on the pin CTR
in order to stop the IC if the CTR pin is pulled to ground. If IC is not in latched condition
when CTR is pulled down, a new starting sequence is performed as CTR pin voltage is
higher than the threshold; this behavior can be used for shutdown.
19/41
Designing with L6585DE
4
AN2870
Designing with L6585DE
Figure 12. Typical application
4.1
PFC stage design
Output voltage and dynamic OVP
Output voltage is set designing a voltage divider connected to INV pin:
Equation 2
⎛ RINV,Hi ⎞
⎟
VOUT = 2.52V ⋅ ⎜1+
⎟
⎜ R
INV
,
Lo
⎠
⎝
The maximum output voltage is set designing a voltage divider connected to CTR pin:
Equation 3
⎛
R
VOUT,MAX = 3.4V ⋅ ⎜1 + CTR,Hi
⎜ R
CTR,Lo
⎝
⎞
⎟
⎟
⎠
Both RINV,Hi and RCTR,Lo should be composed by a suitable number of resistors placed in
series in order to increase the reliability of the application against over-voltages.
20/41
AN2870
Designing with L6585DE
Boost choke design
PFC stage operates in transition mode; for a certain value of input voltage the on time (Ton)
is constant over the entire half period of the input voltage.
The frequency changes along the period of the input voltage: in particular the frequency is
the lowest when the input voltage reaches its maximum.
Moreover the frequency is higher if the output power is low and the frequency variation
changes if input voltage changes.
The internal starter requires a minimum PFC frequency equal to around15 kHz.
Equation 4
fPFC =
⎛
2 ⋅ Vin ⋅ sin(2π ⋅ fmains ⋅ t ) ⎞⎟
Vin2
⋅ ⎜1 −
⎟
2 ⋅ Pin ⋅ L ⎜⎝
Vout
⎠
fPFC,min =
⎛
Vin2
2 ⋅ Vin ⎞⎟
≥ 15kHz
⋅ ⎜1 −
⎜
2 ⋅ Pin ⋅ L ⎝
Vout ⎟⎠
Using Eq.4 with both minimum and maximum value of Vin, the value of L can be selected as
the minimum obtained value. Even the maximum frequency should be checked to avoid to
absorb too much current from Vcc and to degrade the input performances due to excessive
frequency (> 450 kHz) in correspondence to zero input voltage.
The calculation of the maximum frequency is only a rough evaluation of the real frequency;
in fact the presence of the THD optimizer reduces the frequency near the crossover of the
input voltage.
The maximum current flowing into the choke can be evaluated as twice the maximum input
current:
Equation 5
IL,max = 2 ⋅ 2 ⋅
Pin
Vin,min
The ohmic power losses will be evaluated considering the RMS value of the current:
Equation 6
IL,RMS =
Pin
V
3 in,min
2
The choke is realized around of a gapped ferrite core; the core shape has to be selected
considering the electrical parameters (Eq.4,5 and 6), the dimensions of the ballast and the
availability of the selected core. The core should be made by a material suitable for high
frequency operation.
21/41
Designing with L6585DE
AN2870
The number of turns and the length of the gap can be calculated as follows (L in uH, Bmax
in tesla, Ae in square millimeters and μ0=4π*10-7):
Equation 7
Imax L ⎫
Bmax A e ⎪⎪
μ 0N 2 A e
⎬ → lgap = 2 ×
L
L
⎪
AL = 2
⎪
N
⎭
N=
Wire section is selected in order to fit the winding window of the coil former (preferred if
slotted).
In order to evaluate the actual copper losses the DC resistance of the winding must be
multiplied by a factor that depends on skin effect. Using a wire composed by multiple
conductors reduces this factor.
The copper losses can be evaluated as:
Equation 8
PL,Ω = IL2,RMS ⋅ R wire,HF
Ferrite losses can be checked on ferrite manufacturer catalogs.
ZCD auxiliary winding must be able to develop the triggering pulse for ZCD pin
(Varm = 1.4 V). The voltage across the auxiliary winding will be:
Equation 9
(
)
Vaux ,zcd = Vout − 2 ⋅ Vin > m ⋅ 1.4V
The current flowing in ZCD pin must be limited by means of a resistor connected between
auxiliary winding and ZCD pin. Although the maximum ZCD pin current is around 5 mA, a
smaller value should be chosen in order to limit power dissipation and increase the
application reliability.
Equation 10
R ZCD =
22/41
2 ⋅ Vin,max
m ⋅ IZCD
AN2870
Designing with L6585DE
MOSFET selection
PFC MOSFET is to be selected considering the maximum current flowing into the switch,
the maximum voltage between drain and source and the maximum allowed losses.
Maximum allowed losses depend on maximum allowed junction temperature; an ambient
temperature equal to 70 °C – 80 °C is usually considered.
Power losses can be summarized as follows:
●
Conduction losses: due to ohmic resistance of the MOSFET channel during its on
state; these losses are prevalent at minimum input voltage.
●
Switching losses: experienced only during turn off transitions.
●
Capacitive losses: experienced only during turn on transitions when the MOSFET has
to discharge the parasitic capacitance present at its drain. These losses are very high
at higher input voltages.
Conduction losses are related to RDS(on) and RMS value of the drain current:
Equation 11
2
IMOS
,RMS
⎛ P
= 8⎜ in
⎜V
⎝ in,rms
2
⎞ ⎡ 1 4 2 Vin,rms ⎤
⎟ ⎢ −
⎥
⎟ 6
9π VOUT ⎦⎥
⎠ ⎢⎣
Considering a maximum conduction losses less than PCOND,max, the maximum RDS(on),
measured at 100 °C, can be found as follows:
Equation 12
RDS,ON (max) <
PCOND,max
2
IMOS
,RMS
Switching losses are directly related to frequency, to output voltage, to input current and fall
time of drain of the MOSFET. The frequency should be averaged over the half period of the
mains and the fall time of the MOSFET can be found on MOSFET datasheet.
Equation 13
fSW =
Vin2,RMS ⎛ 2 2 VIN,RMS ⎞
⎜1 −
⎟
⋅
π
2 ⋅ Pin ⋅ L ⎜⎝
VOUT ⎟⎠
Equation 14
Pcross = t f fsw VOUTIin,rms = t f fsw VOUT
Pin
Vin,rms
Capacitive losses are present only if instantaneous input voltage is greater than half the
output voltage. In fact when the inductor current becomes zero the parasitic capacitances
seen at the drain node starts to resonate with parasitic inductances causing a damped
oscillation whose peak to peak amplitude is equal to VOUT - Vin.
When Vin<VOUT/2 the drain voltage at MOSFET turn on is almost zero.
23/41
Designing with L6585DE
AN2870
The time when input voltage is greater than VOUT/2 can be calculated as follows:
Equation 15
⎛
VOUT
arcsin⎜
⎜ 2⋅ 2 ⋅V
in,rms
⎝
t1 =
2πfmains
t2 =
1
2fmains
⎞
⎟
⎟
⎠
− t1
Within t2-t1 interval capacitive losses can be written as:
Equation 16
⎛
Pcap = fsw ⎜⎜ 3.3C oss VDrain
⎝
3
2
+
1
(Crss + Coss + Cext ) VDrain
2
Where
Equation 17
VDrain,rms = 2fmains
∫ [2
t2
t1
]
2 ⋅ Vin,rms sin(ωt ) − Vout dt
2
These losses are greater at higher input voltage.
Figure 13 illustrates an example of calculation in wide range application
(Pin = 64 W, MOSFET STx7NM50).
Figure 13. PFC MOSFET losses (example)
24/41
2⎞
⎟
⎟
⎠
AN2870
Designing with L6585DE
Boost diode selection
Boost diode experiences a maximum current equal to maximum boost inductor current, an
average current equal to POUT/VOUT and a RMS current equal to:
Equation 18
2
Id,rms = IL2,rms − IMOS
,RMS =
4 2 2
3 π
Pin
VOUT Vin,rms
The maximum reverse voltage must be greater or equal to VOUT and a fast Schottky diode is
suggested.
Diode power losses can be calculated using the formula reported in diode datasheet:
Equation 19
K1 ⋅ Id,AV + K 2 ⋅ I2d,rms
Bulk capacitor selection
Output voltage ripple is due to capacitance value and equivalent series resistor (ESR) of
bulk capacitor. ESR value is a function of frequency: higher the frequency, lower the ESR
value. The worst ESR will be measured in correspondence of the peak of the input voltage,
when the PFC frequency reaches the minimum frequency.
Equation 20
ΔVOUT =
POUT
+ ESR@ fPFC,min ⋅ ICout ,RMS
4π ⋅ fmains ⋅ VOUT ⋅ C out
Rms value of the bulk capacitor current is:
Equation 21
ICOUT ,RMS =
⎛P
Pin2
32 ⋅ 2
⋅
− ⎜⎜ OUT
9π
Vin,rms ⋅ VOUT ⎝ VOUT
⎞
⎟
⎟
⎠
2
Multiplier biasing and PFC current sense resistor selection
The multiplier biasing proceeds as follows (Figure 14):
1.
Calculate the range of the peak of the input voltage.
2.
Consider the characteristic curve that exploits the maximum slope and the point that
guarantees, on this curve, a linear behavior. Indicate this point as (Vmult,1,VCS,1)
25/41
Designing with L6585DE
AN2870
Figure 14. Multiplier characteristics
3.
At minimum input voltage, Vmult had to be biased to Vmult,1 by means of a voltage
divider connected between the rectified input mains and ground. The divider factor is:
Equation 22
kp =
4.
Vmult,1
Vin,min
=
pk
Rmult,lo
Rmult,lo + Rmult,hi
PFC sense resistor is chosen in order to obtain VCS,1 at maximum input current (i.e. at
minimum input voltage):
Equation 23
RPFCCS =
5.
VCS,1
IL,max
=
VCS,1 ⋅ Vin,min
2 ⋅ 2 ⋅ Pin
Check Vmult when Vin assumes its maximum value: this new bias point should lie on
the linear segment of a characteristic curve.
The upper resistor value should be obtained using a suitable number of resistors in series in
order to increase the reliability of the application. Furthermore a capacitor placed in parallel
with lower resistor helps filtering the high frequency components of the signal; the cut
frequency of this filter can be placed at ten times the mains frequency, i.e. at 500 Hz.
Error amplifier compensation
Error amplifier compensation design proceeds as follows:
Direct gain of the PFC control loop can be written as (cfr AN966):
Equation 24
2
G(s) =
26/41
1 k Mk p Vin,rms R out
4
Vout
RPFCCS
1
R out C out
1+ s
2
AN2870
Designing with L6585DE
Where Rout is the effective resistance of the load (i.e. VOUT2/POUT), kM is the multiplier gain
(reported in datasheet) and Cout is the bulk capacitor.
In order to compensate the loop and reject the ripple superimposed to the output voltage,
the loop gain at 100 Hz should be less than -60 dB. The transfer function of the error
amplifier, compensated with a simple capacitor can be written as:
Equation 25
Gcomp (s ) =
1
sC compRinvh
and:
Equation 26
⎛
1
Gloop (s ) = G(s ) ⋅ Gcomp (s ) = ⎜
⎜ sC compRinvh
⎝
⎛
⎞ ⎜ 1 k Mk p Vin,rms 2 R out
1
⎟⋅⎜
⎟ ⎜4
R
C
V
R
out
pfccs 1 + s out out
⎠ ⎜
2
⎝
⎞
⎟
⎟
= 0.001
⎟
⎟
⎠ s = 2 π100Hz
Using a high value for Rinvh the value of Ccomp is reduced.
Input rectifier
This component is needed to supply the PFC stage with a rectified voltage.
The reverse voltage should be greater than twice Vin,max, the forward current greater than
maximum input current and the power dissipation greater than:
Equation 27
PB =
4
2
Iin,rms(max) VF = 2 2
Pin
Vin,rms(min)
VF
Input capacitor
At this stage of design the current absorption is impulsive. The mean value of this current is
in phase with the input voltage, but the high frequency components have amplitude equal to
twice the amplitude of the mean value, therefore can create interferences with nearby
electronic equipment. An input filter capacitor must be placed between the rectifier and the
PFC stage in order to reduce the high frequency current ripple superimposed to the input
current.
Let be r the maximum allowed ratio between ripple amplitude and mean value of the input
current:
Equation 28
Cin,min =
Iin,RMS
2π ⋅ r ⋅ fsw
min
⋅ Vin,RMS(min)
=
Pin
2π ⋅ r ⋅ fsw
min
⋅ Vin,RMS(min)
2
27/41
Designing with L6585DE
AN2870
The mean value of the PFC frequency is calculated accordingly with Eq.13.
This capacitor may worsen the overall performance of the PFC stage: in fact the energy
stored in it may not be transferred to inductor when the input voltage is near zero. This is the
main reason of the introduction of the THD optimizer.
Other input circuitry
The EMI behavior of the circuit needs to be improved with a suitable EMI filter, a fuse with
inrush limiter can be introduced for improved reliability against burst and surge events and
finally also a surge suppressor (varistor) can be needed.
4.2
Ballast stage design
Resonant network and operating point design
The values of resonant inductor and resonant capacitor and the operating frequencies are
chosen in order to:
a)
Supply the lamp with correct voltage and current during run mode
b)
Maintain lamp voltage lower than Vpre during preheating mode
c)
Develop a suitable high voltage across the lamp during the ignition
The resonant network when the lamp is off has a very high Q factor and the resonant
frequency is very close to the ideal resonant frequency of an LC resonator.
The relationship between lamp voltage and frequency can be easily found using the Fourier
transform and considering the fundamental harmonic of the square wave generated by the
half bridge.
Input voltage will be:
Equation 29
Vbal,pk =
2
Vout
π
Useful parameters are resonant frequency f0, characteristic impedance Z0 and Q factor:
Equation 30
1
⎧
⎪f0 =
2π L res Cres
⎪
⎪
L res
⎪
⎨Z 0 =
C
res
⎪
⎪
Rlamp
V
⎪Q =
= run
⎪⎩
Z0
Irun Z 0
Where Vrun and Irun are respectively the lamp voltage and lamp current.
The suitable frequencies to obtain the desired operating parameters can be calculated as
follows:
28/41
AN2870
Designing with L6585DE
Equation 31
⎛
4 Vout
1 ⎞
1 ⎞
⎛
⎛
⎜ 2 − 2 ⎟ + ⎜ 2 − 2 ⎟ − 4 + ⎜⎜
Q ⎠
Q ⎠
⎝
⎝
⎝ π ⋅ Z 0 ⋅ Q ⋅ 2Irun
2
frun = f0
fpre =
2
2
2
⎤
⎞
⎟ + 4 ⎥ = (OR) = f0 1 + 2Vout
⎥
⎟
πVpre
⎠
⎥⎦
⎡
⎛ 2Vout
f0 ⎢ 2Vout
+ ⎜
⎢
⎜ π ⋅ Z 0 ⋅ Ipre
2 π ⋅ Z 0 ⋅ Ipre
⎝
⎢⎣
fign = f0 1 +
⎞
⎟
⎟
⎠
2Vout
π ⋅ 2 ⋅ Vign
L and C are chosen in order to fit the following constraints:
●
Preheating voltage has to be less than a value reported on lamp datasheet to avoid
early ignition.
Equation 32
Vpre =
●
Vbal,pk
⎛ fpre
f
⎜
− 0
⎜ f0
f
pre
⎝
⎞
⎟
⎟
⎠
2
⋅
fres
< Vpre,max
fpre
In case of current controlled preheating, the Preheating current should be between two
values in order to obtain an effective preheating. These two values depend on the
preheating time, or, better, on the total energy delivered to the lamp during preheating.
Equation 33
Vbal,pk
Ipre =
Z0
●
⎛ fpre
f
⎜
− 0
⎜ f0
f
pre
⎝
⎞
⎟
⎟
⎠
2
[
∈ Iph,min ..Iph,max
]
Run frequency should be less than minimum ignition frequency. This frequency is the
frequency at which the voltage across the lamp reaches its maximum value (reported
on lamp datasheet).
Equation 34
Vign =
Vbal,pk
⎛ fign,min
⎞
f
⎜
− 0 ⎟
⎜ f0
fign,min ⎟⎠
⎝
2
⋅
fres
fign,min
29/41
Designing with L6585DE
AN2870
Equation 35
Vbal,pk
Irun =
⎛
Z0
⎛f ⎞
Q 1 − ⎜⎜ run ⎟⎟
⎜
f
⎝ ⎝ 0 ⎠
2⎜
2⎞
2
⎟ + ⎛⎜ frun ⎞⎟
⎜ f ⎟
⎟
⎝ 0 ⎠
⎠
2
An example of characteristic curves is reported in Figure 15-A and B
Figure 15. (A) voltage frequency response
Figure 15. (B) current frequency response
Ballast inductor experiences the maximum current during ignition, when the operating point
is very close to the resonance frequency.
Equation 36
Iballast,ign
⎛
⎜
⎜
⎜ Vbal,pk
=⎜
⎜ Z0
⎜
⎜⎜
⎝
⎛ fign
1 + ⎜⎜ Q
⎝ f0
⎞
⎟
⎟
⎠
2
⎡ ⎛ f ⎞2 ⎤
⎛f
ign
⎟ ⎥ + ⎜ ign
Q 1 − ⎜⎜
⎜ f
⎢ ⎝ f0 ⎟⎠ ⎥
⎝ 0
⎣
⎦
2⎢
⎞
⎟
⎟
⎠
2
⎞
⎟
⎟
⎟
⎟
⎟
⎟
⎟⎟
⎠
Rhbcs must be chosen in order to obtain the minimum ignition voltage across the lamp:
Equation 37
RHBCS =
Vhbcsh
Iballast,ign
Rhbcs power rating can be calculated considering the RMS value of the low side current
during ignition.
In this case the bias point lies at a frequency close to the resonance frequency, therefore the
current flowing in resonant network is almost sinusoidal.
This allows the designer to approximate the RMS current to:
30/41
AN2870
Designing with L6585DE
Equation 38
Ihbcs,RMS ≈
Ilamp,pk
2
And the power rating to:
Equation 39
Phbcs ≈ Rhbcs ⋅ I2hbcs ,RMS
The real maximum inductor current and lamp voltage can be calculated considering the
maximum threshold value and the tolerances related with value of Rhbcs and Lres.
The design of the inductor proceeds as indicated in Eq 7.
The resonance capacitor is preferably a metallized polyester film capacitor. Blocking
capacitor is around ten times the resonant one: a value greater or equal to 100 nF for the
polyester capacitor is usually chosen.
Parameters setting
In order to fix the run frequency and the preheating frequency, the following curves can be
used. Each curve is related with a particular capacitor value, therefore a capacitor value
must be firstly chosen. The resistances corresponding Frun and Fpre can be graphically
found and are respectively Rrun and the parallel between Rrun and Rpre.
Figure 16. Oscillator characteristic curves
31/41
Designing with L6585DE
AN2870
A more accurate procedure can be followed considering that the reported curves can be
represented by the following equation (f in kHz and R in kΩ):
Equation 40
f=
k
(R)e
In particular the constant, k, and the exponent, e, can be calculated for a given Cosc
(expressed in pF) as follows:
Equation 41
k=
499.6 ⋅ 10 3
(COSC )0.872
Equation 42
e = 1−
Figure 17. (A) k parameter versus Cosc (pF)
1.33
(COSC )0.581
Figure 17. (B) e parameter versus Cosc (pF)
Firstly k and e should be found and then R can be calculated as follows:
Equation 43
R run
⎛ k
= ⎜⎜
⎝ frun
R pre // R run
32/41
1
⎞e
⎟⎟
⎠
⎛ k
=⎜
⎜ fpre
⎝
1
⎞e
⎟
⎟
⎠
AN2870
Designing with L6585DE
The ignition time is equal to the time the capacitor Cign is charged by the RF current and the
EOI leakage current. A precise calculation of this parameter is not needed. It’s
approximately equal to:
Equation 44
Tign = 3Rpre Cign
Preheating time and protection time are related to Tch cycle:
Equation 45
Tpre = 4.63
CD
⎛ 4.63 ⎞
+ RDCD ln⎜
⎟
ITCH
⎝ 1. 5 ⎠
Equation 46
Tprot = 269740 ⋅ CD
Half bridge design
When resonant network works in inductive region, half bridge MOSFETs switch at zero
voltage switching condition.
This implies that high side and low side MOSFETs experience mainly conduction losses
because of their on state resistance.
Equation 47
P cond = R ds,on ⋅ (Irms )
2
Irms can be considered as per Eq 38 or can be calculated considering that the waveform
seen during an on time is a sinusoid having a frequency equal to resonance frequency.
From thermal consideration the maximum Rds,on can be calculated.
In order to drive correctly the high side MOSFET, a suitable boostrap capacitor is needed.
The size of the boostrap capacitor can be calculated considering the allowed Vgs drop, the
total gate capacitance of the High side MOSFET and the Ron of the integrated boostrap
diode.
In steady state, during the ON time of the low side transistor the bootstrap capacitor stores
charges:
Equation 48
Qboot= Cboot⋅ Vcc
During the ON time of the high side transistor, the charges stored in bootstrap capacitor are
shared with total gate capacitance, causing a voltage drop:
33/41
Designing with L6585DE
AN2870
Equation 49
C gate + Cboot =
Qboot
Vcc − ΔV
These charges must be replaced during the subsequent ON time of the low side transistor:
Equation 50
⎞
⎡
⎛ ΔV ⎞ ⎤ ⎛ 1
⎟⎥ < ⎜
− TDeadTime ⎟ = Ton,min
Tboot = −R on Cboot ⋅ ⎢1 − ln⎜⎜
⎟
⎜
⎟
⎢⎣
⎝ Vcc ⎠⎥⎦ ⎝ 2 ⋅ fpre
⎠
End of life detection
Blocking capacitor to GND configuration:
In case of blocking capacitor to ground configuration the tracking mode is suggested. In
order to set this mode a resistor placed between EOLP and GND is needed: its value has to
be chosen as follows:
●
●
220 kΩ < Reolp < 270 kΩ → VW = 240 mV
22 kΩ < Reolp < 27 kΩ → VW = 150 mV
EOL pin biasing proceeds as follows:
The blocking capacitor mean voltage is half of the PFC output voltage and the CTR pin
voltage is equal to:
Equation 51
V CTR = 3.4 ⋅
Vout
VOVP
Therefore the voltage divider connected between Cblock and EOL pin should have a divider
factor equal to:
Equation 52
k eol =
2 ⋅ VCTR
6.8
=
Vout
VOVP
A capacitor placed in parallel with the lower resistor and placed near the IC helps to keep
low the high frequency residual noise.
34/41
AN2870
Designing with L6585DE
Figure 18. EOL - Cblock to ground
Lamp to GND configuration:
In case of lamp to ground configuration the fix reference mode is suggested.
In order to set this mode a resistor placed between EOLP and GND is needed: its value has
to be chosen as follows:
●
75 kΩ < Reolp < 91kΩ → window amplitude = 240 mV
●
620 kΩ < Reolp → window amplitude = 720 mV
The EOL pin biasing proceeds as follows:
A voltage shift is needed in order to detect a null value with a positive referenced
comparator: two Zener diodes are requested.
The current capability of EOL pin is equal to 5.5 µA, therefore the minimum Zener voltage
that guarantees accuracy of the measurement is 8 V.
35/41
Designing with L6585DE
AN2870
Figure 19. EOL - lamp to ground
Consider the case of positive going lamp voltage mean value (VK): the maximum VK allowed
value is equal to:
Equation 53
VK
max
= 2.5 + VW + Vz1 + VF 2
VK
min
= 2.5 − VW − Vz 2 − VF1
In the opposite case it will be:
Equation 54
In order to have a symmetrical behavior, the absolute values of the two voltages have to be
equal.
This brings to the following relation:
Equation 55
⎞
= ⎛⎜ − V
VK
⎟
max ⎝ K min ⎠
⇒ 2.5 + VW + Vz1 + VF2 = −2.5 + VW + Vz2 + VF1
⇒ 2 ⋅ 2.5V = Vz2 − Vz1
The difference of the Zener voltages has to be equal to 5V: twice the reference voltage.
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AN2870
Designing with L6585DE
The maximum deviation of the mean voltage of the lamp, Vlamp,EOL, depends on the lamp
type (e.g. is 15 V for T5-54W lamp).
The following relation can be used to calculate the correct value of the divider's resistors
(REhi and RElo)
Equation 56
VK max = Vlamp,EOL − REhi ⋅ (IRElo + IEOL )
VK max = Vlamp,EOL −
Vlamp,EOL ⋅ REhi
REhi + RElo
− REhi ⋅ 5.5μA
The value of filtering capacitor should be calculated in order to have a cutoff frequency
equal to at least one hundreds of run frequency.
IC power supply design
L6585DE can be supplied by means of either external source, auxiliary winding on PFC
choke or charge pump connected to the middle point of half bridge. The most used method
is the charge pump connected to the middle point of the half bridge.
The charge pump must be able to deliver the correct current to the IC. ICC depends on both
half bridge and PFC driver switching activities. Typical values of ICC are reported on
Figure 20.
The current is delivered by the capacitor during the edges of the middle point of the half
bridge. The slope of these edges is also related to the recovery time of the body diode of the
MOSFETs and to the capacitor itself. Assuming a linear slope the instantaneous current
delivered by the capacitor will be:
Equation 57
Icp,pk = C cp
VOUT
Trise
Equation 58
Icp = Icp,pk ⋅ Trise ⋅ frun ≥ Icc
The diode connected to ground is a Zener diode (15 V is the suggested value): it limits the
voltage across the Vcc pin avoiding an extra stress of the internal active clamp. In order to
limit the current flowing into this diode, when it is directly biased, a low value resistor is
placed in series with the capacitor.
A bigger capacitor (>1 µF) and a 100 nF ceramic capacitor placed near the IC are needed to
filter the Vcc voltage.
At start up the current is sunk from rectified mains and delivered to the IC through a resistor
path. This resistor is chosen in order to guarantee the minimum quiescent current required
by L6585DE (370 µA). Its value influences also the start-up time because it had to charge
the electrolytic capacitor connected to Vcc.
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Designing with L6585DE
Figure 20. Current consumption vs PFC frequency
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AN2870
AN2870
4.3
Designing with L6585DE
PCB hints
The following rules, considered during the PCB design, help to optimize the performance of
the L6585DE.
1. In a board containing both PFC and Ballast section four different ground potentials are
present:
a) PFC signal ground,
b) PFC power ground
c) Ballast signal ground and
d) Ballast power ground.
These traces are usually kept separate and connected together in correspondence of a low
impedance node (the negative terminal of bulk capacitor). A similar rule has to be followed
in the L6585DE: power grounds are to be kept separate and connected to the negative
terminal of the bulk capacitor, signal grounds should be firstly routed to the pin GND (15)
and then the pin 15 is connected to the negative terminal of bulk capacitor. It is very
important that the ground trace relevant to COSC, RRF and CPRE is connected directly to the
GND pin as shortly as possible.
2. Ballast PCBs are usually long and narrow, therefore current loops are to be minimized
in order to reduce the electromagnetically induced interference between PFC stage
and Ballast Stage. This is very important when wide range application has to be
implemented.
3. Regions surrounding the gap of the chokes are usually very noisy therefore signal and
ground traces shouldn’t pass underneath these regions.
4. Traces that connect the gates of the MOSFETs, the OUT pin and the charge pump
components are affected by voltages that vary with very fast edges. They can
capacitively induce noise to closest traces. Therefore if a signal has to pass near these
nodes an increased distance between traces or, eventually, a ground shield has to be
considered.
5. Ground pin of shunt components should be placed as close as possible to star
connection point or, at least, close together, this avoids errors reading the voltage
across them and current sense traces has to be kept as short as possible in order to
avoid HF noise induction. In the second case is preferable to connect signal GND to the
ground of the shunts instead of the star point.
6. Bootstrap capacitor and Vcc ceramic capacitor have to be placed as close as possible
to relevant pins.
7. Error amplifier feedback network must be small and placed near the IC in order to
reduce any loop that can couple radio interference.
8. The drain of the PFC MOSFET, the anode of Boost Diode and the PFC choke are
connected together as close as possible. In fact this node experienced very fast edges
and also very high currents.
39/41
Revision history
5
AN2870
Revision history
Table 2.
40/41
Document revision history
Date
Revision
26-Mar-2009
1
Changes
Initial release
AN2870
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