256k × 16-Bit EDO-DRAM HYB 514175BJ-50/-55/-60 Advanced Information • • • • • • • • • 262 144 words by 16-bit organization 0 to 70 °C operating temperature Fast access and cycle time • Low Power dissipation max. 1100 mW active (-50 version) max. 1045 mW active (-55 version) max. 935 mW active (-60 version) • Standby power dissipation 11 mW standby (TTL) 5.5 mW max. standby (CMOS) • Output unlatched at cycle end allows two-dimensional chip selection • Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh, hidden-refresh and hyper page (EDO) mode capability • 2 CAS/1 WE control • All inputs and outputs TTL-compatible • 512 refresh cycles/16 ms • Plastic Packages: P-SOJ-40-1 400 mil width RAS access time: 50 ns (-50 version) 55 ns (-55 version) 60 ns (-60 version) CAS access time: 13 ns (-50 & -55 version) 15 ns (-60 version) Cycle time: 89 ns (-50 version) 94 ns (-55 version) 104 ns (-60 version) Hyper page mode (EDO) cycle time 20 ns (-50 & -55 version) 25 ns (-60 version) High data rate 50 MHz (-50 & -55 version) 40 MHz (-60 version) Single + 5 V (± 10 %) supply with a built-in VBB generator Semiconductor Group 1 1998-10-01 HYB 514175BJ/BJL-50/-55/-60 256k × 16 EDO-DRAM The HYB 514175BJ is the new generation dynamic RAM organized as 262 144 words by 16-bit. The HYB 514175BJ utilizes CMOS silicon gate process as well as advanced circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514175BJ to be packed in a standard plastic 400 mil wide P-SOJ-40-1 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 5 V (± 10 %) power supply, direct interfacing with high performance logic device families such as Schottky TTL. Ordering Information Type Ordering Code Package Description HYB 514175BJ-50 Q67100-Q2072 P-SOJ-40-1 400 mil 50 ns 256k × 16 EDO-DRAM HYB 514175BJ-55 Q67100-Q2100 P-SOJ-40-1 400 mil 55 ns 256k × 16 EDO-DRAM HYB 514175BJ-60 Q67100-Q2073 P-SOJ-40-1 400 mil 60 ns 256k × 16 EDO-DRAM Truth Table RAS LCAS UCAS WE OE I/O1 - I/O8 I/O9 - I/O16 Operation H L L L L L L L L H H L H L L H L L H H H L L H L L L H H H H H L L L H H H L L L H H H H High-Z High-Z Dout High-Z Dout Din Don't care Din High-Z High-Z High-Z High-Z Dout Dout Don't care Din Din High-Z Standby Refresh Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write − Pin Names A0 - A8 Address Inputs RAS Row Address Strobe UCAS, LCAS Column Address Strobe WE Read/Write Input OE Output Enable I/O1 -I/O16 Data Input/Output VCC Power Supply (+ 5 V) VSS Ground (0 V) N.C. No Connection Semiconductor Group 2 1998-10-01 HYB 514175BJ-50/-55/-60 256k × 16 EDO-DRAM P-SOJ-40-1 V CC I/O1 I/O2 I/O3 I/O4 V CC I/O5 I/O6 I/O7 I/O8 N.C. N.C. WE RAS N.C. A0 A1 A2 A3 V CC 40 V SS 39 I/O16 38 I/O15 37 I/O14 36 I/O13 35 V SS 34 I/O12 33 I/O11 32 I/O10 31 I/O9 30 N.C. 29 LCAS 28 UCAS 27 OE 26 A8 25 A7 24 A6 23 A5 22 A4 21 V SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SPP02811 Pin Configuration (top view) Semiconductor Group 3 1998-10-01 HYB 514175BJ/BJL-50/-55/-60 256k × 16 EDO-DRAM I/O1 I/O2 . . . I/O16 . . .. Data In Buffer WE UCAS LCAS Data Out Buffer OE 16 & 16 No.2 Clock Generator 9 Column Address Buffers (9) 9 A0 A1 Refresh Controller A2 Column Decoder Sense Amplifier I/O Gating A3 16 A4 A5 512 x 16 . .. A7 . .. Refresh Counter (9) A6 9 A8 9 RAS Row Address Buffers (9) 9 Row Decoder .. . 512 .. . No.1 Clock Generator Substrate Bias Generator Memory Array 512 x 512 x 16 V CC V SS SPB02827 Block Diagram Semiconductor Group 4 1998-10-01 HYB 514175BJ-50/-55/-60 256k × 16 EDO-DRAM Absolute Maximum Ratings Operating temperature range ....................................................................................... 0 to + 70 °C Storage temperature range.................................................................................... – 55 to + 150 °C Input/output voltage ....................................................................................................... – 1 to + 6 V Power supply voltage..................................................................................................... – 1 to + 6 V Data out current (short circuit) ............................................................................................... 50 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 2 ns Parameter Symbol Limit Values min. max. Unit Test Condition Input high voltage VIH 2.4 VCC + 0.5 V 1 Input low voltage VIL – 1.0 0.8 V 1 Output high voltage (IOUT = – 5.0 mA) VOH 2.4 – V 1 Output low voltage (IOUT = 4.2 mA) VOL – 0.4 V 1 Input leakage current, any input (0 V < VIN < 7 V, all other inputs = 0 V) II(L) – 10 10 µA 1 Output leakage current (DO is disabled, 0 V < VOUT < VCC) IO(L) – 10 10 µA 1 Average VCC supply current ICC1 – 200 190 170 mA 2, 3, 4 2 mA 200 190 170 mA -50 version -55 version -60 version Standby VCC supply current (RAS = LCAS = UCAS = WE = VIH) ICC2 – Average VCC supply current during RAS-only refresh cycles ICC3 – -50 version -55 version -60 version Average VCC supply current during hyper page mode (EDO) operation ICC4 -50 version -55 version -60 version Semiconductor Group 2, 3, 4 – 190 180 170 5 2, 4 mA 1998-10-01 HYB 514175BJ/BJL-50/-55/-60 256k × 16 EDO-DRAM DC Characteristics (cont’d) TA = 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 2 ns Parameter Symbol Limit Values min. max. Unit Test Condition 1 mA Standby VCC supply current (RAS = LCAS = UCAS = WE = VCC – 0.2 V) ICC5 – Average VCC supply current during CAS-before-RAS refresh mode ICC6 – 1 2, 4 -50 version -55 version -60 version 200 190 170 mA Capacitance TA = 0 to 70 °C; VCC = 5 V ± 10 %, f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A8) CI1 – 5 pF Input capacitance (RAS, UCAS, LCAS, WE, OE) CI2 – 7 pF Output capacitance (l/O1 to l/O16) CIO – 7 pF AC Characteristics 5, 6 TA = 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 2 ns Parameter Symbol Limit Values -50 -55 Unit Note -60 min. max. min. max. min. max. Common Parameters Random read or write cycle time tRC 89 – 94 – 104 – ns RAS precharge time tRP 35 – 35 – 40 – ns RAS pulse width tRAS 50 10k 55 10k 60 10k ns CAS pulse width tCAS 8 10k 8 10k 10 10k ns Row address setup time tASR 0 – 0 – 0 – ns Row address hold time tRAH 8 – 8 – 10 – ns Column address setup time tASC 0 – 0 – 0 – ns Column address hold time tCAH 8 – 8 – 10 – ns RAS to CAS delay time tRCD 12 37 12 43 14 45 ns RAS to column address delay time tRAD 10 25 10 30 12 30 ns Semiconductor Group 6 1998-10-01 HYB 514175BJ-50/-55/-60 256k × 16 EDO-DRAM AC Characteristics (cont’d)5, 6 TA = 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 2 ns Parameter Symbol Limit Values -50 -55 Unit Note -60 min. max. min. max. min. max. RAS hold time tRSH 13 – 13 – 15 – ns CAS hold time tCSH 40 – 45 – 50 – ns CAS to RAS precharge time tCRP 5 – 5 – 5 – ns Transition time (rise and fall) tT 1 50 1 50 1 50 ns Refresh period tREF – 16 – 16 – 16 ms Access time from RAS tRAC – 50 – 55 – 60 ns 8, 9 Access time from CAS tCAC – 13 – 13 – 15 ns 8, 9 Access time from column address tAA – 25 – 25 – 30 ns 8, 10 OE access time tOEA – 13 – 13 – 15 ns Column address to RAS lead time tRAL 25 – 25 – 30 – ns Read command setup time tRCS 0 – 0 – 0 – ns Read command hold time tRCH 0 – 0 – 0 – ns 11 Read command hold time ref. to RAS tRRH 0 – 0 – 0 – ns 11 tCLZ 0 – 0 – 0 – ns 8 Output buffer turn-off delay from CAS tOFF 0 13 0 13 0 15 ns 12 Output buffer turn-off delay from OE tOEZ 0 13 0 13 0 15 ns 12 Data to OE low delay tDZO 0 – 0 – 0 – ns 13 CAS high to data delay tCDD 10 – 10 – 13 – ns 14 OE high to data delay tODD 10 – 10 – 13 – ns 14 Write command hold time tWCH 8 – 8 – 10 – ns Write command pulse width tWP 8 – 8 – 10 – ns Write command setup time tWCS 0 – 0 – 0 – ns Write command to RAS lead time tRWL 13 – 13 – 15 – ns Write command to CAS lead time tCWL 13 – 13 – 15 – ns Data setup time tDS 0 – 0 – 0 – ns 16 Data hold time tDH 8 – 8 – 10 – ns 16 Data to CAS low delay tDZC 0 – 0 – 0 – ns 13 7 Read Cycle CAS to output in low-Z Write Cycle Semiconductor Group 7 15 1998-10-01 HYB 514175BJ/BJL-50/-55/-60 256k × 16 EDO-DRAM AC Characteristics (cont’d)5, 6 TA = 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 2 ns Parameter Symbol Limit Values -50 -55 Unit Note -60 min. max. min. max. min. max. Read-Modify-Write Cycle Read-write cycle time tRWC 118 – 122 – 138 – ns RAS to WE delay time tRWD 64 – 69 – 77 – ns 15 CAS to WE delay time tCWD 27 – 27 – 32 – ns 15 Column address to WE delay time tAWD 39 – 39 – 47 – ns 15 OE command hold time tOEH 10 – 10 – 13 – ns Hyper page mode cycle time tHPC 20 – 20 – 25 – ns CAS precharge time tCP 8 – 8 – 10 – ns Access time from CAS precharge tCPA – 27 – 27 – 32 ns Output data hold time tCOH 5 – 5 – 5 – ns 50 200k 55 200k 60 200k ns 27 – 27 – 32 – ns Hyper Page Mode (EDO) Cycle RAS pulse width in hyper page mode tRAS RAS hold time from CAS precharge tRHCP 7 Hyper Page Mode (EDO) Read-Modify-Write Cycle Hyper page mode read/write cycle time tPRWC 58 – 58 – 68 – ns CAS precharge to WE delay time tCPWD 41 – 41 – 49 – ns CAS setup time tCSR 5 – 5 – 5 – ns CAS hold time tCHR 10 – 10 – 10 – ns RAS to CAS precharge time tRPC 5 – 5 – 5 – ns Write to RAS precharge time tWRP 10 – 10 – 10 – ns Write to RAS hold time tWRH 10 – 10 – 10 – ns 35 – 35 – 40 – ns CAS-before-RAS Refresh Cycle CAS-before-RAS Counter Test Cycle CAS precharge time Semiconductor Group tCPT 8 1998-10-01 HYB 514175BJ-50/-55/-60 256k × 16 EDO-DRAM Notes All voltages are referenced to VSS. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. Address can be changed once or less while RAS = VIL. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle 5. An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6. AC measurements assume tT = 2 ns. 7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8. Measured with the specified current load and 100 pF at VOL = 0.8 V and VOH = 2.0 V. Access time is determined by the latter of tRAC, tCAC, tAA , tCPA , tOEA. tCAC is measured from tristate. 9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as a reference point only. If tRCD is greater than the specified tRCD (MAX.) limit, then access time is controlled by tCAC. 10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as a reference point only. If tRAD is greater than the specified tRAD (MAX.) limit, then access time is controlled by tAA. 11.Either tRCH or tRRH must be satisfied for a read cycle. 12.tOFF (MAX.), tOEZ (MAX.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13.Either tDZC or tDZO must be satisfied. 14.Either tCDD or tODD must be satisfied. 15.tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (MIN.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (MIN.), tCWD > tCWD (MIN.) and tAWD > tAWD (MIN.), the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminated. 16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 1. 2. 3. 4. Semiconductor Group 9 1998-10-01 HYB 514175BJ/BJL-50/-55/-60 256k × 16 EDO-DRAM t RC t RP t RAS VIH RAS VIL t CSH t RCD UCAS LCAS t RSH t CAS VIH t CRP VIL t RAD t ASR t RAL t CAH t ASC t ASR VIH Address Row VIL Column Row t RAH t RCH t RCS t RRH VIH WE VIL t AA t OEA VIH OE VIL t DZC t CDD t DZO I/O (Inputs) t ODD VIH VIL t OFF t CAC t CLZ VOH I/O (Outputs) V OL Hi Z t OEZ Valid Data OUT Hi Z t RAC "H" or "L" SPT03043 Read Cycle Semiconductor Group 10 1998-10-01 HYB 514175BJ-50/-55/-60 256k × 16 EDO-DRAM t RC t RAS t RP VIH RAS VIL t CSH t RCD UCAS LCAS t RSH t CAS VIH t CRP VIL t RAL t RAD t ASR t ASC t CAH t ASR VIH Address Row VIL Column t RAH t CWL t WCS VIH Row t WP WE VIL t WCH t RWL VIH OE VIL t DS I/O (Inputs) t DH VIH Valid Data IN VIL VOH I/O (Outputs) V OL Hi Z "H" or "L" SPT03044 Write Cycle (Early Write) Semiconductor Group 11 1998-10-01 HYB 514175BJ/BJL-50/-55/-60 256k × 16 EDO-DRAM t RC t RAS t RP VIH RAS VIL t CSH t RCD UCAS LCAS t RSH t CAS VIH t CRP VIL t RAD t RAL t CAH t ASC t ASR t ASR VIH Address Row VIL Column Row t RAH t CWL t RWL t WP VIH WE VIL t OEH VIH OE VIL t ODD t DZO t DZC I/O (Inputs) t DH t DS VIH Valid Data VIL t CLZ t OEZ t OEA VOH I/O (Outputs) V OL Hi Z Hi Z "H" or "L" SPT03045 Write Cycle (OE Controlled Write) Semiconductor Group 12 1998-10-01 HYB 514175BJ-50/-55/-60 256k × 16 EDO-DRAM t RWC t RAS VIH RAS VIL t CSH t RP t RSH t RCD UCAS LCAS t CAS t CRP VIH VIL t RAH t ASR t CAH t ASC t ASR VIH Address Row Column Row VIL t RAD t CWL t AWD t RWL t CWD t RWD t WP VIH WE VIL t AA t RCS t OEA t OEH VIH OE VIL t DZC t DS t DZO I/O (Inputs) t DH VIH Valid Data IN VIL t ODD t CAC t OEZ t CLZ VOH I/O (Outputs) V OL Data OUT t RAC "H" or "L" SPT03046 Read-Write (Read-Modify-Write) Cycle Semiconductor Group 13 1998-10-01 HYB 514175BJ/BJL-50/-55/-60 256k × 16 EDO-DRAM t RAS t RCD t RHCP VIH RAS VIL t HPC t RSH t CAS t CP t CRP UCAS LCAS t RP t CAS t CAS t CRP VIH VIL t CSH t RAH t ASR t RAL t CAH t ASC t CAH t CAH t ASC Column 2 Column N t ASC VIH Address Row Column 1 VIL t RAD t RRH t RCS t RCH VIH WE VIL t CAC t AA t OES t OEA t CPA t CAC t AA t CPA t OFF VIH OE VIL t RAC t AA t CAC t CLZ t COH t COH t OEZ VOH I/O (Output) V OL Data OUT 1 Data OUT 2 Data OUT N "H" or "L" SPT03056 Hyper Page Mode (EDO) Read Cycle Semiconductor Group 14 1998-10-01 HYB 514175BJ-50/-55/-60 256k × 16 EDO-DRAM t RAS t RCD t RHCP VIH RAS VIL t HPC t CP t CRP UCAS LCAS t RP t CAS t RSH t CAS t CAS t CRP VIH VIL t CSH t RAH t ASR VIH Address VIL t ASC Row Address t CAH t ASC Column 1 t CAH t RAL t CAH t ASC Column 2 Column N t RAD t RWL t CWL t WCS t CWL t WCS t CWL t WCS t WCH t WP t WCH t WP t WCH t WP VIH WE VIL VIH OE VIL t DH t DS I/O (Input) t DH t DS t DH t DS VIH Data IN 1 Data IN 2 Data IN N VIL "H" or "L" SPT03057 Hyper Page Mode (EDO) Early Write Cycle Semiconductor Group 15 1998-10-01 HYB 514175BJ/BJL-50/-55/-60 256k × 16 EDO-DRAM t RASP VIH RAS VIL t CSH t RP t CP t RCD UCAS LCAS t RSH t PRWC t CAS t CAS t CAS t CRP VIH VIL t ASR t RAD t RAH t ASC t RAL t CAH t CAH t CAH t ASC t ASC t ASR VIH Address Row Column Column Column Row VIL t RWD t CWD t RCS t CPWD t CWD t CWL t CPWD t CWD t CWL t RWL t CWL VIH WE VIL t AWD t AA t AWD t WP t OEA t AWD t WP t OEA t OEH t WP t OEA t OEH t OEH VIH OE VIL t CLZ t DZC t CLZ t ODD t CLZ t CPA t ODD t DZC t DZO VIH I/O (Inputs) V IL Data IN t CAC t RAC VOH I/O (Outputs) V t OEZ t CPA t ODD Data IN t DH t DS t DZC Data IN t DH t AA t DS t OEZ Data OUT Data OUT t DH t CAC t DS t AA t OEZ Data OUT OL "H" or "L" SPT03131 Hyper Page Mode (EDO) Late Write and Read-Modify-Write Cycles Semiconductor Group 16 1998-10-01 HYB 514175BJ-50/-55/-60 256k × 16 EDO-DRAM t RC t RAS t RP VIH RAS VIL t CRP t RPC UCAS LCAS VIH VIL t RAH t ASR t ASR VIH Address Row Row VIL VOH I/O (Outputs) V OL Hi Z "H" or "L" SPT03050 RAS-Only Refresh Cycle Semiconductor Group 17 1998-10-01 HYB 514175BJ/BJL-50/-55/-60 256k × 16 EDO-DRAM t RC t RP t RAS t RP VIH RAS VIL t RPC t CP t CHR t RPC t CSR UCAS LCAS t CRP VIH VIL t WRH t WRP VIH WE VIL VIH OE VIL t ODD I/O (Inputs) VIH VIL t CDD t OEZ VOH Hi Z I/O (Outputs) V OL t OFF "H" or "L" SPT03051 CAS-Before-RAS Refresh Cycle Semiconductor Group 18 1998-10-01 HYB 514175BJ-50/-55/-60 256k × 16 EDO-DRAM t RC t RC t RP t RP t RAS t RAS VIH RAS VIL t RCD UCAS LCAS t RSH t CHR t CRP VIH VIL t RAD t ASC t WRP t RAH t ASR t WRH t CAH t ASR VIH Address Row VIL Column Row t RCS t RRH VIH WE VIL t AA t OEA VIH OE VIL t DZC t CDD t ODD t DZO I/O (Inputs) VIH VIL t CLZ t CAC t OFF t RAC t OEZ VOH I/O (Outputs) V OL Valid Data OUT "H" or "L" Hi Z SPT03053 Hidden Refresh Cycle (Read) Semiconductor Group 19 1998-10-01 HYB 514175BJ/BJL-50/-55/-60 256k × 16 EDO-DRAM t RC t RC t RAS t RP t RAS t RP VIH RAS VIL t RCD UCAS LCAS t RSH t CHR t CRP VIH VIL t RAD t ASC t RAH t ASR t ASR t CAH VIH Address Row VIL Column Row t WCS t WCH t WP t WRH t WRP VIH WE VIL t DS t DH I/O (Input) VIN Valid Data VIL VOH I/O (Output) V OL Hi Z "H" or "L" SPT03054 Hidden Refresh Cycle (Early Write) Semiconductor Group 20 1998-10-01 HYB 514175BJ-50/-55/-60 256k × 16 EDO-DRAM Read Cycle t RAS t RP VIH RAS VIL t CHR t CSR UCAS LCAS t RSH t CP VIH t CAS VIL t RAL t CAH t ASR t ASC VIH Address Column VIL t WRP Row t AA t RRH VIH WE VIL t WRH t CAC t RCS t RCH t OEA VIH OE VIL t CDD t DZC I/O (Inputs) VIH t ODD VIL t OFF t DZO t OEZ t CLZ VOH I/O (Outputs) V OL Write Cycle Data OUT t WCS t RWL t CWL t WRP VIH t WCH WE VIL t WRH t DH VIH OE VIL t DS I/O (Inputs) VIH Data IN VIL VOH I/O (Outputs) V OL Hi Z "H" or "L" SPT03055 CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group 21 1998-10-01 HYB 514175BJ/BJL-50/-55/-60 256k × 16 EDO-DRAM Package Outlines GPJ09018 Plastic Package, P-SOJ-40-1 (SMD) (Plastic small outline J-leaded) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 22 Dimensions in mm 1998-10-01