5-V Low Drop Voltage Regulator TLE 7274 Features • • • • • • Output voltage 5 V ±2% Ultra low current consumption: typ. 20µA 300 mA current capability Very low-drop voltage Short-circuit-proof Suitable for use in automotive electronics P-TO252-3-1 Functional Description The TLE 7274 is a monolithic integrated low-drop voltage regulator for load currents up to 300 mA. An input voltage up to 42 V is regulated to VQ,nom = 5.0 V with a precision of ±2%. The sophisticated design allows to achieve stable operation even with ceramic output capacitors down to 470 nF. The device is designed for P-TO263-3-1 the harsh environment of automotive applications. Therefore it is protected against overload, short circuit and over temperature conditions. Of course the TLE 7274 can be used also in all other applications, where a stabilized 5 V voltage is required. Due to its ultra low stand-by current consumption of typ. 20µA the TLE 7274 is dedicated for use in applications permanently connected to VBAT. An integrated output sink current circuitry keeps the voltage at the Output pin Q below 5.5 V even when reverse currents are applied. Thus connected devices are protected from overvoltage damage. For applications requiring extremely low noise levels the Infineon voltage regulator family TLE 42XY and TLE 44XY is more suited than the TLE 7274. A mV-range output noise on the TLE 7274 caused by the charge pump operation is unavoidable due to the ultra low quiescent current concept. Type Ordering Code Package TLE 7274 D Q67006-A9728 P-TO252-3-1, P-TO252-3-11 TLE 7274 G Q67006-A9731 P-TO263-3-1 Data Sheet 1 Rev. 1.1, 2005-07-30 TLE 7274 TLE 7274 I 1 3 Q Overtemperature Shutdown Bandgap Reference 1 Charge Pump 2, Tab GND Figure 1 Data Sheet AEB03613.VSD Block Diagram 2 Rev. 1.1, 2005-07-30 TLE 7274 GND Ι Q AEP02512 Ι GND Q AEP02281 Figure 2 Pin Configuration P-TO252-3 (D-PAK), P-TO263-3 (D2-PAK)(top view) Table 1 Pin Definitions and Functions Pin No. Symbol Function 1 I Input; block to ground directly at the IC with a ceramic capacitor. 2 GND Ground; Pin 2 internally connected to heatsink. 3 Q Output; block to ground with a ceramic capacitor, C ≥ 470 nF. Data Sheet 3 Rev. 1.1, 2005-07-30 TLE 7274 Table 2 Absolute Maximum Ratings Parameter Symbol Limit Values Unit Test Condition Min. Max. VI II -0.3 45 V – -1 – mA – VQ VQ IQ -0.3 5.5 V – -0.3 6.2 V t < 10 s1) -1 – mA – Tj Tstg -40 150 °C – -50 150 °C – Input I Voltage Current Output Q Voltage Voltage Current Temperature Junction temperature Storage temperature 1) Exposure to these absolute maximum ratings for extended periods (t > 10 s) may affect device reliability. Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Data Sheet 4 Rev. 1.1, 2005-07-30 TLE 7274 Table 3 Operating Range Parameter Symbol Input voltage Junction temperature Limit Values VI Tj Unit Remarks Min. Max. 5.5 42 V – -40 150 °C – Note: In the operating range, the functions given in the circuit description are fulfilled. Table 4 Thermal Resistance Parameter Junction case Junction ambient Rthj-c Rthj-a Rthj-a Limit Values Unit Remarks Min. Max. – 8 K/W – – 80 K/W TO2521) K/W TO2632) Worst case, regarding peak temperature; zero airflow; mounted on a PCB FR4, 80 × 80 × 1.5 mm3, heat sink Junction ambient 1) Symbol – 55 area 300 mm2 2) Worst case, regarding peak temperature; zero airflow; mounted on a PCB FR4, 80 area 300 mm2 × 80 × 1.5 mm3, heat sink The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at Ta = 25 °C and the given supply voltage. Data Sheet 5 Rev. 1.1, 2005-07-30 TLE 7274 Table 1 Electrical Characteristics VI = 13.5 V; – 40 °C < Tj < 150 °C (unless otherwise specified) Parameter Symbol Limit Values Min. Typ. Max. Unit Measuring Condition Output Q Output voltage VQ 4.9 5.0 5.1 V 0.1 mA < IQ < 300 mA; 6 V < VI < 16 V Output voltage VQ 4.9 5.0 5.1 V 0.1 mA < IQ < 100 mA; 6 V < VI < 40 V Output current limitation IQ 320 – – mA 1) Output current limitation IQ – – 800 mA Current consumption; Iq = II - IQ Iq – 20 25 µA Current consumption; Iq = II - IQ Iq – – 35 µA Drop voltage Vdr – 250 500 mV Load regulation ∆VQ, lo -40 15 40 mV Line regulation ∆VQ, li -20 5 20 mV Power supply ripple rejection PSRR – 60 – dB VQ = 0V IQ = 0.1 mA; Tj = 25 °C IQ = 0.1 mA; Tj ≤ 80 °C IQ = 200 mA; Vdr = VI - VQ1) IQ = 5 mA to 250 mA Vl = 10V to 32 V; IQ = 5 mA fr = 100 Hz; Vr = 0.5 Vpp Temperature output voltage drift dVQ/dT – 0.5 – mV/K – Output Capacitor CQ 470 – – nF ESR < 3 Ω 1) Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5 V. Data Sheet 6 Rev. 1.1, 2005-07-30 TLE 7274 Application Information VBat TLE 7274 VCC Q 3 1 I 100 nF 470 + nF Overtemperature Shutdown Bandgap Reference 4.7 µF 1 Charge Pump 2, Tab GND Figure 3 AEA03614.VSD Application Diagram Input, Output An input capacitor is necessary for damping line influences. A resistor of approx. 1 Ω in series with CI, can damp the LC of the input inductivity and the input capacitor. In contrast to most low drop voltage regulators the TLE 7274 only needs moderate capacitance at the output to assure stability of the regulation loop. This offers more design flexibility to the circuit designer providing for cost efficient solutions. The TLE 7274 requires a ceramic output capacitor of at least 470 nF. In order to damp influences resulting from load current surges it is recommended to add an additional electrolytic capacitor of 4.7 µF to 47 µF at the output as shown in Figure 3. Data Sheet 7 Rev. 1.1, 2005-07-30 TLE 7274 Additionally a buffer capacitor CB of > 10µF should be used for the output to suppress influences from load surges to the voltage levels. This one can either be an aluminum electrolytic capacitor or a tantalum capacitor following the application requirements. A general recommendation is to keep the drop over the equivalent serial resistor (ESR) together with the discharge of the blocking capacitor below the allowed Headroom of the Application to be supplied (e.g. typ. dVQ = 350mV). Since the regulator output current roughly rises linearly with time the discharge of the capacitor can be calculated as follows: dVCB = dIQ*dt/CB The drop across the ESR calculates as: dVESR = dI*ESR To prevent a reset the following relationship must be fullfilled: dVC + dVESR < VRH = 350mV Example: Assuming a load current change of CB = 100mA, a blocking capacitor of dIQ = 22µF and a typical regulator reaction time under normal operating conditions of dt ~ 25µs and for special dynamic load conditions, such as load step from very low base load, a reaction time of dt ~ 75µs.. dVC = dIQ*dt/CB = 100mA * 25µs/22µF = 113mV So for the ESR we can allow dVESR = VRH2 - dVC = 350mV - 113mV = 236mV The permissible ESR becomes: ESR = dVESR / dIQ = 236mV/100mA = 2.36Ohm During design-in of the TLE7469 product family, special care needs to be taken with regards to the regulators reaction time to sudden load current changes starting from very low pre-load as well as cyclic load changes. The application note “TLE7x Voltage Regulators - Application Note about Transient Response at ultra low quiescent current Voltage Regulators” (see 3_cip05405.pdf) gives important hints for successful design-in of the Voltage Regulators of the TLE7x family. Data Sheet 8 Rev. 1.1, 2005-07-30 TLE 7274 Typical Performance Characteristics Current Consumption Iq versus Junction Temperature Tj Current Consumption Iq versus Input Voltage VI 1 _ I q - T j. v s d 3 _ IQ -V I.V S D Iq [µ A ] T j = 2 5 °C I q [µ A ] V I = 1 3 .5 V 100 40 IQ = 1 0 0 µ A IQ = 5 0 m A 10 30 IQ = 1 0 m A IQ = 0 .2 m A 20 1 10 0 .0 1 -4 0 -2 0 0 20 40 60 0 80 100 120 140 20 10 30 V I [V ] T j [° C ] Current Consumption Iq versus Output Current IQ Output Voltage VQ versus Junction Temperature Tj 5 A _ V Q -T J .V S D 2 _ IQ - IQ .V S D 30 I q [µ A ] 40 V I = 1 3 .5 V V Q [V ] V I = 1 3 .5 V T j = 2 5 °C T j = -4 0 °C 20 5 .0 5 15 5 .0 0 10 4 .9 5 5 4 .9 0 0 20 40 60 -4 0 -2 0 100 I Q [m A ] Data Sheet IQ = 1 0 0 µ A ...1 0 0 m A 0 20 40 60 80 100 120 140 T j [° C ] 9 Rev. 1.1, 2005-07-30 TLE 7274 Dropout Voltage Vdr versus Output Current IQ Maximum Output Current IQ versus Junction Temperature Tj 6 _ V D R -IQ .V S D 600 8 _ IQ M A X - T J .V S D 620 V d r [m V ] V I = 1 3 .5 V I Q [m A ] T j = 1 5 0 °C 400 580 T j = 2 5 °C 300 560 540 200 T j = -4 0 °C 520 100 100 0 200 500 -4 0 -2 0 300 0 20 40 60 80 100 120 140 T j [° C ] I Q [m A ] Dropout Voltage Vdr versus Junction Temperature Tj Maximum Output Current IQ versus Input Voltage VI 7 _ V D R -T J .V S D 600 9 _ S O A .V S D 600 T j = 1 2 5 °C I Q [m A ] V d r [m V ] I Q lim T j = 2 5 °C IQ = 2 5 0 m A 400 400 300 300 IQ = 1 5 0 m A 200 200 P v m a x = 1 ,1 8 W f o r T O 2 5 2 @ 3 0 0 m m 2 c o o lin g a re a 100 100 IQ = 1 0 m A -4 0 -2 0 0 20 40 60 80 100 120 140 0 T j [° C ] Data Sheet 10 20 30 40 V I [V ] 10 Rev. 1.1, 2005-07-30 TLE 7274 Region of Stability Output Voltage VQ Start-up behaviour 1 4 _ V It im e _ s t a r t u p . v s d 1 2 _ E S R -IQ .V S D 100 C Q = 1 0 n F ...1 0 µ F T j = 2 5 °C E SR CQ [Ω] V Q [V ] IN H = O N 10 5 .0 5 1 IQ = 5 m A 5 .0 0 S t a b le R e g io n 4 .9 0 0 .1 4 .8 0 0 .0 1 0 50 100 150 200 2 1 3 t [m s ] Power Supply Ripple Rejection PSRR versus Frequency f Load Regulation dVQ versus Output Current Change dIQ 1 3 _ P S R R .V S D 80 5 4 I Q [m A ] 1 8 a _ d V Q - d I Q _ V i6 V . v s d 0 VI = 6V ∆VQ PSRR [m V ] [d B ] I Q = 0 .1 m A 60 -1 0 IQ = 3 0 m A T j = -4 0 °C IQ = 1 0 0 m A -1 5 50 T j = 2 5 °C -2 0 40 V R IP P L E = 1 V V IN = 1 3 . 5 V C Q = 1 0 µ F T a n t a lu m T j = 2 5 °C 30 10 100 1k 10k -3 0 100k 0 50 100 150 250 IQ [m A ] f [H z ] Data Sheet T j = 1 5 0 °C -2 5 11 Rev. 1.1, 2005-07-30 TLE 7274 Load Regulation dVQ versus Output Current Change dIQ Line Regulation dVQ versus Input Voltage ChangedVI 1 8 b _ d V Q - d I Q _ V i1 3 5 V . v s d 0 V I = 1 3 .5 V ∆VQ 1 9 _ d V Q -d V I_ _ 1 5 0 C .v s d 0 ∆VQ [m V ] IQ = 1 m A [m V ] -1 0 T j = 1 5 0 °C IQ = 1 0 0 m A IQ = 1 0 m A -2 -1 5 -3 T j = -4 0 °C T j = 2 5 °C -2 0 -4 -2 5 -5 IQ = 2 0 0 m A T j = 1 5 0 °C -3 0 0 50 100 150 -6 250 0 5 10 15 20 25 30 35 40 IQ [m A ] V I [V ] Load Regulation dVQ versus Output Current Change dIQ Line Regulation dVQ versus Input Voltage ChangedVI 1 8 c _ d V Q - d I Q _ V i2 8 V . v s d 0 1 9 _ d V Q -d V I_ 2 5 C .v s d 0 VI = 28 ∆VQ 45 T j = 2 5 °C ∆VQ [m V ] [m V ] IQ = 1 m A -2 -1 0 IQ = 1 0 m A IQ = 1 0 0 m A IQ = 2 0 0 m A -3 -1 5 T j = -4 0 °C -2 0 -4 T j = 2 5 °C -2 5 -5 T j = 1 5 0 °C -3 0 0 50 100 150 -6 250 IQ [m A ] Data Sheet 0 5 10 15 20 25 30 35 40 45 V I [V ] 12 Rev. 1.1, 2005-07-30 TLE 7274 Line Regulation dVQ versus Input Voltage ChangedVI Load Transient Response Peak Voltage dVQ 1 9 _ d V Q -d V I_ -4 0 C .v s d 0 T j = 4 0 °C ∆VQ 2 0 _ L o a d T r a n c ie n t v s tim e 2 5 .v s d [m V ] IQ 1 :1 0 0 m A T j= 2 5 ° C V i = 1 3 .5 V IQ = 1 m A -2 IQ = 1 0 m A IQ = 1 0 0 m A -3 IQ = 2 0 0 m A -4 VQ -5 -6 0 10 5 15 20 25 30 35 40 T = 4 0 µ s/D IV 45 V Q = 1 0 0 m V /D IV V I [V ] Load Transient Response Peak Voltage dVQ Line Transient Response Peak Voltage dVQ 2 0 _ L o a d T r a n c ie n t v s tim e 1 2 5 .v s d IQ 1 :1 0 0 m A 2 1 _ L in e T r a n c ie n t v s tim e 2 5 .v s d T j= 1 2 5 ° C V i = 1 3 .5 V dVI 2V T j= 2 5 ° C V i = 1 3 .5 V VQ VQ T = 4 0 µ s/D IV Data Sheet V Q = 1 0 0 m V /D IV T = 4 0 0 µ s /D IV 13 V Q = 5 0 m V /D IV Rev. 1.1, 2005-07-30 TLE 7274 Line Transient Response Peak Voltage dVQ 2 1 _ L in e T r a n c ie n t v s tim e 1 2 5 .v s d dVI 2V T j= 1 2 5 ° C V i = 1 3 .5 V VQ T = 4 0 0 µ s /D IV Data Sheet V Q = 5 0 m V /D IV 14 Rev. 1.1, 2005-07-30 TLE 7274 Package Outlines 6.5 +0.15 -0.10 2.3 +0.05 -0.10 4.57 0.51 min 0.15 max per side 0.9 +0.08 -0.04 B 5.4 ±0.1 0.8 ±0.15 9.9 ±0.5 6.22 -0.2 1 ±0.1 A 3x 0.75 ±0.1 0...0.15 0.5 +0.08 -0.04 2.28 1 ±0.1 0.25 M A B 0.1 GPT09051 All metal surfaces tin plated, except area of cut. Figure 4 Data Sheet P-TO252-3-1 (Plastic Transistor Single Outline) 15 Rev. 1.1, 2005-07-30 TLE 7274 6.5 +0.15 -0.05 A B (5) 0.5 +0.08 -0.04 0.9 +0.20 -0.01 0...0.15 0.51 min. 0.15 max. per side 2.3 +0.05 -0.10 0.8 ±0.15 (4.24) 1 ±0.1 9.98 ±0.5 6.22 -0.2 5.4 ±0.1 3x 0.75 ±0.1 0.5 +0.08 -0.04 2.28 4.57 0.1 B 0.25 M A B All metal surfaces tin plated, except area of cut. GPT09277 Figure 5 P-TO252-3-11 (Plastic Transistor Single Outline) 2.2 6.4 10.6 5.8 1.2 5.76 Figure 6 Data Sheet Foot Print for P-TO-252-3-1 and P-TO-252-3-11 (Plastic Transistor Single Outline) 16 Rev. 1.1, 2005-07-30 TLE 7274 4.4 10 ±0.2 1.27 ±0.1 B 0.1 A 8.5 1) 0.05 2.4 2.7 ±0.3 4.7 ±0.5 7.55 1) (15) 9.25 ±0.2 1 ±0.3 0...0.3 0...0.15 0.75 ±0.1 0.5 ±0.1 1.05 8 ˚ MAX. 2.54 5.08 1) Figure 7 0.25 M A B 0.1 B Typical All metal surfaces: tin plated, except area of cut. Metal surface min. x=7.25, y=6.9 P-TO263-3-1 (Plastic Transistor Single Outline) 4.6 16.15 9.4 10.8 1.39 1.15 6.23 Figure 8 Foot Print for P-TO263-3-1 (Plastic Transistor Single Outline) You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet 17 Dimensions in mm Rev. 1.1, 2005-07-30 TLE 7274 Remarks Data Sheet 18 Rev. 1.1, 2005-07-30 Edition 2005-07-30 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany © Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.