UT54ACTS220

Standard Products
UT54ACTS220
Clock and Wait-State Generation Circuit
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
‰ 1.2μ CMOS
- Latchup immune
‰ High speed
‰ Low power consumption
‰ Single 5 volt supply
‰ Available QML Q or V processes
‰ Flexible package
- 14-pin DIP
- 14-lead flatpack
‰ UT54ACTS220 - SMD 5962-96753
PINOUTS
14-Pin DIP
Top View
NC
1
14
VDD
CLKOUT
2
13
24MHz
CLKOUT
3
12
CLKIN
NC
4
11
DTACK
TEST
5
10
MRST
48MHz
VSS
6
9
7
8
RCS
DMACK
DESCRIPTION
The UT54ACTS220 is designed to be a companion chip to
UTMC’s UT69151 SμMMIT family for the purpose of generating clock and wait-state signals. The device contains a divide
by two circuit that accepts TTL input levels and drives CMOS
output buffers. The chip accepts a 48MHz clock and generates
a 24MHz clock. The 48MHz clock can have a duty cycle that
varies by ± 20%. The UT54ACT220 generates a 24MHz clock
with a ± 5% duty cycle variation. The wait-state circuit generates
a single wait-state by delaying the falling edge of DTACK into
the SμMMIT. The clock/timing device generates DTACK from
the falling edge of input RCS which is synchronized by the falling edge of 24MHz. The SμMMIT drives inputs RCS and
DMACK.
14-Lead Flatpack
Top View
The devices are characterized over full military temperature
range of -55°C to +125°C.
LOGIC SYMBOL
MRST
48MHz
RCS
DMACK
(10)
S
(6)
(9)
(8)
CTR1
(13)
SRG2
1D
(12)
DTACK
S
(11)
(2)
CLKIN
24MHz
(4)
(3)
TEST
CLKOUT
CLKOUT
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
1
NC
1
14
VDD
CLKOUT
2
13
24MHz
CLKOUT
3
12
CLKIN
NC
4
11
DTACK
TEST
5
10
MRST
48MHz
VSS
6
9
7
8
RCS
DMACK
PIN DESCRIPTION
Pin Number
Pin Name
Description
2
CLKOUT
Buffered version of CLKIN.
3
CLKOUT
Inverted version of CLKIN.
4
CLKIN
Clock Input. This signal can be any arbitrary signal that the user wishes to buffer.
6
48MHz
48MHz Clock. The 24MHz clock is created by dividing this signal by two.
8
DMACK
9
RCS
10
MRST
Master Reset. This input can be used to preset 24MHz, DTACK and TEST. For normal
operation tie MRST to VDD through a resistor.
11
TEST
Test output signal.
12
DTACK
Data Transfer Acknowledge. This signal can be used to drive the DTACK signal of the
SμMMIT if the user requires one wait state during the memory transfer.
13
24MHz
24MHz Clock. This output runs at half the frequency of the 48MHz input. The falling
edge of 24MHz is the signal that latches the DTACK outputs. 24MHz is forced high
whenever MRST is low. Properly loaded, 24MHz will have a 50% duty cycle ± 5%.
DMA Acknowledge. This input is generated by the SμMMIT. When high, this signal will
cause DTACK output to be forced high.
RAM Chip Select. This input is generated by the SμMMIT.
FUNCTIONAL TIMING: Single SμMMIT Wait-State
For both read and write memory cycles, DTACK is an input to the SμMMIT E and SμMMIT LXE/DXE. A non-wait state memory
requires two clock cycles, T1 and T2 of figure 1. For accessing slower memory devices, the UT54ACTS220 holds DTACK to a logical “1”. This results in the stretching of memory cycles by one clock to three clock cycles, TW of figure 1. The SμMMIT E and
SμMMIT LXE/DXE samples the DTACK on the rising edge of the 24 MHz clock. If DTACK is not generated before the rising
edge of the clock, the SμMMIT E and SμMMIT LXE/DXE extends the memory cycle.
48MHz
24MHz
TW
T1
DMACK
RCS
DTACK
Figure 1. Functional Timing
2
T2
LOGIC DIAGRAM
24MHz
D
48MHz
Q
D
CK Q
RST
DTACK
Q
CK Q
PRE
MRST
D
Q
TEST
CK
RCS
Q
PRE
DMACK
CLKIN
CLKOUT
CLKOUT
3
OPERATIONAL ENVIRONMENT
PARAMETER
LIMIT
UNITS
Total Dose
1.0E6
rad(Si)
SEU Threshold 1
80
MeV-cm2/mg
SEL Threshold
>120
MeV-cm2/mg
Neutron Fluence2
1.0E14
n/cm2
Notes:
1. Device storage elements are immune to SEU affects.
2. Not tested, inherent of CMOS technology.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
-0.3 to 7.0
V
VI/O
Voltage any pin
-0.3 to VDD +0.3
V
TSTG
Storage Temperature range
-65 to +150
°C
TJ
Maximum junction temperature
+175
°C
TLS
Lead temperature (soldering 5 seconds)
+300
°C
ΘJC
Thermal resistance junction to case
20
°C/W
II
DC input current
±10
mA
PD
Maximum power dissipation
1
W
Note:
1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
4.5 to 5.5
V
VIN
Input voltage any pin
0 to VDD
V
TC
Temperature range
-55 to + 125
°C
48MHz
Duty Cycle
50 ± 20%
MHz
4
DC ELECTRICAL CHARACTERISTICS 7
(VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
PARAMETER
CONDITION
VIL
Low-level input voltage 1
TTL
VIH
High-level input voltage 1
TTL
IIN
Input leakage current
TTL
VDD = 5.5V
VIN = VDD or VSS
Low-level output voltage 3
Except CLKOUT/CLKOUT
IOL = 8mA, VDD = 4.5V
IOL = 100μA
High-level output voltage 3
IOH = -8mA, VDD = 4.5V
VOL1
VOH1
MIN
MAX
UNIT
0.8
V
2.25
-1
V
1
μA
0.4
0.25
V
3.15
V
Except CLKOUT/CLKOUT
VOL2
CLKOUT/CLKOUT Low-level output
voltage 3
IOL = 100μA
VOH2
CLKOUT/CLKOUT High-level output
voltage 3
IOH = -100μA
Short-circuit output current 2 ,4
VO = VDD and VSS
IOS
0.25
V
4.25
V
+300
mA
VDD = 5.5V
IOL1
IOH1
IOL2
IOH2
IIH
Output current10
VIN = VDD or VSS
(Sink), Except CLKOUT/CLKOUT
VOL = 0.4V
Output current10
VIN = VDD or VSS
(Source), Except CLKOUT/CLKOUT
VOH = VDD - 0.4V
CLKOUT/CLKOUT output current10
VIN = VDD or VSS
(Sink)
VOL = 0.4V
CLKOUT/CLKOUT output current10
VIN = VDD or VSS
(Source)
VOH = VDD - 0.4V
Input current high
VIN = VDD or VSS
8
mA
-8
mA
12
mA
-12
mA
+1.0
μA
-1.0
μA
VIN = 5.5V
IIL
Input current low
VIN = VDD or VSS
VIN = VSS
Ptotal
Power dissipation 2, 8, 9
CL = 50pF
1.0
mW/
MHz
IDDQ
Quiescent Supply Current
VDD = 5.5V
10
μA
VIN = VDD or VSS
5
SYMBOL
ΔIDDQ
PARAMETER
Quiescent Supply Current Delta
CONDITION
For input under test
MIN
MAX
UNIT
1.6
mA
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
CIN
COUT
Input capacitance 5
ƒ = 1MHz @ 0V
15
pF
Output capacitance 5
ƒ = 1MHz @ 0V
15
pF
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
6
AC ELECTRICAL DIAGRAM
48MHz
24MHz
RCS
T1
TW
TW
tSUR
DTACK
tH
tSU
CLKIN
CLKOUT
or
CLKOUT
tPHL or tPLH
7
T2
AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
tPHL1
48MHz ↑ to 24MHz ↓
0
15
ns
tPLH1
48MHz ↑ to 24MHz ↑
0
15
ns
tPHL2
24MHz ↓ to DTACK ↓
0
7
ns
tPLH2
24MHz ↓ to DTACK ↑
0
6
ns
tPLH3
DMACK ↑ to DTACK ↑
3
16
ns
tPLH4
MRST ↓ to 24MHz ↑, DTACK ↑
3
16
ns
tPHL5
CLKIN ↓ to CLKOUT ↓
0
11
ns
tPLH5
CLKIN ↑ to CLKOUT ↑
0
11
ns
tPHL6
CLKIN ↑ to CLKOUT ↓
0
11
ns
tPLH6
CLKIN ↓ to CLKOUT ↑
0
11
ns
tSU3
DTACK ↓ to 24MHz ↑, setup time
12
ns
tH3
24MHz ↑ to DTACK ↑, hold time
20
ns
tSUR
Setup time from RCS ↓ to 24MHz ↓
7
ns
tWM
MRST pulse width low
5
ns
tWC
CLKIN pulse width
12
ns
fMAX
Maximum CLKIN frequency
40
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose ≤ 1E6 rads(Si).
3. Guaranteed by design but not tested.
8
MHz
PACKAGING
Side-Brazed Packages
9
FLATPACK PACKAGES
10
UT54ACTS220: SMD
5962 * ***** ** * * *
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
Package Type:
X = 14-lead ceramic bottom-brazed dual-in-line Flatpack
C = 14-lead ceramic side-brazed dip
Class Designator:
Q = QML Class Q
V = QML Class V
Device Type:
01
Drawing Number:
96753 = UT54ACTS220
Total Dose: (Notes 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory.
4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019
Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in
accordance with MIL-STD-883 Test Method 1019 Condition A.
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