UT54ACS899 - Aeroflex Microelectronic Solutions

Standard Products
UT54ACTS899
9-bit Latchable Transceiver with Parity Generator/Checker
Datasheet
May 16, 2012
www.aeroflex.com/Logic
FEATURES
PIN DESCRIPTION
 Latchable transceiver with output source/sink of 24mA
 Option to select generate parity and check or "feed-through"
data/parity in directions A-to-B or B-to-A
 Independent latch enable for A-to-B and B-to-A directions
 Select pin for ODD/EVEN parity
 ERRA and ERRB output pins for parity checking
 Ability to simultaneously generate and check parity
 m Commercial CMOS
 Operational environment:
- Total dose: 100K rad(Si)
- Single Event Latchup immune
- SEU immune
 Standard Microcircuit Drawing 5962-06240
- QML compliant part
 Package:
- 28-pin ceramic flatpack
Inputs
A0-A7
B0-B7
APAR, BPAR
ODD/EVEN
GBA, GAB
SEL
LEA, LEB
ERRA, ERRB
Outputs
A Bus Data Inputs/Data Outputs
B Bus Data Inputs/Data Outputs
A and B Bus Parity Inputs
ODD/EVEN Parity Select, Active LOW for
EVEN Parity
Output Enables for A or B Bus, Active Low
Select Pin for Feed-through or Generate
Mode, LOW for Generate Mode
Latch Enables for A and B Latches, HIGH
for Transparent Mode
Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs
28-Lead Flatpack
Pinout
DESCRIPTION
The UT54ACTS899 is a 9-bit to 9-bit parity transceiver with
ODD/EVEN
1
28
ERRA
2
27
GAB
transceiver or it can generate/check parity from the 8-bit data
LEA
3
26
busses in either direction. The UT54ACTS899 features inde-
A0
A1
4
5
25
24
B0
B1
A2
6
23
B3
A3
7
22
B4
A4
A5
A6
8
9
10
21
20
19
B5
B6
B7
transparent latches. The device can operate as a feed-through
pendent latch enables for the A-to-B direction and the B-to-A
direction, a select pin for ODD/EVEN parity, and separate
error signal output pins for checking parity.
1
VDD
B2
A7
11
18
BPAR
APAR
12
17
LEB
GBA
13
16
SEL
VSS
14
15
ERRB
LOGIC DIAGRAM
OE
9-bit
Transparent
Latch
LEA
(3)
A0
A1
A2
(4)
(5)
(6)
(27) GAB
9-bit
Output
Buffer
LE
Parity
Generator
(26)
1
mux
0
(25)
(24)
(23)
A3 (7)
A4 (8)
A5 (9)
A6 (10)
A7 (11)
APAR (12)
B2
(22)
B3
B4
(21)
(20)
B5
B6
(19)
B7
(18) BPAR
9-bit
Transparent
Latch
9-bit
Output
Buffer
GBA (13)
B0
B1
(17)
OE
LEB
LE
1
mux
0
Parity
Generator
SEL (16)
(2) ERRA
(15) ERRB
ODD/EVEN (1)
2
FUNCTIONAL DESCRIPTION
The UT54ACTS899 has three principal modes of operation
which are outlined below. These modes apply to both A-to-B
and B-to-A directions.
- Bus A (B) communicates to Bus B (A) in a feed-through mode
if SEL is HIGH. Parity is still generated and checked as
ERRA and ERRB in the feed-through mode (can be used as
an interrupt to signal a data/parity bit error to the CPU).
- Bus A (B) communicates to Bus B (A), parity is generated
and passed on to the B (A) Bus as BPAR (APAR). If LEB
(LEA) is HIGH and the Mode Select (SEL) is LOW, the parity
generated from B[0:7] (A[0:7]) can be checked and monitored by ERRB (ERRA).
- Independent Latch Enables (LEA and LEB) allow other permutations of generating/checking. (see Function Table below)
FUNCTIONAL TABLE
INPUTS
GAB
OPERATION
GBA
SEL
LEA
LEB
H
H
X
X
X
Busses A and B are Tri-State (input A & B simultaneously)
H
L
L
L
H
Generates parity from B[0:7] based on O/E (Note 1). Generated parity --> APAR.
Generated parity checked against BPAR and output as ERRB.
H
L
L
H
H
Generates parity from B[0:7] based on O/E. Generated parity --> APAR.
Generated parity checked against BPAR and output as ERRB.
Generated parity also fed back through the A latch for generate/check as ERRA.
H
L
L
X
L
Generates parity from B latch data based on O/E. Generated parity --> APAR.
Generated parity checked against latched BPAR and output as ERRB.
H
L
H
X
H
H
L
H
H
H
BPAR/B[0:7] --> APAR/A[0:7] Feed-through mode.
Generated parity checked against BPAR and output as ERRB.
BPAR/B[0:7] --> APAR/A[0:7] Feed-through mode.
Generated parity checked against BPAR and output as ERRB.
APAR/A[0:7] fed back through the A latch for generate/check as ERRA.
L
H
L
H
L
Generates parity from A[0:7] based on O/E. Generated parity --> BPAR.
Generated parity checked against APAR and output as ERRA.
L
H
L
H
H
Generates parity from A[0:7] based on O/E. Generated parity --> BPAR.
Generated parity checked against APAR and output as ERRA.
Generated parity also fed back through the B latch for generate/check as ERRB.
L
H
L
L
X
Generates parity from A latch data based on O/E. Generated parity --> BPAR.
Generated parity checked against latched APAR and output as ERRA.
L
H
H
H
L
L
H
H
H
H
APAR/A[0:7)]--> BPAR/B[0:7] Feed-through mode.
Generated parity checked against APAR and output as ERRA.
APAR/A[0:7] --> BPAR/B[0:7] Feed-through mode.
Generated parity checked against APAR and output as ERRA.
BPAR/B[0:7] fed back through the B latch for generate/check as ERRB.
L
L
X
X
X
Output to A bus and B bus (NOT ALLOWED).
H = High voltage level
L = Low voltage level
X = Do not care
Note 1: O/E = ODD/EVEN
3
RADIATION HARDNESS SPECIFICATIONS 1
PARAMETER
LIMIT
UNITS
Total Dose
1.0E5
rads(Si)
SEU Onset LET
>108
MeV-cm2/mg
SEL Immune
>108
MeV-cm2/mg
Neutron Fluence2
1.0E14
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Not tested, inherent of CMOS technology.
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
-0.3 to 6.0
V
VI/O
Voltage any pin during operation
-0.3 to VDD +0.3
V
TSTG
Storage Temperature range
-65 to +150
C
TJ
Maximum junction temperature
+175
C
JC
Thermal resistance junction to case
20
C/W
II
DC input current
+10
mA
PD
Maximum power dissipation

mW
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
4.5 to 5.5
V
VIN
Input voltage any pin
0 to VDD
V
TC
Temperature range
-55 to +125
oC
tINRISE
tINFALL
Maximum input rise or fall time
(VIN transitioning between VIL (max) and VIH (min))
20
ns
4
DC ELECTRICAL CHARACTERISTICS* 1
( VDD = 3.3 + 0.3V, TC = -55C to +125C); Unless otherwise noted, Tc is per the temperature ordered
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
0.8
V
VIL
Low level input voltage2
VDD from 4.5V to 5.5V
VIH
High level input voltage2
VDD from 4.5V to 5.5V
2.0
IIN
Input leakage current
VDD from 4.5 to 5.5
-1
1
A
-10
10
A
-600
600
mA
0.4
V
V
VIN = VDD or VSS
IOZ
Three-state output leakage current
VDD from 4.5 to 5.5
VIN = VDD or VSS
IOS
Short-circuit output current3, 4
VO = VDD or VSS
VDD from 4.5 to 5.5
VOL1
Low-level output voltage5
IOL= 24mA
-55C, +25oC
IOL= 24mA
+125oC
0.5
0.2
IOL= 100A
VIN = 2.0V or 0.8V
VDD = 4.5 to 5.5
VOL2
Low-level output voltage5, 6
-55C, +25oC
0.8
VDD = 5.5V
+125oC
1.0
IOH= -24mA
-55, +25oC
VDD - 0.64
IOH= -24mA
+125oC
VDD - 0.8
IOL= 50mA
V
VIN = 2.0V or 0.8V
VOH1
High-level output voltage5
IOH= -100A
V
VDD - 0.2
VIN = 2.0V or 0.8V
VDD = 4.5 to 5.5V
VOH2
High-level output voltage5, 6
IOH= -50mA
VIN = 2.0V or 0.8V
-55C, 25oC
+125oC
VDD -1.1
V
VDD -1.25
VDD = 5.5V
VIC+
Positive input clamp voltage
For input under test, IIN = +18mA
0.4
1.5
V
-1.5
-0.4
V
VDD = 0.0V
VIC-
Negative input clamp voltage
For input under test, IIN = -18mA
VDD = open
5
Ptotal
CL = 20pF
Power dissipation7, 8, 9
1.0
mW/
MHz
VDD from 4.5 to 5.5
IDDQ
VIN = VDD or VSS
Standby Supply Current VDD
VDD = 5.5
Pre-Rad 25 C
OE=VDD
10
A
Pre-Rad -55oC to +125oC
OE=VDD
160
A
Post-Rad 25oC
OE=VDD
Quiescent Supply Current Delta, TTL input level
For input under test
1.6
mA
21
pF
21
pF
o
IDDQ
o
o
o
VIN = VDD - 2.1V
Pre-Rad 25 C, Pre-Rad -55 C to +125 C
For other inputs
Post-Rad 25oC
VIN = VDD or VSS
VDD = 5.5V
CIN
Input capacitance 10
 = 1MHz @ 0V
VDD from 4.5 to 5.5
COUT
Output capacitance10
 = 1MHz @ 0V
VDD from 4.5 to 5.5
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25×C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. All specifications valid for radiation dose  1E5 rad(Si) per MIL-STD-883, Method 1019.
2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. Supplied as a design limit, but not guaranteed or tested.
5. Per MIL-PRF-38535, for current density  5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF-MHz.
6. Transmission driving tests are performed at VDD = 5.5V, only one output loaded at a time with a duration not to exceed 2ms. The test is guaranteed, if not tested,
for VIN=VIH minimum or VIL maximum.
7. Power dissipation specified per switching output.
8. Guaranteed by characterization.
9. Power does not include power contribution of any CMOS output sink current.
10. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6
AC ELECTRICAL CHARACTERISTICS 1
(VDD = 3.3 + 0.3V, TC = -55C to +125C); Unless otherwise noted, Tc is per the temperature ordered)
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
tPHL1
Propagation Delay - An, Bn to Bn, An
4.0
11.5
ns
tPLH1
Propagation Delay - An, Bn to Bn, An
4.0
11.5
ns
tPHL2
Propagation Delay - APAR, BPAR to BPAR, APAR
4.0
11.5
ns
tPLH2
Propagation Delay - APAR, BPAR to BPAR, APAR
4.0
11.5
ns
tPHL3
Propagation Delay - An, Bn to BPAR, APAR
5.0
12.0
ns
tPLH3
Propagation Delay - An, Bn to BPAR, APAR
5.0
12.0
ns
tPHL4
Propagation Delay - An, Bn to ERRA, ERRB
5.0
12.0
ns
tPLH4
Propagation Delay - An, Bn to ERRA, ERRB
5.0
12.0
ns
tPHL5
Propagation Delay - ODD/EVEN to ERRA, ERRB
4.0
9.0
ns
tPLH5
Propagation Delay - ODD/EVEN to ERRA, ERRB
4.0
9.0
ns
tPHL6
Propagation Delay - ODD/EVEN to APAR, BPAR
4.0
9.0
ns
tPLH6
Propagation Delay - ODD/EVEN to APAR, BPAR
4.0
9.0
ns
tPHL7
Propagation Delay - APAR, BPAR to ERRA, ERRB
4.0
9.0
ns
tPLH7
Propagation Delay - APAR, BPAR to ERRA, ERRB
4.0
9.0
ns
tPHL8
Propagation Delay - SEL to APAR, BPAR
3.5
8.5
ns
tPLH8
Propagation Delay - SEL to APAR, BPAR
3.5
8.5
ns
tPHL9
Propagation Delay - LEA, LEB to Bn, An
3.5
8.5
ns
tPLH9
Propagation Delay - LEA, LEB to An, Bn
3.5
8.5
ns
tPHL10
Propagation Delay - LEA, LEB to BPAR, APAR
4.0
9.0
ns
tPLH10
Propagation Delay - LEA, LEB to APAR, BPAR
4.0
9.0
ns
tPHL11
Propagation Delay - LEA, LEB to ERRA, ERRB
5.0
12.0
ns
tPLH11
Propagation Delay - LEA, LEB to ERRA, ERRB
5.0
12.0
ns
tPZH1
Output Enable Time - GBA or GAB to An, Bn
3.5
9.5
ns
7
tPZL1
Output Enable Time - GBA or GAB to An, Bn
3.5
9.5
ns
tPZH2
Output Enable Time - GBA or GAB to BPAR or APAR
3.5
9.5
ns
tPZL2
Output Enable Time - GBA or GAB to BPAR or APAR
3.5
9.5
ns
tPHZ1
Output Disable Time - GBA or GAB to An, Bn
2.0
6.0
ns
tPLZ1
Output Disable Time - GBA or GAB to An, Bn
2.0
6.0
ns
tPHZ2
Output Disable Time - GBA or GAB to BPAR, to
APAR
2.0
6.0
ns
tPLZ2
Output Disable Time - GBA or GAB to BPAR, to
APAR
2.0
6.0
ns
tS
Setup Time, High or Low, An, Bn, APAR, BPAR to
LEA, LEB
1.0
ns
tH
Hold Time, High or Low, An, Bn, APAR, BPAR to
LEA, LEB
1.5
ns
t W2
Pulse Width for LEA, LEB
4.0
ns
fMAX2
Maximum clock frequency
80
MHz
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25×C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. All specifications valid for radiation >1E5 rads(Si) per MIL-STD-883, Method 1019.
2. Verified by functional test.
Test Load or Equivalent1
VDD
VDD
100ohms
40pF
100ohms
Notes
1. Equivalent test circuit means that DUT performance will be correlated and remain guaranteed to the applicable test circuit, above, whenever a test platform
change necessitates a deviation from the applicable test circuit.
8
AC TIMING DIAGRAMS
An, APAR
(Bn, BPAR)
VIM
VIM
tPLH1,2
tPHL1,2
+3.0V
INPUT
0V
VOH
Bn, BPAR
(An, APAR)
VOM
VOM
VOM
OUTPUT
VOL
Note:
1. VIM = 1.5V, VOM = VDD/2
2. SEL = 3.0V = H
Figure 1. Propagation Delay, An to Bn, Bn to An, APAR to BPAR, BPAR to APAR
An
(Bn)
ODD PARITY
VIM
EVEN PARITY
VIM
ODD PARITY
+3.0V
INPUT
0V
tPHL3
tPLH3
VOH
BPAR
(APAR)
VOM
VOM
OUTPUT
VOL
Note:
1. VIM = 1.5V, VOM = VDD/2
2. SEL = ODD/EVEN = VSS = L
3. LEA (LEB) = 3.0V = H
Figure 2. Propagation Delay, An to BPAR, or Bn to APAR (with Even Parity Mode Shown)
9
An
EVEN PARITY
(Bn)
VIM
VIM
ODD PARITY
EVEN PARITY
+3.0V
INPUT
0V
tPLH4
tPHL4
VOH
ERRA
VOM
VOM
(ERRB)
OUTPUT
VOL
Note:
1. VIM = 1.5V, VOM = VDD/2
2. APAR (BPAR) = ODD/EVEN = VSS = L
3. LEA (LEB) = 3.0V = H
Figure 3. Propagation Delay, An to ERRA or Bn to ERRB (with Even Parity Mode Shown)
An
(Bn)
ODD PARITY
+3.0V
INPUT
0V
+3.0V
ODD/EVEN
VIM
VIM
INPUT
0V
tPLH5
tPHL5
VOH
ERRA
VOM
(ERRB)
VOM
OUTPUT
VOL
Note:
1. VIM = 1.5V, VOM = VDD/2
2. APAR (BPAR) = VSS = L
Figure 4. Propagation Delay, ODD/EVEN to ERRA or ODD/EVEN to ERRB
10
An
(Bn)
EVEN PARITY
+3.0V
INPUT
0V
ODD/EVEN
VIM
+3.0V
INPUT
VIM
0V
tPLH6
tPHL6
VOH
BPAR
(APAR)
VOM
VOM
VOM
OUTPUT
VOL
Note:
1. VIM = 1.5V, VOM = VDD/2
2. SEL = APAR (BPAR) = VSS = L
Figure 5. Propagation Delay, ODD/EVEN to APAR or ODD/EVEN to BPAR (with Even Parity Mode Shown)
An
(Bn)
EVEN PARITY
+3.0V
INPUT
0V
+3.0V
APAR
(BPAR)
VIM
VIM
tPLH7
tPHL7
INPUT
0V
VOH
ERRA
(ERRB)
VOM
VOM
VOM
OUTPUT
VOL
Note:
1. VIM = 1.5V, VOM = VDD/2
2. ODD/EVEN = VSS = L
Figure 6. Propagation Delay, APAR to ERRA or BPAR to ERRB
(With Even Parity Mode Shown with Even Data Parity. Odd Parity Mode would cause Inverted Output.)
11
An
(Bn)
EVEN PARITY
+3.0V
INPUT
0V
0V
+3.0V
+3.0V
VIM
SEL
VIM
INPUT
0V
tPHL8
tPLH8
VOH
BPAR
VOM
VOM
(APAR)
OUTPUT
VOL
Note:
1. VIM = 1.5V, VOM = VDD/2
2. ODD/EVEN = 3.0V = H
3. APAR (BPAR) = VSS = L
Figure 7. Propagation Delay, SEL to BPAR or SEL to APAR
(With Odd Parity Mode Shown with Even Data Parity. Even Parity Mode would cause Inverted Output.)
+3.0V
APAR, An
(BPAR ,Bn)
INPUT
0V
+3.0V
LEA
(LEB)
VIM
VIM
INPUT
0V
tPLH9,10
tPHL9,10
VOH
Bn, BPAR
(An, APAR)
VOM
VOM
OUTPUT
VOL
Note:
1. VIM = 1.5V, VOM = VDD/2
2. SEL = 3.0V = H
Figure 8. Propagation Delay, LEA to BPAR or LEB to APAR, LEA to Bn or LEB to An
12
+3.0V
An
(Bn)
ODD PARITY
EVEN PARITY
ODD PARITY
INPUT
0V
+3.0V
LEA
(LEB)
VIM
VIM
INPUT
0V
tPHL11
tPLH11
VOH
ERRA
VOM
(ERRB)
VOM
OUTPUT
VOL
Note:
1. VIM = 1.5V, VOM = VDD/2
2. APAR (BPAR) = ODD/EVEN = 3.0V = H
Figure 9. Propagation Delay, LEA to ERRA or LEB to ERRB (with Odd Parity Mode Shown)
GBA
VIM
+3.0V
INPUT
VIM
0V
(GAB)
tPZH1,2
tPHZ1,2
VOH
An, APAR
(Bn, BPAR)
VOM+0.2V
VOM
0.8VDD-0.2V
OUTPUT
VOM
Note:
1. VIM = 1.5V, VOM = VDD/2
Figure 10. 3-State Output Enable Time to High Level and Output Disable Time from High Level
13
GBA
V IM
+3.0V
INPUT
0V
VIM
(GAB)
tPZL1,2
tPLZ1,2
VOM
VOM
An, APAR
(Bn, BPAR)
VOM - 0.2V
0.2VDD+0.2V
VOL
OUTPUT
Note:
1. VIM = 1.5V, VOM = VDD/2
Figure 11. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
APAR, An
BPAR ,Bn
+3.0V
VIM INPUT
VALID
0V
tS
tH
+3.0V
LEA, LEB
VIM
VIM
tw
Note:
1. VIM = 1.5V, VOM = VDD/2
Figure 12. Data Setup and Hold Times, Pulse Width High
14
VIM
INPUT
0V
Packaging
NOTE:
1. Seal ring is connected to VSS.
2. Units are in inches.
3. All exposed metalized areas must be gold plated 100 to 225 microinches thick and all bottom side exposed
metalized areas must be gold plated to 60 microinches thick nominal. Both sides shall be over electroplated
nickel undercoating 100 to 350 microinches per MIL-PRF-38535.
Figure 13. 28-pin Ceramic Flatpack
15
ORDERING INFORMATION
UT54ACTS899: SMD
5962 *
06240
**
*
*
*
Lead Finish: (Notes 1 & 2)
(A) = Solder
(C) = Gold
(X)= Factory Option (Gold or Solder)
Case Outline:
(X) = 28-Lead BB Ceramic Flatpack
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Device Types:
(01) = 9-bit latchable Transceiver with Parity Generator/Checker
Drawing Number: 06240
Total Dose: (Note 3)
(R) = 1E5 rads(Si)
Federal Stock Class Designator: No Options
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold).
3. Total dose radiation must be specified when ordering. QML-Q and QML-V are not available without radiation hardening. For prototyping inquiries, contact factory.
16
Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel
COLORADO
Toll Free: 800-645-8862
Fax: 719-594-8468
INTERNATIONAL
Tel: 805-778-9229
Fax: 805-778-1980
NORTHEAST
Tel: 603-888-3975
Fax: 603-888-4585
SE AND MID-ATLANTIC
Tel: 321-951-4164
Fax: 321-951-4254
WEST COAST
Tel: 949-362-2260
Fax: 949-362-2266
CENTRAL
Tel: 719-594-8017
Fax: 719-594-8468
www.aeroflex.com
[email protected]
Aeroflex Colorado Springs, Inc., reserves the right to make
changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
any responsibility or liability arising out of the application or
use of any product or service described herein, except as
expressly agreed to in writing by Aeroflex; nor does the
purchase, lease, or use of a product or service from Aeroflex
convey a license under any patent rights, copyrights,
trademark rights, or any other of the intellectual rights of
Aeroflex or of third parties.
Our passion for performance is defined by three
attributes represented by these three icons:
solution-minded, performance-driven and customer-focused
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