EVAL-ADAS3022EDZ User Guide UG-484 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluation Board for the ADAS3022 16-Bit, 8-Channel, 1 MSPS Data Acquisition System FEATURES Full-featured evaluation board for the ADAS3022 Versatile analog signal conditioning circuitry On-board reference, clock oscillator, and buffers Converter evaluation and development board (EVAL-CED1Z) compatible PC software for control and data analysis (time and frequency domain) KIT CONTENTS EVAL-ADAS3022EDZ evaluation board ADDITIONAL EQUIPMENT NEEDED EVAL-CED1Z board Precision signal source World-compatible 7 V dc supply (enclosed with EVAL-CED1Z) USB cable EVALUATION BOARD DESCRIPTION The EVAL-ADAS3022EDZ is an evaluation board for the ADAS3022 16-bit data acquisition system (DAS). This device integrates an 8-channel multiplexer, a high impedance programmable gain instrumentation amplifier (PGIA) stage with a high common-mode rejection, a precision 16-bit successive approximation (no latency) analog-to-digital converter and precision 4.096 V reference offering an aggregate throughput of 1 million samples per second (1 MSPS). The evaluation board is designed to demonstrate the performance of the ADAS3022 and to provide an easy-to-understand interface for a variety of system applications. A full description of this product is available in the data sheet and should be consulted when utilizing this evaluation board. The evaluation board is intended to be used with the Analog Devices, Inc., converter evaluation and development (CED) board, EVAL-CED1Z, a USB-based capture board connected to P4, the 96-pin interface. On-board components include a high precision, buffered band gap 4.096 V reference (ADR434), reference buffers (AD8032), passive signal conditioning circuitry, and an FPGA for deserializing the serial conversion results and configuring the ADAS3022 via a 4-wire serial interface. The P3 connector allows users to test their own interface with or without the optional Altera FPGA, U6 (programmed using the P2 and passive serial EEPROM, U5). FPGA PROGRAMMING PORT ADAS3022 PROTOTYPE AREA FPGA 96-PIN INTERFACE POWER SERIAL INTERFACE 40-PIN IDC Figure 1. EVAL-ADAS3022EDZ Evaluation Board Rev. A | Page 1 of 32 11064-001 ANALOG INPUTS UG-484 EVAL-ADAS3022EDZ User Guide TABLE OF CONTENTS Features .............................................................................................. 1 Jumpers and Test Points ...............................................................6 Kit Contents ...................................................................................... 1 Evaluation Board Software ...............................................................8 Additional Equipment Needed ....................................................... 1 Software Installation .....................................................................8 Evaluation Board Description......................................................... 1 Powering Up the Board ............................................................. 11 Revision History ............................................................................... 2 Running the Software with the Hardware Connected .......... 11 Evaluation Board Hardware ............................................................ 3 Software Operation .................................................................... 12 Overview........................................................................................ 3 Time Domain Tab ...................................................................... 15 Device Description ....................................................................... 3 Histogram Tab ............................................................................ 16 Jumpers, Solder Pads, and Test Points ....................................... 3 Spectrum Tab .............................................................................. 17 Analog Interface ........................................................................... 3 Summary Tab .............................................................................. 18 FPGA .............................................................................................. 4 Evaluation Board Schematics and Artwork ................................ 19 Reference ....................................................................................... 4 Products on this Evaluation Board .............................................. 27 Evaluation Board Schematics/PCB Layout ............................... 5 Bill of Materials ........................................................................... 27 Basic Hardware Setup .................................................................. 5 Related Links ................................................................................... 29 REVISION HISTORY 2/14—Rev. 0 to Rev. A Changes to Kit Contents Section .................................................... 1 Changes to Reference Section ......................................................... 4 Changes to Evaluation Board Schematics/PCB Layout Section. 5 Changes to Software Installation Section and Figure 4 through Figure 12; Renumbered Sequentially ............................................. 8 Changes to Running the Software with the Hardware Connected Section.......................................................................... 11 Changes to Software Operation Section and Figure 18; Added Figure 19 through Figure 27; Renumbered Sequentially .......... 12 Changes to Time Domain Tab Section and Figure 28 ............... 15 Changes to Histogram Tab Section and Figure 29 ..................... 16 Moved DC Testing Section and AC Testing Section ................. 16 Changes to Spectrum Tab Section and Figure 30 ...................... 17 Moved Summary Tab Section and Figure 31 .............................. 18 11/12—Revision 0: Initial Version Rev. A | Page 2 of 32 EVAL-ADAS3022EDZ User Guide UG-484 EVALUATION BOARD HARDWARE OVERVIEW The EVAL-ADAS3022EDZ evaluation board is designed to offer a simple evaluation of these revolutionary devices. From a block diagram perspective, the board uses a set of analog input test points (or an IDC header), some passive footprints for RC filtering and external reference, the ADAS3022 device, a serial interface to the on-board FPGA, and power that can be supplied locally or via EVAL-CED1Z or externally. Note that the ADAS3022 devices also have an on-chip reference; however, external circuitry is provided for users wanting to test other suitable options. The small prototyping area can be useful for building additional circuitry, if desired. Each block has a specific function as defined in the following sections. Table 1. Typical Input Range Selection Signals Differential ±1 V ±2.5 V ±5 V ±10 V Single Ended1 0 V to 1 V 0 V to 2.5 V 0 V to 5 V 0 V to 10 V 1 Input Range, VIN (V) ±1.28 V ±2.56 V ±10.24 V ±20.48 V ±0.64 V ±1.28 V ±2.56 V ±5.12 V VCM adjusted to half the maximum input voltage. DEVICE DESCRIPTION JUMPERS, SOLDER PADS, AND TEST POINTS The ADAS3022 is a complete data acquisition system (DAS) on a single chip that is capable of converting up to 1 MSPS and can resolve 8 single-ended inputs or 4 fully differential inputs up to ±24.576 V when using ±15 V supplies. It can accept the commonly used bipolar differential, bipolar single-ended, pseudo bipolar, or pseudo unipolar input signals as shown in Table 1 thus allowing the use of almost any direct sensor interface. Numerous solder pads and test points are provided on the evaluation board and are detailed fully in Table 4, Table 5, and Table 6. Note the nomenclature for this evaluation board for a signal that is also connected to an IDC connector would be signal_I. The two 3-pin user selectable jumpers are used for the ADCs reference selection and are fully described in the Reference section. The ADAS3022 is an ideal replacement for a typical 16-bit 1 MSPS precision data acquisition system that simplifies the design challenges by eliminating signal buffering, level shifting, amplification/attenuation, common-mode rejection, settling time, or any of the other analog signal conditioning challenges while allowing smaller form factor, faster time to market, and lower costs. ANALOG INTERFACE Data communication to and from the ADAS3022 occurs asynchronously without any pipeline delay using a common 4-wire serial interface compatible with SPI, FPGA, and DSP. A rising edge on CNV samples the differential analog inputs of a channel or channel pair. The ADAS3022 configuration register allows the user to configure the number of enabled channels, the differential input voltage range, and the interface mode using the evaluation board and software as detailed in this user guide. Complete specifications for the ADAS3022 are provided in the product data sheet and should be consulted in conjunction with this user guide when using the evaluation board. Full details on the EVAL-CED1Z are available on the Analog Devices website. The analog interface is provided with test points for each of the analog inputs IN[7:0] and COM (that is, IN0_I is common to both the test point and to P1). The passive device footprints can be used for filtering, if desired. A simple RC filter made up of 22 Ω and 2700 pF NPO capacitors is provided. Note that the use of stable dielectric capacitors, such as NPO or COG, is required in the analog signal path to preserve the ADAS3022 distortion. Using X5R or other capacitors in the analog signal path greatly reduces the performance of the system. Also, note that many bench top arbitrary waveform generators (AWGs) use 12-bit or 14-bit digital-to-analog converter outputs such that the 16-bit ADAS3022 devices digitize this directly resulting in erroneous looking data. If such an AWG is used, a high-order band-pass filter should be used to filter the unwanted noise from these sources. The ADAS3022 COM input can be routed to P1 or GND using P31. Set the jumper across Pin 1 and Pin 2 to route to P1. Set the jumper across Pin 2 to Pin 3 to GND COM. This is useful for single-ended applications. For dynamic performance, an FFT test can be done by applying a very low distortion ac source, such as an Audio Precision System 2702. This source can be set for balanced or unbalanced, and can be floated or grounded depending on the user’s choice. Rev. A | Page 3 of 32 UG-484 EVAL-ADAS3022EDZ User Guide FPGA External Reference–Factory Configuration The on-board FPGA performs a number of digital functions, one of them being the sample rate conversion controlled using the software. Another function is deserializing the serial conversion results as the CED data capture board uses a 16-bit parallel interface. If desired, the deserialized data can be monitored on the 96-pin edge connecter P1, BD[15:0]. The CED uses a buffered busy signal, BBUSY, as the general interrupt for the data transfer to the CED board. The evaluation board includes the ADR434, A1, which is a 4.096 V precision voltage reference. This reference can drive the ADC REF1 or REF2 (REFx) pin directly or it can also be buffered with U20, the AD8032; both of these are set to the factory default setting. The FPGA also provides the necessary ADAS3022 asynchronous control signals for RESET and power down (PD). The signals from the FPGA to the ADAS3022 can be bypassed by modifying the default solder pad connections. As shown in Figure 2, each digital signal on the ADAS3022 is connected to the larger (top) pad of the three. The default configuration is the small pad and larger pad (no text) which connects the FPGA to the ADAS3022 (CNV, BUSY, and SDO signals shown). The labeled pads, CNV_I, BUSY_I, SDO_I, and so on, are the signals that are routed to P3. To use P3 instead of the FPGA, unsolder the default connections and resolder from the large pad to the xxx_I pads. The FPGA will remain powered; however, if all the signals are bypassed in this fashion, it will not have any influence on the ADAS3022. DEFAULT 11064-003 CONNECTION TO P3 Table 2. Factory Reference Jumper Configuration Jumper Setting P5 P9 REFIN to GND1 REF to BUF (U20) 1 The connection is made through R102 = 10 k to GND. To use another reference source, there are two methods: • For an external unbuffered reference, remove the P9 jumper and connect a source to the REF test point. • Since the ADR434 is a standard 8-lead SOIC, it can also be removed and replaced with the user’s reference. In this case, the user reference and the U20 AD8032 buffer can be used as a reference source. Internal 4.096 V Reference The ADC has an internal 4.096 V precision reference and can be used on most applications. When enabled, 4.096 V will be present on the ADAS3022 REFx pin and test point, REF. In addition, a voltage will also be present on the ADAS3022 REFIN pin and test point, REFIN. The voltage present on REFIN can be used for other purposes, such as to provide the bias voltage; however, it would need a suitable buffer as the output impedance of the REFIN is on the order of a few kilo ohms and loading this voltage down will degrade the internal reference’s performance. Table 3. Internal Reference Jumper Configuration Figure 2. Digital Interface Solder Pads—Partial View Serial Interface The 4-wire serial interface consisting of CS, DIN, SCK, and SDO is present on the digital interface test points and is controlled by the FPGA. The FPGA can be bypassed by using the solder pads. Jumper Setting P5 P9 Open Open Note that the ADAS3022 configuration register needs to be updated either using the included software or by writing the appropriate bits to enable the internal reference. Internal Reference Buffer REFERENCE The ADAS3022 has an internal 4.096 V reference, along with an internal buffer, useful for using an external reference or one can use an external 4.096 V reference directly, such as the ADR434 provided on the evaluation board. The evaluation board can be configured to use any of these references. Two jumpers (P5 and P9) are used for setting the reference in conjunction with software control. The internal reference buffer is useful when using an external 2.5 V reference. When using the internal reference buffer, applying 2.5 V to REFIN, which is directly connected to the ADC’s REFIN pin, produces 4.096 V at the ADCs REFx pin and REF test point. Note that the ADAS3022 configuration register needs to be updated either using the included software or by writing the appropriate bits to enable the internal reference buffer. Rev. A | Page 4 of 32 EVAL-ADAS3022EDZ User Guide UG-484 POWER SUPPLIES AND GROUNDING The on-board ADP3334 low dropout regulators are provided for 2.5 V, 3.3 V, and 5 V and also for the FPGA I/O supply which is user configurable and set to 3.3 V by default. The FPGA core is supplied by a pair of ADP1715 devices set for 1.2 V. Additional power is supplies via the CED board for an alternative +5 V analog and digital 3.3 V/5 V digital through P4. The ADAS3022 device also requires ±15 V supplies for VDDH and VSSH. These must be supplied by the user using a standard lab supply ensuring that the return paths are at the same potential. Refer to CN-0201 for the complete information on generating these ±15 V supplies from a +5 V single supply. The differential input common-mode voltage (VCM) range changes according to the maximum input range selected and the high voltage power supplies (VDDH and VSSH). In other words, the specified operating input voltage of any input pin requires 2.5 V of headroom from the VDDH and VSSH supplies. The evaluation board ground plane consists of a solid plane on one PCB layer shared on another layer with the power plane. To attain high resolution performance, the board was designed to ensure that all digital ground return paths do not cross the analog ground return paths, that is, all analog on one side and digital on the other. EVALUATION BOARD SCHEMATICS/PCB LAYOUT of the ADAS3022 devices. The Evaluation Board Schematics and Artwork section of this user guide shows the schematics of the evaluation board. BASIC HARDWARE SETUP The ADAS3022 evaluation board connects to the EVAL-CED1Z converter evaluation and demonstration board. The EVALCED1Z board is the controller board, which is the communication link between the PC and the main evaluation board. Figure 3 shows a photograph of the connections made between the ADAS3022 daughter board and the EVAL-CED1Z board. 1. 2. 3. 4. The evaluation board is a 6-layer board carefully laid out and tested to demonstrate the specific high accuracy performance Before connecting power, ensure that the EVALADAS3022EDZ and the EVAL-CED1Z boards are connected firmly together. Connect the power supplies on the EVAL-ADAS3022EDZ board. The EVAL-ADAS3022EDZ requires external power supplies of ±15 V. Connect them from a bench top power supply. Connect the EVAL-CED1Z board to the PC via the USB cable enclosed in the EVAL-SDPCB1Z kit. If using a Windows® XP platform, you may need to search for the EVAL-CED1Z drivers. Choose to automatically search for the drivers for the EVAL-CED1Z board if prompted by the operating system. Proceed to the Software Installation section to install the software. Note that the EVAL-CED1Z board must not be connected to the PC’s USB port until the software is installed. The 7 V dc supply can be connected, however, to check that the board has power (green LED lit). EVAL-CED1Z PC EVAL-ADAS3022EDZ SIGNAL SOURCE USB 11064-002 TO WALL WART Figure 3. Hardware Configuration—Setting up the EVAL-ADAS3022EDZ Rev. A | Page 5 of 32 UG-484 EVAL-ADAS3022EDZ User Guide JUMPERS AND TEST POINTS Three-pin jumpers are used to configure the ADC reference. Refer to the Reference section for further details and settings. Table 4. Pin Jumper Descriptions Jumper P5 Default REFIN to GND P7 REF to BUF P31 COM to PIN 1 Function REFIN Select. Buffered reference input selection. Use in conjunction with P7. Note that the ADAS3022 REFx pin and any other circuit traces/test points will produce 4.096 V when using the buffered reference configuration; P7 must be left in the open position. REFIN to A2: Uses the on-board ADR381, A2 (2.5 V) reference. The ADAS3022 must use the buffered reference configuration. REFIN to GND: Disables the ADAS3022 internal reference. The ADAS3022 must use the full external reference configuration. Open: For use either when using the ADAS3022 on-chip reference or when applying an external 2.5 V source. When using the on chip reference, a voltage is present on Pin 2 and any other circuit traces/test points. When using an external source, the ADAS3022 must use the buffered reference configuration. REF Select. External 4.096 V reference input selection. Use in conjunction with P5. Note that the ADAS3022 REFIN pin and any other circuit traces/test points produce 2.5 V when using the internal or external reference configuration and P5 must be left in the open position. REF to A1: Uses the on-board ADR434, A1 (4.096 V), reference. The ADAS3022 must use the external reference configuration. REF to BUF: Uses the on-board ADR434 followed by the AD8032, U20 unity gain buffer. This allows some adjustment to the reference voltage by use of some resistors around the AD8032. The ADAS3022 must use the external reference configuration. Open: For use when using the ADAS3022 on-chip reference or an externally applied source connected directly to Pin 2 or the REF test point. COM Input Select. Center pin connected to ADAS3022 COM pin. Center pin to PIN1 routes COM to P1. Center to PIN3 routes COM to GND. Solder pads jumpers are factory configured and can be changed by the user. Table 5. Analog and Digital Solder Pads Descriptions Jumper P9 P16 P17 P18 P19 P27 P28 P29 P25 Name SDO DIN CNV SCK BUSY RESET PD CS DSPCLK Default 1 to 3 1 to 3 1 to 3 1 to 3 1 to 3 1 to 3 1 to 3 1 to 3 Soldered Function SDO Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P34. DIN Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P35. CNV Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P36. SCK Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P33. BUSY Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P37. RESET Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P38. PD Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P39. CS Interface Select. Pad 1 to Pad 3 for FPGA; Pad 2 to Pad 3 for P3 to P40. CED Clock Source. Rev. A | Page 6 of 32 EVAL-ADAS3022EDZ User Guide UG-484 Table 6. Power Supply Solder Pads Jumper P6 P13 P8 P10 P11 P12 Name VDDH VSSH AVDD – – VIO Default Soldered Soldered +5VA Soldered Soldered Open P14 P15 P33 P34 P35 P22 P23 P24 P26 P30 DVDD VDRVVDRV+ U4 V+ U4 V− −15V −5VA +5VA +5VD +15V +5VD −5VA +5VA VDRV+ VDRV− Soldered Soldered Soldered Soldered Soldered Function VDDH Supply. VSSH Supply. AVDD Supply. Selection of +5 V A, analog supply from the CED board or +5 V from U3. VIO Supply. This solder pad can be used to power the FPGA VIO and ADAS3022 VIO together. FPGA VIO Supply. Supplied from U8, 3.3 V, dedicated digital supply. VIO Supply. Selection of 2.5 V (2V5), 3.3 V (3V3), or DVDD (5V). Note that the ADAS3022 digital outputs are set to this level and are directly wired to the FPGA, U6, which is 3.3 V max. When using the 5 V setting, the ADAS3022 outputs, SDO and BUSY must be resistively divided using the 0603 pads provided on the evaluation board. For this reason, P10 is used as the default. DVDD Supply. Selection of +5 V digital, +5 V D, and +5 V from U3. U20 V−/P34 Supply. Selection of −5 V A, analog supply from the CED board or GND. U20 V+/P35 Supply. Selection of +5 V A, analog supply from the CED board or +5 V from U3. U4 V+ Supply. Selection of VDRV+ or U2. U4 V− Supply. Selection of VDRV− or GND. −15 V CED Supply. −5 V A (Analog) CED Supply. +5 V A (Analog) CED Supply. +5 V D (Digital) CED Supply. +15 V (Analog) CED Supply. Table 7. Test Points (By Signal Type) Test Point IN0_I IN1_I IN2_I IN3_I IN4_I IN5_I IN6_I IN7_I COM_I REF REFIN CNV BUSY SDO SCK PD RESET DIN CSB MSCL VDDH VSSH AVDD DVDD VIO +5VA −5VA +15V −15V +5VD GND(s) Type Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Digital Input Digital Output Digital Output Digital Input Digital Input Digital Input Digital Input Digital Input Digital Output Power Power Power Power Power Power Power Power Power Power Power Description Path for IN0 Input. Path for IN1 Input. Path for IN2 Input. Path for IN3 Input. Path for IN4 Input. Path for IN5 Input. Path for IN6 Input. Path for IN7 Input. Path for COM Input. Direct Connection to ADAS3022 REFx Pin. Direct Connection to ADAS3022 REFIN Pin. Direct Connection to ADAS3022 CNV Pin. Direct Connection to ADAS3022 BUSY Pin. Direct Connection to ADAS3022 SDO Pin. Direct Connection to ADAS3022 SCK Pin. Direct Connection to ADAS3022 PD Pin. Direct Connection to ADAS3022 RESET Pin. Direct Connection to ADAS3022 DIN Pin. Direct Connection to ADAS3022 CS Pin. Eval Board Master Clock Form Y3, 100 MHz Oscillator. Direct Connection to ADAS3022 VDDH Pin. Direct Connection to ADAS3022 VSSH Pin. Direct Connection to ADAS3022 AVDD Pin. Direct Connection to ADAS3022 DVDD Pin. Direct Connection to ADAS3022 VIO Pin. Connected to P24; CED +5 V A. Connected to P23; CED −5 V A. Connected to P30; CED +5 V A. Connected to P22; CED −5 V A. Connected to P26; CED +5 V D. Connected to Eval Board GND Plane. Rev. A | Page 7 of 32 UG-484 EVAL-ADAS3022EDZ User Guide EVALUATION BOARD SOFTWARE SOFTWARE INSTALLATION Close major Windows applications prior to installing the software. System Requirements • • • Windows XP (SP2, 32-bit), Windows Vista (32-bit or 64-bit), or Windows 7 (32-bit or 64-bit) USB 2.0 (for CED board) Administrator privileges The evaluation board software is available for download from the evaluation board page on Analog Devices website. Click the setup.exe file to run the install. The default location for the software is C:\Program Files (x86)\Analog Devices\ ADAS3022 Evaluation Software. 11064-105 Website Download Figure 5. ADAS3022 Evaluation Software Destination Directory Install the evaluation software before connecting the evaluation board and EVAL-CED1Z board to the USB port of the PC to ensure that the evaluation system is correctly recognized when connected to the PC. There are two parts of the software installation process: 11064-106 • ADAS3022 evaluation board software installation • EVAL-CED1Z board driver installation Figure 4 to Figure 9 show the separate steps to install the ADAS3022 evaluation software, while Figure 10 to Figure 12 show the separate steps to install the EVAL-CED1Z drivers. Proceed through all of the installation steps to allow the software and drivers to be placed in the appropriate locations. Only connect the EVAL-CED1Z board to the PC after the software and drivers are installed. 11064-104 Figure 6. ADAS3022 Evaluation Software License Agreement 11064-107 Figure 4. ADAS3022 Evaluation Software Installer Figure 7. ADAS3022 Evaluation Software Start Installation Rev. A | Page 8 of 32 UG-484 Figure 8. ADAS3022 Evaluation Software, Installation In Progress 11064-111 11064-108 EVAL-ADAS3022EDZ User Guide Figure 9. ADAS3022 Evaluation Software Installer, Installation Complete 11064-112 11064-109 Figure 11. CED Drivers Install Setup Wizard, Installation In Progress 11064-113 Figure 12. CED Drivers Install Setup Wizard, Installation Completed 11064-110 Figure 13. Computer Restart Notice Figure 10. CED Drivers Install Setup Wizard Rev. A | Page 9 of 32 UG-484 EVAL-ADAS3022EDZ User Guide On some PCs, the Found New Hardware Wizard may show up. If so, follow the same procedure to install it properly. The USB Device can be opened to view the uninstalled properties. 11064-006 The Device Manager can be used to verify that the driver was installed successfully. Figure 14. Device Manager Troubleshooting the Installation 11064-008 If the driver was not installed successfully, the Device Manager displays a question mark for Other devices because Windows does not recognize the EVAL-CED1Z board. Figure 16. USB Device Properties 11064-007 This is usually the case if the software and drivers were installed by a user without administrator privileges. If so, log on as an administrator with full privileges and reinstall the software. Figure 15. Device Manager Troubleshooting Rev. A | Page 10 of 32 EVAL-ADAS3022EDZ User Guide UG-484 POWERING UP THE BOARD The evaluation board, as configured from the factory, uses the local LDOs for power where necessary. A ±15 V dc lab supply must be connected to the board. Test points (yellow and white) are provided for these external supplies. This evaluation software should be located at <local_drive>:\Program Files\Analog Devices\ADAS3022 Evaluation Software. In order to launch the software, click Start>All Programs> Analog Devices\ADAS3022 Evaluation Software. You can then apply the signal source and capture the data. 11064-009 To uninstall the program, click Start>Control Panel>Add or Remove Programs>Analog Devices ADAS3022 Evaluation Software. Refer to Figure 18 to Figure 31 for further details and features of the software. Figure 17. Test Points RUNNING THE SOFTWARE WITH THE HARDWARE CONNECTED The evaluation board includes software for analyzing the ADAS3022. The EVAL-CED1Z is required when using the software. The software is used to perform the following tests: • • • Histogram tests for determining code transition noise (dc) Time domain analysis Fast Fourier transforms (FFT) for signal-to-noise ratio (SNR), SNR and distortion (SINAD), total harmonic distortion (THD), and spurious free dynamic range (SFDR) Rev. A | Page 11 of 32 UG-484 EVAL-ADAS3022EDZ User Guide SOFTWARE OPERATION Throughput (Label 4) This section describes the full software operation and all windows that appear. When the software is launched, the panel opens and the software searches for hardware connected to the PC. The user software panel launches, as shown in Figure 18. The labels listed in this section correspond to the numbered labels in Figure 18. The default throughput (sampling frequency) is 1,000 samples per second (SPS). The ADAS3022 is capable of operating a maximum sample frequency up to 1,000 kSPS. Samples (Label 5) Select the number of Samples to analyze when running the software. This number is limited to 65,536 samples. File Menu (Label 1) Single Capture (Label 6) and Continuous Capture (Label 7) The File menu, labeled 1 in Figure 18, provides the following: • Save Captured Data saves data to a .csv file. • Take Screenshot saves the current screen. • Print prints the window to the default printer. • Exit quits the application. Single Capture performs a single capture, whereas Continuous Capture performs a continuous capture from the ADC. Tabs There are four tabs available for displaying the data in different formats. Edit Menu (Label 2) The Edit menu, labeled 2, provides the following: Help Menu (Label 3) • • • • The Help menu, labeled 3, offers help from the following sources: To exit the software, go to File>Exit. • • • • Initialize to Default Values: This option resets the software to its initial state. Time Domain Histogram Spectrum Summary Analog Devices website User Guide Context Help About 1 2 3 5 11 9 7 6 4 10 8 12 11064-118 • Figure 18. Setup Screen Rev. A | Page 12 of 32 UG-484 11064-123 EVAL-ADAS3022EDZ User Guide 11064-119 Figure 23. Dialogue Box for Label 8, Advanced Sequencer PGIA Gain Configuration 11064-124 Figure 19. Dialogue Box for Label 8, MUX Settings 11064-120 Figure 24. Dialogue Box for Label 9, PGIA Settings 11064-125 Figure 20. Dialogue Box for Label 8, Input Channel Options 11064-126 11064-121 Figure 25. Dialogue Box for Label 10, AUX/MUX Settings Figure 21. Dialogue Box for Label 8, Alternate Input Channel Options 11064-122 11064-127 Figure 26. Dialogue Box for Label 11, Conversion Mode Settings Figure 27. Dialogue Box for Label 12, Reference Settings Figure 22. Dialogue Box for Label 8, Sequence Options Rev. A | Page 13 of 32 UG-484 EVAL-ADAS3022EDZ User Guide Start Up Refer to the numbered labels in Figure 18. Clicking the blue buttons reveals the dialog boxes shown in Figure 19 through Figure 27. To begin evaluating the device, the on-board supplies must be enabled. • • • • RESET resets the ADAS3022 device to a known state. Click RESET twice: once to reset the ADAS3022 and again to bring it out of the reset state. Note that the CFG is also reset to the default condition. Reference Selection: At this time, it is recommended to use the evaluation board’s externally generated reference (default). To select the on-chip reference, remove the P5 and P7 jumpers and click the button in the REF block to display the Reference Settings dialog box, then choose REFERENCE ENABLED. Auxiliary (AUX±) Channels Selection: The ADAS3022 allows the user to run it in default MUX ONLY mode or by clicking on it to select the auxiliary channel input pair (AUX+, AUX−) IN0−INX AUX in normal mode or sequencer mode. The IN0−INX AUX option converts a dedicated channel through the internal differential auxiliary channel pair (AUX+, AUX−) with the specified input range of ±VREF. This option bypasses the MUX and programmable gain instrumentation amplifier stage, allowing direct access to the SAR ADC core. Update CFG: If the default configuration (channel, channel configuration, reference, and so on) is acceptable, clicking Update CFG writes to the ADAS3022 configuration register (CFG). The ADAS3022 device is configurable using a 16-bit on-chip register, CFG (refer to the ADAS3022 data sheet for more details). Note that after changing any of the CFG register, this button must be clicked for the new setting to take effect. Input Channel To select the input channel, make a selection from the pulldown menu (see Figure 20). Channel Pairing The channels can be paired (up to 4 maximum) or all channels can be referenced to the COM input (see Figure 21). Programmable Gain The most useful and innovative feature of the ADAS3022 is the on-chip programmable gain instrumentation amplifier. This amplifier has the added flexibility of allowing for inputs ranging from ±0.64 V to ±24.574 V. Select the appropriate setting for the input voltage span, not including any common-mode signals, since they are rejected. Note that the ADAS3022 devices do not need the usual level shifting that is common in SAR ADC systems. The ADAS3022 devices can accommodate fully differential, single ended, and bipolar input signal types. Software Controls Within any of the chart panels, these controls are used to control the display. Rev. A | Page 14 of 32 Controls the cursor. Controls zooming in and out. Controls panning. EVAL-ADAS3022EDZ User Guide UG-484 TIME DOMAIN TAB Figure 28 illustrates the Time Domain tab. The ADAS3022 output is twos complement output; however, the software outputs the results in straight binary. 1 11064-131 2 Note that Label 1 shows the Waveform Analysis that reports the amplitude recorded from the captured signal in addition to the frequency of the signal tone, and Label 2 shows that Y-axis units can be displayed in volts or code (LSB). Figure 28. Time Domain Tab Rev. A | Page 15 of 32 UG-484 EVAL-ADAS3022EDZ User Guide HISTOGRAM TAB The histogram is most often used for dc testing or ac testing, where a user tests the ADC for the code distribution for dc input and computes the mean and standard deviation, or transition noise, of the converter, and displays the results. Raw data is captured and passed to the PC for statistical computations. Figure 29 shows the Histogram tab. To perform a histogram test, 1. Select the Histogram tab. 2. Click Single Capture or Continuous Capture. DC Testing To test other dc values, apply a source to the selected analog inputs IN[7:0]_I via test points or P1. It may be required to filter the signal to make the dc source noise compatible with that of the ADC. Note that 0805 and 0603 SMT pads are provided in each signal path and can be used for filtering the source, if necessary. AC Testing Figure 29 shows the histogram for a 1 kHz sine wave applied to the analog inputs IN[7:0]_I via test points or P1 from a quality precision signal source, such as Audio Precision. It may be required to filter the input signal from the ac source. There is no suggested band-pass filter, but consider all choices carefully. The Waveform Analysis (Label 1) chart displays the various measured histogram values for the ADAS3022. 11064-128 1 Figure 29. Histogram Tab Rev. A | Page 16 of 32 EVAL-ADAS3022EDZ User Guide UG-484 SPECTRUM TAB Figure 30 shows the FFT spectrum capture tab. This tab tests the traditional ac characteristics of the converter and displays a fast Fourier transform (FFT) of the results. As in the histogram test, raw data is captured and passed to the PC where the FFT is performed, displaying SNR, SINAD, THD, and SFDR. • • The top part of the image displays the FFT results including SNR, dynamic range, THD, SINAD, and noise performance (see Label 1). The lower part of the image displays the fundamental frequency and amplitude in addition to the 2nd to 5th harmonics (see Label 2). 11064-129 To perform an ac test, apply a sinusoidal signal to the evaluation board to any of the analog inputs IN[7:0]_I, either via test points or P1. Very low distortion—a better than 130 dB input signal source, such as Audio Precision)—is required to allow true evaluation of the part. One possibility is to filter the input signal from the ac source. There is no suggested band-pass filter, but carefully consider the choices. Figure 30 displays the results of the captured data. Figure 30. FFT Spectrum with FFT Results (Top) and with Spectrum Analysis Results (Bottom) Rev. A | Page 17 of 32 UG-484 EVAL-ADAS3022EDZ User Guide SUMMARY TAB 11064-132 Figure 31 shows the Summary tab, which summarizes all the data capture information and displays it in one panel with a synopsis of the information, including key performance parameters such as SNR, THD, and SINAD. Figure 31. Summary Tab Rev. A | Page 18 of 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 P1 GND AUX–I GND DNI R61 50Ω 1 GND DNI R60 50Ω IN0_I BLU AUX+I 3M30326-6002HB 1 GND COM_I BLU 1 CH4I GND DNI R66 50Ω IN3_I 1 BLU 90.9Ω COMI GND 1 R39 90.9Ω 0Ω GND 90.9Ω 0Ω C56 TBD0805 R40 R49 C55 TBD0805 R48 GND C54 2 TBD0805 90.Ω9 0Ω DNI 1 R38 C10 2700pF R47 DNI GND GND 90.9Ω 0Ω C53 2700pF R37 R46 DNI C52 2 TBD0805 90.9Ω 0Ω DNI 1 GND C50 2700pF GND C49 2700pF C48 2 TBD0805 DNI 1 C47 2700pF GND GND C46 2700pF C64 2 TBD0805 C63 2700pF GND C62 2700pF C51 2700pF R36 DNI 1 C61 2 TBD0805 DNI 1 C60 2700pF GND GND C59 2700pF GND R45 DNI C58 2 TBD0805 DNI 1 C57 2700pF GND GND GND R35 90.9Ω 90.9Ω 2700pF 2 TBD0805 C5 R34 0Ω DNI DNI DNI R44 0Ω R43 C4 2700pF GND GND 90.9Ω 0 C3 2700pF R51 R42 DNI C2 2 TBD0805 DNI 1 0 C1 2700pF R50 DNI GND GND PSTRNKPE4117 R41 IN4_I BLU DNI R68 50Ω CH7I GND DNI R67 50Ω IN6_I 1 BLU GND DNI R65 50Ω IN7_I BLU CH6I GND DNI R64 50Ω 1 CH3I CH2I CH1I CH0I PSTRNKPE4117 GND IN5_I 1 BLU CH5I GND DNI R63 50Ω IN2_I 1 BLU GND DNI R62 50Ω IN1_I 1 BLU PSTRNKPE4117 COM 1 COMI P31 IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN0 1 VSSH AUX– AUX+I AUX–I COM COM_2 GND 1 IN7 1 IN6 1 IN5 1 IN4 1 IN3 1 IN2 1 IN1_2 1 IN0_2 VDDH VSSH GND R33 49Ω9 VCM_AUX R52 499Ω TBD0805 R82 AUX–I BLU VCM_AUX R95 TBD0805 1 GND R81 TBD0805 R80 TBD0805 1 AUX+I BLU PD DIG1 RESET DIN CSB IN0 1 IN1 2 IN2 3 IN3 4 AUX+ 5 IN4 6 IN5 7 IN6 8 IN7 9 COM 10 TBD0402 R94 GND C38C92 0.1µF 0.1µF DUT CIRCUITS GND ADAS3XXX R85 GND R86 R54 499Ω GND 499Ω R84 TBD0805 GND GND R53 499Ω 499Ω R38 TBD0805 GND GND AVDD DVDD ACAP DCAP SCK VIO SDO BUSY_AUX CNV 499Ω U4 R87 1 TBD0805 U4 7 ADA4841-2YRZ 5 499Ω R88 TBD0805 C94 DNI ADA4841-2YRZ 6 3 2 30 29 28 27 26 25 24 23 22 21 REFIN GND GND 22Ω R58 R79 499Ω 22Ω R57 IN0 IN1 IN2 IN3 AUX+ IN4 IN5 IN6 IN7 COM ACAP 1 YEL GND +2.5V P20 1 2 3 4 4PJUMPER DCAP 1 YEL AUXPARTFOOTPRINT GND AUX+ GND AUX– C91 TBD0805 DNI COMMON MODE CAP 1 2 3 4 5 6 7 8 9 10 11 12 GEN_QFN40_6X6_PAD C93 U7 RCAP REF RCAP 1 YEL RCAP 2 3 4 5 ACAP IN1 1 CH1I R71 R2 2 3 4 5 C41 DCAP IN0 1 CH0I 1 2 3 PAD 40 39 38 37 36 35 34 33 32 31 C42 AUX– VDDH VSSH TBD0603 TBD0603 C43 C44 11 12 13 14 15 16 17 18 19 20 TBD0805 TBD0805 REF REFIN RCAP 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 2700pF Figure 32. Schematic, DUT, Analog 2700pF Rev. A | Page 19 of 32 U9 GND AVDD DVDD ACAP GND DCAP C68 TBD0603 C67 TBD0603 ADA4841-2YRZ AMPVEE U4 8 V+ V– 4 10µF C84 10µF C72 0.1µF C71 0.1µF C70 0.1µF GND GND P35 1 2 3 P34 1 2 3 C77 0.1µF C76 0.1µF AMPVEE DO NOT INSTALL IF VEE = GND P C89 0.1µF N P C45 0.1µF N AMPVCC RCAP ACAP AVDD C75 0.1µF PLACE CLOSE TO THE DUT SUPPLY DECOUPLING GND C47 10µF C96 10µF C73 0.1µF REF DECOUPLING C65 0.1µF C66 TBD0603 REF REF REFIN GEN_48LQFP 36 35 34 33 32 31 30 29 28 27 26 25 AMPVCC CSB DIN RESET DIG1 PD SCK VIO SDO BUSY_AUX CNV 2 3 4 5 VDRV– GND VDRV+ AUX_AMPVCC AMPVCC C81 TBD0603 VIO C80 TBD0603 DCAP AMPVEE C82 10µF C79 TBD0603 DVDD C78 0.1µF EVAL-ADAS3022EDZ User Guide UG-484 EVALUATION BOARD SCHEMATICS AND ARTWORK 11064-020 P14 VSSH +3.3V DVDD +2.5V GND AVDD BLU P12 VIO GND C15 10µF GND C16 10µF GND +15V –15V GND +15V P33 VIO_FPGA EN_5V_N +5VA +5V VIO 1 BLU VDRV1 BLU GND C14 10µF DVDD 1 BLU GND C13 10µF VDRV– AVDD 1 C12 10µF GND VSSH 1 BLU VIO_FPGA 0Ω 2 10kΩ R11 –5VA 0Ω +5VD +5VD +5VD 1 RED GND C23 10µF VDRV+ BLU 1 R90 R24 -5VA –5VA 1 WHT 1 10kΩ R10 VDRV+ +5VA RED +5VA GND +15V –15V GND+5VA GND1 +15V -15V GND 1 BLK 1 YELWHT 1 1 BLK 1 –5VA P15 +5VD +5VDVDD +5VA +5V P8 –15V P13 GND C11 10µF R69 TBD0805 R25 +15V 2.2µF GND GND GND GND GND GND2 GND3 BLK 1 BLK 1 GND GND GND GND6 GND5 BLK 1 BLK 2.2µF 1 GND U3 ADP3334ACPZ 7 IN1 OUT1 1 8 2 IN2 OUT2 3 6 SD_N FB PAD GND 5 PAD GND C29 AVDD +15V C30 1 2 EN_3.3V_N C26 TBD0805 C27 1 2 1000pF 2 1000pF 1 2 1 2 1 2 3 1 2 3 1 2 3 R13 140kΩ C32 1 JP1 2 0 0Ω R22 1 R152 1 R16 2 1 R19 2 0Ω +5V +3.3V AVDD 0Ω +15V R96 VIO_FPGA EN_2P5V_N GND GND 3 VDD_REF381 1 RED A2 ADR381ARTZ 1 VIN VOUT 2 GND TP TP1 VIN NC2 NC1 VOUT GND TRIM 8 7 6 5 1 0Ω 2 R97 R12 10kΩ TBD0805 1 R91 1 P5 1 2 3 JP2 2 0 REF381_OUT RED ADR434ARMZ 1 2 3 4 A1 EXTERNALREFERENCE 0Ω 1 R20 2 2.2µF 2.2µF 1 R14 2 78.7kΩ 210kΩ C33 64.9kΩ VDDH C37 +15V 1 2 3 4 1 2 3 GND R102 10kΩ REFIN REFIN 1 RED 10 R23 R98 10kΩ TBD0805 C28 C85 GND 0Ω R92 TBD0805 DNI GND 1 R21 2 0Ω 0Ω –IN OUT 1 3 +IN AD8032 2 U20 0kΩ R7 C83 TBD0805 +2.5V 1 REF RED FPGA SUPPLIES GND U11 R5 ADP1715ARMZ-R7 1kΩ 1 EN 2 IN OUT 3 4 ADJ GND R6 5 6 7 8 2kΩ LDO ADJUSTED TO 1.2V GND U10 R3 ADP1715ARMZ-R7 1kΩ 1 EN 2 IN OUT 3 4 ADJ GND R4 5 6 7 8 2kΩ 1 R8 2 0Ω 1 R9 2 0Ω REF GND C88 0.1µF R28 59K 36.5kΩ R27 GND 8 +VS –VS 4 VDRV+ PAD 0 R70 GND GND –IN OUT 7 5 +IN AD8032 6 5 REGULATES FPGA VIO SUPPLIES TO 3.3V (MAX ALLOWED) U8 ADP3334ACPZ +5VD 7 IN1 OUT1 1 8 IN2 OUT2 2 6 SD_N FB 3 R55 140kΩ PAD GND +5VD +5VD U20 AD8032 R101 AUX_AMPVCC REFIN CONNECTION: OPEN: INTERNAL 2.5V BAND GAP 1:EXTERNAL 2.5V BAND GAP, INT REF BUF 3:EXTERNAL 4.096 REFERENCE, INT REF BUF DISABLED P7 REF 0Ω DNI R93 GND PAD GND 5 PAD U2 ADP3334ACPZ 7 IN1 OUT1 1 8 IN2 OUT2 2 6 SD_N FB 3 GND 7 IN1 OUT1 1 8 IN2 OUT2 2 6 3 SD_N FB PAD GND 5 PAD U1 ADP3334ACPZ R29 U12 ADP3334ACPZ 7 IN1 OUT1 1 8 2 IN2 OUT2 6 3 SD_N FB PAD GND 5 PAD C35 C17 R26 2.2µF DNI C31 C86 TBD0805 VDDH 1 BLU C36 2.2µF 2.2µF R1 1 2 1000pF 1000pF C40 1 R18 2 60.4kΩ TBD0805 TBD0805 P6 0.1µF C7 R99 R100 C18 1 2 C19 1 2 LDO ADJUSTED TO1.2V C39 ANALOG SUPPLIES 10µF 0.1µF TBD0805 SUPPLYOPTIONS C20 Rev. A | Page 20 of 32 0.1µF Figure 33. Schematic, Power TBD0805 0.1µF VCM_AUX C9 1 R17 2 300kΩ C34 C87 2 2 2 2 C24 1 2 C25 1 2 R56 2.2µF 2.2µF 2.2µF 2.2µF 2.2µF C21 1 2 C22 1 2 C8 2.2µF 2.2µF 1000pF 1 78.7kΩ 1 1 0.1µF 1 2.2µF 1 3 2 1 VIO_FPGA VPLL VFPGA UG-484 EVAL-ADAS3022EDZ User Guide 11064-021 GND C107 100pF 0Ω R31 CSB PD RESET VIO 0Ω BUSY_AUX R30 CNV DIN VIO VIO R128 0Ω VIO 10kΩ R126 GND GND GND GND GND GND 15kΩ DNI GND 10kΩ DNI R32 R125 R72 R73 R74 3 2 1 P16 P17 DIN_I P19 CNV_I P27 BUSY_I P28 RESET_I P29 PD_I CSB_I 0.1µF C108 CNV DIN SCK SDO CNV 1 BLU DIN 1 BLU SCK 1 BLU SDO 1 BLU VIO_FPGA CSB RESET PD R121 10kΩ 1 1 1 CSB BLU RESET BLU PD BLU BUSY BLU 1 DIG1 GND R122 10kΩ DIG1 BUSY_AUX1 PS_DCLK 1 GND 2 PS_CDONE_N 3 VIO_FPGA 4 PS_CONFIG_N 5 PS_STATUS_N 6 DATA 7 N_CSO 8 ASDO 9 GND 10 3M2510-5002UB P2 ASDO VPLL GND VPLL GND L6 U6 5 VCCD_PLL1 ASDI ASDO C3 IO CLK0 D4 GND IO CLK1 F3 4 EPCS4SI8N IO CLK2 E1 IO CLK3 E2 GND IO K2 DATA0 IO K1 IO DCLK K4 IO K5 IO NCE M1 IO NCONFIG L1 IO F4 IO TCK N_CSO L2 IO TDI J4 IO TMS M2 IO M3 IO N1 IO BANK_1 N2 IO L3 IO P1 IO P2 IO P3 IO C1 IO L4 IO M4 IO C2 IO D5 IO EN_3.3V_N E5 IO E3 EN_5V_N IO EN_2P5V_N E4 IO D3 IO G2 TDO GND_PLL1 N5L5 3 7 U5 VCC N_CSO 1 nCS 8 2 DATA PS_DCLK 6 DCLK DATA GND GND P21 1 2 3 GND EP2C5F256C7N F2 H5 G1 G5 PS_STATUS_N J5 PS_CONFIG_N F1 DATA H4 PS_DCLK H2 MCLK H1 J2 J1 VCCIO3 GND POWER_FPGA VCCIO2 VCCIO1 VIO_FPGA VCCINT VIO BANK_2 B16 G14 K14 R16 TBD0603 DNI 15kΩ DNI TBD0603 DNI TBD0603 DNI 10kΩ R130 R103 10kΩ TBD0603 DNI R75 R76 R77 R78 R132 10kΩ DNI 10kΩ DNI 10kΩ DNI 10kΩ DNI P10 VFPGA 3 2 1 3 2 1 3 2 1 3 2 1 3 2 1 3 2 1 3 2 1 P11 G9 H7 H10 J7 P3 OH_D0 OH_D1 OH_D2 OH_D3 OH_D4 OH_D5 OH_D6 OH_D7 2 2 1 2 VCCIO1 B1 G3 K3 R1 BANK_4 LA_CLK1 LA_CLK2 C110 C109 1 2 VIO_FPGA A2 A15 C7 C10 E7 E10 OH_D8 OH_D9 OH_D10 OH_D11 OH_D12 OH_D13 OH_D14 OH_D15 1000pF GND U6 MSEL0 MSEL1 J13 K12 DSPCLK H16 H15 J15 J16 LA_CLK2 LA_CLK1 EP2C5F256C7N VCCIO4 M7 M10 P7 P10 T2 T15 G8 C9 E8 E9 H3 H14 J3 J14 M8 M9 P8 H8 P9 R2 R15 T1 T16 J9 K9 H9 J8 A1 A16 B2 B15 C8 M5 R3 IO VCCA_PLL1 CLAMP_ENT3 IO P5 IO P4 IO T4 IO R4 IO T5 IO U6 R5 IO T6 IO N8 IO T7 IO R7 IO L7 IO L8 IO T8 IO R8 IO OH_D15 T9 IO OH_D14 R9 IO OH_D13 N9 IO OH_D12 N10 IO OH_D11 T11 IO OH_D10 R11 IO OH_D9 P11 IO OH_D8 L9 IO OH_D7 L10 IO OH_D6 R10 IO OH_D5 T10 IO OH_D4 K11 IO OH_D3 K10 IO OH_D2 N11 IO OH_D1 P12 IO OH_D0 P13 IO T12 IO R12 IO L12 IO T13 IO R13 IO T14 IO R14 IO M11 IO L11 IO GNDA_PLL1 EP2C5F256C7N M6 SDO_I 3M2540-6002UB VIO_FPGA GND GND GND 2 VIO_FPGA R134 10kΩ GND C112 0.1µF C114 0.1µF 0.1µF C117 L13 PS_CDONE_N H13 BD<0> D15 BD<1> D16 BD<2> E16 BD<3> C14 BD<4> D13 BD<5> E14 BD<6> D14 BD<7> N12 BD<8> M12 BD<9> N13 BD<10> N14 P14 BD<12> P15 BD<13> P16 BD<14> N15 BD<15> N16 AD<0> M15 AD<1> M16 AD<2> M14 AD<3> L14 AD<4> L15 L16 BD<11> K16 K15 BWR_N H12 BRESET J12 CONTROL G16 BBUSY G15 BRD_N F15 BCS_N VIO_FPGA F16 ADCOK J11 PLLOK H11 R135 G12 10kΩ G13 M13 EP2C5F256C7N VFPGA VPLL U6 F11 VCCD_PLL2 CLK4 CONF_DONE CLK5 IO CLK6 IO CLK7 IO IO MSEL0 IO MSEL1 IO IO IO IO IO IO IO IO IO IO IO IO IO BANK_3 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO NSTATUS GND_PLL2 F12 D12 GND C113 R59 0.1µF SDO C116 VPLL 0.1µF VIO_FPGA C118 GND C120 P9 0.1µF 2 0.1µF GND 0.1µF C119 C122 VIO 0.1µF GND 2 GND 0.1µF VIO_FPGAVIO_FPGA R136 0Ω 10kΩ R141 10kΩ R140 10kΩ R139 R138 GND R137 0Ω 0.1µF C123 PLLOK ADCOK AC GND R150 0Ω VIO_FPGA GND R151 0Ω GND ADCOK GND ADCOK CR1 AC CR2 GND GND GND GND GND GND VCCIO1 604Ω R89 604Ω R145 10kΩ DSPCLK R144 10kΩ 10kΩ BRESET R142 10kΩ CONTROL R143 BWR_N BRD_N BBUSY BCS_N MSEL0MSEL1 C121 C124 VIO_FPGA C125 SCK_I 0.1µF 2 2 C126 1000pF E12 U6 VCCA_PLL2 B14 IO IO A14 IO C13 IO C12 IO B13 IO A13 B11 IO IO B12 IO A12 IO A11 IO C11 IO G10 IO G11 IO B10 IO A10 IO F10 IO F9 D11 IO IO D10 IO A9 IO B9 IO A8 IO A7 IO B7 IO F7 IO F8 IO D8 IO B6 A6 IO IO G6 IO G7 IO D6 IO C6 IO C5 IO C4 IO B5 IO A5 IO B4 IO A4 A3 IO IO B3 IO E6 IO F6 GNDA_PLL2 E11 EP2C5F256C7N C111 SCK_I SDO_I DIN_I CNV_I BUSY_I RESET_I PD_I CSB_I C127 SCK 0.1µF 2 2 MCLK MCLK 1 YEL MCLK C115 C129 100MHZ Y3 4 V+ 3 1 EN OUT 0.1µF 0.1µF P18 0.1µF 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 0.1µF Rev. A | Page 21 of 32 1 C128 1 C130 Figure 34. Schematic, FPGA C131 1 1 0.1µF 1 1 0.1µF 1 0.1µF VIO EVAL-ADAS3022EDZ User Guide UG-484 11064-022 0.1µF UG-484 EVAL-ADAS3022EDZ User Guide CONTROL 1 VDIG 1 2 1 BRESET BD<12> DSPCLK_CED –15V -5VA +5VA 1 2 P24 P23 1 2 1 2 P22 DSPCLK –5VA_CED +5VA_CED BD<8> BD<9> BD<10> BD<11> BD<13> –5VA_CED +5VA_CED ERNI533402 GND BCS_N 1 1 VDIG BWR_N BCS_N AD<4> AD<2> AD<0> BBUSY 1 BBUSY BD<14> BD<15> +15V ERNI533402 GND BWR_N +15V_CED –5VA_CED +5VA_CED ERNI533402 GND Figure 35. Schematic, 96-Pin Interface 11064-030 P25 AD<3> BRESET AD<1> BD<2> BD<3> BD<4> VDIG BD<5> BD<6> BD<7> P4 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 11064-023 1 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 BD<0> BD<1> P30 1 2 BRD_N +5VD BRD_N P4 CONTROL A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 1 2 P26 P4 Figure 36. Silkscreen, Top Rev. A | Page 22 of 32 UG-484 11064-031 EVAL-ADAS3022EDZ User Guide 11064-024 Figure 37. Silkscreen, Bottom Figure 38. Top Layer 1 Rev. A | Page 23 of 32 EVAL-ADAS3022EDZ User Guide 11064-025 UG-484 11064-026 Figure 39. GND Layer 2 Figure 40. Signal Layer 3 Rev. A | Page 24 of 32 UG-484 11064-027 EVAL-ADAS3022EDZ User Guide 11064-028 Figure 41. Signal Layer 4 Figure 42. Power Layer 5 Rev. A | Page 25 of 32 EVAL-ADAS3022EDZ User Guide 11064-029 UG-484 Figure 43. Bottom Layer 6 Rev. A | Page 26 of 32 EVAL-ADAS3022EDZ User Guide UG-484 PRODUCTS ON THIS EVALUATION BOARD BILL OF MATERIALS Table 8. Qty 5 Reference Description U1 to U3, U8, U12 Part Description IC-ADI LDO Value – Manufacturer Analog Devices Part Number ADP3334ACPZ 2 U10, U11 IC-ADI LDO – Analog Devices ADP1715ARMZ 1 U20 IC-ADI OPAMP – Analog Devices AD8032ARZ 1 U4 IC-ADI OPAMP – Analog Devices ADA4841-2YRZ 1 A1 IC-ADI REFERENCE – Analog Devices ADR434ARMZ 1 A2 IC-ADI REFERENCE – Analog Devices ADR381ARTZ 1 U6 IC-CYCLONE II – Altera Devices EP2C5F256C7N 1 U5 IC SERIAL CONFIG – Altera Devices EPCS4SI8N 1 Y3 IC CRYSTAL OSC 100 MHZ C-MAC SPXO009437-CFPS-73 22 C108, C111 to C131 CAP X7R 0402 0.1 µF Murata GRM155R71C104KA88D 2 1 C45, C89 C107 CAP X7R 0508 CAP NP0 0603 0.1 µF 100 pF TDK Phycomp C1220X7R1E104K 2238 867 15101 6 C17, C20, C24, C25, C36, C88 C66 to C68, C79 to C81 CAP X8R 0603 0.1 µF Murata GRM188R7E104KA01D CAP X7R 0805 0.1 µF Murata GRM21BR71H104KA01L CAP C0G 0805 1000 pF Murata GRM2165C2A102JA01D CAP NPO 0805 2700 pF Murata GRM2165C1H272JA01D CAP NPO 0805 2700 pF Murata GRM2165C1H272JA01D DNI CAP NPO 0805 5600 pF Murata GRM2195C1H562JA01D DNI CAP X5R 0805 2.2 µF Murata GRM21BR71E225KA73L CAP X5R 0805 10 µF Murata GRM21BR61C106KE15L 2 C38,C65, C70, C71, C72, C73, C75, C76, C77, C78, C92 C8, C29 to C31, C86, C109, C110 C43,C44, C46, C47, C49, C50, C57, C59, C60, C62, C63 C1, C3, C4, C6, C10, C51, C53, C55, C56 C2, C5, C48, C52, C54, C58, C61, C64 C7, C9, C18, C19, C21, C22, C26 to C28, C32 to C34, C37, C85, C87 C11 to C16, C23, C35, C69, C74 C84, C90 CAP TANT 10 µF AVX TAJA106K010RNJ 7 C39 to C42, C91, C93, C94 CAP 0805 Murata – 1 R94 RES 0402 0 Panasonic-ECG ERJ-2GE0R00X 4 R32, R72, R73, R103 RES 0603 – Panasonic-ECG – DNI 6 R2, R71, R125, R126, R136, R151 R30, R31, R59, R137, R137, R151 R60 to R68 RES 0603 – Panasonic-ECG – DNI RES 0603 0 Panasonic-ECG ERJ-3GEY0R00V RES 0603, 5% 50 Panasonic-ECG ERJ-3EKF49R9V RES 0603, 5% 10 K Panasonic-ECG ERJ-3EKF1002V 2 R74 to R78, R121, R122, R128, R130, R132, R134, R138 to R144 R125, R126 RES 0603, 5% 15 K Yageo RC0603FR-0715KL 2 R13, R55 RES 0603, 1% 140 K Panasonic-ECG 6 11 7 11 9 8 15 10 6 9 18 CAP X7R 0603 Instructions DNI DNI Rev. A | Page 27 of 32 DNI DNI UG-484 Qty 14 EVAL-ADAS3022EDZ User Guide Part Description RES 0805 Value – Manufacturer Panasonic-ECG Part Number – RES 0805 0 Panasonic-ECG ERJ-6GEY0R00V 2 Reference Description R1, R24 to R26, R29, R80 to R82, R85, R86, R95, R97, R99, R100 R7 to R9, R19 to R23, R41 to R49, R69, R70, R90 to R93, R96, R101 R57, R58 RES 0805, 1% 22 Panasonic-ECG ERJ-6ENF22R0V 9 1 R34 to R40, R50, R55 R27 RES 0805, 1% RES 0805, 1% 90.9 365 Panasonic-ECG Panasonic-ECG ERJ-6ENF90R9V ERJ-6ENF3652V 9 RES 0805, 1% 499 Panasonic-ECG ERJ-6ENF4990V 1 R33, R52 to R54, R79, R83, R84, R87, R88 R28 RES 0805, 1% 590 Panasonic-ECG ERJ-6ENF5902V 2 R89, R145 RES 0805, 1% 604 Panasonic-ECG ERJ-6ENF6040V 2 R3, R5 RES 0805, 5% 1K Panasonic-ECG ERJ-6ENF1001V 2 R4, R6 RES 0805, 5% 2K Panasonic-ECG ERJ-6ENF2001V 6 RES 0805, 5% 10 K Panasonic-ECG ERJ-6ENF1002V 1 R10 to R12, R98, R102, R135 R16 RES 0805, 1% 64.9 K Panasonic-ECG ERJ-6ENF6492V 2 R14, R56 RES 0805, 1% 78.7 K Panasonic-ECG ERJ-6ENF7872V 1 R18 RES 0805, 1% 95.3 K Panasonic-ECG ERJ-6ENF6042V 1 R17 RES 0805, 1% 107 K Yageo RC0805FR-07300KL 1 R15 RES 0805, 1% 210 K Panasonic-ECG ERJ-6ENF2103V 2 CR1,CR2 LED Green Chicago MINI LAMP CMD28-21VGCTR8T1 3 P5, P7, P31 CONN-3 PIN MALE Breakaway Samtec TSW-103-08-G-S 1 P2 CONN-10 PIN MALE RA, shroud 3M 2510-5002UB 1 P1 CONN-26 PIN MALE Shroud 3M 30326-6002HB 1 P3 CONN-40 PIN MALE RA, Shroud 3M 2540-6002UB 1 P4 CONN-96 PIN MALE RA, DIN ERNI 533402 6 GND(S) Test point Black Components Corp TP-104-01-00 2 +15 V, MCLK Test point Yellow Components Corp TP-104-01-04 4 REF, +5 V A, +5 V D, REFIN Test point Red Components Corp TP-104-01-02 2 −15 V, −5 VA Test point White Components Corp TP-104-01-09 26 PD, CNV, CSB, DIN, Test point Blue Components Corp TP-104-01-06 25 SCK, SDO, VIO, AVDD, BUSY, DVDD, VDDH, VSSH, AUX+I, AUX−I, COM_I, IN0_I−IN7_I, RESET, VDRV+, VDRV− Rev. A | Page 28 of 32 Instructions DNI EVAL-ADAS3022EDZ User Guide UG-484 RELATED LINKS Resource AD8032 ADR434 ADP1715 ADP3334 EVAL-CED1Z AN-931 AN-932 Description Product Page, AD8031/AD8032, Low Power, Low Noise Amplifier Product Page, ADR434, 4.096 Precision Reference Product Page, ADP1715, 500 mA Low Dropout CMOS Linear Regulator with Soft Start Product Page, ADP3334, High Accuracy Low IQ, 500 mA, ANYCAP®, Adjustable Low Dropout Regulator Product Page, Converter and Evaluation Development board Application Note, Understanding PulSAR ADC Support Circuitry Application Note, Power Supply Sequencing Rev. A | Page 29 of 32 UG-484 EVAL-ADAS3022EDZ User Guide NOTES Rev. A | Page 30 of 32 EVAL-ADAS3022EDZ User Guide UG-484 NOTES Rev. A | Page 31 of 32 UG-484 EVAL-ADAS3022EDZ User Guide NOTES ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. ©2012–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG11064-0-2/14(A) Rev. A | Page 32 of 32