DC2266A - Demo Manual

DEMO MANUAL DC2266A
LTC2107 and LTC6409
16-Bit, 210Msps ADC with DCCoupled Driver
DESCRIPTION
Demonstration circuit 2266A features the LTC®2107,
210Msps ADC, and the LTC6409 low noise amplifier.
DC2266A supports the LTC2107 DDR LVDS output mode.
The circuitry on the analog inputs is optimized for analog
input frequencies from DC to 100MHz. When driven with
PERFORMANCE SUMMARY
a 50Ω source, the gain will be 6dB. To modify the input for
other input ranges or gains refer to the LTC6409 data sheet.
Design files for this circuit board are available at
http://www.linear.com/demo/DC2266A
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
Specifications are at TA = 25°C
PARAMETER
CONDITIONS
MIN
Supply Voltage – LTC2107 (VIN)
This Supply Must Provide Up to 800mA
3.3
5.0
V
Supply Voltage – LTC6409 (AMPVCC)
This Supply Must Provide Up to 75mA
3.3
5.0
V
Analog Input Range
Depending on PGA Setting
1.6
2.4
VP-P
Maximum Input Level at J1 and J2
2.4VP-P Input Range
1.2
VP-P
1.6VP-P Input Range
0.8
VP-P
Logic Input Voltages
Minimum Logic High
TYP
1.2
0.6
Nominal Logic Levels (100Ω Load, 3.5mA
Mode, 1.25V Common Mode)
Minimum Logic Levels (100Ω Load, 3.5mA
Mode, 1.25V Common Mode)
Sampling Frequency (Encode Clock Frequency)
Convert Clock Level (Single ended)
Minimum Logic Levels (ENC– Tied to GND)
Convert Clock Level (Differential)
Minimum Logic Levels (ENC– Not Tied to GND,
1.2V Common Mode)
UNITS
V
Maximum Logic Low
Logic Output Voltages (Differential)
MAX
0.350
V
V
0.247
V
10
210
MHz
0
2.5
V
0.2
V
dc2266af
1
DEMO MANUAL DC2266A
QUICK START PROCEDURE
The DC2266A is easy to set up to evaluate the performance of the LTC2107 A/D converter. Refer to Figure 1
for proper measurement equipment setup and follow the
procedure below.
3.3V TO 5V
UNREGULATED
The DC1371 Data Acquisition and Collection System was
supplied with the DC2266A board. Follow the DC1371
Quick Start Guide to install the required software and for
connecting the DC1371 to the DC2266A and to a PC.
3.3V TO 5V
ANALOG INPUT – ABSORPTIVE
FILTER IS REQUIRED FOR
DATA SHEET PERFORMANCE
SINGLE-ENDED
INPUT SIGNAL
MATCHED
SOURCE
IMPEDANCE
JUMPERS SHOWN IN THEIR
DEFAULT POSITIONS
THE DC2266A CONNECTS TO
THE DC1371 VIA AN FMC
CONNECTOR
DIFFERENTIAL ENCODE CLOCK
(USE A LOW JITTER SIGNAL
GENERATOR WITH PROPER
FILTERING)
Figure 1. DC2266A Setup (Zoom for Detail)
2
dc2266af
DEMO MANUAL DC2266A
HARDWARE SETUP
SMAS
JUMPERS
J1 AIN–: Negative Analog Input. Apply a signal to J1 from
a 50Ω driver. Absorptive filters are required for optimum
performance. Terminate this channel to an impedance
that matches J2 when using a single-ended input on J2.
If J1 is being driven single-ended, a matching impedance
should be connected on the input J2 for proper balance.
The DC2266A demonstration circuit should have the following jumper settings as default positions (see Figure 1)
which configure the ADC in Serial programming mode.
In the default configuration, JP1-JP2 should be left in
the default locations. This will pull PAR/SER low, and the
required pins high through weak pull-up resistors so the
SPI commands can be sent from the PC. If JP1 is set to
PAR then jumpers JP1-JP2 can be configured manually.
J2 AIN+: Positive Analog Input. Apply a signal to J2 from
a 50Ω driver. Absorptive filters are required for optimum
performance. For a single-ended signal, a matching impedance should be connected on the input J1 for proper
balance. Use this channel when using a single-ended input.
J3 and J4: Encode Clock Input for Differential Signals. By
default, the DC2266A is designed to be driven with a differential clock source connected to J3 and J4. The jumper
position on JP6 can be changed to provide termination
for various signaling standards.
TURRETS
VIN: Positive Input Voltage for the ADC and Digital Buffers.
This voltage feeds a regulator that supplies the proper
voltages for the ADC and buffers. The voltage range for
this turret is 3.3V to 5V.
AMPVCC: Positive Input Voltage for the LTC6409. This
voltage is unregulated and powers the amplifier directly.
The voltage range for this turret is 3.3V to 5V.
EXT REF: Optional Reference Voltage. This pin is connected
directly to the SENSE pin of the ADC. Connect EXT REF to
a 1.25V external reference and the external reference mode
is automatically selected. The external reference must be
1.25V ± 25mV for proper operation. If no external voltage
is supplied, this pin will be pulled up to 2.5V through a
weak pull-up resistor.
GND: Ground Connection. This demo board only has a
single ground plane. This turret should be tied to the GND
terminal of the power supply being used.
JP1: PAR/SER: Selects Parallel or Serial programming
mode (Default: Serial).
CMOS/LVDS: In Serial programming mode (SER), this pin
should be in the LVDS position to allow serial data transfer
(Default: LVDS or up). In the Parallel programming mode
(PAR), this pin controls the digital output mode. When
this pin is in the CMOS position, the full-rate CMOS output
mode is enabled. When this pin is in the LVDS position, the
double data rate LVDS output mode (with 3.5mA output
current) is enabled. Note: when using the DC1371, Parallel
mode DDR LVDS must be selected.
JP2: PGA: In Serial programming mode (SER), this pin is
pulled high through a weak pull-up resistor to allow serial
data transfer. In the Parallel programming mode (PAR),
this pin controls the programmable gain amplifier frontend (PGA). In the 1x jumper position, a front-end gain of
1x is selected, ADC input range of 2.4VP-P. This allows
1.2VP-P to be presented at the input of the amplifier. In the
3/2 jumper position, a front-end gain of 1.5x is selected,
ADC input range of 1.6VP-P which allows 0.8VP-P to be
presented at the input of the amplifier (Default: 3/2 or up).
RAND: In Serial programming mode (SER), this pin is
pulled high through a weak pull-up resistor to allow
serial data transfer. In the Parallel programming mode
(PAR), this pin becomes the digital output randomization
control bit. When this pin is in the OFF position, digital
output randomization is disabled. When this pin is in the
ON position, digital output randomization is enabled. To
decode the randomized data, exclusive-OR each bit with
the least significant bit. This is done for you in PScope™
when the randomizer option is enabled (Default: ON or up).
dc2266af
3
DEMO MANUAL DC2266A
HARDWARE SETUP
JP3: Shutdown: In the RUN position, this results in normal
operation of the ADC. In the SHDN position, the ADC is
powered down and the digital outputs are set in a high
impedance state (Default: RUN or down).
JP4: EEPROM: EEPROM Write Protect. For factory use
only. Should be left in the enable (PROG) position.
JP5: Overflow Test Point: This is a test point for the differential overflow signal. This jumper can be installed to
provide a convenient way to probe the overflow signal
(Default: removed).
JP6: Clock Term: This jumper provides termination voltages for various signaling standards. LVPECL, CML, and
LVDS termination voltages can be selected. The selected
voltage is then used to terminate the clock input through
50Ω resistors. By removing the jumper completely, an
external voltage can be applied directly to pin 5 of JP6 so an
arbitrary signaling scheme can be used (Default: LVPECL).
APPLYING POWER AND SIGNALS TO THE DC2266A
If a DC1371 is used to acquire data from the DC2266A,
the DC1371 must FIRST be connected to a powered USB
port and provided an external 5V BEFORE applying +3.3V
to +5.0V across the pins marked VIN, AMPVCC and GND
on the DC2266A. Regulators on the board produce the
voltages required for the ADC. The LTC6409 is powered
directly. The DC2266A demonstration circuit requires
up to 800mA from the VIN supply, and 75mA from the
AMPVCC supply. The DC2266A should not be removed or
connected to the DC1371 while power is applied.
ANALOG INPUT NETWORK
The input network of the DC2266A can be modified to
accommodate various applications. In the default setup,
both of the inputs are brought out to SMA connectors so
the demo board can be driven with a differential source.
To drive the demo board with a single-ended source simply drive J2 and terminate J1 with the matched source
impedance of the signal source.
As a default, the DC2266A is populated with no filtering
between the input SMAs and the LTC6409. This allows a
custom filter to be designed and used between the signal
source and amplifier.
4
In almost all cases, an off-board absorptive filter will be
required on the analog input of the DC2266A to produce
optimum SNR.
The off-board filter should be located close to the input
of the demo board to avoid reflections from impedance
discontinuities at the driven end of a long transmission line.
Most filters do not present 50Ω outside the passband. In
some cases, 3dB to 10dB pads may be required to make
the filter look more absorptive to obtain low distortion.
The gain of the amplifier can also be changed by varying the feedforward and feedback resistors. For optimal
distortion and noise performance, there is an absorptive
filter (diplexer) network populated after the LTC6409.
This reduces the sampling artifacts seen by the amplifier
and reduces the reflections of these products that return
to the ADC.
Be sure not to overdrive the ADC by setting the gain too
high; refer to the LTC6409 data sheet for resistor value
considerations.
dc2266af
DEMO MANUAL DC2266A
APPLYING POWER AND SIGNALS TO THE DC2266A
ENCODE CLOCK
Apply a differential encode clock to the SMA connectors on
the DC2266A marked J3 and J4. These SMA connectors
are 0.5" apart to accommodate LTC differential clock boards.
For the best noise performance, the encode input must
be driven with a very low jitter, signal generator source.
The amplitude should be as large as possible up to 2VP-P
or 10dBm.
The DC2266A demo board is designed to accept various
differential signaling standards. Changing the position of
JP6 to CML, LVDS, or LVPECL selects the proper termination for your input signal.
SOFTWARE
The DC1371 is controlled by the PScope system software
which can be downloaded from the Linear Technology
website at: www.linear.com/software/
Figure 2: ADC Configuration
Manual Configuration Settings:
Bits: 16
Alignment: 16
If a DC1371 was provided, follow the DC1371 Quick Start
Guide and the instructions below.
FPGA Ld: S2157
To start the data collection software if “PScope.exe” is
installed (by default) in \Program~Files\LTC\PScope\,
double click the PScope icon or bring up the run window
under the start menu and browse to the PScope directory
and select PScope.
Bipolar: Unchecked
If the DC2266A demonstration circuit is properly connected
to the DC1371, PScope should automatically detect the
DC2266A, and configure itself accordingly. If necessary,
the procedure below explains how to manually configure
PScope.
Under the “Configure” menu, go to “ADC Configuration...”
Check the “Config Manually” box and use the following
configuration options, see Figure 2.
Channs: 1
Positive-Edge Clk: Unchecked
If everything is hooked up properly, powered and a suitable, convert clock is present, clicking the “Collect” button
should result in time and frequency plots displayed in
the PScope window. Additional information and help for
PScope is available in the DC1371 Quick Start Guide and in
the online help available within the PScope program itself.
SERIAL PROGRAMMING
PScope has the ability to program the DC2266A board
serially through the DC1371. There are several options
available for the LTC2107 that are only available through
serially programming. PScope allows all of these features
to be tested.
dc2266af
5
DEMO MANUAL DC2266A
APPLYING POWER AND SIGNALS TO THE DC2266A
These options are available by first clicking on the “Set
Demo Bd Options” icon on the PScope toolbar (Figure 3).
This menu allows any of the options available for the
LTC2107 to be programmed serially. The LTC2107 family
has the following options:
Sleep Mode – Selects Between Normal Operation and
Sleep Mode:
Figure 3: PScope Toolbar
This will bring up the menu shown in Figure 4.
n
Off (Default) – Entire ADC is Powered and Active
n
On – The Entire ADC is Powered Down
Dither – Selects Between Internal Dither Being Enabled
or Disabled:
n
Enabled (Default) – Internal Dither Enabled
n
Disabled – Internal Dither Disabled
Gain (PGA) – Selects Input Range of the ADC:
n
1.0 (Default) – Selects the 2.4V Input Range
n
1.5 – Selects the 1.6V Input Range
Duty Cycle Stabilizer – Enables or Disables Duty Cycle
Stabilizer:
n
n
Stabilizer Off (Default) – Duty Cycle Stabilizer
Disabled
Stabilizer On – Duty Cycle Stabilizer Enabled
ClkOut Invert – Selects the Polarity of the CLKOUT Signal:
n
Disabled (Default) – Normal CLKOUT Polarity
n
Enabled – CLKOUT Polarity is Inverted
ClkOut Phase – Selects the Phase Delay of the CLKOUT
Signal:
n
0 deg (Default) – No CLKOUT Delay
n
45 deg – CLKOUT Delayed by 45 Degrees
n
90 deg – CLKOUT Delayed by 90 Degrees
n
135 deg – CLKOUT Delayed by 135 Degrees
Figure 4: Demo Board Configuration Options
6
dc2266af
DEMO MANUAL DC2266A
APPLYING POWER AND SIGNALS TO THE DC2266A
Keep Alive Osc – Enables or Disables the Internal Keep
Alive Oscillator:
n
n
Disabled (Default) – Keep Alive Oscillator is Disabled
Enabled – Keep Alive Oscillator is Enabled
Encode Term – Enables or Disables LVDS Internal Termination:
n
Disabled (Default) – Disables Internal Termination
n
Enabled – Enables Internal Termination
LVDS Current – Selects the LVDS Output Drive Current:
n
n
n
Randomizer – Enables Data Output Randomizer:
n
Disabled (Default) – Disables Data Output Randomizer
n
Enabled – Enables Data Output Randomizer
ABP – Enables or Disables Alternate Bit Polarity (ABP) Mode:
n
Disabled (Default) – Disables Alternate Bit Polarity
Enabled – Enables Alternate Bit Polarity (Before
Enabling ABP, Be Sure the Part is in Offset Binary Mode)
n
Output Test – Selects Digital Output Test Patterns:
n
1.75mA – LVDS Output Driver Current
None (Default) – ADC Data Presented at Output
n
2.1mA – LVDS Output Driver Current
All Out = 1 – All Digital Outputs Are 1
n
2.5mA – LVDS Output Driver Current
All Out = 0 – All Digital Outputs Are 0
n
n
3.0mA – LVDS Output Driver Current
n
3.5mA (Default) – LVDS Output Driver Current
n
4.0mA – LVDS Output Driver Current
n
4.5mA – LVDS Output Driver Current
Two’s Complement – Enables or Disables Two’s Complement Mode:
n
Enabled (Default) – Selects Two’s Complement Mode
n
Disabled – Selects Offset Binary Mode
Checkerboard – OF and D15-D0 Alternate Between
1 0101 0101 1010 0101 and 0 1010 1010 0101 1010
on Alternating Samples
Alternating – Digital Outputs Alternate Between All 1s
and All 0s on Alternating Samples
n
Once the desired settings are selected hit OK and PScope
will automatically update the register of the device on the
DC2266A demo board.
dc2266af
7
DEMO MANUAL DC2266A
PARTS LIST
ITEM
QTY
REFERENCE
PART DESCRIPTION
MANUFACTURER/PART NUMBER
1
2
2
C1, C24
CAP.,1.5pF, C0G, 50V ±0.25pF, 0201
MURATA, GRM0335C1H1R5CA01D
1
C2
CAP., 10μF, X7R, 16V, 10%, 0805
SAMSUNG, CL21B106KOQNNNE
3
2
C3, C12
CAP., 1μF, X5R, 25V, 10%, 0603
TDK, C1608X5R1E105K080AC
4
4
C4, C9, C16, C20
CAP., 10μF, X5R, 16V, 20%, 1206
TDK, C3216X5R1C106M
5
2
C5, C6
CAP., 100μF, X5R, 16V, 20%, 1210
TAIYO YUDEN, EMK325ABJ107MM-T
6
2
C7, C8
CAP., 2200pF, C0G, 25V, 5%, 0402
KEMET, C0402C222J3GACTU
7
3
C10, C26, C27
CAP., 0.1μF, X7R, 50V, 10%, 0402
TDK, C1005X7R1H104K
8
4
C11, C14, C15, C23
CAP., 0.1μF, X5R, 16V, 10%, 0402
AVX, 0402YD104KAT2A
9
1
C13
CAP., 2.2μF, X5R, 16V, 20%, 0603
AVX, 0603YD225MAT2A
10
1
C17
CAP., 2.2μF, X5R, 16V, 20%, 0402
TDK, C1005X5R1C225M050BC
11
0
C18
CAP., OPTION, 0402
OPTION
12
1
C19
CAP., 47μF, X5R, 16V, 20%, 1206
TDK, C3216X5R1C476M160AB
13
4
C21, C22, C25, C28
CAP., 4.7pF, NP0, 50V, ±0.25pF, 0402
TDK, C1005C0G1H4R7C
14
1
E1
TEST POINT, TURRET, 0.064" MTG. HOLE
MILL-MAX, 2308-2-00-80-00-00-07-0
15
3
E2, E3, E4
TEST POINT, TURRET, 0.094" MTG.HOLE
MILL-MAX, 2501-2-00-80-00-00-07-0
16
3
JP1, JP2, JP6
CONN., HEADER, 2 × 3, 2mm, THRU-HOLE,
VERTICAL
SAMTEC, TMM-103-02-L-D
17
2
JP3, JP4
CONN., HEADER, 1 × 3, 2mm, THRU-HOLE,
VERTICAL
SAMTEC, TMM-103-02-L-S
18
1
JP5
CONN., HEADER, 1 × 2, 2mm, THRU-HOLE,
VERTICAL
SAMTEC, TMM102-02-L-S
19
2
J1, J2
CONN., SMA 50Ω EDGE-LAUNCH
AMPHENOL CONNEX, 132372
20
2
J3, J4
CONN., SMA JACK, STRAIGHT, THRU-HOLE
AMPHENOL CONNEX, 132134
21
1
L1
IND., FERRITE BEAD, 47Ω @ 100MHz, 0603
MURATA, BLM18BB470SN1D
22
0
L2
IND., OPTION, 0603
OPTION
23
4
L3, L4, L5, L6
IND., CER. CHIP, 12nH, 2%, 0402
COILCRAFT, 0402CS-12NXGLU
24
1
P1
CONN., HIGH DENSITY ARRAY, MALE, 400 PINS
SAMTEC, SEAM-40-02.0-S-10-2-A-K-TR
25
4
R1, R2, R3, R5
RES., 33Ω, 1/16W, 5%, 0402
YAGEO, RC0402JR-0733RL
26
3
R4, R23, R24
RES., 4.99k, 1/16W, 1%, 0402
YAGEO, RC0402FR-074K99L
27
6
R6, R7, R8, R14, R17, R21
RES., 1k, 1/16W, 5%, 0402
YAGEO, RC0402JR-071KL
28
0
R9
RES., OPTION, 0805
OPTION
29
4
R10, R28, R29, R33
RES., 100Ω, 1/16W, 1%, 0402
YAGEO, RC0402FR-07100RL
30
6
R11, R12, R15, R25, R27, R32
RES., HIGH FREQ., 50Ω, 1/20W, 0.1%, 0402
VISHAY, FC0402E50R0BST1
31
1
R13
RES., 300Ω, 1/16W, 5%, 0402
YAGEO, RC0402JR-07300RL
32
1
R16
RES., 100Ω, 1/16W, 5%, 0402
YAGEO, RC0402JR-07100RL
34
3
R19, R20, R30
RES., HIGH POWER, 49.9Ω, 1/8W, 1%, 0402
VISHAY, CRCW040249R9FKEDHP
35
4
R18, R22, R35, R36
RES., 0Ω JUMPER, 1/16W, 0402
VISHAY, CRCW04020000Z0ED
8
dc2266af
DEMO MANUAL DC2266A
PARTS LIST
ITEM
QTY
REFERENCE
PART DESCRIPTION
MANUFACTURER/PART NUMBER
36
2
R26, R31
RES., 200Ω, 1/16W, 1%, 0402
VISHAY, CRCW0402200RFKED
37
1
R34
RES., 49.9Ω, 1/16W, 1%, 0402
YAGEO, RC0402FR-0749R9L
39
1
U1
ADC, 16-BIT, 210Msps, QFN
LINEAR TECH., LTC2107IUK#PBF
40
1
U2
IC, LDO LINEAR REGULATOR, 2.5V, DFN
LINEAR TECH., LT1965EDD-2.5#PBF
41
1
U3
IC, LDO LINEAR REGULATOR, 1.8V, DFN
LINEAR TECH., LT1965EDD-1.8#PBF
42
1
U4
IC, SERIAL EEPROM, TSSOP-8
MICROCHIP TECH., 24LC32A-I/ST
43
1
U5
IC, HIGH SPEED DIFF. AMP./DRIVER, QFN
LINEAR TECH., LTC6409IUDB#TRMPBF
44
7
XJP1, XJP2, XJP3, XJP4, XJP5, SHUNT, 2mm
XJP6, XJP7
SAMTEC, 2SN-BK-G
dc2266af
9
A
B
C
D
CLK-
CLK+
AIN-
J1
AIN+
J2
E4
J4
J3
1
1
1
1
R36
5
R18 0 OHMS
R8
2
PGA/SCK
VDD
SHDN
SHDN
-IN
Vocm
+IN
C26
+OUT
-OUT
0.1uF
C27
7
1
3
5
3/2
1X
1
6
4
2
R21 1K
OFF
ON
CS/LVDS
R26 200
5
4
RAND/SDI
3
CMOS
1
LVDS
R6
1K
VDD
C1 1.5pF C0G 0201
-
+
U5
LTC6409
AMPQVCC
0.1uF
JP2
4
C24 1.5pF C0G 0201
R31 200
SHDN
RUN
R7
1K
VDD
3
6
5
2
R13
300
1K
JP3
SHUTDOWN
0.1uF
C10
R28 100
R29 100
R22 0 OHMS
0 OHMS
R10 100
R33 100
R35 0 OHMS
AMPQVCC
9
V+
4
V+
V-
10
V- PAD
11
R25 50
JP1
6
4
2
SER
PAR
VDD
R17
1K
VDD
4.7pF NP0
C22
R12 50
R11 50
4.7pF NP0
C25
R15 50
1
2
1
2
AMPVCC
1
3
1
2
C3
1.0uF
PAR/!SER
3
OPT
0402
C18
1.0uF
C12
1206
20%
47uF
C19
6
4
3
5
2
1
JP6
R34 49.9
VDD
LVDS
CML
12nH
L6
L4
12nH
CLOCK TERM
C28
4.7pF NP0
R27 50
R32 50
C21
4.7pF NP0
LV PECL
OPT
0603
L2
12nH
L5
12nH
L3
3
C15
0.1uF
OVDD
R30
49.9
C13
2.2uF
VDD
EXT
REF
E1
C14
0.1uF
R20
49.9
R19
49.9
C17
2.2uF
GND
VCM
GND
AIN-
AIN+
GND
VDD
VDD
VDD
GND
GND
SENSE
C8
2200pF
COG/NPO
2
OVDD
U1
LTC2107
2
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
CUSTOMER NOTICE
R16 100
1
JP5
D13/12P
2
TP1
SCALE = NONE
C. MAYOTT
M.HAWKINS
25
26
27
28
29
30
31
32
33
34
35
36
1
D1/0-
D1/0+
D3/2-
D3/2+
D5/4-
D5/4+
D7/6-
D7/6+
D9/8-
D9/8+
CLKOUT-
CLKOUT+
D11/10-
D11/10+
D13/12-
D13/12+
D15/14-
D15/14+
OF-
OF+
1
DEMO CIRCUIT
IC NO. LTC2107,LTC6409
DATE: Tuesday, March 17, 2015
N/A
SIZE
DC2266A
SHEET
1
OF
2
01A
REV.
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900 www.linear.com
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
1
LTC2107 AND LTC6409 COMBO BOARD
TECHNOLOGY
PGA/SCK
RAND/SDI
CS/LVDS
TITLE: SCHEMATIC
SDO
D5/D4N
D5/D4P
D7/6N
D7/6P
D9/8N
D9/8P
CLKOUTN
CLKOUTP
D11/D10N
D11/10P
D13/12N
APPROVALS
SDO
OVDD
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO
PCB DES.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
APP ENG.
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
C2
10uF
0805
SHDN
C7
2200pF
COG/NPO
C11 0.1uF
12
11
10
9
8
7
6
5
4
3
2
1
R14
1K
PAR/!SER
48
2
1
2
1
V8
PGA
RAND
GND
49
GND
47
GND
13
GND
46
ENC+
14
43
SDI
44
SCK
45
PAR/SER
ENC15
CS
GND
16
SHDN
17
SDO
18
40
OFP
41
OVDD
42
OGND
OGND
19
37
D1/D0N
21
OVdd
20
38
OFN
D1/D0P
39
D15/14P
D3/D2N
22
D15/14N
D3/D2P
23
10
24
5
A
B
C
D
DEMO MANUAL DC2266A
SCHEMATIC DIAGRAM
dc2266af
A
B
C
D
GND
PG_M2C
GND
GND
HA00_P_CC
HA00_N_CC
GND
HA04_P
HA04_N
GND
HA08_P
HA08_N
GND
HA12_P
HA12_N
GND
HA15_P
HA15_N
GND
HA19_P
HA19_N
GND
HB02_P
HB02_N
GND
HB04_P
HB04_N
GND
HB08_P
HB08_N
GND
HB12_P
HB12_N
GND
HB16_P
HB16_N
GND
HB19_P
HB19_N
GND
VADJ
E3
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37
F38
F39
F40
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
5
C9
10uF
16V
1206
VIN
SEAM-10X40PIN
P1F
E2
3.3V-5V
VIN
GND
DP1_M2C_P
DP1_M2C_N
GND
GND
DP2_M2C_P
DP2_M2C_N
GND
GND
DP3_M2C_P
DP3_M2C_N
GND
GND
DP4_M2C_P
DP4_M2C_N
GND
GND
DP5_M2C_P
DP5_M2C_N
GND
GND
DP1_C2M_P
DP1_C2M_N
GND
GND
DP2_C2M_P
DP2_C2M_N
GND
GND
DP3_C2M_P
DP3_C2M_N
GND
GND
DP4_C2M_P
DP4_C2M_N
GND
GND
DP5_C2M_P
DP5_C2M_N
GND
SEAM-10X40PIN
P1A
VDD
6
7
8
SHDN
IN
IN
SENSE
OUT
OUT
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
L1
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
G37
G38
G39
G40
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
VDD
C16
10uF
16V
1206
FERRITE BEAD, 47 OHMS
3
2
1
LT1965EDD-2.5
U2
SEAM-10X40PIN
GND
CLK0_C2M_P
CLK0_C2M_N
GND
GND
LA00_P_CC
LA00_N_CC
GND
LA03_P
LA03_N
GND
LA08_P
LA08_N
GND
LA12_P
LA12_N
GND
LA16_P
LA16_N
GND
LA20_P
LA20_N
GND
LA22_P
LA22_N
GND
LA25_P
LA25_N
GND
LA29_P
LA29_N
GND
LA31_P
LA31_N
GND
LA33_P
LA33_N
GND
VADJ
GND
SEAM-10X40PIN
RES1
GND
GND
DP9_M2C_P
DP9_M2C_N
GND
GND
DP8_M2C_P
DP8_M2C_N
GND
GND
DP7_M2C_P
DP7_M2C_N
GND
GND
DP6_M2C_P
DP6_M2C_N
GND
GND
GBTCLK1_M2C_P
GBTCLK1_M2C_N
GND
GND
DP9_C2M_P
DP9_C2M_N
GND
GND
DP8_C2M_P
DP8_C2M_N
GND
GND
DP7_C2M_P
DP7_C2M_N
GND
GND
DP6_C2M_P
DP6_C2M_N
GND
GND
RES0
P1B
P1G
GND
5
GND
9
GND
4
C4
10uF
16V
1206
4
D3/2-
D7/6-
D11/10-
D15/14-
OF-
C6
100uF
16V
1210
D3/2+
D7/6+
D11/10+
D15/14+
OF+
GND
DP0_C2M_P
DP0_C2M_N
GND
GND
DP0_M2C_P
DP0_M2C_N
GND
GND
LA06_P
LA06_N
GND
GND
LA10_P
LA10_N
GND
GND
LA14_P
LA14_N
GND
GND
LA18_P_CC
LA18_N_CC
GND
GND
LA27_P
LA27_N
GND
GND
SCL
SDA
GND
GND
GA0
12P0V
GND
12P0V
GND
3P3V
GND
SCL
6
7
8
SHDN
IN
IN
OUT
OUT
SENSE
U3
3
2
1
D1/0+
D5/4+
D9/8+
3
C20
10uF
16V
1206
OVDD
D1/0-
D5/4-
D9/8-
D13/12-
3
C5
100uF
16V
1210
CLKOUT+
CLKOUT-
DATA CLOCK
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
J34
J35
J36
J37
J38
J39
J40
R9
OPT
VIN
3.3V_AUX
GND
CLK1_C2M_P
CLK1_C2M_N
GND
GND
HA03_P
HA03_N
GND
HA07_P
HA07_N
GND
HA11_P
HA11_N
GND
HA14_P
HA14_N
GND
HA18_P
HA18_N
GND
HA22_P
HA22_N
GND
HB01_P
HB01_N
GND
PB07_P
HB07_N
GND
HB11_P
HB11_N
GND
HB15_P
HB15_N
GND
HB18_P
HB18_N
GND
VIO_B_M2C
GND
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
SEAM-10X40PIN
P1J
SEAM-10X40PIN
PG_C2M
GND
GND
GBTCLK0_M2C_P
GBTCLK0_M2C_N
GND
GND
LA01_P_CC
LA01_N_CC
GND
LA05_P
LA05_N
GND
LA09_P
LA09_N
GND
LA13_P
LA13_N
GND
LA17_P_CC
LA17_N_CC
GND
LA23_P
LA23_N
GND
LA26_P
LA26_N
GND
TCK
TDI
TDO
3P3VAUX
TMS
TRST_N
GA1
3P3V
GND
3P3V
GND
3P3V
P1D
D13/12+
PGA/SCK
RAND/SDI
SDO
CS/LVDS
LT1965EDD-1.8
SEAM-10X40PIN
SDA
33
33
33
33
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
H36
H37
H38
H39
H40
R1
R2
R3
R5
VREF_A_M2C
PRSNT_M2C_N
GND
CLK0_M2C_P
CLK0_M2C_N
GND
LA02_P
LA02_N
GND
LA04_P
LA04_N
GND
LA07_P
LA07_N
GND
LA11_P
LA11_N
GND
LA15_P
LA15_N
GND
LA19_P
LA19_N
GND
LA21_P
LA21_N
GND
LA24_P
LA24_N
GND
LA28_P
LA28_N
GND
LA30_P
LA30_N
GND
LA32_P
LA32_N
GND
VADJ
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
P1H
SEAM-10X40PIN
P1C
4
GND
5
GND
9
GND
4
GND
HA01_P_CC
HA01_N_CC
GND
GND
HA05_P
HA05_N
GND
HA09_P
HA09_N
GND
HA13_P
HA13_N
GND
HA16_P
HA16_N
GND
HA20_P
HA20_N
GND
HB03_P
HB03_N
GND
HB05_P
HB05_N
GND
HB09_P
HB09_N
GND
HB13_P
HB13_N
GND
HB21_P
HB21_N
GND
HB20_P
HB20_N
GND
VADJ
GND
VREF_B_M2C
GND
GND
CLK1_M2C_P
CLK1_M2C_N
GND
HA02_P
HA02_N
GND
HA06_P
HA06_N
GND
HA10_P
HA10_N
GND
HA17_P_CC
HA17_N_CC
GND
HA21_P
HA21_N
GND
HA23_P
HA23_N
GND
HB00_P_CC
HB00_N_CC
GND
HB06_P_CC
HB06_N_CC
GND
HB10_P
HB10_N
GND
HB14_P
HB14_N
GND
HB17_P_CC
HB17_N_CC
GND
VIO_B_M2C
U4
SDA
SCL
2
M.HAWKINS
SCALE = NONE
C. MAYOTT
6
5
7
3
2
1
4.99K
R23
4.99K
R24
X11
X12
X5
X6
X15
X14
X13
TECHNOLOGY
1
DEMO CIRCUIT
IC NO. LTC2107,LTC6409
DATE: Tuesday, March 17, 2015
N/A
SIZE
DC2266A
SHEET
2
OF
2
01A
REV.
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900 www.linear.com
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
PROG
WP
EEPROM
LTC2107 AND LTC6409 COMBO BOARD
TITLE: SCHEMATIC
X10
X4
2
JP4
R4
4.99K
3.3V_AUX
1
CHASSIS GROUND
X9
X8
X7
X3
X2
X1
TRANSFER STRIP
MOUNTING HOLES ON THERMAL
SCL
SDA
WP
A2
A1
A0
0.1uF
C23
SDA
SCL
APPROVALS
24LC32A
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
CUSTOMER NOTICE
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K30
K31
K32
K33
K34
K35
K36
K37
K38
K39
K40
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
E37
E38
E39
E40
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO
PCB DES.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
APP ENG.
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
SEAM-10X40PIN
P1K
SEAM-10X40PIN
P1E
2
8
VCC
VSS
4
1
3
5
A
B
C
D
DEMO MANUAL DC2266A
SCHEMATIC DIAGRAM
dc2266af
11
DEMO MANUAL DC2266A
DEMONSTRATION BOARD IMPORTANT NOTICE
Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:
This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT
OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety
measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union
directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.
If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date
of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU
OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS
FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR
ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or
agency certified (FCC, UL, CE, etc.).
No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance,
customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.
Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and
observe good laboratory practice standards. Common sense is encouraged.
This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application
engineer.
Mailing Address:
Linear Technology
1630 McCarthy Blvd.
Milpitas, CA 95035
Copyright © 2004, Linear Technology Corporation
12 Linear Technology Corporation
dc2266af
LT 0515 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2015
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