PDF Data Sheet Rev. A

Dual, 16-/12-Bit nanoDAC+
with SPI Interface
AD5689/AD5687
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VDD
VLOGIC
GND
VREF
AD5689/AD5687
SCLK
SYNC
SDIN
INTERFACE LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
VOUTA
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
VOUTB
BUFFER
SDO
LDAC RESET
POWER-ON
RESET
GAIN =
×1/×2
RSTSEL
GAIN
POWERDOWN
LOGIC
11255-001
High relative accuracy (INL): ±2 LSB maximum at 16 bits
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
TUE: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User-selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Low glitch: 0.5 nV-sec
Robust 4 kV HBM and 1.5 kV FICDM ESD ratings
Low power: 3.3 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
Figure 1.
APPLICATIONS
Optical transceivers
Base station power amplifiers
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
Table 1. Related Devices
The AD5689/AD5687 members of the nanoDAC+™ family are
low power, dual, 16-/12-bit, buffered voltage output digital-toanalog converters (DACs). The devices include a gain select pin
giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The
AD5689/AD5687 operate from a single 2.7 V to 5.5 V supply, are
guaranteed monotonic by design, and exhibit less than 0.1% FSR
gain error and 1.5 mV offset error performance. Both devices are
available in a 3 mm × 3 mm LFCSP and a TSSOP package.
Interface
SPI
The AD5689/AD5687 also incorporate a power-on reset circuit
and a RSTSEL pin that ensure that the DAC outputs power up
to zero scale or midscale and remain there until a valid write
takes place. Each part contains a per channel power-down feature
that reduces the current consumption of the device to 4 µA at
3 V while in power-down mode.
The AD5689/AD5687 use a versatile serial peripheral interface
that operates at clock rates up to 50 MHz. Both devices contain
a VLOGIC pin that is intended for 1.8 V/3 V/5 V logic.
Rev. A
I2 C
Reference
Internal
External
Internal
External
16-Bit
AD5689R
AD5689
Not applicable
Not applicable
12-Bit
AD5687R
AD5687
AD5697R
Not applicable
PRODUCT HIGHLIGHTS
1.
2.
3.
High Relative Accuracy (INL).
AD5689 (16-bit): ±2 LSB maximum
AD5687 (12-bit): ±1 LSB maximum
Excellent DC Performance.
Total unadjusted error: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
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Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technical Support
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AD5689/AD5687
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Serial Interface ............................................................................ 18
Applications ....................................................................................... 1
Standalone Operation ................................................................ 19
Functional Block Diagram .............................................................. 1
Write and Update Commands .................................................. 19
General Description ......................................................................... 1
Daisy-Chain Operation ............................................................. 19
Product Highlights ........................................................................... 1
Readback Operation .................................................................. 20
Revision History ............................................................................... 2
Power-Down Operation ............................................................ 20
Specifications..................................................................................... 3
Load DAC (Hardware LDAC Pin) ........................................... 21
AC Characteristics ........................................................................ 4
LDAC Mask Register ................................................................. 21
Timing Characteristics ................................................................ 5
Hardware Reset (RESET) .......................................................... 22
Daisy-Chain and Readback Timing Characteristics................ 6
Reset Select Pin (RSTSEL) ........................................................ 22
Absolute Maximum Ratings ............................................................ 8
Applications Information .............................................................. 23
ESD Caution .................................................................................. 8
Microprocessor Interfacing ....................................................... 23
Pin Configurations and Function Descriptions ........................... 9
AD5689/AD5687 to ADSP-BF531 Interface .......................... 23
Typical Performance Characteristics ........................................... 10
AD5689/AD5687 to SPORT Interface..................................... 23
Terminology .................................................................................... 15
Layout Guidelines....................................................................... 23
Theory of Operation ...................................................................... 17
Galvanically Isolated Interface ................................................. 23
Digital-to-Analog Converters (DACs) .................................... 17
Outline Dimensions ....................................................................... 24
Transfer Function ....................................................................... 17
Ordering Guide .......................................................................... 24
DAC Architecture ....................................................................... 17
REVISION HISTORY
1/16—Rev. 0 to Rev. A
Change to Table 14 ......................................................................... 21
2/13—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
AD5689/AD5687
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; CL = 200 pF.
Table 2.
Parameter
STATIC PERFORMANCE1
AD5689
Resolution
Relative Accuracy
Differential Nonlinearity
AD5687
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Total Unadjusted Error
Min
Unit
Bits
LSB
LSB
Test Conditions/Comments
Gain = 2
Gain = 1
Guaranteed monotonic by design
±1
±1
0.15
Bits
LSB
LSB
mV
mV
% of FSR
% of FSR
% of FSR
% of FSR
µV/°C
ppm
mV/V
±2
±3
±2
µV
µV/mA
µV
Due to single-channel, full-scale output change
Due to load current change
Due to powering down (per channel)
Gain = 1
Gain = 2; see Figure 23
RL = ∞
RL = 1 kΩ
80
V
V
nF
nF
kΩ
µV/mA
80
µV/mA
40
25
2.5
mA
Ω
µs
See Figure 23
Coming out of power-down mode; VDD = 5 V
90
180
µA
µA
V
V
kΩ
kΩ
VREF = VDD = VLOGIC=5.5 V, gain = 1
VREF = VDD = VLOGIC=5.5 V, gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
µA
V
V
pF
Per pin
0.4
+0.1
+0.01
±0.02
±0.01
0
0
±1
±1
1.5
±1.5
±0.1
±0.1
±0.1
±0.2
VREF
2 × VREF
2
10
1
1
1
Reference Input Impedance
LOGIC INPUTS2
Input Current
Input Low Voltage (VINL)
Input High Voltage (VINH)
Pin Capacitance
±2
±3
±1
±0.12
Short-Circuit Current4
Load Impedance at Rails5
Power-Up Time
REFERENCE INPUT
Reference Current6
Reference Input Range
±1
±1
12
Capacitive Load Stability
Resistive Load3
Load Regulation
Max
16
Offset Error Drift2
Gain Temperature Coefficient2
DC Power Supply Rejection Ratio2
DC Crosstalk2
OUTPUT CHARACTERISTICS2
Output Voltage Range
Typ
VDD
VDD/2
16
32
±2
0.3 × VLOGIC
0.7 × VLOGIC
2
Rev. A | Page 3 of 24
Guaranteed monotonic by design
All 0s loaded to DAC register
All 1s loaded to DAC register
Gain = 2; TSSOP
Gain = 1; TSSOP
Of FSR/°C
DAC code = midscale, VDD = 5 V ± 10%
5 V ± 10%, DAC code = midscale;
−30 mA ≤ IOUT ≤ 30 mA
3 V ± 10%, DAC code = midscale;
−20 mA ≤ IOUT ≤ 20 mA
AD5689/AD5687
Parameter
LOGIC OUTPUTS (SDO)2
Output Low Voltage (VOL)
Output High Voltage (VOH)
Floating State Output Capacitance
POWER REQUIREMENTS
VLOGIC
ILOGIC
VDD
VDD
IDD
Normal Mode7
All Power-Down Modes8
Data Sheet
Min
Typ
Max
Unit
Test Conditions/Comments
0.4
V
V
pF
ISINK = 200 μA
ISOURCE = 200 μA
5.5
3
5.5
5.5
V
µA
V
V
0.7
4
6
mA
µA
µA
VLOGIC − 0.4
4
1.8
2.7
VREF + 1.5
0.59
1
Gain = 1
Gain = 2
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
−40°C to +85°C
−40°C to +105°C
1
DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV; it exists only when VREF = VDD with gain = 1 or when VREF/2 =
VDD with gain = 2. Linearity is calculated using a reduced code range of 256 to 65,280 (AD5689) and 12 to 4080 (AD5687).
2
Guaranteed by design and characterization; not production tested.
3
Channel A can have an output current of up to 30 mA. Similarly, Channel B can have an output current of up to 30 mA, up to a junction temperature of 110°C.
4
VDD = 5 V. The devices include current limiting that is intended to protect them during temporary overload conditions. Junction temperature may be exceeded during
current limit, but operation above the specified maximum operation junction temperature can impair device reliability.
5
When drawing a load current at either rail, the output voltage headroom, with respect to that rail, is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 23).
6
Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift.
7
Interface inactive. Both DACs active. DAC outputs unloaded.
8
Both DACs powered down.
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise
noted. Temperature range = −40°C to +105°C, typical at 25°C. Guaranteed by design and characterization, not production tested.
Table 3.
Parameter1
Output Voltage Settling Time
AD5689
AD5687
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Total Harmonic Distortion (THD)2
Output Noise Spectral Density (NSD)
Output Noise
Signal-to-Noise Ratio (SNR)
Spurious Free Dynamic Range (SFDR)
Signal-to-Noise-and-Distortion Ratio
(SINAD)
1
2
Min
Typ
Max
Unit
Test Conditions/Comments
5
5
0.8
0.5
0.13
0.1
0.2
0.3
−80
300
6
90
83
80
8
7
µs
µs
V/µs
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
dB
nV/√Hz
µV p-p
dB
dB
dB
¼ to ¾ scale settling to ±2 LSB
¼ to ¾ scale settling to ±2 LSB
See the Terminology section.
Digitally generated sine wave at 1 kHz.
Rev. A | Page 4 of 24
1 LSB change around major carry
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
DAC code = midscale, 10 kHz, gain = 2
0.1 Hz to 10 Hz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
Data Sheet
AD5689/AD5687
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Power-Up Time
2.7 V ≤ VLOGIC ≤ 5.5 V
Min
Max
20
10
10
10
5
5
10
20
10
15
20
20
30
30
4.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (update single channel or both channels)
SYNC falling edge to SCLK fall ignore
LDAC pulse width low
SCLK falling edge to LDAC rising edge
SCLK falling edge to LDAC falling edge
RESET minimum pulse width low
RESET pulse activation time
Time that is required to exit power-down mode and enter
normal mode of operation; 24th clock edge to 90% of DAC
midscale value with output unloaded
Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 2.7 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
t9
t1
SCLK
t8
t3
t4
t2
t7
SYNC
t6
t5
SDIN
DB23
DB0
t12
t10
LDAC1
t11
LDAC2
RESET
VOUTX
t13
t14
11255-002
1
1.8 V ≤ VLOGIC < 2.7 V
Min
Max
33
16
16
15
5
5
15
20
16
25
30
20
30
30
4.5
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. A | Page 5 of 24
AD5689/AD5687
Data Sheet
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4
and Figure 5. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. VDD =
2.7 V to 5.5 V.
Table 5.
Parameter1
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
1.8 V ≤ VLOGIC < 2.7 V
Min
Max
66
33
33
33
5
5
15
60
60
36
15
2.7 V ≤ VLOGIC ≤ 5.5 V
Min
Max
40
20
20
20
5
5
10
30
30
25
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
Minimum SYNC high time
SDO data valid from SCLK rising edge
SCLK falling edge to SYNC rising edge
t12
15
10
ns
SYNC rising edge to SCLK rising edge
1
Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
Circuit and Timing Diagrams
200µA
VOH (MIN)
CL
20pF
200µA
11255-003
TO OUTPUT
PIN
IOL
IOH
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
SCLK
48
24
t11
t8
t12
t4
SYNC
SDIN
t6
DB23
DB0
INPUT WORD FOR DAC N
DB23
DB0
t10
INPUT WORD FOR DAC N + 1
DB23
SDO
UNDEFINED
DB0
INPUT WORD FOR DAC N
Figure 4. Daisy-Chain Timing Diagram
Rev. A | Page 6 of 24
11255-004
t5
Data Sheet
AD5689/AD5687
t1
SCLK
24
1
t8
t4
t3
24
1
t7
t2
t9
SYNC
t6
t5
DB23
DB0
DB23
INPUT WORD SPECIFIES
REGISTER TO BE READ
SDO
DB23
DB0
NOP CONDITION
t10
DB0
DB23
UNDEFINED
DB0
SELECTED REGISTER DATA
CLOCKED OUT
Figure 5. Readback Timing Diagram
Rev. A | Page 7 of 24
11255-005
SDIN
AD5689/AD5687
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to GND
VLOGIC to GND
VOUT to GND
VREF to GND
Digital Input Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
16-Lead TSSOP, θJA Thermal Impedance,
0 Airflow (4-Layer Board)
16-Lead LFCSP, θJA Thermal Impedance,
0 Airflow (4-Layer Board)
Reflow Soldering Peak Temperature,
Pb Free (J-STD-020)
ESD1
FICDM
1
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−40°C to +105°C
−65°C to +150°C
125°C
112.6°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
70°C/W
260°C
4 kV
1.5 kV
Human body model (HBM) classification.
Rev. A | Page 8 of 24
Data Sheet
AD5689/AD5687
13 RESET
VOUTA 1
GND 2
VDD 3
12 SDIN
AD5689/
AD5687
VREF 1
11 SYNC
10 SCLK
9 VLOGIC
GAIN 8
LDAC 7
SDO 6
VOUTB 5
NC 4
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO
THIS PIN.
2. THE EXPOSED PAD MUST BE TIED TO GND.
11255-006
TOP VIEW
(Not to Scale)
16
RSTSEL
2
15
RESET
VOUTA 3
14
SDIN
NC
GND 4
AD5689/
AD5687
13
SYNC
VDD 5
TOP VIEW
(Not to Scale)
12
SCLK
VLOGIC
NC 6
11
VOUTB 7
10
GAIN
SDO 8
9
LDAC
NOTES
1. NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
Figure 6. 16-Lead LFCSP Pin Configuration
11255-007
14 RSTSEL
16 NC
15 VREF
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 7. 16-Lead TSSOP Pin Configuration
Table 7. Pin Function Descriptions
LFCSP
1
2
3
Pin No.
TSSOP
3
4
5
Mnemonic
VOUTA
GND
VDD
4
5
6
2
7
8
NC
VOUTB
SDO
7
9
LDAC
8
10
GAIN
9
10
11
12
VLOGIC
SCLK
11
13
SYNC
12
14
SDIN
13
15
RESET
14
16
RSTSEL
15
16
17
1
6
N/A
VREF
NC
EPAD
Description
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the AD5689/AD5687.
Power Supply Input. The AD5689/AD5687 can be operated from 2.7 V to 5.5 V. Decouple the supply
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
No Connect. Do not connect to this pin.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Serial Data Output. SDO can be used to daisy-chain a number of AD5689/AD5687 devices together,
or it can be used for readback. The serial data is transferred on the rising edge of SCLK and is valid
on the falling edge of the clock.
LDAC can be operated in two modes: asynchronous and synchronous. Pulsing this pin low allows
either or both DAC registers to be updated if the input registers have new data; both DAC outputs can
be updated simultaneously. This pin can also be tied permanently low.
Gain Select. When this pin is tied to GND, both DACs output a span from 0 V to VREF. If this pin is tied
to VLOGIC, both DACs output a span of 0 V to 2 × VREF.
Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, data is transferred in on the falling edges of the next 24 clocks.
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the
falling edge of the serial clock input.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC
pulses are ignored. When RESET is activated, the input register and the DAC register are updated with
zero scale or midscale, depending on the state of the RSTSEL pin.
Power-On Reset Select. Tying this pin to GND powers up both DACs to zero scale. Tying this pin to
VLOGIC powers up both DACs to midscale.
Reference Input Voltage.
No Connect. Do not connect to this pin.
Exposed Pad. The exposed pad must be tied to GND.
Rev. A | Page 9 of 24
AD5689/AD5687
Data Sheet
10
10
8
8
6
6
4
4
2
2
INL (LSB)
0
–2
–4
0
–2
–4
–6
–6
0
10000
20000
30000
40000
50000
60000
CODE
–10
11255-008
–10
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
–8
0
625
2500
3125
3750 4096
Figure 11. AD5687 INL vs. Code
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
DNL (LSB)
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
–1.0
0
10000
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
–0.8
20000
30000
40000
50000
60000
CODE
–1.0
11255-010
–0.8
0
625
2500
3125
3750 4096
Figure 12. AD5687 DNL vs. Code
10
8
8
6
6
4
4
ERROR (LSB)
10
INL
0
DNL
–2
–4
2
INL
0
DNL
–2
–4
–6
–6
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
–10
–40
10
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
–8
60
110
TEMPERATURE (°C)
11255-012
–8
1875
CODE
Figure 9. AD5689 Differential Nonlinearity (DNL) vs. Code
2
1250
11255-011
DNL (LSB)
1875
CODE
Figure 8. AD5689 Integral Nonlinearity (INL) vs. Code
ERROR (LSB)
1250
11255-009
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
–8
Figure 10. INL Error and DNL Error vs. Temperature
–10
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VREF (V)
Figure 13. INL Error and DNL Error vs. VREF
Rev. A | Page 10 of 24
4.5
5.0
11255-013
INL (LSB)
TYPICAL PERFORMANCE CHARACTERISTICS
AD5689/AD5687
10
0.10
8
0.08
6
0.06
4
0.04
ERROR (% of FSR)
2
INL
0
DNL
–2
–4
–6
GAIN ERROR
0
FULL-SCALE ERROR
–0.02
–0.04
–0.06
VDD = 5V
–0.08 T = 25°C
A
REFERENCE = 2.5V
–0.10
2.7
3.2
3.7
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
–10
2.7
3.2
3.7
4.2
4.7
11255-014
–8
0.02
5.2
SUPPLY VOLTAGE (V)
4.2
4.7
11255-017
ERROR (LSB)
Data Sheet
5.2
SUPPLY VOLTAGE (V)
Figure 17. Gain Error and Full-Scale Error vs. Supply Voltage
Figure 14. INL Error and DNL Error vs. Supply Voltage
1.5
0.10
0.08
1.0
0.04
0.5
FULL-SCALE ERROR
0.02
0
ERROR (mV)
GAIN ERROR
–0.02
OFFSET ERROR
–1.0
40
60
80
100
120
TEMPERATURE (°C)
4.2
4.7
5.2
0.10
TOTAL UNADJUSTED ERROR (% of FSR)
1.2
1.0
0.8
0.6
ZERO-CODE ERROR
0.2
20
40
60
80
100
120
TEMPERATURE (°C)
11255-016
OFFSET ERROR
0
3.7
Figure 18. Zero-Code Error and Offset Error vs. Supply Voltage
VDD = 5V
1.4 T = 25°C
A
REFERENCE = 2.5V
–20
3.2
SUPPLY VOLTAGE (V)
Figure 15. Gain Error and Full-Scale Error vs. Temperature
0.4
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–1.5
2.7
11255-015
VDD = 5V
–0.08 T = 25°C
A
REFERENCE = 2.5V
–0.10
–40
–20
0
20
11255-018
–0.06
ERROR (mV)
0
–0.5
–0.04
0
–40
ZERO-CODE ERROR
VDD = 5V
0.09 TA = 25°C
INTERNAL REFERENCE = 2.5V
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 19. Total Unadjusted Error (TUE) vs. Temperature
Figure 16. Zero-Code Error and Offset Error vs. Temperature
Rev. A | Page 11 of 24
11255-019
ERROR (% of FSR)
0.06
Data Sheet
0.10
1.0
0.08
0.8
0.06
0.6
0.04
0.4
0.02
0.2
0
–0.02
–0.2
–0.04
–0.4
–0.06
–0.6
VDD = 5V
–0.08 T = 25°C
A
INTERNAL REFERENCE = 2.5V
–0.10
2.7
3.2
3.7
4.2
SOURCING 5V
SOURCING 2.7V
–0.8
4.7
5.2
SUPPLY VOLTAGE (V)
–1.0
0
5
10
15
20
25
30
LOAD CURRENT (mA)
Figure 20. TUE vs. Supply Voltage, Gain = 1
Figure 23. Headroom/Footroom vs. Load Current
0
7
VDD = 5V
6 TA = 25°C
GAIN = 2
INTERNAL
5 REFERENCE = 2.5V
–0.01
–0.02
–0.03
4
FULL SCALE
THREE-QUARTER SCALE
VOUT (V)
–0.04
–0.05
–0.06
3
ONE-QUARTER SCALE
ZERO SCALE
0
–0.08
40000
50000
60000 65535
–2
–0.06
CODE
–0.04
–0.02
0
0.02
0.04
0.06
LOAD CURRENT (A)
Figure 21. TUE vs. Code
11255-024
–1
11255-021
VDD = 5V
–0.09 T = 25°C
A
INTERNAL REFERENCE = 2.5V
–0.10
0
10000
20000
30000
25
MIDSCALE
2
1
–0.07
Figure 24. Source and Sink Capability at 5 V
5
VDD = 5V
TA = 25°C
EXTERNAL
REFERENCE = 2.5V
VDD = 3V
TA = 25°C
4 EXTERNAL REFERENCE = 2.5V
GAIN = 1
20
FULL SCALE
3
VOUT (V)
15
10
2
THREE-QUARTER SCALE
MIDSCALE
1
ONE-QUARTER SCALE
0
ZERO SCALE
5
0
540
560
580
600
IDD FULL SCALE (V)
620
640
–2
–0.06
–0.04
–0.02
0
0.02
0.04
LOAD CURRENT (A)
Figure 25. Source and Sink Capability at 3 V
Figure 22. IDD Histogram
Rev. A | Page 12 of 24
0.06
11255-025
–1
11255-022
HITS
TOTAL UNADJUSTED ERROR (% of FSR)
SINKING 5V
0
11255-023
∆VOUT (V)
SINKING 2.7V
11255-020
TOTAL UNADJUSTED ERROR (% of FSR)
AD5689/AD5687
Data Sheet
AD5689/AD5687
3
CHANNEL A
CHANNEL B
SYNC
1.4
1.0
2
0.8
FULL SCALE
GAIN = 1
1
0.4
0
–40
10
60
11255-026
0.2
110
TEMPERATURE (°C)
0
–5
3.5
0
5
10
TIME (µs)
Figure 26. Supply Current vs. Temperature
4.0
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
11255-029
0.6
GAIN = 2
VOUT (V)
SUPPLY CURRENT (mA)
1.2
Figure 29. Exiting Power-Down to Midscale
2.5008
DAC A
DAC B
2.5003
3.0
VOUT (V)
VOUT (V)
2.5
2.0
2.4998
1.5
40
80
160
320
TIME (µs)
2.4988
11255-027
VDD = 5V
0.5 TA = 25°C
REFERENCE = 2.5V
¼ TO ¾ SCALE
0
10
20
0
0.05
4
6
8
10
12
TIME (µs)
Figure 27. Settling Time, 5 V
0.06
2
11255-030
CHANNEL B
TA = 25°C
VDD = 5.25V
REFERENCE = 2.5V
POSITIVE MAJOR CODE TRANSITION
ENERGY = 0.227206nV-sec
2.4993
1.0
Figure 30. Digital-to-Analog Glitch Impulse
0.003
6
CHANNEL A
CHANNEL B
VDD
CHANNEL B
5
3
0.02
2
0.01
1
0
0
VOUT AC-COUPLED (V)
0.03
VDD (V)
4
0.001
0
TA = 25°C
REFERENCE = 2.5V
–0.01
–10
–5
0
5
TIME (µs)
10
–1
15
Figure 28. Power-On Reset to 0 V
–0.002
0
5
10
15
20
TIME (µs)
Figure 31. Analog Crosstalk, Channel A
Rev. A | Page 13 of 24
25
11255-031
–0.001
11255-028
VOUT (V)
0.002
0.04
AD5689/AD5687
Data Sheet
4.0
T
0nF
0.1nF
10nF
0.22nF
4.7nF
3.9
3.8
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
VOUT (V)
3.7
1
3.6
3.5
3.4
3.3
3.2
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
A CH1
802mV
1.600
1.605
1.610
1.615
1.620
1.625
1.630
TIME (ms)
Figure 32. 0.1 Hz to 10 Hz Output Noise Plot
Figure 34. Settling Time vs. Capacitive Load
20
0
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
–10
BANDWIDTH (dB)
–40
–60
–80
–100
–120
–140
–20
–30
–40
–50
–180
0
2000 4000 6000 8000 10000 12000 14000 16000 18000 20000
FREQUENCY (Hz)
11255-033
–160
Figure 33. Total Harmonic Distortion at 1 kHz
VDD = 5V
TA = 25°C
REFERENCE = 2.5V, ±0.1V p-p
–60
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 35. Multiplying Bandwidth, Reference = 2.5 V, ±0.1 V p-p,
10 kHz to 10 MHz
Rev. A | Page 14 of 24
11255-035
0
–20
THD (dBV)
1.595
11255-034
M1.0s
3.0
1.590
11255-032
CH1 10µV
3.1
Data Sheet
AD5689/AD5687
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. Typical INL vs. code plots are shown Figure 8 and
Figure 11.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. Typical DNL vs. code plots are shown in Figure 9 and
Figure 12.
Zero-Code Error
Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the device because the output of the DAC cannot go below 0 V
due to a combination of the offset errors in the DAC and the
output amplifier. Zero-code error is expressed in mV. A plot of
zero-code error vs. temperature is shown in Figure 16.
Full-Scale Error
Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed in
percent of full-scale range (% of FSR). A plot of full-scale error
vs. temperature is shown in Figure 15.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal and is expressed as % of FSR.
Offset Error Drift
Offset error drift is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.
Gain Temperature Coefficient
Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in ppm
of FSR/°C.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured on the device with
Code 512 loaded in the DAC register. It can be negative or
positive.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. It is the ratio of the change in VOUT to a
change in VDD for the full-scale output of the DAC. It is measured
in mV/V. VREF is held at 2 V, and VDD is varied by ±10%.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change and is measured from the rising edge
of SYNC.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by 1 LSB
at the major carry transition, that is, 0x7FFF to 0x8000 (see
Figure 30).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but it is measured when the DAC output is not updated. It is
specified in nV-sec and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated. It is expressed in dB.
Noise Spectral Density (NSD)
NSD is a measurement of the internally generated random noise.
Random noise is characterized as a spectral density. It is measured,
in nV/√Hz, by loading the DAC to midscale and measuring
noise at the output.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change (or soft power-down and powerup) on one DAC while monitoring another DAC kept at
midscale. It is expressed in μV.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in μV/mA.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another DAC.
It is measured in standalone mode and expressed in nV-sec.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa). Then execute a software LDAC and monitor the output of the DAC whose digital code
was not changed. The area of the glitch is expressed in nV-sec.
Rev. A | Page 15 of 24
AD5689/AD5687
Data Sheet
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
analog output change of another DAC. It is measured by loading
the attack channel with a full-scale code change (all 0s to all 1s
and vice versa), using the write to and update commands while
monitoring the output of the victim channel that is at midscale.
The energy of the glitch is expressed in nV-sec.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Rev. A | Page 16 of 24
Data Sheet
AD5689/AD5687
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTERS (DACS)
The AD5689/AD5687 are dual 16-/12-bit, serial input, voltage
output DACs. The parts operate from supply voltages of 2.7 V to
5.5 V. Data is written to the AD5689/AD5687 in a 24-bit word
format via a 3-wire serial interface. The devices incorporate a
power-on reset circuit to ensure that the DAC output powers up
to a known output state. The AD5689/AD5687 also have a
software power-down mode that reduces the typical current
consumption to 4 µA.
The resistor string structure is shown in Figure 37. It is a string
of resistors, each of Value R. The code loaded to the DAC register
determines the node on the string where the voltage is to be
tapped off and fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the
string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
VREF
R
TRANSFER FUNCTION
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
R
D
VOUT = VREF × Gain  N 
 2 
R
DAC ARCHITECTURE
The DAC architecture consists of a string DAC followed by an
output amplifier. Figure 36 shows a block diagram of the DAC
architecture.
VREF
RESISTOR
STRING
REF (–)
GND
Figure 37. Resistor String Structure
Output Amplifiers
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. The actual
range depends on the value of VREF, the GAIN pin, the offset
error, and the gain error. The GAIN pin selects the gain of the
output, as follows:
•
VOUTX
GAIN
(GAIN = 1 OR 2)
Figure 36. Single DAC Channel Architecture Block Diagram
11255-036
DAC
REGISTER
R
•
REF (+)
INPUT
REGISTER
R
11255-037
where:
Gain is the output amplifier gain and is set to 1 by default. It can
be set to ×1 or ×2 using the gain select pin. When the GAIN pin
is tied to GND, both DACs output a span from 0 V to VREF. If
the GAIN pin is tied to VLOGIC, both DACs output a span of 0 V
to 2 × VREF.
D is the decimal equivalent of the binary code that is loaded to
the DAC register as follows: 0 to 4,095 for the 12-bit device and
0 to 65,535 for the 16-bit device.
N is the DAC resolution.
TO OUTPUT
AMPLIFIER
If the GAIN pin is tied to GND, both DAC outputs have
a gain of 1, and the output range is 0 V to VREF.
If the GAIN pin is tied to VLOGIC, both DAC outputs have
a gain of 2, and the output range is 0 V to 2 × VREF.
These amplifiers are capable of driving a load of 1 kΩ in parallel
with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼ to ¾ scale
settling time of 5 µs.
Rev. A | Page 17 of 24
AD5689/AD5687
Data Sheet
SERIAL INTERFACE
The data-word comprises 16-bit or 12-bit input code, followed by
zero don’t care bits for the AD5689 or four don’t care bits for the
AD5687, as shown in Figure 38 and Figure 39, respectively.
These data bits are transferred to the input shift register on the
24 falling edges of SCLK and updated on the rising edge of SYNC.
The AD5689/AD5687 have a 3-wire serial interface (SYNC,
SCLK, and SDIN) that is compatible with SPI, QSPI™, and
MICROWIRE® interface standards as well as most DSPs. See
Figure 2 for a timing diagram of a typical write sequence. The
AD5689/AD5687 contain an SDO pin that allows the user to
daisy-chain multiple devices together (see the Daisy-Chain
Operation section) or read back data.
Commands can be executed on individual DAC channels or on
both DAC channels, depending on the address bits selected.
Table 8. Address Commands
Input Shift Register
The input shift register of the AD5689/AD5687 is 24 bits wide,
and data is loaded MSB first (DB23). The first four bits are the
command bits, C3 to C0 (see Table 9), followed by the 4-bit DAC
address bits, composed of DAC B, DAC A, and two don’t care
bits set to 0 (see Table 8). Finally, the data-word completes the
input shift register.
DAC B
0
1
1
0
0
0
0
Address (n)
0
0
0
0
DAC A
1
0
1
Selected DAC Channel
DAC A
DAC B
DAC A and DAC B
Table 9. Command Definitions
C2
0
0
0
0
1
1
1
1
0
0
0
…
1
C0
0
1
0
1
0
1
0
1
0
1
0
…
1
Description
No operation
Write to Input Register n (dependent on LDAC)
Update DAC Register n with contents of Input Register n
Write to and update DAC Channel n
Power down/power up DAC
Hardware LDAC mask register
Software reset (power-on reset)
Reserved
Set up DCEN register (daisy-chain enable)
Set up readback register (readback enable)
Reserved
Reserved
Reserved
DB23 (MSB)
C3
C2
DB0 (LSB)
C1
C0 DAC
B
0
0
DAC D15 D14 D13 D12 D11 D10
A
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND BITS
11255-038
DATA BITS
ADDRESS BITS
Figure 38. AD5689 Input Shift Register Content
DB23 (MSB)
C3
C2
DB0 (LSB)
C1
C0 DAC
B
0
0
DAC
A D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
DATA BITS
COMMAND BITS
11255-039
C3
0
0
0
0
0
0
0
0
1
1
1
…
1
Command
C1
0
0
1
1
0
0
1
1
0
0
1
…
1
ADDRESS BITS
Figure 39. AD5687 Input Shift Register Content
Rev. A | Page 18 of 24
Data Sheet
AD5689/AD5687
STANDALONE OPERATION
AD5689/
AD5687
68HC11*
The write sequence begins by bringing the SYNC line low. Data
from the SDIN line is clocked into the 24-bit input shift register
on the falling edge of SCLK. After the last of 24 data bits is clocked
in, SYNC is brought high. The programmed function is then
executed; that is, an LDAC-dependent change in DAC register
contents and/or a change in the mode of operation occurs.
If SYNC is taken high before the 24th clock, it is considered a valid
frame and invalid data may be loaded to the DAC. SYNC must
be brought high for a minimum of 20 ns (single channel, see t8
in Figure 2) before the next write sequence so that a falling edge
of SYNC can initiate the next write sequence. Idle SYNC at the
rails between write sequences for an even lower power operation
of the part. The SYNC line is kept low for 24 falling edges of
SCLK, and the DAC is updated on the rising edge of SYNC.
MOSI
SDIN
SCK
SCLK
PC7
SYNC
PC6
LDAC
SDO
MISO
SDIN
AD5689/
AD5687
SCLK
SYNC
LDAC
SDO
When the data has been transferred into the input register of
the addressed DAC, both DAC registers and outputs can be
updated by taking LDAC low while the SYNC line is high.
SDIN
AD5689/
AD5687
WRITE AND UPDATE COMMANDS
SCLK
Write to Input Register n (Dependent on LDAC)
SYNC
LDAC
Command 0001 allows the user to write to the dedicated input
register of each DAC individually. When LDAC is low, the input
register is transparent (if not controlled by the LDAC mask
register).
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 40. Daisy-Chaining Multiple AD5689/AD5687 Devices
Update DAC Register n with Contents of Input Register n
Command 0010 loads the DAC registers/outputs with the
contents of the input registers selected and updates the DAC
outputs directly.
Write to and Update DAC Channel n (Independent
of LDAC)
Command 0011 allows the user to write to the DAC registers
and update the DAC outputs directly.
DAISY-CHAIN OPERATION
For systems that contain several DACs, the SDO pin can be used
to daisy-chain several devices together. SDO is enabled through
a software executable daisy-chain enable (DCEN) command.
Command 1000 is reserved for this DCEN function (see Table 9).
Daisy-chain mode is enabled by setting Bit DB0 in the DCEN
register. The default setting is standalone mode, where DB0
(LSB) = 0. Table 10 shows how the state of the bit corresponds
to the mode of operation of the device.
Table 10. Daisy-Chain Enable (DCEN) Register
DB0 (LSB)
0
1
Description
Standalone mode (default)
DCEN mode
11255-040
SDO
The SCLK pin is continuously applied to the input shift register
when SYNC is low. If more than 24 clock pulses are applied, the
data ripples out of the input shift register and appears on the
SDO line. This data is clocked out on the rising edge of SCLK
and is valid on the falling edge. By connecting this line to the
SDIN input on the next DAC in the chain, a daisy-chain interface
is constructed. Each DAC in the system requires 24 clock pulses.
Therefore, the total number of clock cycles must equal 24 × N,
where N is the total number of devices that are updated. If SYNC
is taken high at a clock that is not a multiple of 24, it is considered
a valid frame and invalid data may be loaded to the DAC. When
the serial transfer to all devices is complete, SYNC is taken high.
This latches the input data in each device in the daisy chain and
prevents any further data from being clocked into the input shift
register. The serial clock can be continuous or a gated clock. A
continuous SCLK source can be used only if SYNC can be held
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
be used, and SYNC must be taken high after the final clock to latch
the data.
Rev. A | Page 19 of 24
AD5689/AD5687
Data Sheet
READBACK OPERATION
Table 11. Modes of Operation
Readback mode is invoked through a software executable
readback command. If the SDO output is disabled via the daisychain mode disable bit in the control register, it is automatically
enabled for the duration of the read operation, after which it is
disabled again. Command 1001 is reserved for the readback
function. This command, in association with selecting one of
the address bits, DAC B or DAC A, selects the register to be read.
Note that only one DAC register can be selected during readback.
The remaining three address bits (which include the two don’t
care bits) must be set to Logic 0. The remaining data bits in the
write sequence are ignored. If more than one address bit is
selected or no address bit is selected, DAC Channel A is read
back by default. During the next SPI write, the data that appears
on the SDO output contains the data from the previously
addressed register.
Operating Mode
Normal Operation Mode
Power-Down Modes
1 kΩ to GND
100 kΩ to GND
Three-State
For example, to read back the DAC register for Channel A,
implement the following sequence:
1.
2.
Write 0x900000 to the AD5689/AD5687 input register.
This setting configures the part for read mode with the
Channel A DAC register selected. Note that all data bits,
DB15 to DB0, are don’t care bits.
Follow this write operation with a second write, a NOP
condition, 0x000000. During this write, the data from the
register is clocked out on the SDO line. DB23 to DB20
contain undefined data, and the last 16 bits contain the
DB19 to DB4 DAC register contents.
PDx1
0
PDx0
0
0
1
1
1
0
1
When both Bit PDx1 and Bit PDx0 (where x is the channel that is
selected) in the input shift register are set to 0, the parts work
normally, with a normal power consumption of 4 mA at 5 V.
However, for the three power-down modes of the AD5689/
AD5687, the supply current falls to 4 μA at 5 V. Not only does
the supply current fall, but the output stage is also internally
switched from the output of the amplifier to a resistor network
of known values. This switchover has the advantage that the
output impedance of the part is known while the part is in
power-down mode. The three power-down options are as follows:
•
•
•
The output is connected internally to GND through a 1 kΩ
resistor.
The output is connected internally to GND through a 100
kΩ resistor.
The output is left open-circuited (three-state).
The output stage is illustrated in Figure 41.
AMPLIFIER
DAC
VOUTX
POWER-DOWN OPERATION
Either or both DACs (DAC B, DAC A) can be powered down to
the selected mode by setting the corresponding bits. See Table 12
for the contents of the input shift register during the power-down/
power-up operation.
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
11255-041
The AD5689/AD5687 contain three separate power-down modes.
Command 0100 controls the power-down function (see Table 9).
These power-down modes are software-programmable by
setting eight bits, Bit DB7 to Bit DB0, in the input shift register.
There are two bits associated with each DAC channel. Table 11
explains how the state of the two bits corresponds to the mode
of operation of the device.
Figure 41. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down, and the DAC register can
be updated while the device is in power-down mode. The time
that is required to exit power-down is typically 4.5 µs for VDD = 5 V
Table 12. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation1
DB23
(MSB)
0
DB22
1
DB21
0
DB20
0
Command bits (C3 to C0)
1
DB19 to DB16
X
DB15 to DB8
X
Address bits; don’t care
DB7
PDB1
DB6
PDB0
Power-down,
select DAC B
X = don’t care.
Rev. A | Page 20 of 24
DB5
1
DB4
1
Set to 1
DB3
1
DB2
1
Set to 1
DB1
PDA1
DB0
(LSB)
PDA0
Power-down,
select DAC A
Data Sheet
AD5689/AD5687
LOAD DAC (HARDWARE LDAC PIN)
Deferred DAC Updating (LDAC Pulsed Low)
The AD5689/AD5687 DACs have double buffered interfaces
consisting of two banks of registers: input registers and DAC
registers. The user can write to any combination of the input
registers. Updates to the DAC register are controlled by
the LDAC pin.
LDAC is held high while data is clocked into the input register
using Command 0001. Both DAC outputs are asynchronously
updated by taking LDAC low after SYNC is taken high. The
update then occurs on the falling edge of LDAC.
LDAC MASK REGISTER
OUTPUT
AMPLIFIER
VREF
16-/12-BIT
DAC
LDAC
DAC
REGISTER
Command 0101 is reserved for a software LDAC mask function,
which allows the address bits to be ignored. A write to the DAC
using Command 0101 loads the 4-bit LDAC mask register (DB3
to DB0). The default setting for each channel is 0; that is, the LDAC
pin works normally. Setting the selected bit to 1 forces the DAC
channel to ignore transitions on the LDAC pin, regardless of
the state of the hardware LDAC pin. This flexibility is useful
in applications where the user wishes to select which channels
respond to the LDAC pin.
VOUTX
SCLK
SYNC
SDIN
INTERFACE
LOGIC
11255-042
INPUT
REGISTER
SDO
The LDAC mask register gives the user extra flexibility and control
over the hardware LDAC pin (see Table 13). Setting an LDAC bit
(DB3, DB0) to 0 for a DAC channel means that the update of
this channel is controlled by the hardware LDAC pin.
Figure 42. Simplified Diagram of Input Loading Circuitry for a Single DAC
Instantaneous DAC Updating (LDAC Held Low)
LDAC is held low while data is clocked into the input register
using Command 0001. Both the addressed input register and
the DAC register are updated on the rising edge of SYNC, and
then the output begins to change (see Table 14 and Table 15).
Table 13. LDAC Overwrite Definition
Load LDAC Register
LDAC Bits
(DB3, DB0)
0
1
1
Table 14. 24-Bit Input Shift Register Contents for LDAC Operation
DB23
(MSB)
0
DB22
1
DB21
0
DB20
1
DB19
X
Command bits (C3 to C0)
1
DB18
X
DB17
X
DB16
X
Address bits, don’t care
LDAC Pin
LDAC Operation
1 or 0
X1
Determined by the LDAC pin.
DAC channels update and override
the LDAC pin. DAC channels see
the LDAC pin as set to 1.
X = don’t care.
1
DB2
0
DB1
0
DB0
(LSB)
DAC A
DB15 to DB4
X
DB3
DAC B
Don’t care
Setting the LDAC bit to 1 overrides the LDAC pin
X = don’t care.
Table 15. Write Commands and LDAC Pin Truth Table1
Command
0001
Description
Write to Input Register n
(dependent on LDAC)
0010
Update DAC Register n with
contents of Input Register n
0011
Write to and update DAC Channel n
Hardware LDAC
Pin State
VLOGIC
GND2
VLOGIC
GND
VLOGIC
GND
Input Register Contents
Data update
Data update
No change
No change
Data update
Data update
DAC Register Contents
No change (no update)
Data update
Updated with input register contents
Updated with input register contents
Data update
Data update
A high-to-low hardware LDAC pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked
(blocked) by the LDAC mask register.
2
When the LDAC pin is permanently tied low, the LDAC mask bits are ignored.
1
Rev. A | Page 21 of 24
AD5689/AD5687
Data Sheet
HARDWARE RESET (RESET)
RESET SELECT PIN (RSTSEL)
RESET is an active low reset that allows the outputs to be cleared
to either zero scale or midscale. The clear code value is user
selectable via the power-on reset select pin (RSTSEL). RESET
must be kept low for a minimum amount of time to complete
the operation (see Figure 2). When the RESET signal is returned
high, the output remains at the cleared value until a new value is
programmed. The outputs cannot be updated with a new value
while the RESET pin is low. There is also a software executable
reset function that resets the DAC to the power-on reset code.
Command 0110 is designated for this software reset function
(see Table 9). Any events on LDAC or RESET during a poweron reset are ignored.
The AD5689/AD5687 contain a power-on reset circuit that
controls the output voltage during power-up. When the RSTSEL
pin is connected low (to GND), the output powers up to zero scale.
Note that this is outside the linear region of the DAC. When the
RSTSEL pin is connected high (to VLOGIC), VOUTX powers up to
midscale. The output remains powered up at this level until a
valid write sequence is sent to the DAC.
Rev. A | Page 22 of 24
Data Sheet
AD5689/AD5687
APPLICATIONS INFORMATION
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5689/AD5687 is achieved
via a serial bus using a standard protocol that is compatible with
DSP processors and microcontrollers. The communications
channel requires a 3-wire or 4-wire interface consisting of a clock
signal, a data signal, and a synchronization signal. Each device
requires a 24-bit data-word with data valid on the rising edge
of SYNC.
AD5689/AD5687 TO ADSP-BF531 INTERFACE
The SPI interface of the AD5689/AD5687 is designed to be
easily connected to industry-standard DSPs and microcontrollers.
Figure 43 shows the AD5689/AD5687 connected to an Analog
Devices Blackfin® DSP. The Blackfin has an integrated SPI port
that connects directly to the SPI pins of the AD5689/AD5687.
AD5689/
AD5687
which provide a low impedance path to ground at high frequencies
to handle transient currents due to internal logic switching.
In systems where there are many devices on one board, it is
often useful to provide some heat sinking capability to allow
the power to dissipate easily.
Each AD5689 or AD5687 has an exposed paddle beneath the
device. Connect this paddle to the GND supply for the part. For
optimum performance, use special considerations to design the
motherboard and to mount the package. For enhanced thermal,
electrical, and board level performance, solder the exposed
paddle on the bottom of the package to the corresponding
thermal land paddle on the PCB. Design thermal vias into the
PCB land paddle area to further improve heat dissipation.
The GND plane on the device can be increased (as shown in
Figure 45) to provide a natural heat sinking effect.
AD5689/
AD5687
ADSP-BF531
GND
PLANE
Figure 43. ADSP-BF531 Interface to the AD5689/AD5687
BOARD
AD5689/AD5687 TO SPORT INTERFACE
The Analog Devices ADSP-BF527 has one SPORT serial port.
Figure 44 shows how one SPORT interface can be used to
control the AD5689/AD5687.
AD5689/
AD5687
ADSP-BF527
GPIO0
GPIO1
SYNC
SCLK
SDIN
LDAC
RESET
11255-044
SPORT_TFS
SPORT_TSCK
SPORT_DTO
Figure 44. SPORT Interface to the AD5689/AD5687
LAYOUT GUIDELINES
Figure 45. Paddle Connection to Board
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. The
iCoupler® products from Analog Devices provide voltage
isolation in excess of 2.5 kV. The serial loading structure of the
AD5689/AD5687 makes these parts ideal for isolated interfaces
because the number of interface lines is kept to a minimum.
Figure 46 shows a 4-channel isolated interface to the AD5689/
AD5687 using an ADuM1400. For more information, visit
www.analog.com/icouplers.
CONTROLLER
In any circuit where accuracy is important, careful consideration of
the power supply and ground return layout helps to ensure the
rated performance. Design the PCB on which the AD5689/
AD5687 are mounted so that the AD5689/AD5687 lie on the
analog plane.
Provide the AD5689/AD5687 with ample supply bypassing of
10 μF in parallel with 0.1 μF on each supply, located as close to
the package as possible, ideally right up against the device. The
10 μF capacitor is of the tantalum bead type. Use a 0.1 μF capacitor with low effective series resistance (ESR) and low effective
series inductance (ESI), such as the common ceramic types,
SERIAL
CLOCK IN
SERIAL
DATA OUT
SYNC OUT
LOAD DAC
OUT
ADuM14001
VIA
VIB
VIC
VID
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 46. Isolated Interface
Rev. A | Page 23 of 24
VOA
VOB
VOC
VOD
TO
SCLK
TO
SDIN
TO
SYNC
TO
LDAC
11255-046
LDAC
RESET
11255-045
PF9
PF8
SYNC
SCLK
SDIN
11255-043
SPISELx
SCK
MOSI
AD5689/AD5687
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.50
BSC
13
PIN 1
INDICATOR
16
1
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
TOP VIEW
0.80
0.75
0.70
4
5
8
0.50
0.40
0.30
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
0.25 MIN
BOTTOM VIEW
08-16-2010-E
PIN 1
INDICATOR
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 47. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
8°
0°
SEATING
PLANE
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 48. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD5689BCPZ-RL7
AD5689BRUZ
AD5689BRUZ-RL7
AD5687BCPZ-RL7
AD5687BRUZ
AD5687BRUZ-RL7
1
Resolution
16 Bits
16 Bits
16 Bits
12 Bits
12 Bits
12 Bits
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Accuracy
±2 LSB INL
±2 LSB INL
±2 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
Package Description
16-Lead LFCSP_WQ
16-Lead TSSOP
16-Lead TSSOP
16-Lead LFCSP_WQ
16-Lead TSSOP
16-Lead TSSOP
Z = RoHS Compliant Part.
©2013–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11255-0-1/16(A)
Rev. A | Page 24 of 24
PackageOption
CP-16-22
RU-16
RU-16
CP-16-22
RU-16
RU-16
Branding
DKW
DL0