AD5668-DSCC: Military Data Sheet

REVISIONS
LTR
DESCRIPTION
DATE
Prepared in accordance with ASME Y14.24
APPROVED
Vendor item drawing
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PMIC N/A
PREPARED BY
Phu H. Nguyen
Original date of drawing
YY MM DD
CHECKED BY
12-11-20
Phu H. Nguyen
APPROVED BY
Thomas M. Hess
SIZE
A
REV
AMSC N/A
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CODE IDENT. NO.
5
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DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil/
TITLE
MICROCIRCUIT, LINEAR, OCTAL, 16-BIT DAC
WITH 5 ppm/°C ON-CHIP REFERENCE,
MONOLITHIC SILICON
DWG NO.
V62/12643
16236
PAGE
1
OF
14
5962-V027-13
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance octal, 16-bit DAC with 5 ppm/°C on-chip
reference microcircuit, with an operating temperature range of -55°C to +125°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/12643
-
Drawing
number
01
X
B
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s).
Device type
Generic
01
AD5668-EP
Circuit function
Octal, 16-bit DAC with 5 ppm/°C on-chip reference
1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter
Number of pins
JEDEC PUB 95
16
JEDEC MO-153-AB
X
Package style
Thin Shrink Small Outline Package
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
Z
DLA LAND AND MARITIME
COLUMBUS, OHIO
Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12643
PAGE
2
1.3 Absolute maximum ratings.
1/
VDD to GND .............................................................................................
Digital input voltage to GND ....................................................................
VOUT to GND ............................................................................................
VREFIN/VREFOUT to GND ............................................................................
Operating temperature range: .................................................................
Storage temperature range .....................................................................
Junction temperature (TJ max) ................................................................
Case outline X:
Power dissipation .............................................................................
θJA thermal impedance .....................................................................
Reflow soldering peak temperature
SnPb ................................................................................................
Pb free ............................................................................................
-0.3 V to +7.0 V
-0.3 V to VDD + 0.3 V
-0.3 V to VDD + 0.3 V
-0.3 V to VDD + 0.3 V
-55°C to +125°C
-65°C to 150°C
150°C
(TJ MAX – TA)/ θJA
150.4 °C/W
240°C
260°C
2. APPLICABLE DOCUMENTS
JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)
JEP95
–
Registered and Standard Outlines for Semiconductor Devices
(Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103
North 10th Street, Suite 240–S, Arlington, VA 22201.)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as
specified in 1.3 and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
1/
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12643
PAGE
3
3.5 Diagrams.
3.5.1
Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2
Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3
Functional block diagram. The functional block diagram shall be as shown in figure 3.
3.5.4
INL – External reference. The INL – External reference shall be as shown in figure 4.
3.5.5
DNL. The DNL shall be as shown in figure 5.
3.5.6
Zero scale error and Offset error vs Temperature. The Zero scale error and Offset error vs Temperature shall be as shown
in figure 6.
3.5.7
Gain error and Full scale error vs Supply voltage. The Gain error and Full scale error vs Supply voltage shall be as shown in
figure 7.
3.5.8
Digital to Analog glitch impulse (negative). The Digital to Analog glitch impulse (negative) shall be as shown in figure 8.
3.5.9
Serial write operation. The serial write operation shall be as shown in figure 9.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12643
PAGE
4
TABLE I. Electrical performance characteristics. 1/
Test
Symbol
Static performance
3/
Resolution
Relative accuracy
Differential nonlinearity
Zero code error
Zero code error drift
Min
Unit
Typ
Max
See FIGURE 4
See FIGURE 5 4/
All 0s loaded to DAC register, See FIGURE 6
±8
±21
±1
14
All 1s loaded to DAC register, See FIGURE 7
-0.2
of FSR/°C
±2.5
16
Full scale error
Gain error
Gain temperature coefficient
Offset error
DC Power supply rejection ratio
1
±2
±1
-80
10
VDD ± 10%
Due to full scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
Due to full scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
DC Crosstalk (External reference)
DC Crosstalk (Internal reference)
Output characteristics
Output voltage range
Limits
Test conditions
2/
-1
±1
Bits
LSB
mV
µV/°C
% FSR
ppm
±14
mV
dB
µV
5
10
25
µV/mA
µV
µV
10
µV/mA
5/
0
RL = ∞
RL = 2 kΩ
Capacity load stability
DC output impedance
Short circuit current
Power up time
Reference inputs
Reference current
Reference input range
Reference input impedance
Reference outputs
Output voltage
Reference temperature coefficient 5/
Reference output impedance
Logic input 5/
Input current
Input low voltage
Input high voltage
Pin capacitance
VDD
2
10
0.5
30
4
VDD = 5 V
Coming out of power down mode, VDD = 5 V
VREF = VDD = 5.5 V (per DAC channel)
40
0
Ω
mA
µs
55
VDD
14.6
At ambient
1.247
1.253
±5
All digital inputs
VDD = 5 V
VDD = 5 V
µA
V
kΩ
V
ppm/°C
kΩ
7.5
VINL
VINH
V
nF
±3
0.8
µA
V
2
3
pF
See footnote at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12643
PAGE
5
TABLE I. Electrical performance characteristics - Continued. 1/
Test
Symbol
Power requirements
VDD
AC characteristics
Output voltage settling time
Slew rate
Digital to Analog glitch impulse
Digital feedthrough
Reference feedthrough
Digital crosstalk
Analog crosstalk
DAC to DAC crosstalk
Multiplying bandwidth
Total harmonic distortion
Output Noise spectral density
Output noise
Min
All digital inputs at 0 or VDD, DAC active
excludes load current
VIH = VDD and VIL = GND
Internal reference off
Internal reference on
IDD (normal mode)
6/
VDD = 4.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
IDD (All power down modes) 7/
VDD = 4.5 V to 5.5 V
Test
Limits
Test conditions
2/
Typ
Max
4.5
VIH = VDD and VIL = GND
Symbol
Unit
5.5
V
1.3
2
1.8
2.6
mA
mA
0.4
1
µA
Limits
Test conditions
8/
Min
¼ to ¾ scale settling to ±2 LSB
1 LSB change around major carry , see FIGURE 8
VREF = 2 V ±0.1 V p-p, frequency = 10 Hz to 20 MHz
VREF = 2 V ±0.2 V p-p
VREF = 2 V ±0.1 V p-p, frequency = 10 kHz
DAC code = 0x8400, 1 kHz
DAC code = 0x8400, 10 kHz
0.1 Hz to 10 Hz
Unit
Typ
Max
6
1.5
4
0.1
-90
0.5
2.5
3
340
-80
120
100
15
10
µs
V/µs
nV-sec
dB
nV-sec
kHz
dB
nV/√Hz
µV p-p
See footnote at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12643
PAGE
6
TABLE I. Electrical performance characteristics - Continued. 1/
Test
Timing characteristics
SCLK cycle time
SCLK high time
SCLK low time
������� to SCLK falling edge setup time
SYNC
Data setup time
Data hold time
������� rising edge
SCLK falling edge to SYNC
������� high time
Minimum SYNC
�������
SYNC rising edge to SCLK fall ignore
������� fall ignore
SCLK falling edge to SYNC
������� pulse width low
LDAC
SCLK falling edge to �������
LDAC rising edge
����� pulse width low
CLR
������� falling edge
SCLK falling edge to LDAC
�����
CLR pulse activation time
1/
2/
3/
4/
5/
6/
7/
8/
9/
Symbol
Limits
Test conditions
9/
Min
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
Typ
Unit
Max
20
8
8
13
4
4
0
15
13
0
10
15
5
0
ns
300
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not
necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
VDD = 1.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise
noted. Temperature range -55°C ≤ TA ≤ +125°C, Typical at +25°C.
Linearity calculated using a reduced code range of this device (Code 512 to 65,024). Output unloaded.
Guaranteed monotonic by design.
Guaranteed by design, and characterization, not production tested.
Interface inactive. All DACs active. DAC outputs unloaded.
All eight DACs powered down.
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise
noted. Temperature range -55°C ≤ TA ≤ +125°C, Typical at +25°C.
All inputs signal are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See
FIGURE 9. VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12643
PAGE
7
Case X
b
e
16
9
c
E
0°-8°
E1
PIN 1
IDENTIFIE
R
1
8
L
DETAIL A
D
SEE
DETAIL A
A1
A
SEATING
PLANE
Symbol
A
A1
b
c
D
Dimensions
Millimeters
Symbol
Min
Max
0.05
0.19
0.09
4.90
1.20
0.15
0.30
0.20
5.10
E
E1
e
L
Millimeters
Min
Max
4.30
4.50
6.40 BSC
0.65 BSC
0.45
0.75
NOTES:
1. All linear dimensions are in millimeters.
2. Falls within JEDEC MO-153-AB.
FIGURE 1. Case outline.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12643
PAGE
8
Case outline X
Terminal
Terminal
symbol
number
�������
16
LDAC
�������
15
SYNC
VDD
14
Terminal
number
1
2
3
4
VOUTA
13
5
6
VOUTC
VOUTE
12
11
7
8
VOUTG
VREFIN/VREFOUT
10
9
Terminal
symbol
SCLK
DIN
GND
VOUTB
VOUTD
VOUTF
FIGURE 2. Terminal connections.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
VOUTH
�����
CLR
CODE IDENT NO.
16236
REV
DWG NO.
V62/12643
PAGE
9
V
V
DD
REFIN
/V
REFOUT
1.25 V/2.5 V
REF
LDAC
INPUT
DAC
STRING
REGISTER
REGISTER
DAC A
INPUT
DAC
STRING
REGISTER
REGISTER
DAC B
INPUT
DAC
STRING
REGISTER
REGISTER
DAC C
INPUT
DAC
STRING
REGISTER
REGISTER
DAC D
INPUT
DAC
STRING
REGISTER
REGISTER
DAC E
INPUT
DAC
STRING
REGISTER
REGISTER
DAC F
INPUT
DAC
STRING
REGISTER
REGISTER
DAC G
INPUT
DAC
STRING
REGISTER
REGISTER
DAC H
BUFFER
V
BUFFER
V
BUFFER
V
OUT
OUT
OUT
A
B
C
SCLK
BUFFER
V
OUT
D
INTERFACE
SYNC
LOGIC
BUFFER
V
OUT
E
DIN
LDAC
BUFFER
V
BUFFER
V
BUFFER
V
POWER-ON
POWER-DOWN
RESET
RESET
OUT
OUT
OUT
GND
CLR
FIGURE 3. Functional block diagram.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12643
PAGE
10
F
G
H
10
V DD =V REF =5 V
8
T A =25°C
6
INTL ERROR(LSB)
4
2
0
-2
-4
-6
-8
-10
0
5k
10k
15k
25k
20k
30k
35k
40k
50k
45k
55k
60k
65k
CODE
FIGURE 4. INL – External reference.
1.0
0.8
0.6
V DD = 3 V
V REFOUT = 1.25 V
T A = 25°C
DNL ERROR (LSB)
0.4
0.2
0
-0.2
-0.4
-0.6
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
0
-1.0
5000
-0.8
CODE
FIGURE 5. DNL.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12643
PAGE
11
1.5
1.0
0.5
ZERO-SCALE ERROR
ERROR(mV)
0
-0.5
OFFSET ERROR
-1.0
-1.5
-2.0
-2.5
-55
-15
-35
25
5
45
85
65
105
125
TEMPERATURE(°C)
FIGURE 6. Zero scale error and Offset error vs Temperature.
1.0
0.5
GAIN ERROR
ERROR (% FSR)
0
FULL-SCALE ERROR
-0.5
-1.0
-1.5
-2.0
2.7
3.2
3.7
4.2
V
DD
4.7
5.2
(V)
FIGURE 7. Gain error and Full scale error vs Supply voltage.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12643
PAGE
12
2.504
V DD =5 V
2.503
V REFOUT =2.5 V
2.502
T A =25°C
4ns/SAMPLE NUMBER
2.501
2.500
GLITCH IMPULSE=3.55nV-s
1 LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
2.499
2.498
V OUT (V)
2.497
2.496
2.495
2.494
2.493
2.492
2.491
2.490
2.489
2.488
2.487
2.486
2.485
0
64
192
128
256
320
384
448
512
SAMPLE
FIGURE 8. Digital to Analog glitch impulse (negative).
t9
t1
t10
SCLK
t8
t4
t3
t2
t7
SYNC
t6
t5
DIN
DB31
DB0
t14
t11
LDAC
SEE NOTE 1
t12
LDAC
SEE NOTE 2
t13
CLR
t15
V OUT
NOTES:
1. Asynchronous �������
LDAC update mode.
������� update mode.
2. Synchronous LDAC
FIGURE 9. Serial write operation.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12643
PAGE
13
4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of
present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current
sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Vendor item drawing
administrative control
number 1/
Device
manufacturer
CAGE code
Vendor part number
V62/12643-01XB
24355
AD5668SRU-EP-1RL7
1/ The vendor item drawing establishes an administrative control number for
identifying the item on the engineering documentation.
CAGE code
24355
DLA LAND AND MARITIME
COLUMBUS, OHIO
Source of supply
Analog Devices
1 Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12643
PAGE
14
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