CMOS, 330 MHz Triple 8-Bit High Speed Video DAC ADV7125 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VAA BLANK BLANK AND SYNC LOGIC SYNC R7 TO R0 8 G7 TO G0 8 B7 TO B0 PSAVE 8 IOR DATA REGISTER 8 DATA REGISTER 8 DATA REGISTER 8 DAC IOR IOG DAC IOB DAC VREF ADV7125 GND Digital video systems High resolution color graphics Digital radio modulation Image processing Instrumentation Video signal reconstruction Automotive infotainment units IOB VOLTAGE REFERENCE CIRCUIT POWER-DOWN MODE CLOCK APPLICATIONS IOG RSET COMP 03097-001 330 MSPS throughput rate Triple 8-bit DACs RS-343A-/RS-170-compatible output Complementary outputs DAC output current range: 2.0 mA to 26.5 mA TTL-compatible inputs Internal reference (1.235 V) Single-supply +5 V/+3.3 V operation 48-lead LQFP and LFCSP Low power dissipation (30 mW minimum at 3 V) Low power standby mode (6 mW typical at 3 V) Industrial temperature range (−40°C to +85°C) RoHS compliant packages Qualified for automotive applications Figure 1. GENERAL DESCRIPTION The ADV7125 (ADV®) is a triple high speed, digital-to-analog converter (DAC) on a single monolithic chip. It consists of three high speed, 8-bit video DACs with complementary outputs, a standard TTL input interface, and a high impedance, analog output current source. The ADV7125 is fabricated in a 5 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7125 is available in 48lead LQFP and 48-lead LFCSP packages. The ADV7125 has three separate 8-bit-wide input ports. A single +5 V/+3.3 V power supply and clock are all that are required to make the device functional. The ADV7125 has additional video control signals, composite SYNC and BLANK, as well as a power save mode. 1. 2. 3. Rev. D PRODUCT HIGHLIGHTS 330 MSPS (3.3 V only) throughput. Guaranteed monotonic to eight bits. Compatible with a wide variety of high resolution color graphics systems, including RS-343A and RS-170. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2002–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADV7125 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Description and Operation .............................................. 12 Applications ....................................................................................... 1 Digital Inputs .............................................................................. 12 Functional Block Diagram .............................................................. 1 Clock Input.................................................................................. 12 General Description ......................................................................... 1 Video Synchronization and Control ........................................ 13 Product Highlights ........................................................................... 1 Reference Input........................................................................... 13 Revision History ............................................................................... 2 DACs ............................................................................................ 13 Specifications..................................................................................... 3 Analog Outputs .......................................................................... 13 5 V Electrical Characteristics ...................................................... 3 Gray Scale Operation ................................................................. 14 3.3 V Electrical Characteristics................................................... 4 Video Output Buffers................................................................. 14 5 V Timing Specifications ........................................................... 5 PCB Layout Considerations ...................................................... 14 3.3 V Timing Specifications ........................................................ 6 Digital Signal Interconnect ....................................................... 14 Absolute Maximum Ratings............................................................ 7 Analog Signal Interconnect....................................................... 15 ESD Caution .................................................................................. 7 Outline Dimensions ....................................................................... 16 Pin Configurations and Function Descriptions ........................... 8 Ordering Guide .......................................................................... 17 Terminology .................................................................................... 11 Automotive Products ................................................................. 17 REVISION HISTORY 4/16—Rev. C to Rev. D Changes to Figure 3 and Table 6 ..................................................... 8 Added Figure 4; Renumbered Sequentially .................................. 8 Added Figure 5 and Table 7; Renumbered Sequentially ........... 10 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 17 2/11—Rev. B to Rev. C Change to Table 6 ............................................................................. 8 7/10—Rev. A to Rev. B Change to Features Section ............................................................. 1 Changes to Clock Frequency Parameter, Table 4 ......................... 6 Changes to Figure 2 .......................................................................... 6 Changes to Figure 4 and Figure 5 ................................................. 11 Changes to Table 7 .......................................................................... 12 Changes to Endnotes to Ordering Guide .................................... 15 Added Automotive Products Section .......................................... 15 3/09—Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to Features Section, Applications Section, and General Description Section ............................................................1 Changes to Figure 3 and Table 6 ......................................................8 Deleted Ground Planes Section, Power Planes Section, and Supply Decoupling Section ........................................................... 11 Changes to Figure 5 ........................................................................ 11 Changes to Table 7, Analog Outputs Section, Figure 6, and Figure 7 ............................................................................................ 12 Changes to Video Output Buffers Section, PCB Layout Considerations Section, and Figure 9 .......................................... 13 Changes to Analog Signal Interconnect Section and Figure 10 .... 14 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 16 10/02—Revision 0: Initial Version Rev. D | Page 2 of 17 Data Sheet ADV7125 SPECIFICATIONS 5 V ELECTRICAL CHARACTERISTICS VAA = 5 V ± 5%, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX, 1 unless otherwise noted, TJ MAX = 110°C. Table 1. Parameter STATIC PERFORMANCE Resolution (Each DAC) Integral Nonlinearity (BSL) Differential Nonlinearity DIGITAL AND CONTROL INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Current, IIN PSAVE Pull-Up Current Min Typ Max Unit Test Conditions/Comments1 8 −1 −1 ±0.4 ±0.25 +1 +1 Bits LSB LSB Guaranteed Monotonic 2 −1 20 10 Input Capacitance, CIN ANALOG OUTPUTS Output Current DAC-to-DAC Matching Output Compliance Range, VOC Output Impedance, ROUT Output Capacitance, COUT Offset Error Gain Error 2 VOLTAGE REFERENCE, EXTERNAL AND INTERNAL Reference Range, VREF POWER DISSIPATION Digital Supply Current 3 Analog Supply Current Standby Supply Current 4 Power Supply Rejection Ratio 0.8 +1 2.0 2.0 +0.025 +5.0 mA mA % V kΩ pF % FSR % FSR 1.235 1.35 V 3.4 10.5 18 67 8 2.1 0.1 9 15 25 72 mA mA mA mA mA mA %/% 1.0 0 26.5 18.5 5 1.4 100 10 −0.025 −5.0 1.12 V V μA μA pF 5.0 0.5 VIN = 0.0 V or VDD Green DAC, SYNC = high RGB DAC, SYNC = low IOUT = 0 mA Tested with DAC output = 0 V FSR = 18.62 mA fCLK = 50 MHz fCLK = 140 MHz fCLK = 240 MHz RSET = 530 Ω RSET = 4933 Ω PSAVE = low, digital, and control inputs at VDD Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz. Gain error = ((Measured (FSC)/Ideal (FSC) − 1) × 100), where Ideal = VREF/RSET × K × (0xFFH) × 4 and K = 7.9896. Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD. 4 These maximum/minimum specifications are guaranteed by characterization in the 4.75 V to 5.25 V range. 1 2 3 Rev. D | Page 3 of 17 ADV7125 Data Sheet 3.3 V ELECTRICAL CHARACTERISTICS VAA = 3.0 V to 3.6 V, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX, 1 unless otherwise noted, TJ MAX = 110°C. Table 2. Parameter 2 STATIC PERFORMANCE Resolution (Each DAC) Integral Nonlinearity (BSL) Differential Nonlinearity DIGITAL AND CONTROL INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Current, IIN PSAVE Pull-Up Current Input Capacitance, CIN ANALOG OUTPUTS Output Current DAC-to-DAC Matching Output Compliance Range, VOC Output Impedance, ROUT Output Capacitance, COUT Offset Error Gain Error 3 VOLTAGE REFERENCE, EXTERNAL Reference Range, VREF VOLTAGE REFERENCE, INTERNAL Voltage Reference, VREF POWER DISSIPATION Digital Supply Current 4 Analog Supply Current Standby Supply Current Power Supply Rejection Ratio Min Typ Max Unit Test Conditions/Comments1 −1 −1 ±0.5 ±0.25 8 +1 +1 Bits LSB LSB RSET = 680 Ω RSET = 680 Ω RSET = 680 Ω +1 V V μA μA pF VIN = 0.0 V or VDD 2.0 0.8 −1 20 10 2.0 2.0 26.5 18.5 1.0 0 1.4 70 10 0 0 1.12 1.235 0 1.35 1.235 2.2 6.5 11 16 67 8 2.1 0.1 mA mA % V kΩ pF % FSR % FSR Green DAC, SYNC = high RGB DAC, SYNC = low Tested with DAC output = 0 V FSR = 18.62 mA V V 5.0 12.0 15 72 5.0 0.5 mA mA mA mA mA mA mA %/% fCLK = 50 MHz fCLK = 140 MHz fCLK = 240 MHz fCLK = 330 MHz RSET = 560 Ω RSET = 4933 Ω PSAVE = low, digital, and control inputs at VDD Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz. These max/min specifications are guaranteed by characterization in the 3.0 V to 3.6 V range. Gain error = ((Measured (FSC)/Ideal (FSC) −1) × 100), where Ideal = VREF/RSET × K × (0xFFH) × 4 and K = 7.9896. 4 Digital supply is measured with continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD. 1 2 3 Rev. D | Page 4 of 17 Data Sheet ADV7125 5 V TIMING SPECIFICATIONS VAA = 5 V ± 5%, 1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX, 2 unless otherwise noted, TJ MAX = 110°C. Table 3. Parameter 3 ANALOG OUTPUTS Analog Output Delay Analog Output Rise/Fall Time 4 Analog Output Transition Time 5 Analog Output Skew 6 CLOCK CONTROL CLOCK Frequency 7 Data and Control Setup6 Data and Control Hold6 CLOCK Period CLOCK Pulse Width High6 CLOCK Pulse Width Low6 CLOCK Pulse Width High6 CLOCK Pulse Width Low6 CLOCK Pulse Width High CLOCK Pulse Width Low Pipeline Delay6 PSAVE Up Time6 Symbol Min t6 t7 t8 t9 fCLK t1 t2 t3 t4 t5 t4 t5 t4 t5 tPD t10 Typ 5.5 1.0 15 1 0.5 0.5 0.5 0.5 1.5 4.17 1.875 1.875 2.85 2.85 8.0 8.0 1.0 Max Unit 2 ns ns ns ns 50 140 240 1.0 2 1.0 10 MHz MHz MHz ns ns ns ns ns ns ns ns ns Clock cycles ns Test Conditions/Comments 50 MHz grade 140 MHz grade 240 MHz grade fCLK_MAX = 240 MHz fCLK_MAX = 240 MHz fCLK_MAX = 140 MHz fCLK_MAX = 140 MHz fCLK_MAX = 50 MHz fCLK_MAX = 50 MHz The maximum and minimum specifications are guaranteed over this range. Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz. 3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies. 4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition. 5 Measured from 50% point of full-scale transition to 2% of final value. 6 Guaranteed by characterization. 7 fCLK maximum specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization. 1 2 Rev. D | Page 5 of 17 ADV7125 Data Sheet 3.3 V TIMING SPECIFICATIONS VAA = 3.0 V to 3.6 V, 1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX, 2 unless otherwise noted, TJ MAX = 110°C. Table 4. Parameter 3 ANALOG OUTPUTS Analog Output Delay, Analog Output Rise/Fall Time 4 Analog Output Transition Time 5 Analog Output Skew 6 CLOCK CONTROL CLOCK Frequency 7 Data and Control Setup6 Data and Control Hold6 CLOCK Period CLOCK Pulse Width High6 CLOCK Pulse Width Low6 CLOCK Pulse Width High6 CLOCK Pulse Width Low6 CLOCK Pulse Width High6 CLOCK Pulse Width Low6 CLOCK Pulse Width High CLOCK Pulse Width Low Pipeline Delay6 PSAVE Up Time6 Symbol Min t6 t7 t8 t9 Typ 7.5 1.0 15 1 fCLK Max Unit 2 ns ns ns ns 50 140 240 330 t1 t2 t3 t4 t5 t4 t5 t4 t5 t4 t5 tPD t10 0.2 1.5 3 1.4 1.4 1.875 1.875 2.85 2.85 8.0 8.0 1.0 1.0 4 Test Conditions/Comments MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns Clock cycles ns 1.0 10 50 MHz grade 140 MHz grade 240 MHz grade 330 MHz grade fCLK_MAX = 330 MHz fCLK_MAX = 330 MHz fCLK_MAX = 240 MHz fCLK_MAX = 240 MHz fCLK_MAX = 140 MHz fCLK_MAX = 140 MHz fCLK_MAX = 50 MHz fCLK_MAX = 50 MHz These maximum and minimum specifications are guaranteed over this range. Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz. 3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for 3.3 V supplies. 4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition. 5 Measured from 50% point of full-scale transition to 2% of final value. 6 Guaranteed by characterization. 7 fCLK maximum specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization. 1 2 t3 t4 t5 CLOCK t2 DIGITAL INPUTS (R7 TO R0, G7 TO G0, B7 TO B0, SYNC, BLANK) t1 t6 t8 ANALOG OUTPUTS (IOR, IOR, IOG, IOG, IOB, IOB) NOTES 1. OUTPUT DELAY (t6) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION. 2. OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION. 3. TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE. Figure 2. Timing Diagram Rev. D | Page 6 of 17 03097-002 t7 Data Sheet ADV7125 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter VAA to GND Voltage on Any Digital Pin Ambient Operating Temperature Range (TA) Storage Temperature Range (TS) Junction Temperature (TJ) Lead Temperature (Soldering, 10 sec) Vapor Phase Soldering (1 Minute) IOUT to GND1 1 Rating 7V GND − 0.5 V to VAA + 0.5 V −40°C to +85°C −65°C to +150°C 150°C 300°C 220°C 0 V to VAA Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Analog output short circuit to any power supply or common GND can be of an indefinite duration. Rev. D | Page 7 of 17 ADV7125 Data Sheet PIN 1 INDICATOR G0 3 G1 4 G2 5 G3 6 G4 7 G5 8 G6 9 G7 10 BLANK 11 SYNC 12 ADV7125 VREF COMP IOR IOR GND 1 GND 2 G0 3 G1 4 G2 5 G3 6 G4 7 G5 8 G6 9 G7 10 BLANK 11 SYNC 12 IOG IOG VAA VAA IOB IOB GND GND VREF COMP IOR IOR IOG IOG VAA VAA IOB IOB GND GND 03097-003 VAA GND GND B0 B1 B2 B3 B4 B5 B6 B7 CLOCK VAA GND GND B0 B1 B2 B3 B4 B5 B6 B7 CLOCK NOTES 1. THE EXPOSED PADDLE MUST BE CONNECTED TO GND. ADV7125 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 13 14 15 16 17 18 19 20 21 22 23 24 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 NOTES 1. THE EXPOSED PADDLE MUST BE CONNECTED TO GND. Figure 3. LFCSP Pin Configuration (CP-48-1) 03097-100 1 2 48 47 46 45 44 43 42 41 40 39 38 37 GND GND R7 R6 R5 R4 R3 R2 R1 R0 GND GND PSAVE RSET 48 47 46 45 44 43 42 41 40 39 38 37 R7 R6 R5 R4 R3 R2 R1 R0 GND GND PSAVE RSET PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. LFCSP Pin Configuration (CP-48-4) Table 6. LFCSP Pin Function Descriptions Pin No. 1, 2, 14, 15, 25, 26, 39, 40 3 to 10, 16 to 23, 41 to 48 Mnemonic GND Description Ground. All GND pins must be connected. 11 G0 to G7, B0 to B7, R0 to R7 BLANK 12 SYNC 13, 29, 30 24 VAA CLOCK 27, 31, 33 IOB, IOG, IOR 28, 32, 34 IOB, IOG, IOR 35 COMP 36 VREF Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of CLOCK. R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the regular printed circuit board (PCB) power or ground plane. Composite Blank Control Input (TTL Compatible). A Logic 0 on this control input drives the analog outputs, IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While BLANK is a Logic 0, the R0 to R7, G0 to G7, and B0 to B7 pixel inputs are ignored. Composite Sync Control Input (TTL Compatible). A Logic 0 on the SYNC input switches off a 40 IRE current source. This is internally connected to the IOG analog output. SYNC does not override any other control or data input; therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK. If sync information is not required on the green channel, the SYNC input should be tied to Logic 0. Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7125 must be connected. Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0 to R7, G0 to G7, B0 to B7, SYNC, and BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven by a dedicated TTL buffer. Differential Blue, Green, and Red Current Outputs (High Impedance Current Sources). These RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω load. If the complementary outputs are not required, these outputs should be tied to ground. Blue, Green, and Red Current Outputs. These high impedance current sources are capable of directly driving a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or not they are all being used. Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic capacitor must be connected between COMP and VAA. Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). Rev. D | Page 8 of 17 Data Sheet Pin No. 37 Mnemonic RSET 38 0 PSAVE EPAD ADV7125 Description A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on IOG (assuming ISYNC is connected to IOG) is given by: RSET (Ω) = 11,445 × VREF (V)/IOG (mA) The relationship between RSET and the full-scale output current on IOR, IOG, and IOB is given by: IOG (mA) = 11,444.8 × VREF (V)/RSET (Ω) (SYNC being asserted) IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω) The equation for IOG is the same as that for IOR and IOB when SYNC is not being used, that is, SYNC tied permanently low. Power Save Control Pin. Reduced power consumption is available on the ADV7125 when this pin is active. Exposed Paddle. The exposed paddle must be connected to GND. Rev. D | Page 9 of 17 RSET PSAVE GND GND R0 R1 R2 R3 R4 R5 R6 Data Sheet R7 ADV7125 48 47 46 45 44 43 42 41 40 39 38 37 GND 1 36 VREF GND 2 35 COMP G0 3 34 IOR G1 4 33 IOR G2 5 ADV7125 32 IOG G3 6 G4 TOP VIEW (Not to Scale) 7 G5 G6 31 IOG 30 VAA 8 29 VAA 9 28 IOB G7 10 27 IOB BLANK 11 26 GND SYNC 12 25 GND 03907-101 CLOCK B7 B6 B5 B4 B3 B2 B1 B0 GND VAA GND 13 14 15 16 17 18 19 20 21 22 23 24 Figure 5. LQFP Pin Configuration Table 7. LQFP Pin Function Descriptions Pin No. 1, 2, 14, 15, 25, 26, 39, 40 3 to 10, 16 to 23, 41 to 48 Mnemonic GND Description Ground. All GND pins must be connected. 11 G0 to G7, B0 to B7, R0 to R7 BLANK 12 SYNC 13, 29, 30 24 VAA CLOCK 27, 31, 33 IOB, IOG, IOR 28, 32, 34 IOB, IOG, IOR 35 COMP 36 37 VREF RSET 38 PSAVE Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of CLOCK. R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the regular printed circuit board (PCB) power or ground plane. Composite Blank Control Input (TTL Compatible). A Logic 0 on this control input drives the analog outputs, IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While BLANK is a Logic 0, the R0 to R7, G0 to G7, and B0 to B7 pixel inputs are ignored. Composite Sync Control Input (TTL Compatible). A Logic 0 on the SYNC input switches off a 40 IRE current source. This is internally connected to the IOG analog output. SYNC does not override any other control or data input; therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK. If sync information is not required on the green channel, the SYNC input should be tied to Logic 0. Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7125 must be connected. Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0 to R7, G0 to G7, B0 to B7, SYNC, and BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven by a dedicated TTL buffer. Differential Blue, Green, and Red Current Outputs (High Impedance Current Sources). These RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω load. If the complementary outputs are not required, these outputs should be tied to ground. Blue, Green, and Red Current Outputs. These high impedance current sources are capable of directly driving a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or not they are all being used. Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic capacitor must be connected between COMP and VAA. Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on IOG (assuming ISYNC is connected to IOG) is given by: RSET (Ω) = 11,445 × VREF (V)/IOG (mA) The relationship between RSET and the full-scale output current on IOR, IOG, and IOB is given by: IOG (mA) = 11,444.8 × VREF (V)/RSET (Ω) (SYNC being asserted) IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω) The equation for IOG is the same as that for IOR and IOB when SYNC is not being used, that is, SYNC tied permanently low. Power Save Control Pin. Reduced power consumption is available on the ADV7125 when this pin is active. Rev. D | Page 10 of 17 Data Sheet ADV7125 TERMINOLOGY Blanking Level The level separating the SYNC portion from the video portion of the waveform. Usually referred to as the front porch or back porch. At 0 IRE units, it is the level that shuts off the picture tube, resulting in the blackest possible picture. Raster Scan The most basic method of sweeping a CRT one line at a time to generate and display images. Color Video (RGB) This refers to the technique of combining the three primary colors of red, green, and blue to produce color pictures within the usual spectrum. In RGB monitors, three DACs are required, one for each color. Reference White Level The maximum positive polarity amplitude of the video signal. Sync Signal (SYNC) The position of the composite video signal that synchronizes the scanning process. Gray Scale The discrete levels of video signal between reference black and reference white levels. An 8-bit DAC contains 256 different levels. Reference Black Level The maximum negative polarity amplitude of the video signal. Sync Level The peak level of the SYNC signal. Video Signal The portion of the composite video signal that varies in gray scale levels between reference white and reference black. Also referred to as the picture signal, this is the portion that can be visually observed. Rev. D | Page 11 of 17 ADV7125 Data Sheet CIRCUIT DESCRIPTION AND OPERATION The ADV7125 contains three 8-bit DACs, with three input channels, each containing an 8-bit register. Also integrated on board the device is a reference amplifier. The CRT control functions, BLANK and SYNC, are integrated on board the ADV7125. Table 8 details the resultant effect on the analog outputs of BLANK and SYNC. DIGITAL INPUTS The CLOCK input of the ADV7125 is typically the pixel clock rate of the system. It is also known as the dot rate. The dot rate, and thus the required CLOCK frequency, is determined by the on-screen resolution, according to the following equation: All these digital inputs are specified to accept TTL logic levels. CLOCK INPUT There are 24 bits of pixel data (color information), R0 to R7, G0 to G7, and B0 to B7, latched into the device on the rising edge of each clock cycle. This data is presented to the three 8-bit DACs and then converted to three analog (RGB) output waveforms (see Figure 6). CLOCK DIGITAL INPUTS (R7 TO R0, G7 TO G0, B7 TO B0, SYNC, BLANK) DATA 03097-004 ANALOG OUTPUTS (IOR, IOR, IOG, IOG, IOB, IOB) Figure 6. Video Data Input/Output The ADV7125 has two additional control signals that are latched to the analog video outputs in a similar fashion. BLANK and SYNC are each latched on the rising edge of CLOCK to maintain synchronization with the pixel data stream. The BLANK and SYNC functions allow for the encoding of these video synchronization signals onto the RGB video output. This is done by adding appropriately weighted current sources to the analog outputs, as determined by the logic levels on the BLANK and SYNC digital inputs. Dot Rate = (Horiz Res) × (Vert Res) × (Refresh Rate)/(Retrace Factor) where: Horiz Res is the number of pixels per line. Vert Res is the number of lines per frame. Refresh Rate is the horizontal scan rate. This is the rate at which the screen must be refreshed, typically 60 Hz for a noninterlaced system, or 30 Hz for an interlaced system. Retrace Factor is the total blank time factor. This takes into account that the display is blanked for a certain fraction of the total duration of each frame (for example, 0.8). Therefore, for a graphics system with a 1024 × 1024 resolution, a noninterlaced 60 Hz refresh rate, and a retrace factor of 0.8, Dot Rate = 1024 × 1024 × 60/0.8 = 78.6 MHz The required CLOCK frequency is thus 78.6 MHz. All video data and control inputs are latched into the ADV7125 on the rising edge of CLOCK, as previously described in the Digital Inputs section. It is recommended that the CLOCK input to the ADV7125 be driven by a TTL buffer (for example, the 74F244). Figure 7 shows the analog output, RGB video waveform of the ADV7125. The influence of SYNC and BLANK on the analog video waveform is illustrated. RED AND BLUE GREEN V mA V 18.67 0.7 26.0 0.975 0 0 WHITE LEVEL 7.2 0.271 BLANK LEVEL 0 0 SYNC LEVEL NOTES 1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75Ω LOAD. 2. VREF = 1.235V, RSET = 530Ω. 3. RS-343 LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS. Figure 7. Typical RGB Video Output Waveform Rev. D | Page 12 of 17 03097-005 mA Data Sheet ADV7125 Table 8. Typical Video Output Truth Table (RSET = 530 Ω, RLOAD = 37.5 Ω) IOG (mA) 0 18.67 − Video 18.67 − Video 18.67 18.67 18.67 18.67 IOR/IOB (mA) 18.67 Video Video 0 0 0 0 VIDEO SYNCHRONIZATION AND CONTROL The ADV7125 has a single composite sync (SYNC) input control. Many graphics processors and CRT controllers have the ability to generate horizontal sync (HSYNC), vertical sync (VSYNC), and composite SYNC. In a graphics system that does not automatically generate a composite SYNC signal, the inclusion of some additional logic circuitry enables the generation of a composite SYNC signal. The sync current is internally connected directly to the IOG output, thus encoding video synchronization information onto the green video channel. If it is not required to encode sync information onto the ADV7125, the SYNC input should be tied to logic low. REFERENCE INPUT The ADV7125 contains an on-board voltage reference. The VREF pin should be connected as shown in Figure 12. (1) IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω) (2) Equation 1 applies to the ADV7125 only, when SYNC is being used. If SYNC is not being encoded onto the green channel, Equation 1 is similar to Equation 2. BLANK 1 1 0 1 0 1 0 1 1 1 1 1 0 0 DAC Input Data 0xFFH Data Data 0x00H 0x00H 0xXXH (don’t care) 0xXXH (don’t care) ANALOG OUTPUTS The ADV7125 has three analog outputs, corresponding to the red, green, and blue video signals. The red, green, and blue analog outputs of the ADV7125 are high impedance current sources. Each one of these three RGB current outputs is capable of directly driving a 37.5 Ω load, such as a doubly terminated 75 Ω coaxial cable. Figure 8 shows the required configuration for each of the three RGB outputs connected into a doubly terminated 75 Ω load. This arrangement develops RS-343A video output voltage levels across a 75 Ω monitor. A suggested method of driving RS-170 video levels into a 75 Ω monitor is shown in Figure 9. The output current levels of the DACs remain unchanged, but the source termination resistance, ZS, on each of the three DACs is increased from 75 Ω to 150 Ω. IOR, IOG, IOB Z0 = 75Ω DACs ZS = 75Ω (SOURCE TERMINATION) (CABLE) ZL = 75Ω (MONITOR) TERMINATION REPEATED THREE TIMES FOR RED, GREEN, AND BLUE DACs Figure 8. Analog Output Termination for RS-343A IOR, IOG, IOB Using a variable value of RSET allows for accurate adjustment of the analog output video levels. Use of a fixed 560 Ω RSET resistor yields the analog output levels quoted in the Specifications section. These values typically correspond to the RS-343A video waveform values, as shown in Figure 7. DACs SYNC 0 18.67 − Video 18.67 − Video 18.67 18.67 18.67 18.67 full-scale output current against temperature and power supply variations. A resistance, RSET, connected between the RSET pin and GND, determines the amplitude of the output video level according to Equation 1 and Equation 2 for the ADV7125. IOG (mA) = 11,444.8 × VREF (V)/RSET (Ω) IOR/IOB (mA) 03097-006 IOG (mA) 26.0 Video + 7.2 Video 7.2 0 7.2 0 Z0 = 75Ω DACs ZS = 150Ω (SOURCE TERMINATION) (CABLE) ZL = 75Ω (MONITOR) TERMINATION REPEATED THREE TIMES FOR RED, GREEN, AND BLUE DACs The ADV7125 contains three matched 8-bit DACs. The DACs are designed using an advanced, high speed, segmented architecture. The bit currents corresponding to each digital input are routed to either the analog output (bit = 1) or GND (bit = 0) by a sophisticated decoding scheme. Because all this circuitry is on one monolithic device, matching between the three DACs is optimized. As well as matching, the use of identical current sources in a monolithic design guarantees monotonicity and low glitch. The on-board operational amplifier stabilizes the 03097-007 Video Output Level White Level Video Video to BLANK Black Level Black to BLANK BLANK Level SYNC Level Figure 9. Analog Output Termination for RS-170 More detailed information regarding load terminations for various output configurations, including RS-343A and RS-170, is available in the AN-205 Application Note, Video Formats and Required Load Terminations. Figure 7 shows the video waveforms associated with the three RGB outputs driving the doubly terminated 75 Ω load of Figure 8. As well as the gray scale levels (black level to white Rev. D | Page 13 of 17 ADV7125 Data Sheet GRAY SCALE OPERATION The ADV7125 can be used for standalone, gray scale (monochrome) or composite video applications (that is, only one channel used for video information). Any one of the three channels, red, green, or blue, can be used to input the digital video data. The two unused video data channels should be tied to Logic 0. The unused analog outputs should be terminated with the same load as that for the used channel, that is, if the red channel is used and IOR is terminated with a doubly terminated 75 Ω load (37.5 Ω), IOB and IOG should be terminated with 37.5 Ω resistors (see Figure 10). VIDEO OUTPUT R0 R7 DOUBLY TERMINATED 75Ω LOAD IOR IOG ADV7125 37.5Ω G0 G7 IOB 37.5Ω B7 GND 03097-008 B0 Figure 10. Input and Output Connections for Standalone Gray Scale or Composite Video VIDEO OUTPUT BUFFERS The ADV7125 is specified to drive transmission line loads. The analog output configuration to drive such loads is described in the Analog Outputs section and illustrated in Figure 11. However, in some applications, it may be required to drive long transmission line cable lengths. Cable lengths greater than 10 meters can attenuate and distort high frequency analog output pulses. The inclusion of output buffers compensates for some cable distortion. Buffers with large full power bandwidths and gains between two and four are required. These buffers also need to be able to supply sufficient current over the complete output voltage swing. Analog Devices produces a range of suitable op amps for such applications. These include the AD843, AD844, AD847, and AD848 series of monolithic op amps. In very high frequency applications (80 MHz), the AD8061 is recommended. More information on line driver buffering circuits is given in the relevant op amp data sheets. Use of buffer amplifiers also allows implementation of other video standards besides RS-343A and RS-170. Altering the gain components of the buffer circuit results in any desired video level. Z1 Z2 +VS IOR, IOG, IOB DACs ZS = 75Ω (SOURCE TERMINATION) 2 4 AD848 3 0.1µF 6 7 0.1µF 75Ω Z0 = 75Ω (CABLE) ZL = 75Ω (MONITOR) –VS GAIN (G) = 1 + Z1 Z2 03097-009 level), Figure 7 also shows the contributions of SYNC and BLANK for the ADV7125. These control inputs add appropriately weighted currents to the analog outputs, producing the specific output level requirements for video applications. Table 8 details how the SYNC and BLANK inputs modify the output levels. Figure 11. AD848 as an Output Buffer PCB LAYOUT CONSIDERATIONS The ADV7125 is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the excellent noise performance of the ADV7125, it is imperative that great care be given to the PCB layout. Figure 12 shows a recommended connection diagram for the ADV7125. The layout should be optimized for lowest noise on the ADV7125 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. Shorten the lead length between groups of VAA and GND pins to minimize inductive ringing. It is recommended to use a 4-layer printed circuit board with a single ground plane. The ground and power planes should separate the signal trace layer and the solder side layer. Noise on the analog power plane can be further reduced by using multiple decoupling capacitors (see Figure 12). Optimum performance is achieved by using 0.1 μF and 0.01 μF ceramic capacitors. Individually decouple each VAA pin to ground by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. It is important to note that while the ADV7125 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, pay close attention to reducing power supply noise. A dc power supply filter (Murata BNX002) provides EMI suppression between the switching power supply and the main PCB. Alternatively, consideration can be given to using a 3terminal voltage regulator. DIGITAL SIGNAL INTERCONNECT Isolate the digital signal lines to the ADV7125 as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane. Due to the high clock rates used, long clock lines to the ADV7125 should be avoided to minimize noise pickup. Connect any active pull-up termination resistors for the digital inputs to the regular PCB power plane (VCC) and not to the analog power plane. Rev. D | Page 14 of 17 Data Sheet ADV7125 ANALOG SIGNAL INTERCONNECT For optimum performance, the analog outputs should each have a source termination resistance to ground of 75 Ω (doubly terminated 75 Ω configuration). This termination resistance should be as close as possible to the ADV7125 to minimize reflections. Place the ADV7125 as close as possible to the output connectors, thus minimizing noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane and not the analog power plane, thereby maximizing the high frequency power supply rejection. Additional information on PCB design is available in the AN-333 Application Note, Design and Layout of a Video Graphics System for Reduced EMI. POWER SUPPLY DECOUPLING (0.1µF AND 0.01µF CAPACITOR FOR EACH VAA GROUP) 0.1µF VAA 0.01µF 13, 29, 30 0.1µF 35 COMP VAA VAA 41 TO 48 1kΩ VREF 36 R7 TO R0 1 AD1580 3 TO 10 RSET 37 VIDEO DATA INPUTS G7 TO G0 VAA 1µF 2 RSET 530Ω IOR 34 16 TO 23 B7 TO B0 MONITOR (CRT) COAXIAL CABLE 75Ω 75Ω IOG 32 75Ω ADV7125 IOB 28 75Ω 12 SYNC 11 BLANK 24 CLOCK 38 PSAVE 75Ω BNC CONNECTORS IOR 33 IOG 31 75Ω 75Ω COMPLEMENTARY OUTPUTS IOB 27 03097-010 GND 1, 2, 14, 15, 25, 26, 39, 40 Figure 12. Typical Connection Diagram Rev. D | Page 15 of 17 ADV7125 Data Sheet OUTLINE DIMENSIONS 0.75 0.60 0.45 9.20 9.00 SQ 8.80 1.60 MAX 37 48 36 1 PIN 1 7.20 7.00 SQ 6.80 TOP VIEW 1.45 1.40 1.35 0.15 0.05 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY SEATING PLANE (PINS DOWN) 25 12 13 24 0.27 0.22 0.17 VIEW A 0.50 BSC LEAD PITCH 051706-A VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 13. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.30 0.23 0.18 0.60 MAX 0.60 MAX 37 48 1 36 PIN 1 INDICATOR 6.85 6.75 SQ 6.65 0.50 REF 5.25 5.10 SQ 4.95 EXPOSED PAD 12 25 0.50 0.40 0.30 TOP VIEW 1.00 0.85 0.80 SEATING PLANE 12° MAX 13 24 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 14. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm × 7 mm Body and 0.85 mm Package Height (CP-48-1) Dimensions shown in millimeters Rev. D | Page 16 of 17 PIN 1 INDICATOR 06-05-2012-A 7.10 7.00 SQ 6.90 Data Sheet ADV7125 0.30 0.23 0.18 PIN 1 INDICATOR 36 1 0.50 BSC TOP VIEW 0.80 0.75 0.70 0.45 0.40 0.35 5.20 5.10 SQ 5.00 EXPOSED PAD 12 25 24 13 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 48 37 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WKKD. 112408-B 7.00 BSC SQ Figure 15. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm × 7 mm Body and 0.75 mm Package Height (CP-48-4) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2, 3 ADV7125KSTZ50 ADV7125KSTZ50-REEL ADV7125KSTZ140 ADV7125JSTZ240 ADV7125JSTZ330 ADV7125WBSTZ170 ADV7125WBSTZ170-RL ADV7125BCPZ170 ADV7125BCPZ170-RL ADV7125WBCPZ170 ADV7125WBCPZ170-RL Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C 0°C to +70°C 0°C to +70°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 48-Lead Low Profile Quad Flat Package [LQFP] 48-Lead Low Profile Quad Flat Package [LQFP] 48-Lead Low Profile Quad Flat Package [LQFP] 48-Lead Low Profile Quad Flat Package [LQFP] 48-Lead Low Profile Quad Flat Package [LQFP] 48-Lead Low Profile Quad Flat Package [LQFP] 48-Lead Low Profile Quad Flat Package [LQFP] 48-Lead Lead Frame Chip Scale Package [LFCSP] 48-Lead Lead Frame Chip Scale Package [LFCSP] 48-Lead Lead Frame Chip Scale Package [LFCSP] 48-Lead Lead Frame Chip Scale Package [LFCSP] Speed Option 50 MHz 50 MHz 140 MHz 240 MHz 330 MHz 170 MHz 170 MHz 170 MHz 170 MHz 170 MHz 170 MHz Package Option ST-48 ST-48 ST-48 ST-48 ST-48 ST-48 ST-48 CP-48-1 CP-48-1 CP-48-4 CP-48-4 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. 3 ADV7125JSTZ330 is available in a 3.3 V option only. 1 2 AUTOMOTIVE PRODUCTS The ADV7125W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ©2002–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03097-0-4/16(D) Rev. D | Page 17 of 17