AD5235-EP Data Sheet

FEATURES
Dual-channel, 1024-position resolution
25 kΩ nominal resistance
Low temperature coefficient: 35 ppm/°C
Nonvolatile memory stores wiper settings
Permanent memory write protection
Wiper setting readback
Resistance tolerance stored in EEMEM
Predefined linear increment/decrement instructions
Predefined ±6 dB/step log taper increment/decrement
instructions
SPI-compatible serial interface
2.7 V to 5 V single supply or ±2.5 V dual supply
26 bytes extra nonvolatile memory for user-defined
information
100-year typical data retention, TA = 55°C
Power-on refreshed with EEMEM settings
Enhanced Features
Supports defense and aerospace applications (AQEC)
Temperature range: −40°C to +125°C
Controlled manufacturing baseline
1 assembly/test site
1 fabrication site
Enhanced product change notification
Qualification data available on request
APPLICATIONS
DWDM laser diode driver, optical supervisory systems
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, time constants
Programmable power supply
Low resolution DAC replacement
Sensor calibration
GENERAL DESCRIPTION
The AD5235-EP is a dual-channel, nonvolatile memory,1
digitally controlled potentiometer2 with 1024-step resolution.
The device performs the same electronic adjustment function as a
mechanical potentiometer with enhanced resolution, solid state
reliability, and superior low temperature coefficient performance.
The AD5235-EP’s versatile programming via an SPI®-compatible
serial interface allows 16 modes of operation and adjustment
including scratchpad programming, memory storing and restoring,
increment/decrement, ±6 dB/step log taper adjustment, wiper setting
readback, and extra EEMEM1 for user-defined information such as
memory data for other components, look-up tables, or system
identification information.
FUNCTIONAL BLOCK DIAGRAM
CS
AD5235-EP
ADDR
DECODE
RDAC1
REGISTER
CLK
SDI
SERIAL
INTERFACE
SDO
PR
WP
RDY
EEMEM1
POWER-ON
RESET
A1
W1
RDAC1
RDAC2
REGISTER
RTOL*
26 BYTES
USER EEMEM
B1
A2
W2
EEMEM
CONTROL
EEMEM2
VDD
RDAC2
B2
VSS
GND
09185-001
Enhanced Product
Nonvolatile Memory, Dual
1024-Position Digital Potentiometer
AD5235-EP
*RAB TOLERANCE
Figure 1.
In scratchpad programming mode, a specific setting can be
programmed directly to the RDAC2 register that sets the resistance
between Terminal W and Terminal A, and Terminal W and
Terminal B. This setting can be stored into the EEMEM and
is restored automatically to the RDAC register during system
power-on.
The EEMEM content can be restored dynamically or through
external PR strobing, and a WP function protects EEMEM contents.
To simplify the programming, the independent or simultaneous
linear-step increment or decrement commands can be used to move
the RDAC wiper up or down, one step at a time. For logarithmic
±6 dB changes in the wiper setting, the left or right bit shift
command can be used to double or halve the RDAC wiper setting.
The AD5235-EP patterned resistance tolerance is stored in the
EEMEM. Therefore, in readback mode, the host processor can
know the actual end-to-end resistance. The host can execute the
appropriate resistance step through a software routine that simplifies
open-loop applications as well as precision calibration and
tolerance matching applications.
The AD5235-EP is available in a thin, 16-lead TSSOP package.
The part is guaranteed to operate over the extended industrial
temperature range of −40°C to +125°C.
Full details about this enhanced product, including theory of
operation, register details, and applications information, are
available in the AD5235 data sheet, which should be consulted
in conjunction with this data sheet.
1
2
The terms nonvolatile memory and EEMEM are used interchangeably.
The terms digital potentiometer and RDAC are used interchangeably.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
AD5235-EP
Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................7 Applications ....................................................................................... 1 ESD Caution...................................................................................7 General Description ......................................................................... 1 Pin Configuration and Function Descriptions..............................8 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................9 Revision History ............................................................................... 2 Test Circuits ..................................................................................... 13 Specifications..................................................................................... 3 Outline Dimensions ....................................................................... 14 Electrical Characteristics ............................................................. 3 Ordering Guide .......................................................................... 14 Interface Timing and EEMEM Reliability Characteristics ..... 5 REVISION HISTORY
7/12—Rev. 0 to Rev. A
Change to Features Section .............................................................. 1
Changes to Electrical Characteristics Section and Table 1 .......... 3
Changes to Interface Timing and EEMEM Reliability
Characteristics Section and Table 2 ................................................ 5
Changes to Typical Performance Characteristics Section ............ 9
Added Figure 14 and Figure 16, Renumbered Sequentially ......10
Deleted Figure 21 .............................................................................11
Added Figure 23...............................................................................12
7/10—Revision 0: Initial Version
Rev. A | Page 2 of 16
Enhanced Product
AD5235-EP
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = −2.5 V, VA = VDD, VB = VSS, −40°C < TA < +125°C, unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
(All RDACs)
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient
Wiper Resistance
Nominal Resistance Match
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (All RDACs)
Resolution
Differential Nonlinearity3
Integral Nonlinearity3
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Terminal Voltage Range4
Capacitance Ax, Bx5
Capacitance Wx5
Common-Mode Leakage Current5, 6
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Logic High
Symbol
Conditions
Min
R-DNL
R-INL
∆RAB/RAB
(∆RAB/RAB)/∆T × 106
RW
RWB
RWB
Code = full scale
−1
−2
−8
RAB1/RAB2
N
DNL
INL
(∆VW/VW)/∆T × 106
VWFSE
VWZSE
VA, VB, VW
CA, CB
CW
ICM
VIH
VIL
VIH
VIL
VIH
Input Logic Low
VIL
Output Logic High (SDO, RDY)
Output Logic Low
Input Current
Input Capacitance5
VOH
VOL
IIL
CIL
Typ1
35
30
IW = 1 V/RWB, VDD = 5 V, code =
half scale
IW = 1 V/RWB, VDD = 3 V, code =
half scale
Code = full scale, TA = 25°C
LSB
LSB
%
ppm/°C
Ω
65
±0.1
%
10
+1
+1
15
0
5
VSS
VDD
Bits
LSB
LSB
ppm/°C
LSB
LSB
11
V
pF
80
pF
0.01
±1
2.4
0.8
2.1
0.6
2.0
μA
V
V
V
V
V
0.5
V
0.4
±2.25
V
V
μA
pF
4.9
5
Rev. A | Page 3 of 16
+1
+2
+8
Ω
−7
0
f = 1 MHz, measured to GND,
code = half-scale
f = 1 MHz, measured to GND,
code = half-scale
VW = VDD/2
With respect to GND, VDD = 5 V
With respect to GND, VDD = 5 V
With respect to GND, VDD = 3 V
With respect to GND, VDD = 3 V
With respect to GND, VDD = +2.5 V,
VSS = −2.5 V
With respect to GND, VDD = +2.5 V,
VSS = −2.5 V
RPULL-UP = 2.2 kΩ to 5 V
IOL = 1.6 mA, VLOGIC = 5 V
VIN = 0 V or VDD
Unit
50
−1
−1
Code = half scale
Code = full scale
Code = zero scale
Max
AD5235-EP
Parameter
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
Enhanced Product
Symbol
Conditions
Min
VDD
VDD/VSS
IDD
ISS
VSS = 0 V
2.7
±2.25
EEMEM Store Mode Current
IDD (store)
EEMEM Restore Mode Current7
ISS (store)
IDD (restore)
Power Dissipation8
Power Supply Sensitivity5
DYNAMIC CHARACTERISTICS5, 9
Bandwidth
Total Harmonic Distortion
VW Settling Time
ISS (restore)
PDISS
PSS
BW
THDW
tS
Resistor Noise Density
Crosstalk (CW1/CW2)
eN_WB
CT
Analog Crosstalk
CTA
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND, VDD = +2.5 V,
VSS = −2.5 V
VIH = VDD or VIL = GND, VSS = GND,
ISS ≈ 0
VDD = +2.5 V, VSS = −2.5 V
VIH = VDD or VIL = GND, VSS = GND,
ISS ≈ 0
VDD = +2.5 V, VSS = −2.5 V
VIH = VDD or VIL = GND
ΔVDD = 5 V ± 10%
−3 dB, VDD/VSS = ±2.5 V
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = VDD, VB = 0 V,
VW = 0.50% error band,
Code 0x000 to Code 0x200
TA = 25°C
VA = VDD, VB = 0 V, measured VW1
with VW2 making full-scale change
VDD = VA1 = +2.5 V,
VSS = VB1 = −2.5 V, measured
VW1 with VW2 = 5 V p-p @ f = 1 kHz,
Code 1 = 0x200, Code 2 = 0x3FF
1
−6
Typ1
2
−2
Max
Unit
5.5
±2.75
7
V
V
μA
μA
2
mA
−2
320
mA
μA
−320
10
0.006
40
0.01
μA
μW
%/%
125
0.009
4
kHz
%
μs
20
30
nV/√Hz
nV-s
−110
dB
Typicals represent average readings at 25°C and VDD = 5 V.
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. IW ~ 50 μA for VDD = 2.7 V and IW ~ 400 μA for VDD = 5 V (see Figure 25).
3
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = VSS. DNL specification limits of
±1 LSB maximum are guaranteed monotonic operating conditions (see Figure 26).
4
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables groundreferenced bipolar signal adjustment.
5
Guaranteed by design and not subject to production test.
6
Common-mode leakage current is a measure of the dc leakage from any Terminal A, Terminal B, or Terminal W to a common-mode bias level of VDD/2.
7
EEMEM restore mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register (see Figure 22). To
minimize power dissipation, a NOP, Instruction 0 (0x0) should be issued immediately after Instruction 1 (0x1).
8
PDISS is calculated from (IDD × VDD) + (ISS × VSS).
9
All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V.
2
Rev. A | Page 4 of 16
Enhanced Product
AD5235-EP
INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS
Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input
control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are
measured using both VDD = 2.7 V and VDD = 5 V.
Table 2.
Parameter
Clock Cycle Time (tCYC)
CS Setup Time
CLK Shutdown Time to CS Rise
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay2
CLK to SDO Data Hold Time
CS High Pulse Width3
CS High to CS High3
RDY Rise to CS Fall
CS Rise to RDY Fall Time
Store EEMEM Time4, 5
Read EEMEM Time4
CS Rise to Clock Rise/Fall Setup
Preset Pulse Width (Asynchronous)6
Preset Response Time to Wiper Setting6
Power-On EEMEM Restore Time6
FLASH/EE MEMORY RELIABILITY
Endurance7
Symbol
t1
t2
t3
t4, t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t16
t17
tPRW
tPRESP
tEEMEM
Conditions
Clock level high or low
From positive CLK transition
From positive CLK transition
RP = 2.2 kΩ, CL < 20 pF
RP = 2.2 kΩ, CL < 20 pF
Min
20
10
1
10
5
5
Typ1
40
50
50
0
10
4
0
0.15
15
7
Applies to Instructions 0x2, 0x3
Applies to Instructions 0x8, 0x9, 0x10
10
50
PR pulsed low to refresh wiper positions
30
30
TA = 25°C
1
100
Data Retention8
100
1
Max
0.3
50
30
Unit
ns
ns
tCYC
ns
ns
ns
ns
ns
ns
ns
ns
tCYC
ns
ms
ms
μs
ns
ns
μs
μs
MCycles
kCycles
Years
Typicals represent average readings at 25°C and VDD = 5 V.
Propagation delay depends on the value of VDD, RPULL-UP, and CL.
Valid for commands that do not activate the RDY pin.
4
The RDY pin is low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 μs; CMD_9, CMD_10 ~ 7 μs;
CMD_2, CMD_3 ~ 15 ms; PR hardware pulse ~ 30 μs.
5
Store EEMEM time depends on the temperature and EEMEM writes cycles. Higher timing is expected at a lower temperature and higher write cycles.
6
Not shown in Figure 2 and Figure 3.
7
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +125°C.
8
Retention lifetime equivalent at junction temperature (TJ) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
2
3
Rev. A | Page 5 of 16
AD5235-EP
Enhanced Product
Timing Diagrams
CPHA = 1
t12
CS
CLK
CPOL = 1
t13
t3
t1
t2
t5
B23
B0
t17
t4
t7
SDI
t6
HIGH
OR LOW
B23 (MSB)
t8
t11
t10
B24*
SDO
HIGH
OR LOW
B0 (LSB)
B23 (MSB)
t9
B0 (LSB)
t14
t15
t16
09185-002
RDY
*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE LSB OF THE CHARACTER PREVIOUSLY TRANSMITTED.
THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2. CPHA = 1 Timing Diagram
CPHA = 0
CS
t12
t1
t2
CLK
CPOL = 0
t3
t5
B23
t13
t17
B0
t4
t7
SDI
t6
HIGH
OR LOW
t10
t8
HIGH
OR LOW
B0 (LSB)
B23 (MSB IN)
t11
t9
SDO
B23 (MSB OUT)
B0 (LSB)
t14
*
t15
t16
*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE MSB OF THE CHARACTER JUST RECEIVED.
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 3. CPHA = 0 Timing Diagram
Rev. A | Page 6 of 16
09185-003
RDY
Enhanced Product
AD5235-EP
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
VSS to GND
VDD to VSS
VA, VB, VW to GND
IA, IB, IW
Pulsed1
Continuous
Digital Input and Output Voltage to GND
Operating Temperature Range2
Maximum Junction Temperature (TJ max)
Storage Temperature Range
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
Thermal Resistance
Junction-to-Ambient, θJA
Junction-to-Case, θJC
Package Power Dissipation
Rating
–0.3 V to +7 V
+0.3 V to −7 V
7V
VSS − 0.3 V to VDD + 0.3 V
±2.5 mA
±1.1 mA
−0.3 V to VDD + 0.3 V
−40°C to +125°C
150°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
215°C
220°C
150°C/W
28°C/W
(TJ max − TA)/θJA
1
Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Includes programming of nonvolatile memory.
Rev. A | Page 7 of 16
AD5235-EP
Enhanced Product
CLK 1
16
RDY
SDI 2
15
CS
14
PR
GND 4
AD5235-EP
13
WP
VSS 5
TOP VIEW
(Not to Scale)
12
VDD
A1 6
11
A2
W1 7
10
W2
B1 8
9
B2
SDO 3
09185-004
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
CLK
SDI
SDO
4
5
GND
VSS
6
7
8
9
10
11
12
13
A1
W1
B1
B2
W2
A2
VDD
WP
14
PR
15
16
CS
RDY
Description
Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.
Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO
output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and
after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI
bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This
previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up
resistor in the range of 1 kΩ to 10 kΩ is needed.
Ground Pin, Logic Ground Reference.
Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink
35 mA for 30 ms when storing data to EEMEM.
Terminal A of RDAC1.
Wiper terminal of RDAC1. ADDR (RDAC1) = 0x0.
Terminal B of RDAC1.
Terminal B of RDAC2.
Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1.
Terminal A of RDAC2.
Positive Power Supply.
Optional Write Protect. When active low, WP prevents any changes to the present contents, except PR strobe.
CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Execute a NOP instruction before returning to WP
high. Tie WP to VDD, if not used.
Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM
register. Factory default loads midscale 51210 until EEMEM is loaded with a new value by the user. PR is activated
at the logic high transition. Tie PR to VDD, if not used.
Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.
Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8,
Instruction 9, Instruction 10, and PR.
Rev. A | Page 8 of 16
Enhanced Product
AD5235-EP
TYPICAL PERFORMANCE CHARACTERISTICS
–40
+25
+85
+125
0.20
0.20
0.15
R-DNL ERROR (LSB)
0.10
0.05
0
0.05
0
0.15
–0.10
0
200
400
600
800
1000
–0.15
400
600
800
1000
Figure 8. R-DNL vs. Code, TA = −40°C, +25°C, +85°C, +125°C Overlay
0.10
0.08
0.06
0.04
0.02
0
0.02
180
160
140
120
100
80
60
40
20
200
400
600
800
09185-006
0
0
1000
DIGITAL CODE
0
256
512
768
1023
CODE (Decimal)
09185-009
0.12
POTENTIOMETER MODE TEMPCO (ppm/°C)
–40
+25
+85
+125
0.14
Figure 9. (∆VW/VW)/∆T × 106 Potentiometer Mode Tempco
Figure 6. DNL vs. Code, TA = −40°C, +25°C, +85°C, +125°C Overlay
200
–40
+25
+85
+125
180
RHEOSTAT MODE TEMPCO (ppm/°C)
0.15
0.10
0.05
0
0.05
0.10
0.15
160
140
120
100
80
60
40
20
200
400
600
DIGITAL CODE
800
1000
09185-007
0
0
0
256
512
768
CODE (Decimal)
Figure 10. (∆RWB/RWB)/∆T × 106 Rheostat Mode Tempco
Figure 7. R-INL vs. Code, TA = −40°C, +25°C, +85°C, +125°C Overlay,
Rev. A | Page 9 of 16
1023
09185-010
0.20
0.20
200
200
0.16
0.04
0
DIGITAL CODE
Figure 5. INL vs. Code, TA = −40°C, +25°C, +85°C, +125°C Overlay
DNL ERROR (LSB)
0.05
–0.05
DIGITAL CODE
R-INL ERROR (LSB)
0.10
0.10
09185-005
INL ERROR (LSB)
0.15
0.20
–40
+25
+85
+125
09185-008
0.25
AD5235-EP
Enhanced Product
60
2.7V
3.0V
3.3V
5.0V
5.5V
40
300
IDD (µA)
30
200
20
0
200
400
600
800
1000
CODE (Decimal)
0
09185-011
0
0
IDD
IDD
IDD
IDD
IDD
2
3
4
5
Figure 14. IDD vs. Digital Input Voltage
0.12
= 2.7V
= 3.3V
= 3.0V
= 5.0V
= 5.5V
0.10
1
0.08
THD + N (%)
IDD/ISS (µA)
2
VDIO (V)
Figure 11. Wiper On Resistance vs. Code
3
1
09185-014
100
10
0
–1
0.06
0.04
–2
–3
–55
–50
= 2.7V
= 3.3V
= 3.0V
= 5.0V
= 5.5V
–40
0.02
–20
0
25
40
60
85
100
110
125
TEMPERATURE (°C)
0
10
09185-012
ISS
ISS
ISS
ISS
ISS
1k
10k
100k
FREQUENCY (Hz)
Figure 12. IDD vs. Temperature
50
100
09185-015
WIPER ON RESISTANCE (Ω)
50
2.7V
3.0V
3.3V
5.0V
5.5V
400
Figure 15. THD + Noise vs. Frequency
10
FULL SCALE
MIDSCALE
ZERO SCALE
40
1
THD + N (%)
20
1
2
3
4
5
6
7
FREQUENCY (MHz)
8
9
10
Figure 13. IDD vs. Clock Frequency
0.001
0.0001
0.001
0.01
0.1
AMPLITUDE (V rms)
Figure 16. THD + Noise vs. Amplitude
Rev. A | Page 10 of 16
1
10
09185-016
0
0.1
0.01
10
09185-013
I DD (µA)
30
Enhanced Product
AD5235-EP
3
–3
VDD
–6
VW (FULL SCALE)
f–3dB = 125kHz
–12
1k
10k
100k
1M
FREQUENCY (Hz)
09185-017
VDD/VSS = ±2.5V
VA = 1V rms
D = MIDSCALE
10µs/DIV
Figure 20. Power-On Reset
Figure 17. −3 dB Bandwidth vs. Resistance (See Figure 31)
2.5196
0
CODE 0x200
–10
0x100
2.512
2.508
AMPLITUDE (V)
GAIN (dB)
–20
0x040
0x020
–30
0x010
0x008
–40
2.500
2.496
2.492
0x002
2.488
0x001
2.484
10k
100k
1M
FREQUENCY (Hz)
09185-018
1k
2.4796
Figure 18. Gain vs. Frequency vs. Code, (See Figure 31)
–10
2.504
0x004
–50
0
VDD = VSS = 5V
CODE = 0x200 TO 0x1FF
2.516
0x080
–60
VDD = 5V
VA = 5V
VB = 0V
TA = 25°C
1V/DIV
0
20
40
60
80
100
120
144
TIME (µs)
Figure 21. Midscale Glitch Energy
VDD = 5V ± 10% AC
VSS = 0V, V A = 4V, V B = 0V
MEASURED AT VW WITH CODE = 0x200
TA = 25°C
CS (5V/DIV)
–20
VDD = 5V
TA = 25°C
CLK (5V/DIV)
–40
–50
SDI (5V/DIV)
–60
–80
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
IDD (2mA/DIV)
Figure 22. IDD vs. Time when Storing Data to EEMEM
Figure 19. PSRR vs. Frequency
Rev. A | Page 11 of 16
02816-023
–70
09185-019
PSRR (dB)
–30
09185-021
–9
09185-020
GAIN (dB)
0
AD5235-EP
Enhanced Product
100
2.50
2.45
2.40
0
0.5
1.0
1.5
TIME (µs)
2.0
09185-024
WIPER VOLTAGE (V)
2.55
Figure 23. Digital Feedthrough
VA = VB = OPEN
TA = 25°C
10
1
RAB = 25kΩ
0.1
0.01
0
128
256
384
512
640
CODE (Decimal)
Figure 24. IWB_MAX vs. Code
Rev. A | Page 12 of 16
768
896
1023
09185-125
THEORECTICAL (IWB_MAX – mA)
2.60
Enhanced Product
AD5235-EP
TEST CIRCUITS
Figure 25 to Figure 35 define the test conditions used in the Specifications section.
NC
IW
+15V
A
W
VIN
B
VMS
09185-026
OP42
B
2.5V
Figure 25. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
–15V
Figure 31. Gain vs. Frequency
RSW =
DUT
DUT
V+
W
B
VMS
B
0.1V
ISW
CODE = 0x00
W
V+ = VDD
1LSB = V+/2N
09185-027
A
VOUT
+
ISW
–
0.1V
VSS TO VDD
A = NC
09185-033
NC = NO CONNECT
DUT
OFFSET
GND
09185-032
DUT
A
W
Figure 32. Incremental On Resistance
Figure 26. Potentiometer Divider Nonlinearity Error (INL, DNL)
NC
VW
VSS GND
B
ICM
W
VCM
VMS1
RW = [VMS1 – VMS2]/IW
09185-028
B
NC
NC = NO CONNECT
Figure 27. Wiper Resistance
Figure 33. Common-Mode Leakage Current
VDD
A1
VA
VIN
V+ = VDD ±10%
~
A
PSRR (dB) = 20 LOG
W
B
PSS (%/%) =
VMS
(
∆VMS
∆VDD
)
NC
W2
W1
B1
∆VDD%
Figure 34. Analog Crosstalk
200µA
IOL
DUT B
5V
W
VIN
TO OUTPUT
PIN
VOUT
09185-030
OP279
OFFSET
GND
OFFSET BIAS
OP279
VOUT
A
DUT
B
09185-031
W
OFFSET BIAS
IOH
Figure 35. Load Circuit for Measuring VOH and VOL (The diode bridge test
circuit is equivalent to the application circuit with RPULL-UP of 2.2 kΩ.)
5V
VIN
VOH (MIN)
OR
VOL (MAX)
CL
50pF
200µA
Figure 29. Inverting Gain
OFFSET
GND
VOUT
B2
VSS
CTA = 20 LOG[VOUT/VIN]
NC = NO CONNECT
Figure 28. Power Supply Sensitivity (PSS, PSRR)
A
A2
RDAC2
∆VMS%
09185-029
V+
VDD
RDAC1
09185-036
W
VMS2
A
09185-035
A
VDD
DUT
09185-034
IW = VDD/RNOMINAL
DUT
Figure 30. Noninverting Gain
Rev. A | Page 13 of 16
AD5235-EP
Enhanced Product
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.65
BSC
0.30
0.19
COPLANARITY
0.10
0.20
0.09
SEATING
PLANE
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 36. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5235BRU25-EP-RL7
R AB (kΩ)
25
Temperature Range
−40°C to +125°C
Rev. A | Page 14 of 16
Package Description
16-Lead TSSOP
Package Option
RU-16
Enhanced Product
AD5235-EP
NOTES
Rev. A | Page 15 of 16
AD5235-EP
Enhanced Product
NOTES
©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09185-0-7/12(A)
Rev. A | Page 16 of 16
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