AD5235-DSCC: Military Data Sheet (Rev. A)

REVISIONS
LTR
DESCRIPTION
A
Change in Table I for new re-design. - PHN
DATE
APPROVED
13-03-12
Thomas M. Hess
Prepared in accordance with ASME Y14.24
Vendor item drawing
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PMIC N/A
PREPARED BY
Phu H. Nguyen
Original date of drawing
YY MM DD
CHECKED BY
10-12-14
APPROVED BY
Thomas M. Hess
A
REV
AMSC N/A
TITLE
Phu H. Nguyen
SIZE
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
CODE IDENT. NO.
MICROCIRCUIT, DIGITAL, NONVOLATILE
MEMORY, DUAL 1024-POSITION DIGITAL
POTENTIOMETER, MONOLITHIC SILICON
DWG NO.
V62/11605
16236
A
PAGE
1
OF
13
5962-V054-13
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance non volatile memory, dual 1024-position digital
potentiometer microcircuit, with an operating temperature range of -40°C to +125°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/11605
-
Drawing
number
01
X
B
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s).
Device type
Generic
01
Circuit function
AD5235-EP
Nonvolatile memory, dual 1024-position
digital potentiometer
1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter
Number of pins
X
16
JEDEC PUB 95
Package style
JEDEC MO-153
Small outline Package
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
Z
DLA LAND AND MARITIME
COLUMBUS, OHIO
Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/11605
PAGE
2
1.3 Absolute maximum ratings.
1/
Voltage referenced :
VDD to GND ............................................................................
VSS to GND ............................................................................
VDD to VSS ..............................................................................
VA, VB, VW to GND .................................................................
Current referenced, IA, IB, IW:
Pulsed 2/ ..............................................................................
Continuous .............................................................................
Digital input and output voltage to GND ........................................
Ambient operating temperature range 3/ .....................................
Storage temperature range ...........................................................
Maximum junction temperature (TJ) ..............................................
Lead temperature, soldering:
Vapor phase (60 sec) ................................................................
Infrared (15 sec) ........................................................................
Thermal resistance, junction to ambient (θJA) ...............................
Thermal resistance, junction to case (θJC) .....................................
Package power dissipation ...........................................................
-0.3 V to +7.0 V
+0.3 V to -7.0 V
7.0 V
VSS – 0.3 V to VDD + 0.3 V
±2.5 mA
±1.1 mA
-0.3 V to VDD + 0.3 V
-40°C to +125°C
-65°C to +150°C
150°C
215°C
220°C
150°C /W
28°C /W
(TJ max – TA)/ θJA
2. APPLICABLE DOCUMENTS
JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)
JEP95
JESD22a117
JESD51-2a
–
–
–
Registered and Standard Outlines for Semiconductor Devices
Electrical Erasable programmable ROM (EEPROM) Program/Erase endurance and data retention test.
Integrated Circuits Thermal Test Method Environment Conditions – Natural Convection (Still Air)
(Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103
North 10th Street, Suite 240–S, Arlington, VA 22201-2107).
1/
2/
3/
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the
package, and maximum applied voltage across any two of the A, B and W terminals at a given resistance.
Includes programming of nonvolatile memory.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/11605
PAGE
3
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as
specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Terminal functions. The terminal functions shall be as shown in figure 3.
3.5.3 Functional block diagram. The functional block diagram shall be as shown in figure 4.
3.5.4 Timing diagrams. The timing diagrams shall be as shown in figure 5 and 6.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/11605
PAGE
4
TABLE I. Electrical performance characteristics. 1/
Test
Symbol
DC characteristic-RHEOSTAT mode (All RDACs)
Resistor differential nonlinearity 4/
R-DNL
Resistor integral nonlinearity 4/
R-INL
Nominal resistor tolerance
∆RAB/RAB
6
Resistance temperature coefficient
(∆RAB/RAB)∆Tx10
Wipe resistance
RW
Test conditions
2/
unless otherwise specified
Limits
Min
RWB
RWB
Code = full scale
Typ
3/
-1
-2
-8
35
30
50
±0.1
IW = 1 V/RWB, VDD = 5 V, code = half scale
IW = 1 V/RWB, VDD = 3 V, code = half scale
Nominal resistance match
RAB1/RAB2
Code = full scale, TA = 25°C
DC characteristics – Potentiometer divider mode (All RDACs)
Resolution
N
Differential nonlinearity 5/
DNL
Integral nonlinearity
5/
INL
Voltage divider temperature
(∆VW/VW)∆T x
Code = half scale
6
coefficient
10
Full scale error
VWFSE
Code = full scale
Zero scale error
VWZSE
Code = zero scale
Resistor terminals
Terminal voltage range 6/
VA, VB, VW
Capacitance Ax, Bx 7/
CA, CB
f = 1 MHz, measured to GND,
code = half scale
Capacitance Wx 7/
CW
Common mode leakage current 7/ 8/
ICM
VW = VDD/2
Digital inputs and outputs
Input logic high
VIH
With respect to GND, VDD = 5 V
Input logic low
VIL
With respect to GND, VDD = 5 V
Input logic high
VIH
With respect to GND, VDD = 3 V
Input logic low
VIL
With respect to GND, VDD = 3 V
Input logic high
VIH
With respect to GND, VDD = +2.5 V,
VSS = -2.5 V
Input logic low
VIL
With respect to GND, VDD = +2.5 V,
VSS = -2.5 V
Output logic high (SDO, RDY)
VOH
RPULL-UP = 2.2 kΩ to 5 V
Output logic low
VOL
IOL = 1.6 mA, VLOGIC = 5 V
Input current
IIL
Input capacitance 7/
CIL
Unit
Max
+1
+2
+8
LSB
LSB
%
65
ppm/°C
Ω
%
10
+1
+1
-1
-1
15
Bits
LSB
LSB
ppm/°C
-7
0
0
5
LSB
LSB
VSS
VDD
V
pF
±1
µA
11
80
0.01
2.4
V
0.8
2.1
0.6
2.0
0.5
4.9
0.4
±2.25
µA
pF
5
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/11605
PAGE
5
TABLE I. Electrical performance characteristics - Continued. 1/
Test
Symbol
Power supplies
Single supply power range
Dual supply power range
Positive supply current
Negative supply current
VDD
VDD/VSS
IDD
ISS
EEMEM store mode current
IDD(store)
EEMEM restore mode current 9/
ISS(store)
IDD(restore)
Power dissipation 10/
Power supply sensitivity 7/
Dynamic characteristics
7/ 11/
Bandwidth
Total harmonic distortion
VW settling time
Resistor noise density
Crosstalk (CW1/CW2)
Analog crosstalk
ISS(restore)
PDISS
PSS
BW
THDW
ts
eN_WB
CT
CTA
Test conditions
2/
unless otherwise specified
VSS = 0 V
Limits
Min
Typ
3/
2.7
±2.25
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND, VDD = +2.5 V,
VSS = -2.5 V
VIH = VDD or VIL = GND, VSS = GND,
ISS ≈ 0
VDD = +2.5 V, VSS = -2.5 V
VIH = VDD or VIL = GND, VSS = GND,
ISS ≈ 0
VDD = +2.5 V, VSS = -2.5 V
VIH = VDD or VIL = GND
∆VDD = 5 V ± 10%
-6
2
-2
Max
5.5
±2.75
7
V
V
µA
µA
2
mA
-2
320
mA
µA
-320
10
0.006
-3 dB, VDD/VSS = ±2.5 V
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = VDD, VB = 0 V,
VW = 0.50% error band,
Code 0x000 to code 0x200
TA = 25°C
VA = VDD, VB = 0 V,
measured VW1 with VW2 making full scale
change
VDD = VA1 = +2.5 V, VSS = VB1 = -2.5 V,
measured VW1 with
VW2 = 5 [email protected] = 1 kHz,
Code 1 = 0x200, code 2 = 0x3FF
Unit
40
0.01
µA
µW
%/%
125
0.009
4
kHz
%
µs
20
30
nV/√Hz
nV-s
-110
dB
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/11605
PAGE
6
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Interface timing and EEMEM reliability characteristics
Clock cycle time (tCYC)
t1
��� setup time
t2
CS
��� rise
t3
CLK shut down time for CS
Input clock pulse width
t4 , t5
Data setup time
t6
Data hold time
t7
��� to SDO-SPI line acquire
t8
CS
��� to SDO-SPI line release
t9
CS
CLK to SDO propagation delay 13/
t10
CLK to SDO data hold time
t11
��� high pulse width 14/
t12
CS
��� high to CS
��� high 14/
t13
CS
��� fall
t14
RDY rise to CS
���
t15
CS rise to RDY fall time
Store EEMEM time 15/ 16/
t16
Read EEMEM time 15/
t16
���
t17
CS rise to clock rise/Fall setup
Preset pulse width (Asynchronous) 17/
tPRW
Preset response time to wiper setting 17/
tPRESP
Power ON EEMEM restore time 17/
tEEMEM
Flash/EE memory reliability
Endurance
18/
Limits
Test conditions
2/
unless otherwise specified
Min
Unit
Max
12/
20
10
1
10
5
5
Clock level high or low
From positive CLK transition
From positive CLK transition
ns
ns
tCYC
ns
40
50
50
RP = 2.2 kΩ, CL < 20 pF
RP = 2.2 kΩ, CL < 20 pF
0
10
4
0
0.15
15
7
Applies to instruction 0x2, 0x3
Applies to instruction 0x8, 0x9, and 0x10
0.3
50
30
15
50
����pulsed low to refresh wiper positions
PR
30
30
1
TA = 25°C
MCycles
kCycles
Years
100
Data retention
19/
tCYC
ns
ms
ms
µs
ns
ns
µs
µs
100
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/11605
PAGE
7
TABLE I. Electrical performance characteristics - Continued.
1/
2/
3/
4/
5/
6/
7/
8/
9/
10/
11/
12/
13/
14/
15/
16/
17/
18/
19/
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not
necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
VDD = 3 V to 5.5 V, VSS =0; VDD = 2.5 V, VSS = -2.5 V, VA = VDD, VB = VSS, -40°C < TA < 125°C (unless otherwise noted). The part
can be operated at 2.7 V single supply, except from 0°C to -40°C, where a minimum of 3 V is needed.
Typicals (TYP) represent average readings at 25°C and VDD = 5V.
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the
minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. IW ~ 50
µA for VDD = 2.7 V and IW ~ 400 µA for VDD = 5 V.
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD
and VB = VSS. DNL specification limits of ±1 LSB maximum guaranteed monotonic operating conditions.
Resistor terminal A, Resistor terminal B, and resistor terminal W has no limitations on polarity with respect to each other. Dual supply
operation enables ground-referenced bipolar signal adjustment.
Guaranteed by design and not subject to production test.
Common mode leakage current is a measure of the dc leakage from any terminal A, terminal B, or terminal W to a common mode bias
level of VDD/2.
EEMEM response mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the
RDAC register. To minimize power dissipation, on a NOP, instruction 0 (0x0) should be issued immediately after instruction 1 (0x1).
PDISS is calculated from (IDD x VDD) + (ISS x VSS).
All dynamic characteristics use VDD = +2.5 V and VSS = -2.5 V.
Guaranteed by design and not subject to production test. See the timing diagrams section for the location of measured values. All
input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level 0f 1.5 V. Switching
characteristics are measured using both VDD = 3 V and VDD = 5 V.
Propagation delay depends on the value of VDD, RPULL-UP, and CL.
Valid for commands that do not activate the RDY pin.
���� hardware pulse;
RDY pin low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR
���� hardware pulse ~30 µs.
CMD_8 ~ 20 µs; CMD_9, CMD_10 ~ 7 µs; CMD_2, CMD_3 ~ 15 ms; PR
Store EEMEM time depends on the temperature and EEMEJM writes cycles. Higher timing is expected at a lower temperature and
higher write cycles.
Not shown in FIGURE 5 and FIGURE 6.
Endurance is qualified to 100,000 cycles per JEDEC standard 22, method A117 and measured at -40°C, +25°C, and +125°C.
Retention life time equivalent at junction temperature (TJ) = 85°C per JEDEC standard 22, method A117. Retention lifetime based on
an activation energy of 1 eV derates with junction temperature in the Flash/EE memory.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
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DWG NO.
V62/11605
PAGE
8
Case X
Symbol
A
A1
b
c
D
Dimensions
Millimeters
Symbol
Min
Max
0.05
0.19
0.09
4.90
1.20
0.15
0.30
0.20
5.10
E
E1
e
L
Millimeters
Min
Max
4.30
4.50
6.40 TYP
0.65 BSC
0.45
0.75
FIGURE 1. Case outline.
DLA LAND AND MARITIME
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CODE IDENT NO.
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Case outline X
Terminal
Terminal
symbol
number
Terminal
number
1
2
3
4
5
6
7
8
CLK
SDI
SDO
GND
VSS
A1
W1
B1
Terminal
symbol
16
15
14
13
12
11
10
9
RDY
���
CS
����
PR
�����
WP
VDD
A2
W2
B2
FIGURE 2. Terminal connections.
Pin No.
1
2
Mnemonic
CLK
SDI
3
SDO
4
5
GND
VSS
6
7
8
9
10
11
12
13
A1
W1
B1
B2
W2
A2
VDD
�����
WP
14
����
PR
15
���
CS
16
RDY
Description
Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
Serial Data Input. Shifts in one bit at a time on positive clock CLK
edges. MSB loads first.
Serial Data Output. Serves readback and daisy-chain functions. Command 9 and
Command 10 activate the SDO output for the readback function, delayed by 24 or 25
clock pulses, depending on the clock polarity before and after the data-word (see
Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded
SDI bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see
Figure 2 and Figure 3). This previously shifted out SDI can be used for daisy-chaining
multiple devices. Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10
kΩ is needed.
Ground Pin, Logic Ground Reference.
Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual
supply, it must be able to sink 35 mA for 30 ms when storing data to EEMEM.
Terminal A of RDAC1.
Wiper terminal of RDAC1.ADDR(RDAC1)=0x0.
Terminal B of RDAC1.
Terminal B of RDAC2.
Wiper terminal of RDAC2.ADDR(RDAC2)=0x1.
Terminal A of RDAC2.
Positive Power Supply.
����� prevents any changes to the present
Optional Write Protect. When active low, WP
���� strobe. CMD_1 and COMD_8 refresh the RDAC register from
contents, except PR
����� high. Tie WP
����� to VDD, if
EEMEM. Execute a NOP instruction before returning to WP
not used.
Optional Hardware Override Preset. Refreshes the scratchpad register with current
contents of the EEMEM register. Factory default loads midscale 51210 until EEMEM is
���� is activated at the logic high transition. Tie
loaded with a new value by the user. PR
���� to VDD, if not used.
PR
���
Serial Register Chip Select Active Low. Serial register operation takes place when CS
returns to logic high.
Ready. Active high open-drain output. Identifies completion of Instruction 2,
����.
Instruction 3, Instruction 8, Instruction 9, Instruction 10, and PR
FIGURE 3. Terminal functions.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
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DWG NO.
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10
FIGURE 4. Functional block diagram.
DLA LAND AND MARITIME
COLUMBUS, OHIO
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CODE IDENT NO.
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NOTES:
1. The extra bit that is not defined is normally the LSB of the character previously transmitted.
The CPOL = 1 microcontroller command aligns the incoming data to the positive edge of the clock.
FIGURE 5. Timing diagram.
NOTES:
1. The extra bit that is not defined is normally the MSB of the character just received.
The CPOL = 0 microcontroller command aligns the incoming data to the positive edge of the clock.
FIGURE 6. Timing diagram.
DLA LAND AND MARITIME
COLUMBUS, OHIO
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CODE IDENT NO.
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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of
present or continued availability as a source of supply for the item.
Vendor item drawing
administrative control number 1/
Device
manufacturer
CAGE code
Vendor part number
V62/11605-01XB
24355
AD5235BRU25-EP-RL7
1/
The vendor item drawing establishes an administrative control number for
identifying the item on the engineering documentation.
CAGE code
24355
DLA LAND AND MARITIME
COLUMBUS, OHIO
Source of supply
Analog Devices
Rt 1 Industrial Park
PO Box 9106
Norwood, MA 02062
Point of contact: 7910 Triad Center Drive
Greensboro, NC 27409-9605
SIZE
A
CODE IDENT NO.
16236
REV
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DWG NO.
V62/11605
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