Blackfin FPGA EZ-Extender Manual (Rev. 1.0)

Blackfin FPGA EZ-Extender
Manual
Revision 1.0, October 2005
Part Number
82-000920-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106
a
Copyright Information
© 2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.
Printed in the USA.
Limited Warranty
The Blackfin FPGA EZ-Extender is warranted against defects in materials
and workmanship for a period of one year from the date of purchase from
Analog Devices or from an authorized dealer.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices logo, Blackfin, VisualDSP++, and EZ-KIT Lite are
registered trademarks of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.
Regulatory Compliance
The Blackfin FPGA EZ-Extender has been certified to comply with the
essential requirements of the European EMC directive 89/336/EEC
(inclusive 93/68/EEC) and, therefore, carries the “CE” mark.
The Blackfin FPGA EZ-Extender had been appended to Analog Devices
Development Tools Technical Construction File referenced
“DSPTOOLS1” dated December 21, 1997 and was awarded CE Certification by an appointed European Competent Body and is on file.
The EZ-KIT Lite evaluation system contains ESD
(electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human
body and equipment and can discharge without
detection. Permanent damage may occur on devices
subjected to high-energy discharges. Proper ESD
precautions are recommended to avoid performance
degradation or loss of functionality. Store unused
EZ-KIT Lite boards in the protective shipping
package.
CONTENTS
PREFACE
Product Overview ........................................................................... ix
Purpose of This Manual .................................................................. xi
Intended Audience .......................................................................... xi
Manual Contents ........................................................................... xii
What’s New in This Manual ........................................................... xii
Technical or Customer Support ..................................................... xiii
Supported Products ....................................................................... xiii
Product Information ...................................................................... xiv
Related Documents .................................................................. xiv
Notation Conventions .................................................................... xvi
FPGA EZ-EXTENDER INTERFACES
FPGA EZ-Extender Setup ............................................................. 1-1
FPGA Software and Firmware ....................................................... 1-2
FPGA EZ-Extender Overview ....................................................... 1-3
FPGA EZ-EXTENDER HARDWARE REFERENCE
System Architecture ...................................................................... 2-2
Programming the FPGA ................................................................ 2-3
Blackfin FPGA EZ-Extender Manual
v
CONTENTS
FPGA Programming via JTAG ................................................ 2-4
FPGA Programming via Serial ROM ....................................... 2-5
FPGA Programming via Blackfin Application .......................... 2-6
Programming the Serial ROM ....................................................... 2-7
Serial ROM via JTAG Header ................................................. 2-7
Power ........................................................................................... 2-8
Power In Header (P12) ............................................................ 2-9
3.3V Header (P13) .................................................................. 2-9
2.5V Header (P42) ................................................................ 2-10
1.2V Header (P43) ................................................................ 2-10
Jumpers ...................................................................................... 2-11
Serial ROM Boot Jumper (JP1) ............................................. 2-12
Config Done Jumper (JP2) .................................................... 2-12
Config Program Jumper (JP3) ............................................... 2-13
Boot Jumper (JP4) ................................................................ 2-14
FPGA Input Jumpers (JP5) ................................................... 2-14
Push Buttons and LEDs .............................................................. 2-15
Program Push Button (SW1) ................................................. 2-15
PB1 Push Button (SW3) ....................................................... 2-15
PB2 Push Button (SW4) ....................................................... 2-16
Status LEDs (LED1–8) ......................................................... 2-17
Power LED (LED9) .............................................................. 2-17
Done LED (LED10) ............................................................. 2-17
Connectors ................................................................................. 2-18
vi
Blackfin FPGA EZ-Extender Manual
CONTENTS
Expansion Interface (P1–3 and J1–3) ..................................... 2-19
IDC Connectors (P8, P14, P16, and P17) .............................. 2-19
IDC Connectors (P5 and P7) ................................................ 2-20
High-Speed Connector (P4) .................................................. 2-20
BILL OF MATERIALS
SCHEMATICS
INDEX
Blackfin FPGA EZ-Extender Manual
vii
CONTENTS
viii
Blackfin FPGA EZ-Extender Manual
PREFACE
Thank you for purchasing the Blackfin® Field-Programmable Gate Array
(FPGA) EZ-Extender, Analog Devices, Inc. (ADI) extension board to the
EZ-KIT Lite® evaluation system for ADSP-BF533, ADSP-BF537, and
ADSP-BF561 Blackfin processors.
The Blackfin processors are embedded processors that support a Media
Instruction Set Computing (MISC) architecture. This architecture is the
natural merging of RISC, media functions, and digital signal processing
characteristics towards delivering signal processing performance in a
microprocessor-like environment.
The EZ-KIT Lite and FPGA EZ-Extender are designed to be used in conjunction with the VisualDSP++® development environment.
VisualDSP++ offers a powerful programming tool with new flexibility that
significantly decreases the time required to port software code to a processor, reducing time-to-market.
To learn more about Analog Devices development software, go to
http://www.analog.com/processors/tools/.
Product Overview
The Blackfin FPGA EZ-Extender is a separately sold extension board that
plugs onto the expansion interface of the ADSP-BF533, ADSP-BF537, or
ADSP-BF561 EZ-KIT Lite evaluation system. The extension board aids
the design and prototyping phases of ADSP-BF533, ADSP-BF537, or
ADSP-BF561 processor targeted applications.
Blackfin FPGA EZ-Extender Manual
ix
Product Overview
The board extends the capabilities of the evaluation system by providing a
Xilinx FPGA with external memory, IDC connectors for off-board connections, and a small bread board area.
The Blackfin FPGA EZ-Extender features:
• Xilinx Spartan III Field-Programmable Gate Array
D
D
XC3S1000
FG456 package
• Asynchronous static random access memory (SRAM)
D
D
D
Directly connected to FPGA
2 MB (512K x 16 bits x 2 chips)
TSOP44 package
• 25 MHz oscillator
D
Directly connected to global clock of FPGA
• Socket for auxiliary oscillator
D
Directly connected to global clock of FPGA
• IDC thru-hole connectors
D
D
Allows quick access to Blackfin and FPGA pins for probing
Allows access to Blackfin and FPGA pins for off-board
connections
• High-speed connector
D
Allows access to Blackfin and FPGA pins for high-speed
application
• Expansion interface connectors
D
x
Allows access to ADI’s family of Blackfin EZ-Extenders
Blackfin FPGA EZ-Extender Manual
Preface
• Two push buttons
D
D
Directly connected to FPGA
One with external debounce circuitry and one without
• Eight flag LEDs
D
Directly connected to FPGA
Before using any of the interfaces, follow the setup procedure in “FPGA
EZ-Extender Setup” on page 1-1.
Example programs are available to demonstrate the capabilities of the
Blackfin FPGA EZ-Extender board.
Purpose of This Manual
The Blackfin FPGA EZ-Extender Manual describes the operation and configuration of the components on the extension board. A schematic and a
bill of materials are provided as a reference for future Blackfin processor
board designs.
Intended Audience
This manual is a user’s guide and reference to the Blackfin FPGA
EZ-Extender. Programmers who are familiar with the Analog Devices
Blackfin processor architecture, operation, and development tools are the
primary audience for this manual. The user should also be familiar with
basic FPGA development and Xilinx’s Spartan III family of FPGAs.
Programmers who are unfamiliar with VisualDSP++ or EZ-KIT Lite evaluation software should refer to the ADSP-BF533, ADSP-BF537, or
ADSP-BF561 Evaluation System Manual, VisualDSP++ online Help, and
user’s or getting started guides. For the locations of these documents, refer
to “Related Documents”.
Blackfin FPGA EZ-Extender Manual
xi
Manual Contents
Manual Contents
The manual consists of:
• Chapter 1, “FPGA EZ-Extender Interfaces” on page 1-1
Provides basic board information.
• Chapter 2, “FPGA EZ-Extender Hardware Reference” on page 2-1
Provides information on the hardware aspects of the board.
• Appendix A, “Bill Of Materials” on page A-1
Provides a list of components used to manufacture the
EZ-Extender board.
• Appendix B, “Schematics” on page B-1
Provides the resources to allow EZ-KIT Lite board-level debugging
or to use as a reference design.
appendix is not part of the online Help. The online Help
L This
viewers should go to the PDF version of the Blackfin FPGA
EZ-Extender Manual located in the Docs\EZ-KIT Lite Manuals
folder on the installation CD to see the schematics. Alternatively,
the schematics can be found on the Analog Devices Web site,
www.analog.com/processors.
What’s New in This Manual
This is the first edition of the Blackfin FPGA EZ-Extender Manual.
xii
Blackfin FPGA EZ-Extender Manual
Preface
Technical or Customer Support
You can reach Analog Devices, Inc. Customer Support in the following
ways:
• Visit the Embedded Processing and DSP products Web site at
http://www.analog.com/processors/technicalSupport
• E-mail tools questions to
[email protected]
• E-mail processor questions to
[email protected] (World wide support)
[email protected] (Europe support)
[email protected] (China support)
• Phone questions to 1-800-ANALOGD
• Contact your Analog Devices, Inc. local sales office or authorized
distributor
• Send questions by mail to:
Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA
Supported Products
The Blackfin FPGA EZ-Extender is designed as an extension board to the
ADSP-BF533, ADSP-BF537, and ADSP-BF561 EZ-KIT Lite evaluation
systems.
Blackfin FPGA EZ-Extender Manual
xiii
Product Information
Product Information
You can obtain product information from the Analog Devices Web site,
from the product CD-ROM, or from the printed publications (manuals).
Analog Devices is online at www.analog.com. Our Web site provides information about a broad range of products—analog integrated circuits,
amplifiers, converters, and digital signal processors.
Related Documents
For information on product related development software, see the following publications.
Table 1. Related Processor Publications
Title
• ADSP-BF533 Embedded Processor Datasheet
• ADSP-BF536/ADSP-BF537 Embedded Processor Datasheet
• ASP-BF561 Blackfin Embedded Symmetric
Multi-Processor Datasheet
General functional description, pinout, and
timing.
• ADSP-BF533 Blackfin Processor Hardware
Reference
• ADSP-BF537 Blackfin Processor Hardware
Reference
• ASP-BF561 Blackfin Processor Hardware
Reference
Description of internal processor architecture
and all register functions
Blackfin Processor Instruction Set Reference
xiv
Description
Description of all allowed processor assembly
instructions.
Blackfin FPGA EZ-Extender Manual
Preface
Table 2. Related VisualDSP++ Publications
Title
• ADSP-BF533 EZ-KIT Lite Evaluation System Manual
• ADSP-BF537 EZ-KIT Lite Evaluation System Manual
• ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Description
Description of the EZ-KIT Lite features and
usage.
Note: For the ADSP-BF537 EZ-KIT Lite,
there is additional Getting Started with
ADSP-BF537 EZ-KIT Lite.
VisualDSP++ User’s Guide
Description of VisualDSP++ features and usage
VisualDSP++ Assembler and Preprocessor Manual
Description of the assembler function and
commands
VisualDSP++ C/C++ Complier and Library
Manual for Blackfin Processors
Description of the complier function and commands for Blackfin processors
VisualDSP++ Linker and Utilities Manual
Description of the linker function and commands
VisualDSP++ Loader Manual
Description of the loader function and commands
All documentation is available online. Most documentation is available in
printed form.
Visit the Technical Library Web site to access all processor and tools manuals and data sheets:
http://www.analog.com/processors/resources/technicalLibrary.
For more information on the Xilinx Spartan III FPGA, refer to the
datasheet located at www.xilinx.com.
Blackfin FPGA EZ-Extender Manual
xv
Notation Conventions
Notation Conventions
Text conventions used in this manual are identified and described as
follows.
Example
Description
{this | that}
Alternative required items in syntax descriptions appear within curly
brackets and separated by vertical bars; read the example as this or
that. One or the other is required.
[this | that]
Optional items in syntax descriptions appear within brackets and separated by vertical bars; read the example as an optional this or that.
[this,…]
Optional item lists in syntax descriptions appear within brackets
delimited by commas and terminated with an ellipse; read the example
as an optional comma-separated list of this.
.SECTION
Commands, directives, keywords, and feature names are in text with
letter gothic font.
filename
Non-keyword placeholders appear in text with italic style format.
L
a
[
Note: For correct operation, ...
A Note provides supplementary information on a related topic. In the
online version of this book, the word Note appears instead of this
symbol.
Caution: Incorrect device operation may result if ...
Caution: Device damage may result if ...
A Caution identifies conditions or inappropriate usage of the product
that could lead to undesirable results or product damage. In the online
version of this book, the word Caution appears instead of this symbol.
Warning: Injury to device users may result if ...
A Warning identifies conditions or inappropriate usage of the product
that could lead to conditions that are potentially hazardous for the
devices users. In the online version of this book, the word Warning
appears instead of this symbol.
conventions, which apply only to specific chapters, may
L Additional
appear throughout this document.
xvi
Blackfin FPGA EZ-Extender Manual
1 FPGA EZ-EXTENDER
INTERFACES
This chapter provides the setup procedures for both the Blackfin
Field-Programmable Gate Array (FPGA) EZ-Extender and EZ-KIT Lite
(ADSP-BF533, ADSP-BF537 or ADSP-BF561). It also provides an overview of the extender board.
The information is presented in the following order.
• “FPGA EZ-Extender Setup” on page 1-1
• “FPGA Software and Firmware” on page 1-2
• “FPGA EZ-Extender Overview” on page 1-3
FPGA EZ-Extender Setup
It is very important to set up all of the components of the system containing the FPGA EZ-Extender before applying power to that system. The
following procedure is recommended.
Power your system when these steps are completed:
1. Read the applicable design interface section in this chapter—the
text provides an overview of the capabilities of the EZ-Extender.
2. Read “System Architecture” on page 2-2 to understand the physical
connections of the extender board. For detailed information, refer
to “Schematics on page B-1”.
Blackfin FPGA EZ-Extender Manual
1-1
FPGA Software and Firmware
3. Remove any rubber feet attached to the EZ-KIT Lite if the feet
cover the printed circuit board (PCB) mounting holes. In place of
the rubber feet, install the four nylon feet and screws provided with
the FPGA EZ-Extender. Install the nylon feet in the mounting
holes of the EZ-KIT Lite’s PCB. Flip the EZ-KIT Lite upside
down so that the three expansion headers (J1–3) are facing up.
4. Set the switches and jumpers on the FPGA EZ-Extender board.
Use the block diagram in Figure 2-1 on page 2-2 in conjunction
with “Jumpers” on page 2-11.
5. Set the switches and jumpers on the EZ-KIT Lite board. If not
already, familiarize yourself with the documentation and schematics of the EZ-KIT Lite (see “Related Documents” on page -xiv).
Compare the expansion interface signals of the FPGA EZ-Extender
board with the signals of the EZ-KIT Lite board to ensure there is
no contention. For example, it may be necessary to disable other
devices connected to the expansion interface of the processor and
disable the push buttons on the EZ-KIT Lite.
6. Install the FPGA EZ-Extender on the EZ-KIT Lite via the
three-connector expansion interface. Figure 1-1 shows how an
FPGA EZ-Extender plugs onto an EZ-KIT Lite.
7. Configure any other interfacing boards, for example, another
EZ-Extender.
FPGA Software and Firmware
For information on the FPGA software, refer to the FPGA
Readme.txt file located in the …\Blackfin\EZ-KITs\FPGA
subdirectory of the VisualDSP++ installation directory.
1-2
Software
EZ-EXTENDER
Blackfin FPGA EZ-Extender Manual
FPGA EZ-Extender Interfaces
Figure 1-1. FPGA EZ-Extender Setup
FPGA EZ-Extender Overview
The Blackfin FPGA EZ-Extender connects a Xilinx® Spartan III
Field-Programmable Gate Array (FPGA for short) to the ADSP-BF533,
ADSP-BF537, or the ADSP-BF561 EZ-KIT Lite. The FPGA connects to
the Blackfin processor via the expansion interface.
The extender board, by default, is powered by an external 7V power supply provided with the product. You can also power the FPGA
EZ-Extender by the expansion interface of the EZ-KIT Lite or an external
power supply. An external supply must be used whenever application code
exceeds the recommended core and IO power supported by the FPGA
EZ-Extender. For more information on the jumper and connector settings
required to power the extender, review “Power” on page 2-8 as well as the
schematics in Appendix C.
Blackfin FPGA EZ-Extender Manual
1-3
FPGA EZ-Extender Overview
The FPGA EZ-Extender contains 2 MB of asynchronous SRAM memory,
powered by a 3.3V supply. The SRAM memory connects to banks 6 and 7
of the FPGA and can perform simple data storage instructions in application-specific code.
The FPGA EZ-Extender includes a 25 MHz oscillator (U6) connected to
the FPGA via the dedicated global clock 1 (GCLK1) pin, facilitating development of applications that require a clock. A second clock socket (U7) is
left unpopulated to allow a user to place an oscillator with a specific frequency for the FPGA. The second clock socket connects to the global
clock 6 (GCLK6) pin of the FPGA.
The extender has eight LEDs (LED1–8) and two push buttons (SW3–4) for
applications that require status reporting and user control. The push buttons are active low and when pressed, provide a logic 0 to the respective
FPGA nets. For inputs that require a permanent input low, use the jumper
inputs on JP4. When a jumper is populated on one of the four nets of JP4,
the respective pin is hard wired to a logic 0. For more information about
the LEDs, push button switches, and jumper inputs, refer to “FPGA
EZ-Extender Hardware Reference” on page 2-1.
There are various ways to program the FPGA. By default, the FPGA is
programmed in its slave serial mode by the flash programming utility in
VisualDSP++. The program configures the FPGA using the Blackfin processor’s flag pins and/or serial port pins. For more information on how to
use the flash programming utility within VisualDSP++, refer to the
FPGA Software Readme.txt file located in the
…\Blackfin\EZ-KITs\FPGA EZ-EXTENDER subdirectory of the VisualDSP++
installation directory.
A second method of programming the FPGA is by using a Xilinx JTAG
cable and software. The Xilinx JTAG cable connects to the FPGA JTAG
header (P15). For more information about programming the FPGA via a
Xilinx JTAG cable, refer to the manufacturer’s website at www.xilinx.com.
1-4
Blackfin FPGA EZ-Extender Manual
FPGA EZ-Extender Interfaces
The third and final way to program the FPGA is via the Xilinx serial
ROM on the FPGA EZ-Extender. The serial ROM used for FPGA is
shipped with the extender and is pre-programmed. If the serial ROM
needs to be re-programmed with new code, use an Xilinx JTAG cable and
software and connect the Xilinx JTAG cable to the flash JTAG header
(P6).
More information about programming the serial ROM can be found at
www.xilinx.com. More details about the different ways to program the
FPGA can be found in “FPGA EZ-Extender Hardware Reference” on
page 2-1.
Blackfin FPGA EZ-Extender Manual
1-5
FPGA EZ-Extender Overview
1-6
Blackfin FPGA EZ-Extender Manual
2 FPGA EZ-EXTENDER
HARDWARE REFERENCE
This chapter describes the hardware design of the Field-Programmable
Gate Array (FPGA) EZ-Extender.
The following topics are covered.
• “System Architecture” on page 2-2
Describes the configuration of the extender board and explains
how the board components interface with the processor and
EZ-KIT Lite.
• “Programming the FPGA” on page 2-3
Describes the different methods of programming the FPGA.
• “Programming the Serial ROM” on page 2-7
Describes the method of programming the serial ROM.
• “Power” on page 2-8
Describes the methods to power the extender board.
• “Jumpers” on page 2-11
Describes the function of the configuration jumpers.
• “Push Buttons and LEDs” on page 2-15
Describes the function of the push buttons and LEDs.
• “Connectors” on page 2-18
Describes the function of the extender connectors.
Blackfin FPGA EZ-Extender Manual
2-1
System Architecture
System Architecture
A block diagram of the Blackfin FPGA EZ-Extender is shown in
Figure 2-1.
Power
C o n n e c to r
P rim a ry E x p a n s io n In te rfa c e
(to B la c k F in E Z -K IT )
JTAG
C o n n e c to r
JTA G
C o n n e c to r
2M B SR AM
(5 1 2 k x 3 2 -b its )
H ig h S p e e d
C o n n e c to r
M e m o ry
In te rfa c e
3 .3 V
X ilin x
S p a rta n 3
X C 3 S 1 0 0 0 -4 F G 4 5 6 C
FPGA
S e ria l
F la s h
L E D , D IP S w itc h ,
P u s h B u tto n s
R e g u la to rs
S P I, S P O R T (2 x ),
P P I(2 x ), G P IO ,
T im e rs , T W I
2 .5 V
1 .2 V
25M H z
O s c illa to r
Socket
S P I, S P O R T (2 x ),
P P I(2 x ), G P IO ,
T im e rs , T W I
S e c o n d a ry E x p a n s io n In te rfa c e
(to T e s t p o in ts a n d o th e r E Z E x te n d e rs )
.1 in c h h e a d e rs
Figure 2-1. Block Diagram
2-2
Blackfin FPGA EZ-Extender Manual
FPGA EZ-Extender Hardware Reference
Programming the FPGA
Before using the Blackfin FPGA EZ-Extender, follow the steps in “FPGA
EZ-Extender Setup” on page 1-1.
Figure 2-2 is a block diagram of the FPGA programming connections.
Figure 2-2. FPGA Programming Block Diagram
Blackfin FPGA EZ-Extender Manual
2-3
Programming the FPGA
There are three ways to program the FPGA:
• Using the FPGA JTAG header, as described in “FPGA Programming via JTAG” on page 2-4
• Using the Xilinx serial ROM, as described in “FPGA Programming
via Serial ROM” on page 2-5
• Using the Blackfin processor, as described in “FPGA Programming
via Blackfin Application” on page 2-6
The done LED (LED10) lights up once the FPGA is programmed, signifying
that the task is complete. To erase the contents of the FPGA at any time,
de-press the program switch SW1.
FPGA Programming via JTAG
To program the FPGA via the JTAG header, create the appropriate program file using the Xilinx ISE software provided at www.xilinx.com. Once
the program file is created, use a Xilinx JTAG cable and connect it to P15 of
the FPGA EZ-Extender (the P15 connections are shown in Table 2-1).
Table 2-1. P15 Connections for PFGA Programming via JTAG
2-4
P15 Pin Number
Signal Name
1
3.3V
2
GND
3
TCK
4
TDO
5
TDI
6
TMS
Blackfin FPGA EZ-Extender Manual
FPGA EZ-Extender Hardware Reference
In addition to removing JP1 (serial ROM boot jumper) as shown in
Table 2-2, set the boot jumper, JP4, to JTAG mode. The JP4 settings for
JTAG boot are shown in Table 2-3. See “Boot Jumper (JP4)” on
page 2-14 for more information.
Table 2-2. JP1 Settings for FPGA Programming via JTAG
JP1 Pin Name
Pins Connected
Flash done
JP1.1
and JP1.2
Jumper Setting
Unpopulated
Table 2-3. JP4 Settings for FPGA Programming via JTAG
JP4 Pin Name
Pins Connected
Jumper Setting
M0
JP4.1
and JP4.2
Unpopulated
M1
JP4.3
and JP4.4
Populated
M2
JP4.5
and JP4.6
Unpopulated
FPGA Programming via Serial ROM
To program the FPGA with the contents of the serial ROM, populate the
JP1 jumper. When populated, JP1 connects the chip enable pin of the
serial ROM to the done bit of the FPGA. Once the FPGA is programmed,
the done bit automatically goes high, and the enable pin of the serial
ROM chip becomes a logic 1. The JP1 settings for serial ROM boot are
shown in Table 2-4. See “Programming the Serial ROM” on page 2-7 for
more information.
The done LED (LED10) remains lit to signify that the FPGA is programmed. See “Done LED (LED10)” on page 2-17 for more information.
Table 2-4. JP1 Settings for FPGA Programming via Serial ROM
JP1 Pin Name
Pins Connected
Flash done
JP1.1
and JP1.2
Blackfin FPGA EZ-Extender Manual
Jumper Setting
Populated
2-5
Programming the FPGA
In addition to JP1, set the boot mode jumper, JP4, to master serial mode.
The JP4 settings for serial ROM boot are shown in Table 2-5. See “Boot
Jumper (JP4)” on page 2-14 for more information.
Table 2-5. JP4 Settings for FPGA Programming in Master Serial Mode
JP4 Pin Name
Pins Connected
Jumper Setting
M0
JP4.1
and JP4.2
Populated
M1
JP4.3
and JP4.4
Populated
M2
JP4.5
and JP4.6
Populated
FPGA Programming via Blackfin Application
By default, the FPGA EZ-Extender is configured by the flash programming utility within VisualDSP++. The software is located in the
…\Blackfin\EZ-KITs\FPGA EZ-EXTENDER subdirectory of the VisualDSP++
installation directory. The FPGA Software Readme.txt file located in the
same subdirectory provides all the necessary instructions required for running the application.
generating a program file using the Xilinx software tools,
L When
remember to generate a slave serial program file in the Intel
MCS-86 Hexadecimal Object (.mcs) file format.
To boot the FPGA from the Blackfin processor, unpopulate jumper JP1
and set jumper JP4 to slave serial mode, as shown in Table 2-6 and
Table 2-7. See “Serial ROM Boot Jumper (JP1)” on page 2-12 and “Boot
Jumper (JP4)” on page 2-14 for more information.
Table 2-6. JP1 Settings for FPGA Programming via Blackfin Processor
2-6
JP1 Pin Name
Pins Connected
Flash done
JP1.1
and JP1.2
Jumper Setting
Unpopulated
Blackfin FPGA EZ-Extender Manual
FPGA EZ-Extender Hardware Reference
Table 2-7. JP4 Settings for FPGA Programming via Blackfin Processor
JP4 Pin Name
Pins Connected
Jumper Setting
M0
JP4.1
and JP4.2
Unpopulated
M1
JP4.3
and JP4.4
Unpopulated
M2
JP4.5
and JP4.6
Unpopulated
Programming the Serial ROM
The FPGA EZ-Extender allows the user to program the serial ROM. The
serial ROM can be programmed by using a Xilinx JTAG cable, ISE software, and the flash JTAG header on the FPGA EZ-Extender.
Serial ROM via JTAG Header
To program the serial ROM via the JTAG header, create the appropriate
program file using the Xilinx software provided at www.xilinx.com. Once
the program file is created, use a Xilinx JTAG cable and connect it to P6.
The P6 connections are shown in Table 2-8.
Table 2-8. P6 Connections for Serial ROM
P6 Pin Number
Signal Name
P6 Pin Number
Signal Name
1
3.3V
4
TDO
2
GND
5
TDI
3
TCK
6
TMS
Blackfin FPGA EZ-Extender Manual
2-7
Power
Power
The FPGA EZ-Extender can be powered from the enclosed power supply,
EZ-KIT Lite, or external power supply. The power source for the extender
is selected based on the power requirements of the application.
An external 7V power supply is shipped with the extender board. The
power supply uses three switching regulators: VR1 is used to power the
2.5V power plane, VR2 is used to power the 1.2V power plane, and VR3 is
used to power the 3.3V plane. All of the regulators can supply a maximum
current of 2 Amps. To understand the power requirements of your application, run the Xilinx power estimator software. The software can be
located at www.xilinx.com.
Table 2-9 states the current limitations of each method. Each method
requires a correctly configured header, described in the following sections.
Table 2-9. Power Limitations
Power Source
1.2V Supply
2.5V Supply
3.3V Supply
ADSP-BF533, ADSP-BF537, or
ADSP-BF561 EZ-KIT Lite
500 mA
500 mA
500 mA
FPGA EZ-Extender power supply1
2A
2A
2A
External power supply
2A
2A
2A
1
2-8
Default setting
Blackfin FPGA EZ-Extender Manual
FPGA EZ-Extender Hardware Reference
Power In Header (P12)
The P12 header supplies the power to the on board 1.2V and the 2.5V regulators. The P42 and P43 headers supply the power to the external 1.2V
and 2.5V planes, as described in “2.5V Header (P42)” and “1.2V Header
(P43)” on page 2-10.
Power Source
FPGA EZ-Extender power
P12 Setting
supply1
ADSP-BF533, ADSP-BF537, or ADSP-BF561
EZ-KIT Lite 5V power supply
1
Jumper on P12.1 and P12.2
Jumper on P12.2 and P12.3
Default setting
3.3V Header (P13)
Power Source
P13 Setting
ADSP-BF533, ADSP-BF537, or ADSP-BF561
EZ-KIT Lite 3.3V power supply
Jumper on P13.1 and P13.2
FPGA EZ-Extender power supply1
Jumper on P13.2 and P13.3
External power supply
No jumper; connect supply to P13.2 and
GND
1
Default setting
using an external power supply, do not plug in the power
[ When
supply shipped with the FPGA EZ-Extender. This can seriously
damage the board. As an extra measure of precaution, remove all
jumpers from P12.
Blackfin FPGA EZ-Extender Manual
2-9
Power
2.5V Header (P42)
Power Source
P42 Setting
FPGA EZ-Extender Power Supply1
No Jumper
External power supply
Connect P42.1 to external 2.5V
Connect P42.2 to external GND
1
Default setting
using an external power supply, do not plug in the power
[ When
supply shipped with the FPGA EZ-Extender. This can seriously
damage the board. As an extra measure of precaution, remove all
jumpers from P12.
1.2V Header (P43)
Power Source
FPGA EZ-Extender power
External power supply
1
P43 Setting
supply1
No Jumper
Connect P42.1 to external 2.5V
Connect P42.2 to external GND
Default setting
using an external power supply, do not plug in the power
[ When
supply shipped with the FPGA EZ-Extender. This can seriously
damage the board. As an extra measure of precaution, remove all
jumpers from P12.
2-10
Blackfin FPGA EZ-Extender Manual
FPGA EZ-Extender Hardware Reference
Jumpers
Before using the Blackfin FPGA EZ-Extender, follow the steps in “FPGA
EZ-Extender Setup” on page 1-1.
Figure 2-3 shows the locations of all jumper headers. A two-pin jumper
can be placed on the respective jumper header for different functionality.
The following sections describe all possible jumper settings and associated
functionality.
Figure 2-3. Jumper Locations
Blackfin FPGA EZ-Extender Manual
2-11
Jumpers
Serial ROM Boot Jumper (JP1)
By default, the serial ROM boot jumper, JP1, is unpopulated. When
unpopulated, the FPGA EZ-Extender programs via the Blackfin processor
or the Xilinx JTAG header.
When JP1 is left populated, the jumper connects the serial ROM chip
enable pin to the done bit of the FPGA. At power-up, the done bit is
driven low by the FPGA, causing the FPGA to enable the serial ROM as a
programming source. After the FPGA is programmed, the done bit is
driven high by the FPGA, causing the FPGA to drive high the chip enable
pin of the serial ROM.
Both JP1 and JP4 must be set up for correct FPGA programming. “Boot
Jumper (JP4)” on page 2-14 summarizes the JP4 settings. Table 2-10 summarizes the JP1 settings. See Table 2-4 on page 2-5 and Table 2-6 on
page 2-6 for more information on JP1.
Table 2-10. JP1 Settings
Boot Source
JP1 Setting
ADSP-BF533, ADSP-BF537, or
ADSP-BF561 processor via VisualDSP++1
Unpopulated
JTAG header
Unpopulated
Serial ROM
Populated
1
Default setting
Config Done Jumper (JP2)
The configuration done jumper, JP2, connects the done bit of the FPGA
to the Blackfin processor’s PF3 flag pin of the ADSP-BF533 and
ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT
2-12
Blackfin FPGA EZ-Extender Manual
FPGA EZ-Extender Hardware Reference
Lite. By default, the jumper is populated and acts as a monitor for the
done bit by the Blackfin processor (the bit indicates that the FPGA programming is complete).
Table 2-11 summarizes the jumper settings.
Table 2-11. JP2 Settings
Functionality
JP2 Setting
Done bit connected to Blackfin processor’s PF3
flag pin1
Populated
Done bit disconnected from Blackfin processor’s
flag pin
Unpopulated
PF3
1
Default setting
Config Program Jumper (JP3)
The configuration program jumper, JP3, connects the program bit of the
FPGA to the Blackfin processor’s flag pin. By default, JP3 is populated.
The jumper assures that the program bit is asserted by the Blackfin processor to initiate the FPGA programming through VisualDSP++ software.
Table 2-12 summarizes the jumper settings.
Table 2-12. JP3 Settings
Functionality
JP3 Setting
Program bit connected to the Blackfin processor’s
flag pin1
Populated
Program bit disconnected from the Blackfin processor’s flag pin
Unpopulated
1
Default setting
Blackfin FPGA EZ-Extender Manual
2-13
Jumpers
Boot Jumper (JP4)
The boot jumper, JP4, configures the FPGA mode pins (M[2:0]). Based on
the jumper settings, the FPGA is set to be programmed by the JTAG
header, serial ROM, or Blackfin processor.
Table 2-13 summarizes the jumper settings. See Table 2-3 on page 2-5 for
the JTAG header boot settings, Table 2-5 on page 2-6 for the serial ROM
boot settings, and Table 2-7 on page 2-7 for the Blackfin processor boot
settings.
Table 2-13. JP4 Settings
Boot Source
JP4.1 and JP4.2
M0
JP4.3 and JP4.4
M1
JP4.5 and JP4.6
M2
ADSP-BF533,
ADSP-BF537, or
ADSP-BF561 processor1
Unpopulated
Unpopulated
Unpopulated
JTAG header
Unpopulated
Populated
Unpopulated
Serial ROM
Populated
Populated
Populated
1
Default setting
FPGA Input Jumpers (JP5)
The FPGA input jumpers, JP5.2–5.8, drive select FPGA nets to a logic 0
and can be used for any user logic that requires a steady state input. You
can set internal pull-ups on these nets in the FPGA and, when a low is
required, populate the respective jumper.
Table 2-14 summarizes the jumper settings.
2-14
Blackfin FPGA EZ-Extender Manual
FPGA EZ-Extender Hardware Reference
Table 2-14. JP5 Settings
Reference Designator
FPGA Pin Number
JP5.2
Y3
JP5.4
Y2
JP5.6
U10
JP5.8
AB11
Push Buttons and LEDs
Before using the Blackfin FPGA EZ-Extender, follow the steps in “FPGA
EZ-Extender Setup” on page 1-1.
Figure 2-4 shows the locations of all push buttons and LEDs. The following sections describe the associated functionality of all the push buttons
and LEDs.
Program Push Button (SW1)
The program push button, SW1, erases the contents of the FPGA. The
push button can be used as a hard reset—the FPGA must be completely
re-programmed once SW1 is de-pressed. See “Programming the FPGA” on
page 2-3 for more information.
PB1 Push Button (SW3)
The PB1 push button, SW3, is a general-purpose input push button. The
switch with a connected debounce circuit eliminates the need to re-create
it in the FPGA. The push button connects to pin C11 of the FPGA.
Blackfin FPGA EZ-Extender Manual
2-15
Push Buttons and LEDs
Figure 2-4. Push Button and LED Locations
PB2 Push Button (SW4)
The PB2 push button, SW4, is a general-purpose input push button. The
switch does not have a connected debounce circuit; you may need to create it in the FPGA if required by a specific application. The push button
connects to pin H5 of the FPGA.
2-16
Blackfin FPGA EZ-Extender Manual
FPGA EZ-Extender Hardware Reference
Status LEDs (LED1–8)
Eight status LEDs, LED1–8, connect to the FPGA and act as status flags in
any application that requires it. Table 2-15 shows the LED/FPGA
connections.
Table 2-15. Status LED (LED1–8) Settings
Reference Designator
FPGA Pin Number
LED1
U11
LED2
W11
LED3
AB10
LED4
Y10
LED5
AB9
LED6
W9
LED7
AB8
LED8
V10
Power LED (LED9)
The power LED, LED9, connects to the 2.5V power supply and, when lit,
signifies that the FPGA EZ-Extender is powered properly.
Done LED (LED10)
The done LED, LED10, connects to the done pin of the FPGA. At
power-up, the FPGA is blank and needs to be programmed. When lit, the
LED indicates that the FPGA is programmed successfully.
Blackfin FPGA EZ-Extender Manual
2-17
Connectors
Connectors
Before using the Blackfin FPGA EZ-Extender, follow the steps in “FPGA
EZ-Extender Setup” on page 1-1.
This section describes the connector functionality and provides information about the mating connectors. The connector locations are shown in
Figure 2-5.
Figure 2-5. Connector Locations
2-18
Blackfin FPGA EZ-Extender Manual
FPGA EZ-Extender Hardware Reference
Expansion Interface (P1–3 and J1–3)
Connectors P1–3 of the expansion interface are used to plug in the
EZ-Extender to the ADSP-BF533, ADSP-BF537, or ADSP-BF561
EZ-KIT Lite.
Connectors J1–3 of the expansion interface are used to plug in another
extender board, such as the Blackfin USB-LAN EZ-Extender. Your own
custom board can be plugged into J1–3 as well.
in another EZ-Extender or a customer board to the
[ Plugging
expansion interface can de-grade the overall system performance.
The extra overall load can cause the user to add wait states or slow
down the system bus to get all of the boards to work properly.
For the J1–3 and P1–3 connector availability and pricing, contact Samtec.
Part Description
Manufacturer
Part Number
90-position 0.05” spacing, SMT Samtec
(J1, J2, J3)
SFC-145-T2-F-D-A
90-position 0.05” spacing
(P1, P2, P3)
TFC-145-32-F-D
Samtec
IDC Connectors (P8, P14, P16, and P17)
The P8, P14, P16, and P17 connectors are standard 0.1” IDC headers. The
connectors are in a 13 x 2 configuration and designed for signal probing,
bread boarding, and other signal accesses.
Part Description
Manufacturer
Part Number
IDC13x2 0.1” header
Berg
54102-T08-13
Mating Connector
IDC 13x2 0.1” plug
Samtec
Blackfin FPGA EZ-Extender Manual
SSW-113-01-T-D
2-19
Connectors
IDC Connectors (P5 and P7)
The P5 and P7 connectors are standard 0.1” IDC headers. The connectors
are in a 14 x 2 configuration and designed for signal probing, bread
boarding, and other signal accesses.
Part Description
Manufacturer
Part Number
IDC14x2 0.1” header
FCI
68737-428HLF
IDC14x2 0.1” header
Sullins
GEC14DAAN
Mating Connector
IDC 14x2 0.1” plug
Samtec
SSW-114-01-T-D
High-Speed Connector (P4)
The high-speed connector, P4, facilitates development of applications
where use of the standard IDC connectors is complicated due to signal
integrity issues.
For the P4 connector and cable assembly availability and pricing, contact
Samtec.
Part Description
Manufacturer
Part Number
QTS 25x2 high-speed connector
Samtec
QTS-025-01-F-D-A
Mating Connector
QSS 25x2 high-speed connector
2-20
Samtec
QSS-025-01-F-D-A
Blackfin FPGA EZ-Extender Manual
A BILL OF MATERIALS
The bill of materials corresponds to the board schematics on page B-1.
Please check the latest schematics on the Analog Devices website,
http://www.analog.com/Processors/Processors/DevelopmentTools/tec
hnicalLibrary/manuals/DevToolsIndex.html#Evaluation%20Kit%20Manuals.
Blackfin FPGA EZ-Extender Manual
A-1
A-2
Blackfin FPGA EZ-Extender Manual
3
1
1
9
10
3
5
8
1
4
2
1
3
7
1
2
1
1
1
6
#
Ref.
8 PIN DIP TH-TH
CARRIER SOCKETED PIN
PWR 2.5MM_JACK
CON005 RA
SI2343DS SOT23D
PFET_30V
IS61LV51216 TSOP44
512KX16_SRAM
XCF04S TSSOP20
XILINX_4MBIT_FLASH
LM3475MF SOT23-5
BUCK-CONTROLLER
XC3S1000 FG456
SPARTAN3-FPGA
74LVC157 TSSOP16
QUAD MUX
25MHZ SMT OSC003
SN74LVC1G125 SOT23-5
SINGLE-3STATE-BUFFER
Description
U7
J4
Q1-3
U3,U5
U4
VR1-3
U1
U2
U6
U8
Reference Designator
MILL-MAX
SWITCHCRAFT
VISHAY
ISSI
XILINX
NATIONAL
XILINX
PHILIPS
EPSON
TI
Manufacturer
614-93-308-31-007
SC1152-ND12
SI2343DS-T1-E3
IS61LV51216-10TLI
XCF04SVOG20C
LM3475MF
XC3S1000-4FGG456C
74LVC157APW
SG-8002CA-PWT 25MHZ
SN74LVC1G125DBVR
Part Number
#
3
3
3
2
2
1
9
1
3
1
Ref.
11
12
13
14
15
16
Blackfin FPGA EZ-Extender Manual
17
18
19
20
600 100MHZ 200MA 0603
0.50 BEAD
3A HSM350J DO214AB
SCHOT_RECT
10uF 16V 10% C
TANT
AMBER-SMT LED001
GULL-WING
QTS 25X2 CON041
SMT
IDC 6X1 IDC6X1
HEADER
IDC 14X2 IDC14X2
HEADER
0.05 45X2 CON019
SMT SOCKET
0.05 45x2 CON018
HEADER
SPST-MOMENTARY
SWT013 6MM
Description
FER2
D1-3
C4
LED1-8,LED10
P4
P6,P15
P5,P7
J1-3
P1-3
SW1,SW3-4
Reference Designator
MURATA
MICRO-SEMI
AVX
PANASONIC
SAMTEC
FCI
FCI
SAMTEC
SAMTEC
PANASONIC
Manufacturer
BLM11A601SPT
HSM350J
TAJC106K025R
LN1461C-TR
QTS-025-01-F-D-A
90726-406HLF
68737-428HLF
SFC-145-T2-F-D-A
TFC-145-32-F-D
EVQ-PAD04M
Part Number
Bill Of Materials
A-3
A-4
Blackfin FPGA EZ-Extender Manual
3
8
10
30
31
32
3
26
1
4
25
29
7
24
56
1
23
28
1
22
5
1
21
27
#
Ref.
330 1/10W 5% 0603
10K 1/10W 5% 0603
10UH 17 20% IND005
1UF 16V 10% 0603
0.01UF 16V 10% 0603
X7R
0.1UF 16V 10% 0603
X7R
100UF 10V 10% C
TANT-LOW-ESR
1000PF 10V 20% 805
10UF 6.3V 10% 805
X7R
190 100MHZ 5A FER002
3.9NF 50V 5% 805
2A S2A_RECT DO-214AA
SILICON RECTIFIER
Description
R10,R24,R34-41
R1,R6,R21-22,R28-29,
R46-47
L1-3
C5
C11-13,C17-34,C36-37,
C39-54,C57-70,C80-82
C3,C38,C56,C84-85
CT1-3
C1-2,C10,C74
C14-16,C35,C55,C83,
C86
FER1
C6
D5
Reference Designator
VISHAY
PANASONIC
COILCRAFT
PANASONIC
AVX
AVX
AVX
YAGEO
AVX
MURATA
PANASONIC
VISHAY
Manufacturer
CRCW0603331JRT1
ERJ-3GEYJ103V
MSS1278-103MXB
ECJ-1VB1C105K
0603YC103KAT2A
0603YC104KAT2A
TPSC107K010R0075
1206CG229C9B200
080560106KAT2A
DLW5BSN191SQ2
ECH-U1C392JB5
S2A
Part Number
#
9
1
1
2
2
5
1
1
1
1
1
1
3
Ref.
33
34
35
36
37
38
39
40
Blackfin FPGA EZ-Extender Manual
41
42
43
44
45
IDC 2X1 IDC2X1
GOLD
GREEN-SMT LED001
GULL-WING
2.15K 1/16W 1% 0603
1.05K 1/16W 1% 0603
31.6K 1/16W 1% 0603
4.99K 1/16W 1% 0603
390PF 25V 5% 0603
NPO
100 1/16W 5% 402
33 1/10W 1% 0603
10K 1/10W 1% 0603
200K 1/16W 1% 0603
10 1/10W 5% 0603
0 1/10W 5% 0603
Description
JP1-3
LED9
R18
R11
R17
R13
C7
R5,R7-8,R23,R44
R2,R26
R14,R19
R20
R42
R3-4,R9,R12,R15-16,
R27,R58-59
Reference Designator
PANASONIC
PANASONIC
PANASONIC
PANASONIC
STACKPOLE
AVX
PANASONIC
YAGEO
PANASONIC
VISHAY
PANASONIC
PANASONIC
Manufacturer
LN1361C
ERJ-3EKF2151V
ERJ-3EKF1051V
ERJ-3EKF3162V
RMC 1/16 4.99K 1% R
06033A391FAT2A
ERJ-2GEJ101X
9C06031A33R0FKHFT
P10.0KHTR-ND
CRCW06032003FRT1
ERJ-3GEYJ100V
ERJ-3GEY0R00V
Part Number
Bill Of Materials
A-5
A-6
Blackfin FPGA EZ-Extender Manual
#
5
1
1
4
1
3
Ref.
46
47
48
49
50
51
10UF 10V 10% 805
2.5A RESETABLE FUS001
IDC 13X2 IDC13X2
IDC 4X2 IDC4X2
IDC 3X2 IDC3X2
IDC 3X1 IDC3X1
Description
C8, C9, C71
F1
P8,P14,P16-17
JP5
JP4
P9-13
Reference Designator
PANASONIC
RAYCHEM CORP.
BERG
SULLINS
BERG
BERG
Manufacturer
ECJ-2FB1A106K
SMD250-2
54102-T08-13
S2012-04
54102-T08-03
54101-T08-03
Part Number
A
B
C
D
1
1
2
2
BLACKFIN FPGA EZ-EXTENDER
Schematic
3
3
DNP = Do Not Populate
ANALOG
DEVICES
4
Title
Size
A
B
C
Nashua, NH 03063
4
PH: 1-800-ANALOGD
BLACKFIN FPGA EZ-EXTENDER
TITLE
Board No.
C
Date
20 Cotton Road
Rev
A0199-2005
1.0
Sheet
9-9-2005_10:40
D
1
of
12
A
B
C
D
3.3V
FPGA BOOT FLASH
(2Mbit)
R1
10K
0603
FLASH JTAG HEADER
3.3V
FPGA JTAG HEADER
3.3V
3.3V
P15
1
U4
1
1.2V
2.5V
2
1
P6
1
3
2
CONFIG_CLK_TSCLK1
3
FLASH_DOUT
3
CLK
1
D0
8
OE/~RESET
10
CE
7
CF
13
CEO
FLASH_TCK
CONFIG_INIT_B_TFS1
4
FLASH_TDO
5
JP1
FLASH_TDI
6
1
CONFIG_DONE
2
FLASH_DONE
IDC2X1
2X1
FLASH_TMS
IDC6X1
6X1
FPGA_TCK
18
VCCINT
4
FPGA_TDO
19
VCCO
5
VCCJ
U1
FPGA_TDI
20
6
A6
FPGA_TMS
IDC6X1
6X1
2
NC1
9
NC2
12
NC3
14
NC4
5
TMS
6
TCK
4
TDI
17
TDO
FLASH_TMS
FLASH_TCK
FLASH_TDI
FLASH_TDO
15
3.3V
NC5
16
NC6
GND
J10
GND_J10
J11
GND_J11
J12
GND_J12
J13
GND_J13
J14
GND_J14
J20
GND_J20
K9
GND_K9
K10
GND_K10
K11
GND_K11
K12
GND_K12
K13
GND_K13
K14
GND_K14
L9
GND_L9
L10
GND_L10
L11
GND_L11
L12
GND_L12
L13
GND_L13
L14
GND_L14
M9
GND_M9
M10
GND_M10
M11
GND_M11
M12
GND_M12
M13
GND_M13
M14
GND_M14
N9
GND_N9
N10
GND_N10
N11
GND_N11
N12
GND_N12
N13
GND_N13
N14
GND_N14
P3
GND_P3
P9
GND_P9
P10
GND_P10
P11
GND_P11
P12
GND_P12
P13
GND_P13
P14
GND_P14
P20
GND_P20
Y9
GND_Y9
Y14
GND_Y14
AA2
GND_AA2
AA21
GND_AA21
AB1
GND_AB1
AB22
GND_AB22
VCCAUX_A6
A17
VCCAUX_A17
F1
VCCAUX_F1
F22
VCCAUX_F22
U1
VCCAUX_U1
U22
VCCAUX_U22
AB6
VCCAUX_AB6
AB17
VCCAUX_AB17
11
G7
VCCINT_G7
G8
XCF04S
TSSOP20
VCCINT_G8
G15
VCCINT_G15
G16
R22
10K
0603
R28
10K
0603
R6
10K
0603
VCCINT_G16
R21
10K
0603
H7
VCCINT_H7
H16
VCCINT_H16
R7
VCCINT_R7
R16
VCCINT_R16
R44
100
402
2
T7
VCCINT_T7
T8
FPGA_TCK
U2
VCCINT_T8
T15
2
FLASH_DOUT
R8
100
402
1A
5
BOOTMODE JUMPER
2A
11
3A
4
14
1Y
4A
9
3Y
6
4Y
1B
M0
12
M1
2B
M2
10
JP4
1
2
3
4
5
6
13
3B
R7
100
402
FPGA_TMS
R4
0
0603
IDC3X2
3X2
4B
M0
CONFIG_CLK_TSCLK1
15
M1
EN
M2
~A/B
R5
100
402
74LVC157
TSSOP16
AA22
CCLK
A2
PROG_B
AB21
DONE
B3
HSWAP_EN
SW1
SWT013
SPST-MOMENTARY
CONFIG_DONE
R3
0
0603
3
3.3V
LED10
AMBER-SMT
LED001
3.3V
25MHZ SYSTEM CLOCK
EXTRA CLOCK SOCKET
R29
10K
0603
R25
10K
0603
DNP
R2
33
0603
U6
1
OE
OUT
3
R26
33
0603
U7
1
OE/NC
B4_L32N_GCKL1_AA12
25MHZ
OSC003
5
OUT
3
DIP
DIP8SOC
C19
0.01UF
0603
C20
0.01UF
0603
C21
0.01UF
0603
C11
0.01UF
0603
C12
0.01UF
0603
C13
0.01UF
0603
2.5V
OSC
C18
0.01UF
0603
A1
GND_A1
A22
GND_A22
B2
GND_B2
B21
GND_B21
C9
GND_C9
C14
GND_C14
J3
GND_J3
J9
GND_J9
XC3S1000
FG456
IO_L32_0_GCLK6_A11
1.2V
C17
0.01UF
0603
R24
330
0603
3.3V
C32
0.01UF
0603
4
AB2
M0
AA1
M1
AB3
M2
CONFIG_PROG_B
1
FLASH_DONE
VCCINT_T16
A21
TCK
B1
TDI
B22
TDO
A20
TMS
FPGA_TDO
7
3
VCCINT_T15
FPGA_TDI
CONFIG_DIN_DT1PRI
2Y
DT1PRI
T16
2
C22
0.01UF
0603
C23
0.01UF
0603
C24
0.01UF
0603
C25
0.01UF
0603
C15
10UF
805
C16
10UF
805
C26
0.01UF
0603
C27
0.01UF
0603
C31
0.01UF
0603
C30
0.01UF
0603
C29
0.01UF
0603
C28
0.01UF
0603
SKT
FLASH
MUX
DNP = Do Not Populate
ANALOG
DEVICES
C14
10UF
805
Title
Size
FPGA
Date
A
B
C
Nashua, NH 03063
4
PH: 1-800-ANALOGD
BLACKFIN FPGA EZ-EXTENDER
FPGA CONFIG
Board No.
C
FPGA
20 Cotton Road
Rev
A0199-2005
1.0
Sheet
9-27-2005_11:44
D
2
of
12
A
B
C
D
3.3V
2MBYTES FPGA SRAM
(512k x 16bits x 2chips)
1
1
U1
M7
H3
VCCO_7_H3
H6
VCCO_7_H6
J7
VCCO_7_J7
K7
VCCO_7_K7
L7
VCCO_7_L7
VCCO_6_M7
N7
VCCO_6_N7
P7
VCCO_6_P7
U3
U5
R3
SRAM_A0
2
SRAM_A0
1
SRAM_A1
2
SRAM_A2
3
A0
A1
4
SRAM_A4
5
SRAM_A5
18
SRAM_A6
19
SRAM_A7
20
SRAM_A8
21
SRAM_A9
22
SRAM_A10
23
SRAM_A11
24
SRAM_A12
25
SRAM_A13
26
SRAM_A14
27
SRAM_A15
42
SRAM_A16
43
SRAM_A17
44
SRAM_A18
28
SRAM_D16
8
SRAM_D17
9
SRAM_D18
SRAM_A2
D2
A3
SRAM_A3
10
SRAM_D19
13
SRAM_D20
14
SRAM_D21
15
SRAM_D22
16
SRAM_D23
29
SRAM_D24
30
SRAM_D25
31
SRAM_D26
32
SRAM_D27
35
SRAM_D28
36
SRAM_D29
37
SRAM_D30
38
SRAM_D31
D3
D4
A5
D5
SRAM_A4
A4
SRAM_A5
D6
A7
D7
SRAM_A6
A6
A8
SRAM_A7
SRAM_A8
D8
D9
A10
D10
SRAM_A9
A9
A11
D11
A12
D12
A13
D13
A14
D14
A15
D15
1
A0
2
A1
3
A2
4
A3
5
A4
18
A5
19
A6
20
A7
21
A8
22
A9
23
A10
24
A11
25
A12
26
A13
27
A14
42
A15
43
A16
44
A17
28
A18
SRAM_A1
D1
A2
SRAM_A3
7
D0
SRAM_A10
SRAM_A11
SRAM_A12
SRAM_A13
SRAM_A14
SRAM_A15
SRAM_A16
A16
SRAM_A17
A17
SRAM_A18
SRAM_WE
SRAM_OE
40
39
8
SRAM_D1
9
SRAM_D2
10
SRAM_D3
D1
D2
D3
13
D4
14
D5
15
D6
16
D7
29
D8
30
D9
31
D10
32
D11
VCCO_6_R6
SRAM_D5
FLASH_TDI
SRAM_D6
FLASH_TMS
SRAM_D7
FLASH_TDO
SRAM_D8
SRAM_D30
SRAM_D10
SRAM_D28
SRAM_D11
SRAM_D27
SRAM_D25
36
SRAM_D13
SRAM_D24
37
SRAM_D14
SRAM_D16
38
SRAM_D15
SRAM_D17
D13
D14
D15
W4
IO_L16N_6_W4
W3
IO_L16P_6_W3
W2
IO_L17N_6_W2
W1
IO_L17P_6_VREF_6_W1
V5
IO_L19N_6_V5
U5
SRAM_D31
SRAM_D9
SRAM_WE
WE
SRAM_OE
OE
BHE
IO_L19P_6_U5
V4
IO_L20N_6_V4
V3
IO_L20P_6_V3
V2
IO_L21N_6_V2
V1
IO_L21P_6_V1
T6
IO_L22N_6_T6
T5
IO_L22P_6_T5
U4
IO_L23N_6_U4
T4
IO_L23P_6_T4
U3
IO_L24N_6_VREF_6_U3
U2
IO_L24P_6_U2
T3
IO_L26N_6_T3
R4
IO_L26P_6_R4
T2
IO_L27N_6_T2
T1
IO_L27P_6_T1
R5
IO_L28N_6_R5
P6
IO_L28P_6_P6
R2
IO_L29N_6_R2
R1
IO_L29P_6_R1
P5
IO_L31N_6_P5
P4
IO_L31P_6_P4
P2
IO_L32N_6_P2
P1
IO_L32P_6_P1
N6
IO_L33N_6_N6
N5
IO_L33P_6_N5
N4
IO_L34N_6_VREF_6_N4
N3
IO_L34P_6_N3
N2
IO_L35N_6_N2
N1
IO_L35P_6_N1
M6
IO_L38N_6_M6
M5
IO_L38P_6_M5
M4
IO_L39N_6_M4
M3
IO_L39P_6_M3
M2
IO_L40N_6_M2
M1
IO_L40P_6_VREF_6_M1
SRAM_D19
SRAM_D18
SRAM_D21
SRAM_D20
SRAM_A14
SRAM_D22
SRAM_D23
SRAM_A18
BLE
SRAM_A16
IS61LV51216
TSOP44
IS61LV51216
TSOP44
SRAM_A11
SRAM_A10
SRAM_A15
SRAM_A13
SRAM_A12
SRAM_OE
SRAM_A17
SRAM_A2
SRAM_A4
SRAM_A6
3
C2
IO_Y1
SRAM_D29
SRAM_D4
SRAM_D12
35
D12
Y1
FLASH_TCK
SRAM_D26
CE
41
R6
6
CE
17
WE
41
OE
40
BHE
39
BLE
6
17
VCCO_6_R3
SRAM_D0
A18
SRAM_CE
SRAM_CE
7
D0
SRAM_A8
SRAM_WE
SRAM_A0
SRAM_A1
SRAM_A3
SRAM_A5
SRAM_A7
SRAM_CE
IO_C2
Y3
B6_L01N_Y3
IO_L01N_6_VRP_6_Y3
Y2
B6_L01P_Y2
A11
D1
IO_L16N_7_D1
C1
IO_L16P_7_VREF_7_C1
E4
IO_L17N_7_E4
D4
IO_L17P_7_D4
D3
IO_L19N_7_VREF_7_D3
D2
IO_L19P_7_D2
F4
IO_L20N_7_F4
E3
IO_L20P_7_E3
E1
IO_L21N_7_E1
E2
IO_L21P_7_E2
G6
IO_L22N_7_G6
F5
IO_L22P_7_F5
F2
IO_L23N_7_F2
F3
IO_L23P_7_F3
H5
IO_L24N_7_H5
G5
IO_L24P_7_G5
G3
IO_L26N_7_G3
G4
IO_L26P_7_G4
G1
IO_L27N_7_G1
G2
IO_L27P_7_VREF_7_G2
H1
IO_L28N_7_H1
H2
IO_L28P_7_H2
J4
IO_L29N_7_J4
H4
IO_L29P_7_H4
J5
IO_L31N_7_J5
J6
IO_L31P_7_J6
J1
IO_L32N_7_J1
J2
IO_L32P_7_J2
K5
IO_L33N_7_K5
K6
IO_L33P_7_K6
K3
IO_L34N_7_K3
K4
IO_L34P_7_K4
K1
IO_L35N_7_K1
K2
IO_L35P_7_K2
L5
IO_L38N_7_L5
L6
IO_L38P_7_L6
L3
IO_L39N_7_L3
L4
IO_L39P_7_L4
L1
IO_L40N_7_VREF_7_L1
L2
IO_L40P_7_L2
IO_L01P_6_VRN_6_Y2
A4
A5
D1
D2
A15
A10
D0
A14
A3
A9
D13
2
D7
A8
A13
PB2
D6
A12
A19
A2
A7
A1
A6
SRAM_D3
A18
SRAM_D2
SRAM_D0
SRAM_D7
SRAM_D6
SRAM_D13
SRAM_D1
SRAM_D5
SRAM_D4
3
SRAM_D8
SRAM_D9
SRAM_D14
SRAM_D15
SRAM_D11
SRAM_D12
SRAM_A9
SRAM_D10
C3
IO_L01N_7_VRP_7_C3
C4
IO_L01P_7_VRN_7_C4
A16
D3
XC3S1000
FG456
3.3V
3.3V
3.3V
DNP = Do Not Populate
4
C36
0.01UF
0603
C37
0.01UF
0603
C33
0.01UF
0603
C34
0.01UF
0603
C39
0.01UF
0603
C42
0.01UF
0603
C41
0.01UF
0603
C40
0.01UF
0603
C43
0.01UF
0603
C46
0.01UF
0603
C45
0.01UF
0603
ANALOG
DEVICES
C44
0.01UF
0603
Title
Size
SRAM
FPGA
Date
A
B
C
Nashua, NH 03063
4
PH: 1-800-ANALOGD
BLACKFIN FPGA EZ-EXTENDER
SRAM, FPGA BANKS 7 + 8
Board No.
C
SRAM
20 Cotton Road
Rev
A0199-2005
1.0
Sheet
9-27-2005_11:44
D
3
of
12
A
B
C
D
EXPANSION INTERFACE TYPE B
1
1
5V_EI
Expansion Connector 1
Bottom Of Board
Top Of Board
P1_[5:86]
P1
1
2
3
4
5
6
A1
A1
A2
7
8
A3
A4
9
10
A5
A6
11
12
A7
A8
13
14
A10
15
16
A12
17
18
A14
19
20
A16
21
22
P1_5
A18
2
1
4
3
6
5
A3
8
7
A2
A5
10
9
A4
A7
12
11
A6
A9
A9
14
13
A8
A11
A11
16
15
A10
A13
A13
18
17
A12
A15
A15
20
19
A14
A17
A17
22
21
A16
A19
A19
P1_5
23
24
24
23
P1_25
25
26
P1_26
P1_26
26
25
P1_25
P1_27
27
28
P1_28
P1_28
28
27
P1_27
P1_29
29
30
P1_30
P1_30
30
29
P1_29
P1_31
31
32
P1_32
P1_32
32
31
P1_31
P1_33
33
34
P1_34
P1_34
34
33
P1_33
P1_35
35
36
P1_36
P1_36
36
35
P1_35
A18
2
37
38
38
37
D0
39
40
D1
D1
40
39
D0
D2
41
42
D3
D3
42
41
D2
D4
43
44
D5
D5
44
43
D4
D6
45
46
D7
D7
46
45
D6
D8
47
48
D9
D9
48
47
D8
D10
49
50
D11
D11
50
49
D10
D12
51
52
D13
D13
52
51
D12
D15
D15
D14
3
J1
2
53
54
54
53
P1_55
55
56
P1_56
P1_56
56
55
P1_55
P1_57
57
58
P1_58
P1_58
58
57
P1_57
P1_59
59
60
P1_60
P1_60
60
59
P1_59
P1_61
61
62
P1_62
P1_62
62
61
P1_61
P1_63
63
64
P1_64
P1_64
64
63
P1_63
P1_65
65
66
P1_66
P1_66
66
65
P1_65
P1_67
67
68
P1_68
P1_68
68
67
P1_67
P1_69
69
70
P1_70
P1_70
70
69
P1_69
71
72
72
71
73
74
74
73
75
76
76
75
77
78
78
77
79
80
80
79
81
82
82
81
83
84
84
83
85
86
86
85
87
88
88
87
89
90
90
89
EXPANSION_PPI_CLK
PP1
PP3
UDEF2
UDEF4
UDEF6
UDEF8
UDEF10
45X2
CON018
PP0
B1_L24P_E15_J1_72
PP2
B1_L22P_B16_J1_74
UDEF1
UDEF3
B1_L19P_D16_J1_76
B1_L16P_C17_J1_78
UDEF5
B1_L15P_E17_J1_80
UDEF7
B1_L10P_B18_J1_82
UDEF9
B1_L09P_D18_J1_84
UDEF11
B1_L06P_B19_J1_86
D14
3
B1_L24N_D15_J1_71
B1_L22N_A16_J1_73
B1_L19N_C16_J1_75
B1_L16N_B17_J1_77
B1_L15N_D17_J1_79
B1_L10N_A18_J1_81
B1_L09N_C18_J1_83
B1_L06N_A19_J1_85
45X2
CON019
5V_EI
DNP = Do Not Populate
C35
10UF
805
4
ANALOG
DEVICES
C38
0.1UF
0603
Title
Size
Expanison Connector
P1
A
B
C
Nashua, NH 03063
4
PH: 1-800-ANALOGD
BLACKFIN FPGA EZ-EXTENDER
EXPANSION INTERFACE CONNECTOR 1
Board No.
C
Date
20 Cotton Road
Rev
A0199-2005
1.0
Sheet
10-18-2005_16:16
D
4
of
12
A
B
2.5V
3.3V
C
D
VCCO_1
VCCO_1
P9
1
VCCO_1
R30
DNP
0603
3.3V
2
3
1
1
IDC3X1
3X1
B1_L01N_VRP_C19
VCCO_0_C8
VCCO_0_F8
F15
VCCO_1_F15
VCCO_0_G9
VCCO_0_G10
B1_L22N_A16_J1_73
G13
B1_L19P_D16_J1_76
VCCO_1_G13
G11
VCCO_0_G11
B1_L19N_C16_J1_75
G14
VCCO_1_G14
B1_L31P_E12
AMS0
D14
A17
UDEF4
D8
UDEF1
D9
D10
D11
2
D12
D15
PP0
PP1
PP2
UDEF2
UDEF3
PP3
UDEF5
UDEF7
UDEF8
UDEF9
UDEF6
UDEF11
AMS3
AMS2
UDEF10
AMS1
ABE1
ABE0
ARDY
3
ARE
AWE
AOE
PB1
D4
D5
A10
IO_A12
D9
IO_F6
IO_F13
IO_VREF_0_A3
IO_F16
IO_VREF_0_E5
IO_VREF_1_E13
IO_VREF_0_F7
IO_L06N_0_D5
C5
IO_L09P_1_D18
IO_L10N_0_E6
IO_L10N_1_VREF_1_A18
C18
IO_L09P_0_A5
D18
D6
A18
B18
IO_L10P_0_D6
IO_L10P_1_B18
C6
IO_L15N_1_D17
IO_L15P_0_B6
IO_L15P_1_E17
IO_L16N_0_E7
IO_L16N_1_B17
E17
B17
D7
C17
IO_L16P_0_D7
IO_L16P_1_C17
IO_L19N_0_B7
IO_L19N_1_C16
IO_L19P_0_A7
IO_L19P_1_D16
IO_L22N_0_E8
IO_L22N_1_A16
A7
E8
C16
D16
IO_L22P_1_B16
IO_L24N_0_B8
IO_L24N_1_D15
A8
IO_L24P_1_E15
IO_L25N_1_B15
IO_L25P_0_E9
IO_L25P_1_A15
B9
IO_L27P_1_E14
F10
IO_L28N_1_A14
C10
IO_L28P_1_B14
IO_L29N_0_C10
IO_L29P_1_D13
IO_L30N_0_F11
IO_L30N_1_A13
A13
E11
B13
IO_L30P_0_E11
D11
IO_L30P_1_B13
C11
IO_L31N_0_D11
B4
IO_L31P_0_VREF_0_C11
E12
IO_L31P_1_E12
IO_L01N_1_VRP_1_C19
IO_L01P_0_VRN_0_A4
IO_L01P_1_VRN_1_B20
A4
IO_L01N_0_VRP_0_B4
B1_L15N_D17_J1_79
B1_F16
B1_L15P_E17_J1_80
B1_L31N_D12
B1_L16N_B17_J1_77
B1_L30N_A13
B1_L16P_C17_J1_78
B1_L29N_C13
B1_L19N_C16_J1_75
B1_L28N_A14
IO_L32_0_GCLK6_A11
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
B11
IO_L32N_0_GCLK7_B11
A11
IO_L32P_0_GCLK6_A11
IO_L32N_1_GCLK5_B12
IO_L32P_1_GCLK4_C12
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
B1_L29P_D13
B1_L01P_VRN_B20
B1_L29N_C13
B1_A12
35
36
B1_L28P_B14
B1_E13
37
38
39
B1_L28N_A14
B1_E16
40
B1_L27P_E14
41
42
43
B1_L27N_D14
B1_F17
44
B1_L25P_A15
B1_L31P_E12
45
46
B1_L25N_B15
B1_L30P_B13
47
48
49
50
B1_L29P_D13
B1_L01P_VRN_B20
B1_L01N_VRP_C19
B1_F14
B1_A12
B1_F12
B1_E13
B1_F13
B1_E16
B1_F16
B1_F17
B1_L09P_D18_J1_84
B1_L09N_C18_J1_83
B1_L06P_B19_J1_86
B1_L06N_A19_J1_85
2
CON041
25X2
B1_L28P_B14
LAYOUT NOTE: PLACE NEAR FPGA
R27
0
0603
3.3V
EXPANSION_PPI_CLK
IO_L32_0_GCLK7_B11
R52
DNP
0603
B1_L29P_D13
B1_L27N_D14
B1_L30N_A13
B1_L25N_B15
C19
B20
B1_L24N_D15_J1_71
B1_L31N_D12
B1_L22N_A16_J1_73
B1_L31P_E12
B1_L19N_C16_J1_75
B1_L01N_VRP_C19
B1_L16N_B17_J1_77
B1_L01P_VRN_B20
B1_L15N_D17_J1_79
B1_L10N_A18_J1_81
IO_L32_0_GCLK7_B11
8
B1_L32N_GCLK5_B12
IDC13X2
13X2
B1_L30P_B13
D12
IO_L31N_1_VREF_1_D12
B1_F13
B1_L29N_C13
D13
IO_L29P_0_B10
B1_L10N_A18_J1_81
B1_L28P_B14
C13
IO_L29N_1_C13
B10
F11
7
B1_L28N_A14
B14
IO_L28P_0_E10
B1_F12
6
B1_L30N_A13
B1_L32P_GCLK4_C12
B1_L27P_E14
A14
IO_L28N_0_F10
B1_L09P_D18_J1_84
B1_L27N_D14
E14
E10
B1_F14
4
B1_L25P_A15
D14
IO_L27P_0_A9
B1_L09N_C18_J1_83
5
2
B1_L25N_B15
A15
IO_L27N_1_D14
B1_L01N_VRP_C19
B1_L30P_B13
B1_L24P_E15_J1_72
B15
IO_L27N_0_B9
A9
6
B1_L24N_D15_J1_71
E15
IO_L25N_0_F9
E9
5
B1_L32P_GCLK4_C12
B1_L22P_B16_J1_74
D15
IO_L24P_0_A8
F9
B1_L06P_B19_J1_86
3
B1_L22N_A16_J1_73
B16
IO_L22P_0_D8
B8
B1_L32N_GCLK5_B12
B1_L19P_D16_J1_76
A16
D8
B1_L06N_A19_J1_85
B1_L10P_B18_J1_82
D17
IO_L15N_0_C6
P14
1
B1_F14
IO_L06P_1_B19
IO_L09N_1_C18
B7
B1_L10N_A18_J1_81
B1_E13
A19
IO_L09N_0_B5
E7
B1_F17
B19
IO_L06P_0_C5
B6
B1_L10P_B18_J1_82
F14
IO_L06N_1_VREF_1_A19
B1_L15N_D17_J1_79
3.3V
B1_F16
E13
IO_VREF_1_F14
D5
E6
B1_L15P_E17_J1_80
B1_F13
F17
IO_F17
A5
B1_F12
F16
IO_VREF_0_C7
B5
B1_L16N_B17_J1_77
F13
C7
F7
B1_E16
F12
IO_F12
E5
B1_L16P_C17_J1_78
IO_E16
IO_D10
A3
B1_A12
E16
IO_D9
F6
B1_L31N_D12
A12
IO_A10
D10
4
B1_L22P_B16_J1_74
G12
VCCO_1_G12
G10
ABE3
2
3
B1_L24N_D15_J1_71
R31
DNP
0603
C15
VCCO_1_C15
G9
ABE2
1
B1_L24P_E15_J1_72
C8
F8
P4
B1_L01P_VRN_B20
U1
B12
B1_L32N_GCLK5_B12
C12
B1_L09N_C18_J1_83
B1_L32P_GCLK4_C12
B1_L06N_A19_J1_85
XC3S1000
FG456
P8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
B1_L10N_A18_J1_81
B1_L10P_B18_J1_82
R53
DNP
0603
B1_L27P_E14
B1_L25P_A15
3
B1_L16P_C17_J1_78
B1_L24P_E15_J1_72
B1_L16N_B17_J1_77
B1_L22P_B16_J1_74
R54
DNP
0603
B1_L19P_D16_J1_76
B1_L15P_E17_J1_80
B1_L16P_C17_J1_78
B1_L15N_D17_J1_79
B1_L15P_E17_J1_80
B1_L24N_D15_J1_71
B1_L10P_B18_J1_82
B1_L22N_A16_J1_73
B1_L09P_D18_J1_84
B1_L19N_C16_J1_75
B1_L06P_B19_J1_86
R49
DNP
0603
IDC13X2
13X2
R48
DNP
0603
R50
DNP
0603
R51
DNP
0603
3.3V
VCCO_1
DNP = Do Not Populate
4
C54
0.01UF
0603
C47
0.01UF
0603
C48
0.01UF
0603
C49
0.01UF
0603
C50
0.01UF
0603
C51
0.01UF
0603
C52
0.01UF
0603
ANALOG
DEVICES
C53
0.01UF
0603
Title
Size
FPGA
Date
A
B
C
Nashua, NH 03063
4
PH: 1-800-ANALOGD
BLACKFIN FPGA EZ-EXTENDER
FPGA BANKS 0 + 1
Board No.
C
FPGA
20 Cotton Road
Rev
A0199-2005
1.0
Sheet
9-27-2005_11:44
D
5
of
12
A
B
C
D
1
1
3.3V_EI
Expansion Connector 2
Bottom Of Board
Top Of Board
P2_[5:86]
P2
1
2
2
1
3
4
4
3
P2_5
5
6
P2_6
P2_6
6
5
P2_5
P2_7
7
8
P2_8
P2_8
8
7
P2_7
10
9
12
11
14
13
9
10
11
12
13
14
15
16
16
15
17
18
P2_18
P2_18
18
17
P2_19
19
20
P2_20
P2_20
20
19
P2_19
P2_21
21
22
P2_22
P2_22
22
21
P2_21
23
24
24
23
25
26
26
25
27
28
28
27
29
30
30
29
31
32
32
31
33
34
34
33
35
36
36
35
37
38
38
37
39
40
40
39
41
42
42
41
43
44
PF14
44
43
45
46
PF12
46
45
47
48
PF10
48
47
49
50
PF8
50
49
51
52
PF6
52
51
53
54
PF4
54
53
55
56
PF2
56
55
57
58
PF0
58
57
59
60
60
59
61
62
62
61
63
64
64
63
65
66
66
65
67
68
68
67
69
70
70
69
P2_71
71
72
P2_72
P2_72
72
71
P2_71
P2_73
73
74
P2_74
P2_74
74
73
P2_73
SCK
SPIDS0
P2_15
NMI
TMR3
TMR1
2
DR1SEC
DR1PRI
RFS1
RSCLK1
DR0SEC
DR0PRI
RFS0
RSCLK0
PF15
PF13
PF11
PF9
PF7
PF5
PF3
PF1
AMS3
AMS2
AMS1
AMS0
3
J2
ARDY
ARE
MOSI
MISO
UDEF12
TMR2
B2_L40P_L22_J2_10
B2_L39P_L20_J2_12
IO_L01P_2_VRN_2_C21_J2_16
B2_L38P_L18_J2_24
TMR0
B2_L35P_K22_J2_26
DT1SEC
B2_L34P_K20_J2_28
DT1PRI
B2_L33P_K18_J2_30
CONFIG_INIT_B_TFS1
B2_L32P_J22_J2_32
CONFIG_CLK_TSCLK1
B2_L31P_J19_J2_34
DT0SEC
B2_L29P_H22_J2_36
DT0PRI
B2_L28P_J17_J2_38
TFS0
TSCLK0
B2_L27P_G22_J2_40
B2_L26P_H19_J2_42
B2_L22P_G18_J2_44
B2_L24P_F21_J2_46
B2_L23P_G19_J2_48
B2_L21P_E22_J2_50
B2_L20P_E20_J2_52
B2_L19P_F18_J2_54
B2_L17P_D22_J2_56
B2_L16P_D19_J2_58
ABE3
ABE3
ABE2
ABE2
ABE1
ABE1
ABE0
ABE0
AOE
AOE
AWE
AWE
B2_L40N_L21_J2_9
B2_L39N_L19_J2_11
P2_15
B2_C22_J2_17
B2_L38N_L17_J2_23
B2_L35N_K21_J2_25
B2_L33N_K17_J2_29
B2_L32N_J21_J2_31
B2_L31N_J18_J2_33
B2_L29N_H21_J2_35
B2_L28N_H18_J2_37
B2_L27N_G21_J2_39
B2_L26N_G20_J2_41
B2_L22N_G17_J2_43
B2_L24N_F20_J2_45
B2_L23N_F19_J2_47
B2_L21N_E21_J2_49
B2_L20N_E19_J2_51
B2_L19N_E18_J2_53
B2_L17N_D21_J2_55
B2_L16N_D20_J2_57
AMS3
AMS2
AMS1
AMS0
3
ARDY
ARE
75
76
76
75
P2_77
77
78
P2_78
P2_78
78
77
P2_77
P2_79
79
80
P2_80
P2_80
80
79
P2_79
P2_81
81
82
P2_82
P2_82
82
81
P2_81
P2_83
83
84
P2_84
P2_84
84
83
P2_83
P2_85
85
86
P2_86
P2_86
86
85
P2_85
87
88
88
87
89
90
90
89
45X2
CON018
2
B2_L34N_K19_J2_27
45X2
CON019
3.3V_EI
DNP = Do Not Populate
C55
10UF
805
4
ANALOG
DEVICES
C56
0.1UF
0603
Title
Size
Date
A
B
C
Nashua, NH 03063
4
PH: 1-800-ANALOGD
BLACKFIN FPGA EZ-EXTENDER
EXPANSION INTERFACE CONNECTOR 2
Board No.
C
Expanison Connector
P2
20 Cotton Road
Rev
A0199-2005
1.0
Sheet
9-14-2005_12:03
D
6
of
12
A
B
C
D
VCCO_2
3.3V
2.5V
P10
1
2
3
3.3V
VCCO_2
IDC3X1
3X1
1
1
3.3V
U1
H17
VCCO_2_H17
M16
VCCO_3_M16
H20
VCCO_2_H20
N16
VCCO_3_N16
J16
VCCO_2_J16
VCCO_3_P16
K16
VCCO_2_K16
VCCO_2_L16
B2_L27N_G21_J2_39
R17
VCCO_3_R17
L16
P7
R20
VCCO_3_R20
CONFIG_DONE
JP2
1
2
B2_L28N_H18_J2_37
PF3
B2_L29N_H21_J2_35
IDC2X1
2X1
B2_C22_J2_17
B2_L16N_D20_J2_57
B2_L16P_D19_J2_58
B2_L17N_D21_J2_55
B2_L17P_D22_J2_56
B2_L19N_E18_J2_53
B2_L19P_F18_J2_54
B2_L20N_E19_J2_51
B2_L20P_E20_J2_52
B2_L21N_E21_J2_49
B2_L21P_E22_J2_50
2
B2_L22N_G17_J2_43
B2_L22P_G18_J2_44
B2_L23N_F19_J2_47
B2_L23P_G19_J2_48
B2_L24N_F20_J2_45
B2_L24P_F21_J2_46
B2_L26N_G20_J2_41
B2_L26P_H19_J2_42
B2_L27N_G21_J2_39
B2_L27P_G22_J2_40
B2_L28N_H18_J2_37
B2_L28P_J17_J2_38
B2_L29N_H21_J2_35
B2_L29P_H22_J2_36
B2_L31N_J18_J2_33
B2_L31P_J19_J2_34
B2_L32N_J21_J2_31
B2_L32P_J22_J2_32
B2_L33N_K17_J2_29
B2_L33P_K18_J2_30
3
B2_L34N_K19_J2_27
B2_L34P_K20_J2_28
B2_L35N_K21_J2_25
B2_L35P_K22_J2_26
B2_L38N_L17_J2_23
B2_L38P_L18_J2_24
B2_L39N_L19_J2_11
B2_L39P_L20_J2_12
B2_L40N_L21_J2_9
B2_L40P_L22_J2_10
IO_L01N_2_VRP_2_C20
IO_L01P_2_VRN_2_C21_J2_16
C22
IO_Y21
D20
IO_L16N_2_D20
IO_L16P_3_Y22
IO_L17N_2_D21
F18
IO_L19P_2_F18
E19
IO_L20N_2_E19
E20
IO_L21N_2_E21
E22
C20
IO_L01N_2_VRP_2_C20
C21
IO_L01P_2_VRN_2_C21
DR1SEC
DT1SEC
V22
IO_L21N_3_V22
IO_L21P_3_V21
T17
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
IO_L26N_3_T20
DR0SEC
T19
IO_L31P_3_P17
IO_L32P_3_P21
N18
N17
N21
M18
IO_L38N_3_M18
B2_L20N_E19_J2_51
B2_L21N_E21_J2_49
B2_L22N_G17_J2_43
VCCO_2
PF11
B2_L23N_F19_J2_47
PF10
B2_L24N_F20_J2_45
B2_L26N_G20_J2_41
PF0
M20
R32
DNP
0603
PF3
M19
IO_L39P_3_M19
PF2
M22
IO_L40N_3_VREF_3_M22
B2_L19N_E18_J2_53
PF7
PF1
M17
IO_L38P_3_M17
IO_L39N_3_M20
TSCLK0
PF8
N22
IO_L35P_3_N21
B2_L17N_D21_J2_55
PF9
N19
IO_L35N_3_N22
B2_L16N_D20_J2_57
PF6
N20
IO_L34P_3_VREF_3_N19
IO_L01N_2_VRP_2_C20
RSCLK0
P21
IO_L33P_3_N17
B2_L39P_L20_J2_12
B2_L40P_L22_J2_10
3.3V
PF12
P22
IO_L34N_3_N20
B2_L38P_L18_J2_24
B2_L26P_H19_J2_42
PF13
P17
IO_L33N_3_N18
B2_L26N_G20_J2_41
PF14
P18
IO_L32N_3_P22
B2_L35P_K22_J2_26
B2_L24P_F21_J2_46
PF15
R19
IO_L31N_3_P18
B2_L34P_K20_J2_28
2
CONFIG_CLK_TSCLK1
P19
IO_L29P_3_R19
B2_L33P_K18_J2_30
RSCLK1
R21
IO_L29N_3_P19
B2_L40N_L21_J2_9
CONFIG_INIT_B_TFS1
R22
IO_L28P_3_R21
B2_L32P_J22_J2_32
RFS1
T21
IO_L28N_3_R22
B2_L31P_J19_J2_34
DT0SEC
T22
IO_L27N_3_T22
IO_L27P_3_T21
B2_L29P_H22_J2_36
R55
DNP
0603
TFS0
T20
B2_L28P_J17_J2_38
B2_L23P_G19_J2_48
B2_L24N_F20_J2_45
RFS0
T18
B2_L27P_G22_J2_40
R56
DNP
0603
DT1PRI
R18
IO_L26P_3_T19
B2_L23N_F19_J2_47
DR1PRI
U20
IO_L24P_3_T18
M21
IO_L40P_3_M21
IO_L01P_3_VRN_3_Y19
4
IDC14X2
14X2
DT0PRI
U21
IO_L24N_3_R18
IO_L01N_3_VRP_3_Y20
3
R57
DNP
0603
DR0PRI
U18
IO_L23N_3_U21
LAYOUT NOTE: PLACE NEAR FPGA
TMR2
IO_L22N_3_T17
IO_L23P_3_VREF_3_U20
B2_L39N_L19_J2_11
TMR3
V21
IO_L22P_3_U18
B2_L34N_K19_J2_27
B2_L38N_L17_J2_23
IO_L20P_3_V20
E21
B2_L33N_K17_J2_29
UDEF12
V20
IO_L20P_2_E20
2
PF2
B2_L35N_K21_J2_25
U19
IO_L20N_3_U19
2
IDC2X1
2X1
NMI
W20
IO_L19P_3_W20
JP3
1
TMR1
W21
IO_L19N_3_W21
CONFIG_PROG_B
TMR0
W19
IO_L17P_3_VREF_3_W19
IO_L19N_2_E18
SCK
V19
IO_L17N_3_V19
E18
IO_L21P_2_E22
G17
IO_L22N_2_G17
G18
IO_L22P_2_G18
F19
IO_L23N_2_VREF_2_F19
G19
IO_L23P_2_G19
F20
IO_L24N_2_F20
F21
IO_L24P_2_F21
G20
IO_L26N_2_G20
H19
IO_L26P_2_H19
G21
IO_L27N_2_G21
G22
IO_L27P_2_G22
H18
IO_L28N_2_H18
J17
IO_L28P_2_J17
H21
IO_L29N_2_H21
H22
IO_L29P_2_H22
J18
IO_L31N_2_J18
J19
IO_L31P_2_J19
J21
IO_L32N_2_J21
J22
IO_L32P_2_J22
K17
IO_L33N_2_K17
K18
IO_L33P_2_K18
K19
IO_L34N_2_VREF_2_K19
K20
IO_L34P_2_K20
K21
IO_L35N_2_K21
K22
IO_L35P_2_K22
L17
IO_L38N_2_L17
L18
IO_L38P_2_L18
L19
IO_L39N_2_L19
L20
IO_L39P_2_L20
L21
IO_L40N_2_L21
L22
IO_L40P_2_VREF_2_L22
MOSI
Y22
IO_L16P_2_D19
D21
IO_L17P_2_VREF_2_D22
B2_L32N_J21_J2_31
W22
IO_L16N_3_W22
D19
D22
B2_L31N_J18_J2_33
Y21
IO_C22
1
P16
Y20
PF5
IO_L01N_2_VRP_2_C20
PF4
IO_L01P_2_VRN_2_C21_J2_16
SPIDS0
Y19
P5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
B2_C22_J2_17
IO_L01P_2_VRN_2_C21_J2_16
B2_L16P_D19_J2_58
B2_L17P_D22_J2_56
B2_L19P_F18_J2_54
B2_L20P_E20_J2_52
3
B2_L21P_E22_J2_50
B2_L22P_G18_J2_44
B2_L23P_G19_J2_48
B2_L24P_F21_J2_46
B2_L26P_H19_J2_42
IDC14X2
14X2
R33
DNP
0603
MISO
XC3S1000
FG456
3.3V
DNP = Do Not Populate
VCCO_2
ANALOG
DEVICES
4
C60
0.01UF
0603
C59
0.01UF
0603
C58
0.01UF
0603
FPGA
C57
0.01UF
0603
C61
0.01UF
0603
C82
0.01UF
0603
C81
0.01UF
0603
C62
0.01UF
0603
Title
Size
FPGA
A
B
C
Nashua, NH 03063
4
PH: 1-800-ANALOGD
BLACKFIN FPGA EZ-EXTENDER
FPGA BANKS 2 + 3
Board No.
C
Date
20 Cotton Road
Rev
A0199-2005
1.0
Sheet
9-27-2005_11:44
D
7
of
12
A
B
C
D
EXPANSION INTERFACE (TYPE B)
1
5V_EI
1
3.3V_EI
Expansion Connector 3
Bottom Of Board
Top Of Board
P3_[1:90]
J3
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
24
23
25
26
26
25
27
28
28
27
29
30
30
29
31
32
32
31
33
34
34
33
35
36
36
35
37
38
38
37
39
40
40
39
41
42
42
41
43
44
44
43
P3_45
45
46
P3_46
P3_46
46
45
P3_45
P3_47
47
48
P3_48
P3_48
48
47
P3_47
P3_49
49
50
P3_50
P3_50
50
49
P3_49
P3_51
51
52
P3_52
P3_52
52
51
P3_51
P3_53
53
54
P3_54
P3_54
54
53
P3_53
P3_55
55
56
P3_56
P3_56
56
55
P3_55
P3_57
57
58
P3_58
P3_58
58
57
P3_57
P3_59
59
60
P3_60
P3_60
60
59
P3_59
P3_61
61
62
P3_62
P3_62
62
61
P3_61
P3_63
63
64
P3_64
P3_64
64
63
P3_63
65
66
66
65
P3_67
67
68
P3_68
P3_68
68
67
P3_67
P3_69
69
70
P3_70
P3_70
70
69
P3_69
P3_71
71
72
P3_72
P3_72
72
71
P3_71
P3_73
73
74
P3_74
P3_74
74
73
P3_73
P3_75
75
76
P3_76
P3_76
76
75
P3_75
P3_77
77
78
P3_78
P3_78
78
77
P3_77
P3_79
79
80
P3_80
P3_80
80
79
P3_79
81
82
P3_82
P3_82
82
81
83
84
P3_84
P3_84
84
83
85
86
P3_86
P3_86
86
85
87
88
88
87
89
90
90
89
UDEF14
RX0
RX1
UDEF16
UDEF18
UDEF20
UDEF22
UDEF24
UDEF26
UDEF28
UDEF30
2
CLK_OUT_EXP1
UDEF31
UDEF33
UDEF35
UDEF37
UDEF39
UDEF41
3
BR
BG
BGH
3.3V_EI
P3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
UDEF15
TX0
B5_L01P_CS_B_AA3_J3_2
B5_L06P_AA4_J3_6
TX1
B5_L09P_W5_J3_8
UDEF17
B5_L10P_VRN_AA5_J3_10
UDEF19
B5_L15P_V6_J3_12
UDEF21
B5_L16P_Y6_J3_14
UDEF23
B5_L19P_W7_J3_16
UDEF25
B5_L22P_AA7_J3_18
UDEF27
B5_L24P_V8_J3_20
UDEF29
B5_L25P_AA8_J3_22
RESET
B5_U7_J3_28
B5_L32N_GCLK3_AA11_J3_30
UDEF32
B5_L27P_V9_J3_32
UDEF34
B5_L28P_D7_AA9_J3_34
UDEF36
B5_L29P_W10_J3_36
UDEF38
UDEF40
P3_42
B5_L30P_AA10_J3_38
B5_L31P_D5_V11_J3_40
P3_42
B5_L01N_RDWR_B_Y4_J3_1
B5_L06N_AB4_J3_5
B5_L09N_Y5_J3_7
B5_L10N_VRP_AB5_J3_9
B5_L15N_W6_J3_11
B5_L16N_AA6_J3_13
B5_L19N_Y7_J3_15
B5_L22N_AB7_J3_17
B5_L24N_W8_J3_19
B5_L25N_AB8_J3_21
B5_U6_J3_23
2
B5_V7_J3_29
B5_L27N_W9_J3_31
B5_L28N_D6_AB9_J3_33
B5_L29N_Y10_J3_35
B5_L30N_AB10_J3_37
B5_L31N_D4_W11_J3_39
B5_U9_J3_41
3
B5_U10_J3_81
B5_U11_J3_83
B5_V10_J3_85
5V_EI
P3_89
45X2
CON018
C86
10UF
805
C85
0.1UF
0603
C83
10UF
805
UDEF43
B5_AB11_J3_90
P3_89
45X2
CON019
C84
0.1UF
0603
DNP = Do Not Populate
ANALOG
DEVICES
4
Title
Expanison Connector
P3
Expanison Connector
P3
Size
A
B
C
Nashua, NH 03063
4
PH: 1-800-ANALOGD
BLACKFIN FPGA EZ-EXTENDER
EXPANSION INTERFACE CONNECTOR 1
Board No.
C
Date
20 Cotton Road
Rev
A0199-2005
1.0
Sheet
9-9-2005_10:29
D
8
of
12
A
B
2.5V
3.3V
C
D
VCCO_5
3.3V
P11
1
VCCO_5
2
3
1
3.3V
1
IDC3X1
3X1
U1
P17
T12
VCCO_5_T9
VCCO_4_T13
VCCO_5_T10
VCCO_4_T14
VCCO_5_T11
T13
VCCO_4_T12
T14
U15
VCCO_4_U15
Y15
VCCO_4_Y15
B5_U6_J3_23
T10
B5_L24P_V8_J3_20
T11
U8
B5_L25P_AA8_J3_22
Y8
B5_L27P_V9_J3_32
VCCO_5_U8
VCCO_5_Y8
B5_L28P_D7_AA9_J3_34
U16
RESET
IO_U16
U17
UDEF35
IO_U17
W13
TX0
IO_W13
W14
UDEF19
IO_W14
V18
UDEF41
IO_VREF_4_V18
Y16
UDEF28
IO_VREF_4_Y16
AB13
UDEF15
IO_L06N_4_VREF_4_W18
Y18
UDEF39
IO_L06P_4_Y18
AA18
UDEF37
IO_L09P_4_AB18
V17
UDEF34
IO_L10N_4_V17
W17
UDEF33
IO_L10P_4_W17
Y17
UDEF32
IO_L15N_4_Y17
AA17
UDEF31
IO_L15P_4_AA17
V16
UDEF30
IO_L16N_4_V16
W16
UDEF29
IO_L16P_4_W16
AA16
UDEF27
IO_L19N_4_AA16
AB16
UDEF26
IO_L19P_4_AB16
V15
UDEF25
IO_L22N_4_VREF_4_V15
W15
UDEF24
IO_L22P_4_W15
AA15
UDEF23
IO_L24N_4_AA15
AB15
UDEF22
IO_L24P_4_AB15
U14
UDEF21
IO_L25N_4_U14
V14
UDEF20
IO_L25P_4_V14
AA14
CONFIG_DIN_DT1PRI
IO_L27N_4_DIN_D0_AA14
AB14
UDEF17
IO_L27P_4_D1_AB14
U13
TX1
IO_L28N_4_U13
V13
RX1
IO_L28P_4_V13
Y13
RX0
R46
10K
0603
IO_L09N_4_AA18
AB18
UDEF36
3
IO_L05P_4_AB19
W18
UDEF40
3.3V
IO_L05N_4_AA19
AB19
UDEF43
2
IO_VREF_4_AB13
AA19
BR
IO_L29N_4_Y13
AA13
UDEF14
IO_L29P_4_AA13
U12
UDEF16
IO_L30N_4_D2_U12
V12
UDEF38
IO_L30P_4_D3_V12
W12
CONFIG_INIT_B_TFS1
IO_L31N_4_INIT_B_W12
U7
IO_U7
U9
IO_U9
U10
IO_U10
U11
IO_U11
V7
IO_V7
V10
IO_V10
U6
IO_VREF_5_U6
AB11
IO_VREF_5_AB11
Y4
IO_L01N_5_RDWR_B_Y4
AA3
IO_L01P_5_CS_B_AA3
AB4
IO_L06N_5_AB4
AA4
IO_L06P_5_AA4
Y5
IO_L09N_5_Y5
W5
IO_L09P_5_W5
W6
IO_L15N_5_W6
V6
IO_L15P_5_V6
AA6
IO_L16N_5_AA6
Y6
IO_L16P_5_Y6
Y7
IO_L19N_5_Y7
W7
IO_L19P_5_VREF_5_W7
AB7
IO_L22N_5_AB7
AA7
IO_L22P_5_AA7
W8
IO_L24N_5_W8
V8
IO_L24P_5_V8
AB8
IO_L25N_5_AB8
AA8
IO_L25P_5_AA8
W9
IO_L27N_5_VREF_5_W9
V9
IO_L27P_5_V9
AB9
IO_L28N_5_D6_AB9
AA9
IO_L28P_5_D7_AA9
Y10
IO_L29N_5_Y10
W10
IO_L29P_5_VREF_5_W10
AB10
IO_L30N_5_AB10
AA10
IO_L30P_5_AA10
W11
IO_L31N_5_D4_W11
V11
IO_L31P_5_D5_V11
B5_U7_J3_28
B5_L29P_W10_J3_36
B5_U9_J3_41
B5_L30P_AA10_J3_38
B5_U10_J3_81
B5_L31P_D5_V11_J3_40
B5_U11_J3_83
B5_U10_J3_81
B5_V7_J3_29
B5_AB11_J3_90
B5_V10_J3_85
AA20
AB20
BGH
IO_L01N_4_VRP_4_AA20
IO_L01P_4_VRN_4_AB20
IO_L10P_5_VRN_5_AA5
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
AB5
AA5
B5_U9_J3_41
B5_L24N_W8_J3_19
B5_L25N_AB8_J3_21
B5_L27N_W9_J3_31
B5_L28N_D6_AB9_J3_33
B5_L29N_Y10_J3_35
B5_L30N_AB10_J3_37
B5_L31N_D4_W11_J3_39
B5_U11_J3_83
B5_V10_J3_85
IDC13X2
13X2
B5_L01N_RDWR_B_Y4_J3_1
B5_L01P_CS_B_AA3_J3_2
B5_L06N_AB4_J3_5
B5_L06P_AA4_J3_6
2
B5_L09N_Y5_J3_7
B5_L09P_W5_J3_8
B5_L15N_W6_J3_11
B5_L15P_V6_J3_12
B5_L16N_AA6_J3_13
B5_L16P_Y6_J3_14
B5_L19N_Y7_J3_15
B5_L19P_W7_J3_16
B5_L22N_AB7_J3_17
B5_L22P_AA7_J3_18
3.3V
B5_L24N_W8_J3_19
B5_L24P_V8_J3_20
B5_L25N_AB8_J3_21
B5_L25P_AA8_J3_22
B5_L27N_W9_J3_31
B5_L32N_GCLK3_AA11_J3_30
B5_L27P_V9_J3_32
B5_L01P_CS_B_AA3_J3_2
B5_L28N_D6_AB9_J3_33
B5_L06P_AA4_J3_6
B5_L28P_D7_AA9_J3_34
B5_L09P_W5_J3_8
B5_L29N_Y10_J3_35
B5_U7_J3_28
B5_L29P_W10_J3_36
B5_L30N_AB10_J3_37
B5_L10P_VRN_AA5_J3_10
B5_L30P_AA10_J3_38
B5_L15P_V6_J3_12
B5_L31N_D4_W11_J3_39
B5_L16P_Y6_J3_14
B5_L31P_D5_V11_J3_40
B5_L19P_W7_J3_16
B5_L22P_AA7_J3_18
IO_L10N_5_VRP_5_AB5
4
B5_AB11_J3_90
IO_L31P_4_DOUT_BUSY_Y12
BG
2
3
B5_U6_J3_23
Y12
UDEF18
1
T9
P16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
B5_L32P_GCLK2_Y1
B5_L01N_RDWR_B_Y4_J3_1
B5_L06N_AB4_J3_5
B5_L09N_Y5_J3_7
B5_V7_J3_29
3
B5_L10N_VRP_AB5_J3_9
B5_L15N_W6_J3_11
B5_L16N_AA6_J3_13
B5_L19N_Y7_J3_15
B5_L22N_AB7_J3_17
IDC13X2
13X2
B5_L10N_VRP_AB5_J3_9
B5_L10P_VRN_AA5_J3_10
VCCO_5
R9
0
0603
AA12
AB12
CLK_OUT_EXP1
IO_L32N_4_GCLK1_AA12
IO_L32N_5_GCLK3_AA11
IO_L32P_4_GCLK0_AB12
IO_L32P_5_GCLK2_Y11
AA11
Y11
B5_L32N_GCLK3_AA11_J3_30
B5_L32P_GCLK2_Y1
XC3S1000
FG456
B4_L32N_GCKL1_AA12
R43
DNP
0603
B5_L10N_VRP_AB5_J3_9
B5_L10P_VRN_AA5_J3_10
3.3V
VCCO_5
DNP = Do Not Populate
R45
DNP
0603
ANALOG
DEVICES
4
C67
0.01UF
0603
C70
0.01UF
0603
C69
0.01UF
0603
C68
0.01UF
0603
C63
0.01UF
0603
C66
0.01UF
0603
C65
0.01UF
0603
FPGA
C64
0.01UF
0603
Title
Nashua, NH 03063
4
PH: 1-800-ANALOGD
BLACKFIN FPGA EZ-EXTENDER
FPGA BANKS 4 + 5
FPGA
Size
Board No.
C
Date
A
20 Cotton Road
B
C
Rev
A0199-2005
1.0
Sheet
9-27-2005_11:44
D
9
of
12
A
B
C
D
1
1
3.3V
B5_L25N_AB8_J3_21
B5_L27N_W9_J3_31
B5_L28N_D6_AB9_J3_33
R47
10K
0603
U8
B5_L30N_AB10_J3_37
2
B5_L31N_D4_W11_J3_39
SW3
SWT013
SPST-MOMENTARY
B5_U11_J3_83
R42
10
0603
1
B5_L29N_Y10_J3_35
4
PB1
SN74LVC1G125
SOT23-5
C5
1UF
0603
B5_V10_J3_85
2
2
2.5V
R23
100
402
LED7
AMBER-SMT
LED001
LED6
AMBER-SMT
LED001
LED5
AMBER-SMT
LED001
LED4
AMBER-SMT
LED001
LED3
AMBER-SMT
LED001
LED2
AMBER-SMT
LED001
LED1
AMBER-SMT
LED001
LED8
AMBER-SMT
LED001
PB2
LED9
GREEN-SMT
LED001
SW4
SWT013
SPST-MOMENTARY
3.3V
R39
330
0603
R37
330
0603
R38
330
0603
R36
330
0603
R35
330
0603
R34
330
0603
R10
330
0603
R41
330
0603
R40
330
0603
C80
0.01UF
0603
SN74LVC1G125
3
3
JP5
1
2
3
4
5
6
7
8
B6_L01N_Y3
B6_L01P_Y2
B5_U10_J3_81
B5_AB11_J3_90
IDC4X2
4X2
DNP = Do Not Populate
ANALOG
DEVICES
4
Title
Size
A
B
C
Nashua, NH 03063
4
PH: 1-800-ANALOGD
BLACKFIN FPGA EZ-EXTENDER
USER IO
Board No.
C
Date
20 Cotton Road
Rev
A0199-2005
1.0
Sheet
9-27-2005_11:44
D
10
of
12
A
B
C
D
UNREG_IN
D5
2A
DO-214AA
F1
2.5A
FUS001
FER1
CHOKE_COIL
4
3
1
2
S2A_RECT
J4
1
C1
1000PF
805
1
2
C4
10UF
C
C3
0.1UF
0603
1
3
POWER
CON005
2.5MM_JACK
C2
1000PF
805
FER2
0603
5V_EI
Q1
SI2343DS
SOT23D
2.5V
UNREG_IN
L3
10UH
IND005
P42
1
3
2
2
1
2
2
P12
1
VR1
2
4
3
R12
0
0603
IDC3X1
3X1
3
VIN
SW
EN
GND
5
1
CT1
100UF
C
D1
SCHOT_RECT
DO214AB
3A
R59
0
0603
2
IDC2X1
2X1
DNP
R18
2.15K
0603
2
3.3V_EI
3.3V
1
C10
1000PF
805
FB
C71
10UF
805
P13
Q3
SI2343DS
SOT23D
LM3475MF
SOT23-5
UNREG_IN
1
L2
10UH
IND005
2
3
R11
1.05K
0603
3
2
IDC3X1
3X1
1
C73
DNP
0603
2
VR3
R16
0
0603
4
VIN
SW
5
3
EN
2
GND
1
D3
SCHOT_RECT
DO214AB
3A
CT3
100UF
C
1
R58
0
0603
R17
31.6K
0603
C74
1000PF
805
FB
LM3475MF
SOT23-5
1.2V
3
3
Q2
SI2343DS
SOT23D
C9
10UF
805
L1
10UH
IND005
C72
DNP
0603
P43
1
R19
10K
0603
3
2
1
2
2
VR2
4
R15
0
0603
3
VIN
SW
EN
GND
5
1
D2
SCHOT_RECT
DO214AB
3A
CT2
100UF
C
R20
200K
0603
IDC2X1
2X1
DNP
R13
4.99K
0603
2
1
C6
3.9NF
805
FB
LM3475MF
SOT23-5
C8
10UF
805
C7
390PF
0603
R14
10K
0603
DNP = Do Not Populate
ANALOG
DEVICES
4
Title
Size
A
B
C
Nashua, NH 03063
4
PH: 1-800-ANALOGD
BLACKFIN FPGA EZ-EXTENDER
POWER
Board No.
C
Date
20 Cotton Road
Rev
A0199-2005
1.0
Sheet
9-27-2005_11:24
D
11
of
12
A
B
C
D
1
1
TP79
TP106
TP103
P22
1
2
TP77
P26
TP93
1
2
TP104
P30
1
2
805
805
805
P23
1
P27
P31
2
TP107
TP96
1
2
TP95
TP20
1
TP115
P34
1
TP69
2
TP10
P35
1
TP88
805
805
805
P24
1
P28
P32
P36
1
2
TP105
TP98
1
2
P25
1
TP97
TP42
1
805
2
TP102
1
805
2
805
2
TP31
TP90
805
P29
TP99
TP100
TP63
TP78
2
TP87
2
TP52
P37
1
TP91
805
P40
TP111
2
TP89
TP113
TP112
805
P33
1
2
805
805
805
TP101
TP94
2
1
2
3
4
5
6
TP114
TP40
TP116
TP38
TP117
TP39
SOT23-6
PRT_NUM=DNE
TP92
P41
1
2
3
4
5
6
TP37
TP36
TP35
SOT23-6
805
2
2
TP82
TP44
TP83
TP85
TP84
TP74
TP72
TP73
TP70
TP71
TP46
P18
TP68
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P19
1
TP19
TP67
TP17
TP66
TP18
TP65
TP21
TP64
TP23
TP62
TP22
TP61
TP25
TP60
TP24
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TP26
TP45
TP27
TP48
TP28
TP47
TP29
TP50
TP30
TP49
TP32
TP41
TP33
TP43
TP34
P20
1
3
2
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TP54
TP119
TP55
TP14
TP86
TP12
TP56
TP13
TP57
TP9
TP58
TP11
TP59
TP7
TP81
TP8
TP53
TP16
TP51
TP15
SOIC20
P21
1
TP4
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TP125
TP118
TP124
TP123
TP122
TP121
TP120
TP5
TP6
SOIC20
SOIC16
SOIC16
3
3
TP76
TP80
TP75
P38
1
2
3
SOT23D
TP109
TP108
TP110
P39
1
2
3
SOT23D
DNP = Do Not Populate
ANALOG
DEVICES
4
Title
Size
A
B
C
Nashua, NH 03063
4
PH: 1-800-ANALOGD
BLACKFIN FPGA EZ-EXTENDER
PROTO AREA
Board No.
C
Date
20 Cotton Road
Rev
A0199-2005
1.0
Sheet
9-14-2005_12:04
D
12
of
12
I
INDEX
Numerics
connectors
map of locations, 2-18
2.5V header (P42), 2-17
J1-3 (expansion), 2-19
P1-3 (expansion), 2-19
A
P14 (IDC), 2-19
P15 (JTAG header), 2-4
ADSP-BF533/37/61 EZ-KIT Lite interface, 2-1
P16-17 (IDC), 2-19
ADSP-BF533/37/61 processors, boot mode
P4 (high-speed), 2-20
settings, 2-14
P5 (IDC), 2-20
architecture, of this EZ-Extender, 2-2
P6 (JTAG), 2-7
asynchronous static random access memory
P7 (IDC), 2-20
(SRAM), x
P8 (IDC), 2-19
auxiliary oscillator, x
customer support, xiii
B
bill of materials, A-1
block diagram, of this EZ-Extender, 2-2
boot jumper, See JP4
D
done LED (LED10), 2-17
E
C
configuration jumpers, See JP2, JP3
expansion interface
connectors (P1-3, J1-3), 2-19
of ADSP-BF533/37/61 EZ-KIT Lites, ix,
1-3
external power supply, 1-3, 2-8
F
Field-Programmable Gate Array, See FPGA
Blackfin FPGA EZ-Extender Manual
I-1
INDEX
FPGA
documentation, 1-2
input jumpers (JP5), 2-14
software/firmware, 1-2
Xilinx Spartan package, x, 1-3
FPGA pins
AB10 (LED3), 2-17
AB11 (JP5.8), 2-15
AB8 (LED7), 2-17
AB9 (LED5), 2-17
C11 (PB1/SW3), 2-15
H5 (PB2/SW3), 2-16
M2-0 (JP4), 2-14
U10 (JP5.6), 2-15
U11 (LED1), 2-17
V10 (LED8), 2-17
W11 (LED2), 2-17
W9 (LED6), 2-17
Y10 (LED4), 2-17
Y3-2 (JP5.2-5.4), 2-15
FPGA programming
block diagram, 2-3
via ADSP-BF533/37/6 processors, 2-6
via JTAG header, 2-4
via serial ROM, 2-5
G
J
JTAG
cable, 1-4, 2-7
header (P6), 1-5, 2-4, 2-7, 2-14
jumpers
map of locations, 2-11
JP1 (boot jumper), 2-5, 2-12
JP2 (confug done), 2-12
JP3 (config program), 2-13
JP4.1-4.6 (boot mode select), 2-5, 2-6, 2-14
JP5.2-5.6 (FPGA input), 2-14
L
LEDs
map of locations, 2-15
LED10 (FPGA done pin), 2-4, 2-5, 2-17
LED1-8 (status), 2-17
LED9 (power), 2-17
M
M2-0 (JP4) pins, 2-5
master serial boot mode, 2-6
MCS-86 Hexadecimal Object (.mcs) file
format, 2-6
N
GCLK1 (global clock 1) pin, 1-4
notation conventions, xvi
GCLK6 (global clock 6) pin, 1-4
general-purpose input push buttons, 2-15, 2-16
O
H
oscillator, x, 1-4
high-speed connector (P4), 2-20
P
I
IDC connectors, x, 2-19, 2-20
installation, of this EZ-Extender, 1-1
I-2
P12 (power in) header, 2-9
P13 (3.3V header), 2-9
P42 (2.5V header), 2-10
P43 (1.2V header), 2-10
PB1 push button (SW3), 2-15
Blackfin FPGA EZ-Extender Manual
INDEX
PB2 push button (SW4), 2-16
PF14 flag pin (ADSP-BF537 EZ-KIT Lite),
2-12
PF3 flag pin (ADSP-BF533/61 EZ-KIT Lite),
2-12
power
1.2V header (P43), 2-10
2.5V header (P42), 2-10
3.3V header (P13), 2-9
in header (P12), 2-9
LED (LED9), 2-17
limitations, 2-8
supplies, 1-3, 2-8
printed circuit board (PCB), 1-2
product overview, ix
program push button (SW1), 2-4, 2-15
push buttons
See also SWx
map of locations, 2-15
SRAM memory banks, 1-4
status reporting, 1-4, 2-17
SW1 (program) push button, 2-4, 2-15
SW3 (PB1) push button, 2-15
SW4 (PB2) push button, 2-16
switching regulators, 2-8
T
TCK signal, 2-7
TDI signal, 2-7
TDO signal, 2-7
TMS signal, 2-7
V
VisualDSP++
flash programming utility, 1-4, 2-6
FPGA documentation, 2-6
VR1-3 regulators, 2-8
S
X
serial ROM, 1-5
boot jumper (JP1), 2-12, 2-14
programming via JTAG Header, 2-7
setup, of this EZ-Extender, 1-1
slave serial mode, 2-6
Xilinx
JTAG cable/software, 1-4, 2-4, 2-7
JTAG header, 2-12
serial ROM, 1-5
Blackfin FPGA EZ-Extender Manual
I-3
INDEX
I-4
Blackfin FPGA EZ-Extender Manual
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