ADSP-BF537 EZ-KIT Lite Evaluation System Manual (Rev. 1.0)

ADSP-BF537 EZ-KIT Lite®
Evaluation System Manual
Revision 1.0, January 2005
Part Number
82-000865-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106
a
Copyright Information
© 2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.
Printed in the USA.
Limited Warranty
The EZ-KIT Lite evaluation system is warranted against defects in materials and workmanship for a period of one year from the date of purchase
from Analog Devices or from an authorized dealer.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices logo, VisualDSP++, the VisualDSP++ logo, Blackfin,
the CROSSCORE logo, and EZ-KIT Lite are registered trademarks of
Analog Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.
Regulatory Compliance
The ADSP-BF537 EZ-KIT Lite evaluation system has been certified to
comply with the essential requirements of the European EMC directive
89/336/EEC (inclusive 93/68/EEC) and, therefore, carries the “CE”
mark.
The ADSP-BF537 EZ-KIT Lite evaluation system had been appended to
Analog Devices Development Tools Technical Construction File referenced “DSPTOOLS1” dated December 21, 1997 and was awarded CE
Certification by an appointed European Competent Body and is on file.
The EZ-KIT Lite evaluation system contains ESD
(electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human
body and equipment and can discharge without
detection. Permanent damage may occur on devices
subjected to high-energy discharges. Proper ESD
precautions are recommended to avoid performance
degradation or loss of functionality. Store unused
EZ-KIT Lite boards in the protective shipping
package.
CONTENTS
PREFACE
Purpose of This Manual .................................................................. xv
Intended Audience ......................................................................... xvi
Manual Contents ........................................................................... xvi
What’s New in This Manual .......................................................... xvii
Technical or Customer Support ..................................................... xvii
Supported Processors .................................................................... xviii
Product Information .................................................................... xviii
MyAnalog.com ....................................................................... xviii
Processor Product Information .................................................. xix
Related Documents .................................................................. xix
Online Technical Documentation ............................................. xxi
Accessing Documentation From VisualDSP++ ..................... xxii
Accessing Documentation From Windows ........................... xxii
Accessing Documentation From Web .................................. xxii
Printed Manuals .................................................................... xxiii
VisualDSP++ Documentation Set ...................................... xxiii
Hardware Tools Manuals ................................................... xxiii
Processor Manuals ............................................................. xxiii
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
v
CONTENTS
Data Sheets ....................................................................... xxiv
Notation Conventions .................................................................. xxv
USING EZ-KIT LITE
Package Contents ......................................................................... 1-2
Default Configuration .................................................................. 1-3
Installation and Session Startup ..................................................... 1-5
Evaluation License Restrictions ..................................................... 1-6
Memory Map ............................................................................... 1-6
SDRAM Interface ......................................................................... 1-8
Flash Memory .............................................................................. 1-9
CAN Interface ............................................................................ 1-10
Ethernet Interface ....................................................................... 1-11
ELVIS Interface .......................................................................... 1-11
Audio Interface ........................................................................... 1-12
LEDs and Push Buttons .............................................................. 1-13
Example Programs ...................................................................... 1-13
Background Telemetry Channel .................................................. 1-14
VisualDSP++ Interface ................................................................ 1-14
Trace Window ...................................................................... 1-14
Enabling Trace Buffer ....................................................... 1-15
Reading Trace Buffer Data ................................................ 1-15
Target Options ...................................................................... 1-16
Reset Options ................................................................... 1-16
On Emulator Exit ............................................................. 1-17
vi
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
CONTENTS
Other Options .................................................................. 1-17
Restricted Software Breakpoints ............................................. 1-18
EZ-KIT LITE HARDWARE REFERENCE
System Architecture ...................................................................... 2-2
External Bus Interface Unit ...................................................... 2-3
SPORT0 Audio Interface ......................................................... 2-3
SPI Interface ........................................................................... 2-4
Programmable Flags (PFs) ........................................................ 2-4
UART Port .............................................................................. 2-7
Expansion Interface ................................................................. 2-7
JTAG Emulation Port .............................................................. 2-8
Jumper and Switch Settings ........................................................... 2-9
CAN Enable Switch (SW2) ...................................................... 2-9
Ethernet Mode Select Switch (SW3) ...................................... 2-10
UART Enable Switch (SW4) .................................................. 2-10
Push Button Enable Switch (SW5) ......................................... 2-11
Flash Enable Switch (SW6) .................................................... 2-11
Audio Enable Switch (SW7) .................................................. 2-12
Boot Mode Select Switch (SW16) .......................................... 2-13
3V Power Selection Jumper (JP3) ........................................... 2-13
Core Voltage Selection Jumper (JP4) ...................................... 2-13
Expansion Interface Voltage Selection Jumper (JP5) ............... 2-14
UART Loop Jumper (JP9) ..................................................... 2-15
ELVIS Oscilloscope Configuration Switch (SW1) ................... 2-15
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
vii
CONTENTS
ELVIS Function Generator Configuration Switch (SW8) ....... 2-16
ELVIS Processor Core Current Measurement Jumpers (JP1 and JP7)
2-16
ELVIS IO Current Measurement Jumper (JP2) ...................... 2-17
ELVIS Voltage Selection Jumper (JP6) ................................... 2-17
ELVIS Select Jumper (JP8) .................................................... 2-18
LEDs and Push Buttons .............................................................. 2-19
Reset Push Button (SW9) ...................................................... 2-19
Programmable Flag Push Buttons (SW13–10) ........................ 2-20
Power LED (LED7) .............................................................. 2-20
Reset LEDs (LED8 and LED9) ............................................. 2-20
User LEDs (LED1–6) ........................................................... 2-21
USB Monitor LED (LED10) ................................................. 2-21
Connectors ................................................................................. 2-22
Audio Connectors (J9 and J10) ............................................. 2-23
CAN Connectors (J5 and J11) .............................................. 2-23
Ethernet Connector (J4) ....................................................... 2-23
RS232 Connector (J6) .......................................................... 2-24
Power Connector (J7) ........................................................... 2-24
Expansion Interface Connectors (J1–3) .................................. 2-25
JTAG Connector (P4) ........................................................... 2-25
SPORT0 Connector (P6) ...................................................... 2-26
SPORT1 Connector (P7) ...................................................... 2-26
PPI Connector (P8) .............................................................. 2-26
SPI Connector (P9) ............................................................... 2-27
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ADSP-BF537 EZ-KIT Lite Evaluation System Manual
CONTENTS
Two-Wire Interface Connector (P10) ..................................... 2-27
TIMERS Connector (P11) .................................................... 2-27
UART1 Connector (P12) ...................................................... 2-28
BILL OF MATERIALS
INDEX
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
ix
CONTENTS
x
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
PREFACE
Thank you for purchasing the ADSP-BF537 EZ-KIT Lite®, Analog
Devices, Inc. evaluation system for Blackfin® processors.
The Blackfin processor family embodies a new type of embedded processor designed specifically to meet the computational demands and power
constraints of today’s embedded audio, video, and communications applications. They deliver breakthrough signal-processing performance and
power efficiency within a reduced instruction set computing (RISC) programming model.
Blackfin processors support a media instruction set computing (MISC)
architecture This architecture is the natural merging of RISC, media functions, and digital signal processing (DSP) characteristics. Blackfin
processors deliver signal-processing performance in a microprocessor-like
environment.
Based on the Micro Signal Architecture (MSA), Blackfin processors combine a 32-bit RISC instruction set, dual 16-bit multiply accumulate
(MAC) DSP functionality, and 8-bit video processing performance that
had previously been the exclusive domain of very-long instruction word
(VLIW) media processors.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
xi
The evaluation board is designed to be used in conjunction with the VisualDSP++® development environment to test the capabilities of the
ADSP-BF537 Blackfin processors. The VisualDSP++ development environment gives you the ability to perform advanced application code
development and debug, such as:
• Create, compile, assemble, and link application programs written
in C++, C and ADSP-BF537 assembly
• Load, run, step, halt, and set breakpoints in application program
• Read and write data and program memory
• Read and write core and peripheral registers
• Plot memory
Access to the ADSP-BF537 processor from a personal computer (PC) is
achieved through a USB port or an optional JTAG emulator. The USB
interface gives unrestricted access to the ADSP-BF537 processor and the
evaluation board peripherals. Analog Devices JTAG emulators offer faster
communication between the host PC and target hardware. Analog Devices
carries a wide range of in-circuit emulation products. To learn more about
Analog Devices emulators and processor development tools, go to
http://www.analog.com/dsp/tools/.
ADSP-BF537 EZ-KIT Lite provides example programs to demonstrate
the capabilities of the evaluation board.
ADSP-BF537 EZ-KIT Lite installation is part of the VisuL The
alDSP++ installation. The EZ-KIT Lite is a licensed product that
offers an unrestricted evaluation license for the first 90 days. Once
the initial unrestricted 90-day evaluation license expires:
• VisualDSP++ allows a connection to the ADSP-BF537
EZ-KIT Lite via the USB Debug Agent interface only. Connections to simulators and emulation products are no longer
allowed.
xii
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
Preface
• The linker restricts a users program to 20 KB of internal
memory for code space with no restrictions for data space.
The board features:
• Analog Devices ADSP-BF537 processor
D
D
D
D
Core performance to 600 MHz
External bus performance to 133 MHz
182-pin Mini-BGA package
25 MHz crystal CLKIN oscillator
• Synchronous Dynamic Random Access Memory (SDRAM)
D
MT48LC32M8 - 64 MB (8M x8-bits x 4 banks) x 2 chips
• Flash Memory
D
4MB (2M x 16-bits)
• Analog Audio Interface
D
D
D
D
AD1871 96 kHz analog-to-digital codec (ADC)
AD1854 96 kHz digital-to-audio codec (DAC)
1 input stereo jack
1 output stereo jack
• Ethernet Interface
D
10-BaseT (10 Mbits/sec) and 100-BaseT (100 Mbits/sec)
Ethernet Medium Access Controller (MAC)
D
SMSC LAN83C185 device
• Controller Area Network (CAN) Interface
D
Philips TJA1041 high-speed CAN transceiver
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
xiii
• National Instruments Educational Laboratory Virtual Instrumentation Suite Interface (ELVIS)
D
LabVIEW™-based virtual instruments
D
Multifunction data acquisition device
D
Bench-top workstation and prototype board
• Universal Asynchronous Receiver/Transmitter (UART)
D
D
ADM3202 RS-232 line driver/receiver
DB9 female connector
• LEDs
D
10 LEDs: 1 power (green), 1 board reset (red), 1 USB (red),
6 general purpose (amber), and 1 USB monitor (amber)
• Push Buttons
D
5 push buttons: 1 reset, 4 programmable flags with
debounce logic
• Expansion Interface
D
All processor signals
• Other Features
D
JTAG ICE 14-pin header
The EZ-KIT Lite board has flash memory with a total of 4 MB. The flash
memory can be used to store user-specific boot code, allowing the board
to run as a stand-alone unit. For more information, see “Flash Memory”
on page 1-9. The board also has 64 MB of SDRAM, which can be used by
the user at runtime.
xiv
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
Preface
interfaces with the audio circuit, facilitating development of audio
signal processing applications. SPORT0 also connects to an off-board connector for communication with other serial devices. For information
about SPORT0, see “SPORT0 Audio Interface” on page 2-3.
SPORT0
The UART of the processor connects to an RS232 line driver and a DB9
female connector, providing an interface to a PC or other serial device.
Additionally, the EZ-KIT Lite board provides access to all of the processor’s peripheral ports. Access is provided in the form of a three-connector
expansion interface. For information about the expansion interface, see
“Expansion Interface” on page 2-7.
Purpose of This Manual
The ADSP-BF537 EZ-KIT Lite Evaluation System Manual provides
instructions for installing the product hardware (board). The text
describes the operation and configuration of the board components and
provides guidelines for running your own code on the ADSP-BF537
EZ-KIT Lite. Finally, a schematic and a bill of materials are provided as a
reference for future designs.
EZ-KIT Lite users should use this manual in conjunction with the Getting
Started with ADSP-BF537 EZ-KIT Lite, which familiarizes users with the
hardware capabilities of the evaluation system and demonstrates how to
access these capabilities in the VisualDSP++ environment.
The product software installation is detailed in the VisualDSP++ Installation Quick Reference Card.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
xv
Intended Audience
Intended Audience
The primary audience for this manual is a programmer who is familiar
with Analog Devices processors. This manual assumes that the audience
has a working knowledge of the appropriate processor architecture and
instruction set. Programmers who are unfamiliar with Analog Devices
processors can use this manual but should supplement it with other texts
(such as the ADSP-BF537 Blackfin Processor Hardware Reference and
Blackfin Processor Instruction Set Reference) that describe your target
architecture.
Programmers who are unfamiliar with VisualDSP++ should refer to the
VisualDSP++ online Help and user’s or getting started guides. For the
locations of these documents, see “Related Documents”.
Manual Contents
The manual consists of:
• Chapter 1, “Using EZ-KIT Lite” on page 1-1
Describes the EZ-KIT Lite functionality from a programmer’s perspective and provides an easy-to-access memory map.
• Chapter 2, “EZ-KIT Lite Hardware Reference” on page 2-1
Provides information on the EZ-KIT Lite hardware components.
• Appendix A, “Bill Of Materials” on page A-1
Provides a list of components used to manufacture the EZ-KIT
Lite board.
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ADSP-BF537 EZ-KIT Lite Evaluation System Manual
Preface
• Appendix B, “Schematics” on page B-1
Provides the resources to allow EZ-KIT Lite board-level debugging
or to use as a reference design.
appendix is not part of the online Help. The online Help
L This
viewers should go to the PDF version of the ADSP-BF537 EZ-KIT
Lite Evaluation System Manual located in the Docs\EZ-KIT Lite
folder on the installation CD to see the schematics. Alternatively, the schematics can be found on the Analog Devices Web
site, www.analog.com/processors.
Manuals
What’s New in This Manual
This is the first edition of the ADSP-BF537 EZ-KIT Lite Evaluation System Manual.
Technical or Customer Support
You can reach DSP Tools Support in the following ways.
• Visit the Embedded Processing and DSP products Web site at
http://www.analog.com/processors/technicalSupport
• E-mail tools questions to
[email protected]
• E-mail processor questions to
[email protected]
• Phone questions to 1-800-ANALOGD
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
xvii
Supported Processors
• Contact your Analog Devices, Inc. local sales office or authorized
distributor
• Send questions by mail to:
Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA
Supported Processors
This evaluation system supports the Analog Devices ADSP-BF537 Blackfin embedded processors.
Product Information
You can obtain product information from the Analog Devices Web site,
from the product CD-ROM, or from the printed publications (manuals).
Analog Devices is online at www.analog.com. Our Web site provides information about a broad range of products—analog integrated circuits,
amplifiers, converters, and digital signal processors.
MyAnalog.com
MyAnalog.com is a free feature of the Analog Devices Web site that allows
customization of a Web page to display only the latest information on
products you are interested in. You can also choose to receive weekly
e-mail notifications containing updates to the Web pages that meet your
interests. MyAnalog.com provides access to books, application notes, data
sheets, code examples, and more.
xviii
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
Preface
Registration:
Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com.
Registration takes about five minutes and serves as means for you to select
the information you want to receive.
If you are already a registered user, just log on. Your user name is your
e-mail address.
Processor Product Information
For information on embedded processors and DSPs, visit our Web site at
www.analog.com/processors, which provides access to technical publications, data sheets, application notes, product overviews, and product
announcements.
You may also obtain additional information about Analog Devices and its
products in any of the following ways.
• E-mail questions or requests for information to
[email protected]
• Fax questions or requests for information to
1-781-461-3010 (North America)
+49 (89) 76 903-557 (Europe)
• Access the FTP Web site at
ftp ftp.analog.com or ftp
137.71.23.21
ftp://ftp.analog.com
Related Documents
For information on product related development software, see the following publications.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
xix
Product Information
Table 1. Related Processor Publications
Title
Description
ADSP-BF536/ADSP-BF537 Embedded Processor
Data Sheet
General functional description, pinout, and
timing.
ADSP-BF537 Blackfin Processor Hardware Reference
Description of internal processor architecture and all register functions.
Blackfin Processor Programming Reference
Description of all allowed processor assembly instructions.
Table 2. Related VisualDSP++ Publications
xx
Title
Description
ADSP-BF537 EZ-KIT Lite Evaluation System
Manual
Description of the hardware capabilities of
the evaluation system; description of how to
access these capabilities in the VisualDSP++
environment.
VisualDSP++ User’s Guide
Description of VisualDSP++ features and
usage.
VisualDSP++ Assembler and Preprocessor Manuals
Description of the assembler function and
commands.
VisualDSP++ C/C++ Complier and Library Manual for Blackfin Processors
Description of the complier function and
commands for Blackfin processors.
VisualDSP++ Linker and Utilities Manual
Description of the linker function and commands.
VisualDSP++ Loader Manual
Description of the loader/splitter function
and commands.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
Preface
you plan to use the EZ-KIT Lite board in conjunction with a
L IfJTAG
emulator, also refer to the documentation that accompanies
the emulator.
All documentation is available online. Most documentation is available in
printed form.
Visit the Technical Library Web site to access all processor and tools manuals and data sheets:
http://www.analog.com/processors/resources/technicalLibrary
Online Technical Documentation
Online documentation comprises the VisualDSP++ Help system, software
tools manuals, hardware tools manuals, processor manuals, the Dinkum
Abridged C++ library, and Flexible License Manager (FlexLM) network
license manager software documentation. You can easily search across the
entire VisualDSP++ documentation set for any topic of interest. For easy
printing, supplementary .PDF files of most manuals are provided in the
Docs folder on the VisualDSP++ installation CD.
Each documentation file type is described as follows.
File
Description
.CHM
Help system files and manuals in Help format
.HTM or
.HTML
Dinkum Abridged C++ library and FlexLM network license manager software documentation. Viewing and printing the .HTML files requires a browser, such as
Internet Explorer 4.0 (or higher).
.PDF
VisualDSP++ and processor manuals in Portable Documentation Format (PDF).
Viewing and printing the .PDF files requires a PDF reader, such as Adobe Acrobat
Reader (4.0 or higher).
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
xxi
Product Information
If documentation is not installed on your system as part of the software
installation, you can add it from the VisualDSP++ CD at any time by running the Tools installation. Access the online documentation from the
VisualDSP++ environment, Windows® Explorer, or the Analog Devices
Web site.
Accessing Documentation From VisualDSP++
To view VisualDSP++ Help, click on the Help menu item or go to the
Windows task bar and navigate to the VisualDSP++ documentation via
the Start menu.
To view ADSP-BF537 EZ-KIT Lite Help, which is part of the VisualDSP++ Help system, use the Contents or Search tab of the Help
window.
Accessing Documentation From Windows
In addition to any shortcuts you may have constructed, there are many
ways to open VisualDSP++ online Help or the supplementary documentation from Windows.
Help system files (.CHM) are located in the Help folder, and .PDF files are
located in the Docs folder of your VisualDSP++ installation CD-ROM.
The Docs folder also contains the Dinkum Abridged C++ library and the
FlexLM network license manager software documentation.
Your software installation kit includes online Help as part of the Windows® interface. These help files provide information about VisualDSP++
and the ADSP-BF537 EZ-KIT Lite evaluation system.
Accessing Documentation From Web
Download manuals at the following Web site:
http://www.analog.com/processors/resources/technicalLibrary/manuals.
xxii
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
Preface
Select a processor family and book title. Download archive (.ZIP) files, one
for each manual. Use any archive management software, such as WinZip,
to decompress downloaded files.
Printed Manuals
For general questions regarding literature ordering, call the Literature
Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts.
VisualDSP++ Documentation Set
To purchase VisualDSP++ manuals, call 1-603-883-2430. The manuals
may be purchased only as a kit.
If you do not have an account with Analog Devices, you are referred to
Analog Devices distributors. For information on our distributors, log onto
http://www.analog.com/salesdir/continent.asp.
Hardware Tools Manuals
To purchase EZ-KIT Lite and In-Circuit Emulator (ICE) manuals, call
1-603-883-2430. The manuals may be ordered by title or by product
number located on the back cover of each manual.
Processor Manuals
Hardware reference and instruction set reference manuals may be ordered
through the Literature Center at 1-800-ANALOGD (1-800-262-5643),
or downloaded from the Analog Devices Web site. Manuals may be
ordered by title or by product number located on the back cover of each
manual.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
xxiii
Product Information
Data Sheets
All data sheets (preliminary and production) may be downloaded from the
Analog Devices Web site. Only production (final) data sheets (Rev. 0, A,
B, C, and so on) can be obtained from the Literature Center at
1-800-ANALOGD (1-800-262-5643); they also can be downloaded from
the Web site.
To have a data sheet faxed to you, call the Analog Devices Faxback System
at 1-800-446-6212. Follow the prompts and a list of data sheet code
numbers will be faxed to you. If the data sheet you want is not listed,
check for it on the Web site.
xxiv
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
Preface
Notation Conventions
Text conventions used in this manual are identified and described as
follows.
Example
Description
Close command
(File menu)
Titles in reference sections indicate the location of an item within the
VisualDSP++ environment’s menu system (for example, the Close command appears on the File menu).
{this | that}
Alternative required items in syntax descriptions appear within curly
brackets and separated by vertical bars; read the example as this or
that. One or the other is required.
[this | that]
Optional items in syntax descriptions appear within brackets and separated by vertical bars; read the example as an optional this or that.
[this,…]
Optional item lists in syntax descriptions appear within brackets delimited by commas and terminated with an ellipse; read the example as an
optional comma-separated list of this.
.SECTION
Commands, directives, keywords, and feature names are in text with
letter gothic font.
filename
Non-keyword placeholders appear in text with italic style format.
L
a
[
Note: For correct operation, ...
A Note provides supplementary information on a related topic. In the
online version of this book, the word Note appears instead of this
symbol.
Caution: Incorrect device operation may result if ...
Caution: Device damage may result if ...
A Caution identifies conditions or inappropriate usage of the product
that could lead to undesirable results or product damage. In the online
version of this book, the word Caution appears instead of this symbol.
Warning: Injury to device users may result if ...
A Warning identifies conditions or inappropriate usage of the product
that could lead to conditions that are potentially hazardous for the
devices users. In the online version of this book, the word Warning
appears instead of this symbol.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
xxv
Notation Conventions
conventions, which apply only to specific chapters, may
L Additional
appear throughout this document.
xxvi
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
1 USING EZ-KIT LITE
This chapter provides specific information to assist you with development
of programs for the ADSP-BF537 EZ-KIT Lite evaluation system.
• “Package Contents” on page 1-2
Lists the items contained in your ADSP-BF537 EZ-KIT Lite
package.
• “Default Configuration” on page 1-3
Shows the default configuration of the ADSP-BF537 EZ-KIT Lite.
• “Installation and Session Startup” on page 1-5
Instructs how to start a new or open an existing ADSP-BF537
EZ-KIT Lite session using VisualDSP++.
• “Evaluation License Restrictions” on page 1-6
Describes the restrictions of the VisualDSP++ demo license
shipped with the EZ-KIT Lite.
• “Memory Map” on page 1-6
Defines the ADSP-BF537 EZ-KIT Lite board’s memory map.
• “SDRAM Interface” on page 1-8·
Defines the register values to configure the on-board SDRAM.
• “Flash Memory” on page 1-9
Describes the on-board flash memory.
• “CAN Interface” on page 1-10
Describes the on-board Controller Area Network interface.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
1-1
Package Contents
• “Ethernet Interface” on page 1-11
Describes the on-board Fast Ethernet Medium Access Controller
interface.
• “ELVIS Interface” on page 1-11
Describes the on-board National Instruments Educational Laboratory Virtual Instrumentation Suite interface.
• “Audio Interface” on page 1-12
Describes the on-board audio circuit.
• “LEDs and Push Buttons” on page 1-13
Describes the board’s general-purpose IO pins and buttons.
• “Background Telemetry Channel” on page 1-14
Highlights the advantages of the Background Telemetry Channel
feature of VisualDSP++.
• “VisualDSP++ Interface” on page 1-14
Describes the trace, target options, and breakpoint restriction facilities of the EZ-KIT Lite system available through VisualDSP++.
For more detailed information about programming the ADSP-BF537
Blackfin processor, see the documents referred to as “Related
Documents”.
Package Contents
Your ADSP-BF537 EZ-KIT Lite evaluation system package contains the
following items.
• ADSP-BF537 EZ-KIT Lite board
• VisualDSP++ Installation Quick Reference Card
1-2
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
Using EZ-KIT Lite
• CD containing:
D
VisualDSP++ software
D
ADSP-BF537 EZ-KIT Lite debug software
D
USB driver files
D
Example programs
D
ADSP-BF537 EZ-KIT Lite Evaluation System Manual (this
document)
• Universal 7V DC power supply
• 7-foot Ethernet crossover cable
• 7-foot Ethernet Patch cable
• 6-foot 3.5 mm male-to-male audio cable
• 3.5 mm headphones
• 10-foot USB 2.0 cable
• Registration card (please fill out and return)
If any item is missing, contact the vendor where you purchased your
EZ-KIT Lite or contact Analog Devices, Inc.
Default Configuration
The ADSP-BF537 EZ-KIT Lite board is designed to run outside your personal computer as a stand-alone unit. You do not have to open your
computer case.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
1-3
Default Configuration
The EZ-KIT Lite evaluation system contains ESD
(electrostatic discharge) sensitive devices. Electrostatic
charges readily accumulate on the human body and
equipment and can discharge without detection. Permanent damage may occur on devices subjected to
high-energy discharges. Proper ESD precautions are
recommended to avoid performance degradation or
loss of functionality. Store unused EZ-KIT Lite boards
in the protective shipping package.
When removing the EZ-KIT Lite board from the package, handle the
board carefully to avoid the discharge of static electricity, which may damage some components. Figure 1-1 shows the default jumper settings,
switches, connector locations, and LEDs used in installation. Confirm
that your board is set up in the default configuration before using the
board.
Figure 1-1. EZ-KIT Lite Hardware Setup
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ADSP-BF537 EZ-KIT Lite Evaluation System Manual
Using EZ-KIT Lite
Installation and Session Startup
correct operation, install the software and hardware in the
L For
order presented in the VisualDSP++ Installation Quick Reference
Card.
1. Verify that the yellow USB monitor LED (LED10, located near the
USB connector) is lit. This signifies that the board is communicating properly with the host PC and is ready to run VisualDSP++.
2. From the Start menu, navigate to the VisualDSP++ environment
via the Programs menu.
If you are running VisualDSP++ for the first time, the New Session
dialog box appears on the screen (skip the rest of the procedure and
go to step 3).
If you have run VisualDSP++ previously, the last opened session
appears on the screen.
To switch to another session, via the Session List dialog box, hold
down the Ctrl key while starting VisualDSP++ (go to step 5).
3. In Debug target, select Blackfin Emulators/EZ-KIT Lites.
In Platform, select the appropriate EZ-KIT Lite via a debug agent
(ADSP-BF537 EZ-KIT Lite via Debug Agent).
In Session name, type a new name or accept the default.
4. Click OK to return to the Session List.
5. Highlight the session and click Activate.
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1-5
Evaluation License Restrictions
Evaluation License Restrictions
The ADSP-BF537 EZ-KIT Lite installation is part of the VisualDSP++
installation. The EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for the first 90 days. Once the initial
unrestricted 90-day evaluation license expires:
• VisualDSP++ allows a connection to the ADSP-BF537 EZ-KIT
Lite via the USB Debug Agent interface only. Connections to simulators and emulation products are no longer allowed.
• The linker restricts a users program to 20 KB of internal memory
for code space with no restrictions for data space.
EZ-KIT Lite hardware must be connected and powered up to
L The
use VisualDSP++ with a valid evaluation or permanent license.
Refer to the VisualDSP++ Installation Quick Reference Card for details.
Memory Map
The ADSP-BF537 processor has internal SRAM that can be used for
instruction or data storage. The configuration of internal SRAM is
detailed in the ADSP-BF537 Blackfin Processor Hardware Reference.
The ADSP-BF537 EZ-KIT Lite board includes two types of external
memory, SDRAM and flash.
The size of the SDRAM is 64 Mbytes (32M x 16-bit). The processor’s
memory select pin, ~SMS0, is configured for the SDRAM.
The size of the flash memory is 4 Mbytes (2M x 16-bits). The processor’s
asynchronous memory select pins ~AMS3–0 are configured for the flash.
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Using EZ-KIT Lite
Table 1-1. EZ-KIT Lite Evaluation Board Memory Map
Start Address
External
Memory
End Address
Content
0x0000 0000
0x03FF FFFF
SDRAM Bank 0 (SDRAM). See “SDRAM Interface” on page 1-8.
0x2000 0000
0x200F FFFF
ASYNC Memory Bank 0. See “Flash Memory” on
page 1-9.
0x2010 0000
0x201F FFFF
ASYNC Memory Bank 1. See “Flash Memory” on
page 1-9.
0x2020 0000
0x202F FFFF
ASYNC Memory Bank 2. See “Flash Memory” on
page 1-9.
0x2030 0000
0x203F FFFF
ASYNK Memory Bank 3. See “Flash Memory” on
page 1-9.
0x203F 0000
All other locations
Internal
Memory
MAC Address
Not used
0xFF80 0000
0xFF80 3FFF
Data Bank A SRAM 16 KB
0xFF80 4000
0xFF80 7FFF
Data Bank A SRAM/CACHE 16 KB
0xFF90 0000
0xFF90 7FFF
Data Bank B SRAM 16 KB
0xFF90 4000
0xFF90 7FFF
Data Bank B SRAM/CACHE 16 KB
0xFFA0 0000
0xFFA0 7FFF
Instruction Bank A SRAM 32 KB
0xFFA1 0000
0xFFA1 3FFF
Instruction Bank B SRAM 16 KB
0xFFA0 8000
0xFFA0 BFFF
Instruction SRAM/CACHE 16 KB
0xFFB0 0000
0xFFB0 0FFF
Scratch Pad SRAM 4 KB
0xFFC0 0000
0xFFDF FFFF
System MMRs 2 MB
0xFFE0 0000
0xFFFF FFFF
Core MMRs 2 MB
All other locations
Reserved
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
1-7
SDRAM Interface
SDRAM Interface
The three SDRAM control registers must be initialized in order to use the
MT48LC32M8A2 32M x 16 bits (64 MB) SDRAM memory. When you
are in a VisualDSP++ session and connected to the EZ-KIT Lite board,
the SDRAM registers are configured automatically through the debugger
each time the processor is reset. The values in Table 1-2 are used whenever
Bank 0 is accessed through the debugger (for example, when viewing
memory windows or loading a program). The numbers were derived for
maximum flexibility and work for a system clock frequency between
54 MHz and 133 MHz.
Table 1-2. EZ-KIT Lite Session SDRAM Default Settings1
Register
Value
Function
EBIU_SDGCTL
0x0091998D
Calculated with SCLK = 133 MHz
16-bit data path
External buffering timing disabled
tWR = 2 SCLK cycles
tRCD = 3 SCLK cycles
tRP = 3 SCLK cycles
tRAS = 6 SCLK cycles
pre-fetch disabled
CAS latency = 3 SCLK cycles
SCLK1 disabled
EBIU_SDBCTL
0x00000025
Bank 0 enabled
Bank 0 size = 64 MB
Bank 0 column address width = 10 bits
EBIU_SDRRC
0x000003A0
Calculated with SCLK = 54 MHz
RDIV = 416 clock cycles
1
54 MHz <= SCLK <= 133 MHz.
The EBIU_SDGCTL register can only be re-written within the user code by
first placing the chip in self-refresh (see the ADSP-BF537 Blackfin Processor Hardware Reference). Clearing the appropriate checkbox on the Target
1-8
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
Using EZ-KIT Lite
Options dialog box, which is accessible through the Settings pull-down
menu, disables automatic and allows manual configuration. For more
information, see “Target Options” on page 1-16.
Automatic configuration of SDRAM is not optimized for any SCLK frequency. Table 1-3 shows the optimized configuration for the SDRAM
registers using a 120 MHz and 133 MHz SCLK. Only the EBIU_SDRRC
register needs to be modified in the user code to achieve maximum
performance.
Table 1-3. SDRAM Optimum Settings
Register
SCLK = 133 MHz
(CCLK = 400 MHz)
SCLK = 120 MHz
(CCLK = 600 MHz)
EBIU_SDGCTL
0x0091 998D
0x0091 998D
EBIU_SDBCTL
0x0000 0025
0x0000 0025
EBIU_SDRRC
0x0000 0408
0x0000 03A0
An example program is included in the EZ-KIT installation directory to
demonstrate how to set up the SDRAM interface.
Flash Memory
The flash interface of the ADSP-BF537 EZ-KIT Lite contains a 4 MB
(2M x 16-bits) ST Micro M29W320DB device. The size of the flash
memory is controlled by the flash address range switch, SW6 (see “Flash
Enable Switch (SW6)” on page 2-11). The default for the SW6 switch is all
positions ON, which allows the user to have access to the full 4 MB of the
flash memory. If any of the ~AMS signals need to be connected to the board
by plugging into the expansion interface, the signal can be disconnected
from the flash by turning the appropriate position of the SW6 switch to
OFF. Each ~AMS signal accounts for 1 MB of flash memory. The amount of
available flash memory decreases as ~AMS signals are being turned OFF.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
1-9
CAN Interface
The last sector in the flash memory (0x1F8000–0x1FFFFF) is reserved for
the Media Access Control (MAC) address. Each board has a unique MAC
address. The sector is protected and is not erased even when the entire
flash erase command is issued. The memory sector can be changed only by
changing the JP10 jumper from pins 1–2 to pins 2–3. Refer to the flash
memory data sheet for information on protected sectors.
Example code is provided in the EZ-KIT Lite installation directory to
demonstrate how to program the flash memory.
Table 1-4 shows a sample value for the asynchronous memory configuration register.
Table 1-4. Asynchronous Memory Control Register Setting Example
Register
Value
Function
EBIU_AMBCTL0
0x7BB07BB0
Timing control for Banks 1 and 0
CAN Interface
The Controller Area Network (CAN) interface contains a Philips
TJA1041 high-speed CAN transceiver. The PF14 programmable flag connects to the enable control input (EN). The PF15 programmable flag
connects to the standby control input (~STB). The PF13 programmable flag
connects to the error and power-on indication output (ERR). The PJ4 connects to the receive data output (RXD), and PJ5 connected to the transmit
data input (TXD).
The CAN interface can be disconnected from the processor by turning
positions 1 though 4 of the SW2 switch to OFF. When in the OFF position,
these signals can be used elsewhere on the board. See “CAN Enable Switch
(SW2)” on page 2-9 for more information.
The CAN interface contains two 4-position modular connectors.
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ADSP-BF537 EZ-KIT Lite Evaluation System Manual
Using EZ-KIT Lite
Example programs are included in the EZ-KIT installation directory to
demonstrate the CAN circuit operation.
Ethernet Interface
The ADSP-BF537 processor is able to directly connect to a network with
the help of an embedded Fast Ethernet Medium Access Controller
(MAC). The MAC supports both 10-BaseT (10 Mbits/sec) and
100-BaseT (100 Mbits/sec) operations. The 10/100 Ethernet MAC
peripheral of the ADSP-BF537 processor is fully compliant with the IEEE
802.3-2002 standard and provides programmable features designed to
minimize supervision, bus utilization, or message processing by the rest of
the processor system.
The Ethernet interface contains a SMSC LAN83C185 device. The
LAN83C185 is a low-power highly-integrated analog interface IC for
high-performance embedded Ethernet applications.
The Ethernet connector is a RJ45 connector with built-in magnetics and
LEDs.
802.3af Power-over-Ethernet (PoE) is supported when the EZ-KIT Lite
connects to a Blackfin USB-LAN EZ-Extender.
Example programs are included in the EZ-KIT installation directory to
demonstrate the Ethernet circuit operation.
ELVIS Interface
The ADSP-BF537 EZ-KIT Lite board contains the National Instruments
Educational Laboratory Virtual Instrumentation Suite (NI ELVIS) interface. The interface features the DC voltage and current measurement
modules, oscilloscope and bode analyzer modules, function generator,
arbitrary waveform generator, and digital IO.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
1-11
Audio Interface
The ELVIS interface is a LabVIEW-based design and prototype environment for university science and engineering laboratories. The ELVIS
interface consists of LabVIEW-based virtual instruments, a multifunction
data acquisition (DAQ) device, and a custom-designed bench-top workstation and prototype board. This combination provides a ready-to-use
suite of instruments found in most educational laboratories. Because the
interface is based on LabVIEW and provides complete data acquisition
and prototyping capabilities, the system is ideal for academic coursework
that range from lower-division classes to advanced project-based
curriculums.
For more information on ELVIS and example demonstration programs,
visit National Instruments Web site at www.ni.com.
Audio Interface
The audio circuit provides one channel of stereo input and one channel of
stereo output via 3.5 mm stereo jacks. The SPORT0 interface of the processor is linked with the stereo audio data input and output pins of the audio
circuit. The audio circuit consists of an AD1871 analog-to-digital converter (ADC) and an AD1854 digital-to-analog converter (DAC).
The processor is responsible for generating the frame sync and bit clocks
because the audio interface of the EZ-KIT Lite operates in slave mode.
The audio interface samples data at a 48 kHz sample rate. The serial data
interface operates in Two Wire Interface mode and connects to SPORT0 of
the processor.
The audio interface can be disconnected from SPORT0 by turning positions
1 and 5 of the SW7 switch OFF. When in the OFF position, the SPORT0 signals can be used on the SPORT0 connector (P6) or the expansion interface
(see “Audio Enable Switch (SW7)” on page 2-12 for more information).
Example programs are included in the EZ-KIT installation directory to
demonstrate the audio circuit operation.
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Using EZ-KIT Lite
LEDs and Push Buttons
The EZ-KIT Lite provides four push buttons and six LEDs for general-purpose IO.
The six LEDs, labeled LED1 through LED6, are accessed via the PF11–PF6
processor pins. For information on how to program the pins, refer to the
ADSP-BF537 Blackfin Processor Hardware Reference.
The four general-purpose push button are labeled SW10 through SW13. A
status of each individual button can be read through programmable flag
(PF) inputs, PF2 through PF5. A PF reads “1” when a corresponding switch
is being pressed-on. When the switch is released, the PF reads “0”. A connection between the push button and PF input is established through the
SW5 DIP switch. See “Push Button Enable Switch (SW5)” on page 2-11
for details.
An example program is included in the EZ-KIT installation directory to
demonstrate the functionality of the LEDs and push buttons.
Example Programs
Example programs are provided with the ADSP-BF537 EZ-KIT Lite to
demonstrate various capabilities of the evaluation board. These programs
are installed with the EZ-KIT Lite software and can be found in the
…\Blackfin\EZ-KITs\ADSP-BF537\Examples subdirectory of the VisualDSP++ installation directory. Please refer to the readme file provided
with each example for more information.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
1-13
Background Telemetry Channel
Background Telemetry Channel
The ADSP-BF537 USB debug agent supports the Background Telemetry
Channel (BTC), which facilitates data exchange between VisualDSP++
and the processor without interrupting processor execution.
The BTC allows the user to view a variable as it is updated or changed, all
while the processor continues to execute. For increased performance of the
BTC, including faster reading and writing, please check out our latest line
of processor emulators on the web at
www.analog.com. For more information about the Background Telemetry
Channel, see the VisualDSP++ User’s Guide or online Help.
VisualDSP++ Interface
This section provides information on the following parts of the VisualDSP++ graphical user interface:
• “Trace Window” on page 1-14
• “Target Options” on page 1-16
• “Restricted Software Breakpoints” on page 1-18
Trace Window
Choosing the Trace command from the View–>Debug Windows menu
opens the Trace window (Figure 1-2).
The trace buffer stores a history of the last 16 changes in program flow
taken by the program sequencer. View the history to recreate the program
sequencer’s most recent path.
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ADSP-BF537 EZ-KIT Lite Evaluation System Manual
Using EZ-KIT Lite
Figure 1-2. Trace Window
The trace buffer does not track changes in flow caused by zero-overhead
loops or while in the reset service routine.
use the trace buffer, ensure your program leaves the reset service
L Toroutine.
Enabling Trace Buffer
To view trace history in the Trace window, first, enable the trace buffer
(choose Enable Trace from the Tools–>Trace menu). On each halt, the
Trace window is updated with the changes that occurred since the last
halt. Reading the trace buffer destroys the trace buffer’s contents and discards the information previously stored before the last run.
Reading Trace Buffer Data
The first column between the square brackets (in blue) indicates the line
number in the Trace window.
The second column between square brackets, which comes in vertical
pairs, shows the trace number. For each discontinuity, the first (top position) is the source trace, and the second (bottom position) is the
destination trace. The third column in between square brackets shows the
addresses of the instructions. Each address is followed by the assembly
instruction.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
1-15
VisualDSP++ Interface
The trace grows upward. In Figure 1-2, trace 0 occurred before trace 1,
which occurred before trace 2, and so on.
Target Options
Choosing Target Options from the Settings menu opens the Target
Options dialog box (Figure 1-3). Use target options to control certain
aspects of the processor on the ADSP-BF537 EZ-KIT Lite evaluation
system.
Figure 1-3. Target Options Dialog Box
Reset Options
Reset options control how the processor behaves when a reset occurs. The
reset options are described in Table 1-5.
Table 1-5. Reset Options
Option
Description
Core reset
Resets the core when the debugger executes a reset.
System reset
Resets the peripherals when the debugger executes a reset.
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Using EZ-KIT Lite
On Emulator Exit
This target option controls processor behavior when VisualDSP++ relinquishes processor control (for example, when exiting VisualDSP++). The
option is described in Table 1-6.
Table 1-6. On Emulator Exit Target Options
Option
Description
On Emulator Exit Determines the state the processor is left in when the emulator relinquishes
control of the processor:
Reset DSP and Run causes the processor to reset and begin execution from
its reset vector location.
Run from current PC causes the processor to begin running from its current
location.
Stall the DSP resets the processor and then writes a JUMP 0 to the first location in internal memory so the processor is stuck in a tight loop after exiting.
Other Options
Table 1-7 describes other available target options.
Table 1-7. Miscellaneous Target Options
Option
Description
Verify all writes to target
memory
Validates all memory writes to the processor. After each write, a read
is performed and the values are checked for a matching condition.
Enable this option during initial program development to locate
and fix initial build problems (such as attempting to load data into
non-existent memory).
Clear this option to increase performance while loading executable
files, since VisualDSP++ does not perform the extra reads that are
required to verify each write.
Reset cycles counter on
run
Resets the cycle count registers to zero before a Run command is
issued. Select this option to count the number of cycles executed
between breakpoints in a program.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
1-17
VisualDSP++ Interface
Table 1-7. Miscellaneous Target Options (Cont’d)
Option
Description
Use opcode scan method
Enables the debugger to use a highly-optimized JTAG scan method;
provides extremely fast communication between the EZ-KIT Lite
and the processor. In certain circumstances, causes JTAG scan failures. Typically, JTAG scan failures occur when this option is combined with debugging situations that hold off or stall the core (such
as debugging, loading, or viewing external memory). Clearing this
option uses a less optimized JTAG scan method.
Use XML reset values
Uses a section in the processor-specific .XML file located in the
installation’s system folder. The file defines registers that are reset to
certain values; the values are read at startup and subsequently used
to set the registers when a reset is performed through VisualDSP++.
Mask interrupts during
step
Disables interrupts while single stepping through code.
Restricted Software Breakpoints
The EZ-KIT Lite development system restricts breakpoint placement when
certain conditions are met. That is, under some conditions, breakpoints cannot be placed effectively. Such conditions depend on bus architecture, pipeline
depth, and ordering of the EZ-KIT Lite and its target processor.
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ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2 EZ-KIT LITE HARDWARE
REFERENCE
This chapter describes the hardware design of the ADSP-BF537 EZ-KIT
Lite board. The following topics are covered.
• “System Architecture” on page 2-2
Describes the configuration of the ADSP-BF537 EZ-KIT Lite
board and explains how the board components interface with the
processor.
• “Jumper and Switch Settings” on page 2-9
Shows the location and describes the function of the configuration
jumpers and switches.
• “LEDs and Push Buttons” on page 2-19
Shows the location and describes the function of the LEDs and
push buttons.
• “Connectors” on page 2-22
Shows the location and gives the part number for all of the connectors on the board. Also, the manufacturer and part number
information is given for the mating parts.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2-1
System Architecture
System Architecture
This section describes the processor’s configuration on the EZ-KIT Lite
board.
Figure 2-1. System Architecture
The EZ-KIT Lite has been designed to demonstrate the capabilities of the
ADSP-BF537 Blackfin processor. The processor has IO voltage of 3.3V.
The core voltage of the processor is supplied by the internal voltage
regulator.
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EZ-KIT Lite Hardware Reference
The core voltage and the core clock rate can be set on the fly by the processor. The input clock is 25 MHz. A 32.768 kHz crystal supplies the Real
Time Clock (RTC) inputs of the processor. The default boot mode for the
processor is flash boot. See “Boot Mode Select Switch (SW16)” on
page 2-13 for information about changing the default boot mode.
External Bus Interface Unit
The External Bus Interface Unit (EBIU) connects external memory to the
ADSP-BF537 processor. The unit includes a 16-bit wide data bus, an
address bus, and a control bus. On the EZ-KIT Lite, the EBIU connects
to the SDRAM, flash, and expansion interfaces.
64 Mbytes (32M x 16 bits) of SDRAM connect to the synchronous memory select 0 pin (~SMS0). Refer to “SDRAM Interface” on page 1-8 for
information about configuring the SDRAM. Note that SDRAM clock is
the processor’s Clock Out (CLK OUT), which must not exceed 133 MHz.
The flash memory device connects to the asynchronous memory select signals, ~AMS3 through ~AMS0. The device provides a total of 4 Mbytes of
flash memory. The processor can use this memory for both booting and
storing information during normal operation. Refer to “Flash Memory”
on page 1-9 for details.
All of the address, data, and control signals are available externally via the
expansion interface (J1–3). The pinout of these connectors can be found
in Appendix B, “Schematics” on page B-1.
SPORT0 Audio Interface
The SPORT0 interface connects to the audio circuit, the SPORT0 connector
(P6), and the expansion interface. The audio circuit uses the primary data
transmit and receive pins to input and output data from the audio input
and outputs.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2-3
System Architecture
The pinout of the SPORT connector and the expansion interface connectors
can be found in Appendix B, “Schematics” on page B-1.
SPI Interface
The processor’s Serial Peripheral Interconnect (SPI) interface is connected
to the SPI connector (P9) and the expansion interface.
Programmable Flags (PFs)
The processor has 48 general-purpose input/output (GPIO) signals spread
across three ports (PF, PG and PH). The pins have multiple functions,
depending on the setup of the processor. Table 2-1 shows how the programmable flag pins are used on the EZ-KIT Lite.
Table 2-1. Programmable Flag Connections
2-4
Processor Pin
Other Processor Function
EZ-KIT Lite Function
PF0
GPIO/DMAR0
UART0
Transmit
PF1
GPIO/DMAR1
UART0
Receive
PF2
UART1_TX/TMR7
Push button (SW13). See “Programmable
Flag Push Buttons (SW13–10)” on
page 2-20.
PF3
UART1_RX/TMR6/TACI6
Push button (SW12). See “Programmable
Flag Push Buttons (SW13–10)” on
page 2-20.
PF4
TMR5/SPI_SSEL6
Push button (SW11). See “Programmable
Flag Push Buttons (SW13–10)” on
page 2-20.
PF5
TMR4/SPI_SSEL5
Push button (SW10). See “Programmable
Flag Push Buttons (SW13–10)” on
page 2-20.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Table 2-1. Programmable Flag Connections (Cont’d)
Processor Pin
Other Processor Function
EZ-KIT Lite Function
PF6
TMR3/SPI_SSEL4
LED (LED1). See “LEDs and Push Buttons”
on page 1-13 and “Push Button Enable
Switch (SW5)” on page 2-11 for information on how to disable the push button.
PF7
TMR2/PPI_FS3
LED (LED2). See “LEDs and Push Buttons”
on page 1-13 and “Push Button Enable
Switch (SW5)” on page 2-11 for information on how to disable the push button.
PF8
TMR1/PPI_FS2
LED (LED3). See “LEDs and Push Buttons”
on page 1-13 and “Push Button Enable
Switch (SW5)” on page 2-11 for information on how to disable the push button.
PF9
TMR0/PPI_FS1
LED (LED4). See “LEDs and Push Buttons”
on page 1-13 and “ELVIS Processor Core
Current Measurement Jumpers (JP1 and
JP7)” on page 2-16 for information on how
to disable the push button.
PF10
SPI_SSEL1
LED (LED5). See “LEDs and Push Buttons”
on page 1-13 and “ELVIS Processor Core
Current Measurement Jumpers (JP1 and
JP7)” on page 2-16 for information on how
to disable the push button.
PF11
SPI_MOSI
LED (LED6). See “LEDs and Push Buttons”
on page 1-13 and “ELVIS Processor Core
Current Measurement Jumpers (JP1 and
JP7)” on page 2-16 for information on how
to disable the push button.
PF12
SPI_MISO
Audio Reset
PF13
SPI_SCK
CAN ERR
PF14
SPI_SS/TACLK0
CAN EN
PF15
PPI4_CLK/TMRCLK
CAN STB
PG0
PPI_D0
ELVIS_TRIGGER
PG1
PPI_D1
ELVIS_PF1
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2-5
System Architecture
Table 2-1. Programmable Flag Connections (Cont’d)
2-6
Processor Pin
Other Processor Function
EZ-KIT Lite Function
PG2
PPI_D2
ELVIS_PF2
PG3
PPI_D3
ELVIS_PF5
PG4
PPI_D4
ELVIS_PF6
PG5
PPI_D5
ELVIS_PF7
PG6
PPI_D6
UART0_CTS
PG7
PPI_D7
UART0_RTS
PG8
PPI_D8/DR1SEC
Not used
PG9
PPI_D9/DT1SEC
Not used
PG10
PPI_D10/RSCLK1
Not used
PG11
PPI_D11/RFS1
Not used
PG12
PPI_D12/DR1PRI
Not used
PG13
PPI_D13/TSCLK1
Not used
PG14
PPI_D14/TFS1
No used
PG15
PPI_D15/DT1PRI
USB_IRQ
PH0
ETXD0
ETXD
PH1
ETXD1
ETXD1
used for Ethernet interface
PH2
ETXD2
ETXD2
used for Ethernet interface
PH3
ETXD3
ETXD3
used for Ethernet interface
PH4
ETXEN
ETXEN
used for Ethernet interface
PH5
MII_TXCLK/RMII_REF_CLK
MII_TXCLK
PH6
MII_PHYINT/RMII_MDINT
Not used
PH7
COL
COL
PH8
ERXD0
ERXD0
used for Ethernet interface
PH9
ERXD1
ERXD1
used for Ethernet interface
used for USB bus power
used for Ethernet interface
used for Ethernet interface
used for Ethernet interface
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Table 2-1. Programmable Flag Connections (Cont’d)
Processor Pin
Other Processor Function
EZ-KIT Lite Function
PH10
ERXD2
ERXD2
used for Ethernet interface
PH11
ERXD3
ERXD3
used for Ethernet interface
PH12
ERXDV/TACLK5
ERXDV
used for Ethernet interface
PH13
ERXCLK/TACLK6
ERXCLK
PH14
ERXER/TACLK7
ERXER
PH15
MII_CRS/RMII_CRS_DV
MII_CRS
used for Ethernet interface
used for Ethernet interface
used for Ethernet interface
UART Port
The processor’s Universal Asynchronous Receiver/Transmitter (UART)
port connects to the ADM3202 RS232 line driver as well as to the expansion interface. The RS232 line driver connects to the DB9 female
connector, providing an interface to a PC or other serial device.
Expansion Interface
The expansion interface consists of three 90-pin connectors. Table 2-2
shows the interfaces each connector provides. For the exact pinout of these
connectors, refer to Appendix B, “Schematics” on page B-1. The mechanical dimensions of the connectors can be obtained from Technical or
Customer Support.
Analog Devices offers many EZ-Extender products that plug on to the
expansion interface. For more information on these products, visit the
Analog Devices Web site at www.analog.com.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2-7
System Architecture
Table 2-2. Expansion Interface Connectors
Connector
Interfaces
J1
5V, G ND, Address, Data, PPI
J2
3.3V, GND, SPI, NMI, TMR2–0, SPORT0, SPORT1, PF15–0, EBUI control
signals
J3
5V, 3.3V, GND, UART, Flash IO, Reset, Video control signals
Limits to the current and to the interface speed must be taken into consideration when using the expansion interface. The maximum current limit is
dependent on the capabilities of the regulator used. Additional circuitry
can also add extra loading to signals, decreasing their maximum effective
speed.
Devices does not support and is not responsible for the
[ Analog
effects of additional circuitry.
JTAG Emulation Port
The JTAG emulation port allows an emulator to access the processor’s
internal and external memory through a 6-pin interface. The JTAG emulation port of the processor connects also to the USB debugging interface.
When an emulator connects to the board at P4, the USB debugging interface is disabled. See “JTAG Connector (P4)” on page 2-25 for more
information about the connector.
To learn more about available emulators, contact Analog Devices (see
“Processor Product Information”).
2-8
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Jumper and Switch Settings
This section describes the operation of the jumpers and switches. The
jumpers and switch locations are shown in Figure 2-2.
Figure 2-2. Jumper and Switch Locations
CAN Enable Switch (SW2)
The Controller Area Network (CAN) enable switch (SW2) disconnects the
CAN signals from the GPIO pins of the processor. When the SW2 switch is
in the OFF position, the associated GPIO signal (see Table 2-3) can be
used on the expansion interface.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2-9
Jumper and Switch Settings
Table 2-3. CAN Enable Switch (SW2)
CAN Signal
SW2 Switch Position (Default)
Processor Signal
ENABLE
1 (ON)
PF14
STANDBY
2 (ON)
PF15
ERROR
3 (ON)
PF13
RECEIVE DATA
4 (ON)
PJ4
Ethernet Mode Select Switch (SW3)
The Ethernet mode select switch (SW3) controls the configuration of the
10/100 digital block in the LAN83C185 PHY device (see Table 2-4).
Table 2-4. Ethernet Mode Select Switch (SW3)
SW3 Switch Position
Ethernet Mode
3
2
1
ON
ON
ON
10Base-T Half Duplex. Auto-negotiation disabled.
ON
ON
OFF
10Base-T Full Duplex. Auto-negotiation disabled.
ON
OFF
ON
100Base-T Half Duplex. Auto-negotiation disabled.
ON
OFF
OFF
100Base-T Full Duplex. Auto-negotiation disabled.
OFF
ON
ON
100Base-T Half Duplex. Auto-negotiation enabled.
OFF
ON
OFF
Repeater mode. Auto-negotiation enabled.
OFF
OFF
ON
Power Down mode
OFF
OFF
OFF
All capable. Auto-negotiation enabled. (Default)
UART Enable Switch (SW4)
The UART enable switch (SW4) disconnects UART signals from the GPIO
pins of the processor. When the switch is in the OFF position, the associated GPIO signal (see Table 2-5) can be used on the expansion interface.
2-10
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Table 2-5. UART Enable Switch (SW4)
EZ-KIT Lite Signal
SW4 Switch Position (Default)
Processor Signal
TX
1 (ON)
PF0
CTS
2 (ON)
PG6
RX
3 (ON)
PPF1
RTS
4 (OFF)
PG7
Push Button Enable Switch (SW5)
The push button enable switch (SW5) disconnects the associated with the
push button circuit drivers from the GPIO pins of the processor. When
the SW5 switch is in the OFF position, the associated GPIO signal (see
Table 2-6) can be used on the expansion interface.
Table 2-6. Push Button Enable Switch (SW5)
Push Button
SW5 Switch Position (Default)
Processor Signal
(
)
PB2 ( SW12)
PB3 ( SW11)
PB4 ( SW10)
1 (ON)
PF2
2 (ON)
PF3
3 (ON)
PF4
4 (ON)
PF5
PB1 SW13
Flash Enable Switch (SW6)
The flash enable switch (SW6) disconnects ~AMS signals from flash memory,
allowing other devices to utilize the signals via the expansion interface. For
each switch listed in Table 2-7 that is turned OFF, the size of available flash
memory is reduced by 1 MB.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2-11
Jumper and Switch Settings
Table 2-7. Flash Enable Switch (SW6)
Processor Signal
SW6 Switch Position (Default)
~AMS0
~AMS1
~AMS2
~AMS3
1 (ON)
2 (ON)
3 (ON)
4 (ON)
Audio Enable Switch (SW7)
The audio enable switch (SW7) disconnects the audio signals from the processor (positions 1–5) and determines how the clock for the audio circuit
is generated and connected (position 6–8). Position 8 determines if the
ADC is in master or slave mode. When in master mode (position 8 is ON),
the ADC generates the clock. When in slave mode (position 8 is OFF), the
processor generates the clock. Positions 6 and 7 connect the transmit and
receive clocks together (see Table 2-8).
Table 2-8. Audio Enable Switch (SW7)
EZ-KIT Lite Signal
SW7 Switch Position (Default)
Processor Signal
DR0PRI
1 (ON)
PJ8
RSCLK0
2 (ON)
PJ6
RFS0
3 (ON)
PJ7
TSCLK0
4 (ON)
PG9
TFS0
5 (ON)
PJ10
Clock Loopback
6 (ON)
FS Loopback
7 (ON)
ADC Master/Slave
8 (ON)
2-12
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Boot Mode Select Switch (SW16)
The rotary switch (SW16) determines the boot mode of the processor.
Table 2-9 shows the available boot mode settings. By default, the
ADSP-BF537 processor boots from on-board flash memory.
Table 2-9. Boot Mode Select Switch (SW16)
SW16 Position
Processor Boot Mode
0
Execute from 16-bit external memory
1
Boot from 16-bit flash memory. (Default)
2
Reserved
3
Boot from SPI memory
4
Boot from SPI host
5
Boot from Serial TWI Memory
6
Boot from TWI host
7
Boot from UART host
3V Power Selection Jumper (JP3)
The 3V power selection jumper (JP3) selects the power source for the
3-volt parts. In a standard mode of operation, the parts are powered by the
on-board switching regulator circuit (ADP3025) via an external power supply. When a Blackfin USB-LAN EZ-Extender connects to the EZ-KIT
Lite, power can be derived from the USB bus power or Power-over-Ethernet (802.3af). In this case, the board can operate without an external
power supply. The jumper settings are shown in Table 2-10.
Core Voltage Selection Jumper (JP4)
The core voltage selection jumper (JP4) is not used in the current design.
The jumper settings shown in Table 2-11 must not be changed.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2-13
Jumper and Switch Settings
Table 2-10. 3V Power Selection Jumper (JP3)
JP3 Position
Mode
1&2
3V parts powered from on-board switching regulator. (Default)
2&3
3V parts powered from an external power supply: USB-bus power or
Power-over-Ethernet
Table 2-11. Core Voltage Selection Jumper (JP4)
JP4 Position
Mode
1 and 2
Not used
2 and 3
Default setting
Expansion Interface Voltage Selection Jumper
(JP5)
The expansion interface voltage selection jumper (JP5) selects the power
source for the 5-volt signal on the expansion interface. In a standard mode
of operation, the signal is powered by the on-board switching regulator
circuit (ADP3025) via an external power supply. When a Blackfin
USB-LAN EZ-Extender connects to the board, power can be derived from
the USB bus power or Power-over-Ethernet (802.3af). In this case, the
board can operate without an external power supply. The jumper setting is
shown in Table 2-12.
Table 2-12. Expansion Interface Voltage Selection Jumper (JP5)
JP5 Setting
Mode
ON
5V signal powered from on-board switching regulator. (Default)
OFF
5V signal powered from external power supply: USB-bus power or
Power-over-Ethernet
2-14
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
UART Loop Jumper (JP9)
The UART loop jumper (JP9) is for looping the transmit and receive signals. The default is in the OFF position.
ELVIS Oscilloscope Configuration Switch (SW1)
The oscilloscope configuration switch (SW1) determines which audio circuit signals connect to channels A and B of the oscilloscope. The switch is
used only when the board connects to the Educational Laboratory Virtual
Instrumentation Suite (ELVIS) interface (see “ELVIS Interface” on
page 1-11). Each channel must have only one signal selected at a time (see
Table 2-13).
Table 2-13. Oscilloscope Configuration Switch (SW1)
Channel
SW1 Switch Position (Default)
Audio Circuit Signal
A
1 (OFF)
AMP_LEFT_IN
A
2 (OFF)
AMP_RIGHT_IN
A
3 (OFF)
LEFT_OUT
A
4 (OFF)
RIGHT_OUT
B
5 (OFF
AMP_LEFT_IN
B
6 (OFF)
AMP_RIGHT_IN
B
7 (OFF)
LEFT_OUT
B
8 (OFF)
RIGHT_OUT
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2-15
Jumper and Switch Settings
ELVIS Function Generator Configuration Switch
(SW8)
The function generator configuration switch (SW8) controls which signals
connect to the left and right input signals of the audio interface. The SW8
switch is used only when the board connects to the ELVIS interface (see
“ELVIS Interface” on page 1-11). Each channel must have only one signal
selected at a time, as described in Table 2-14.
Table 2-14. Function Generator Configuration Switch (SW8)
Channel
SW8 Switch Position (Default)
Audio Signal
AMP_LEFT_IN
1 (ON)
LEFT_IN
AMP_RIGHT_IN
2 (ON)
RIGHT_IN
AMP_LEFT_IN
3 (OFF)
DAC0
AMP_RIGHT_IN
4 (OFF)
DAC1
AMP_LEFT_IN
5 (OFF)
FUNCT_OUT
AMP_RIGHT_IN
6 (OFF)
FUNCT_OUT
ELVIS Processor Core Current Measurement
Jumpers (JP1 and JP7)
The JP1 and JP7 jumpers select the method for the core current measurement of the processor. The feature is supported only when the circuit
connects to an ELVIS station or to a NI DAQ card (see “ELVIS Interface”
on page 1-11). When JP1 and JP7 connect to neither system, the circuit
must be bypassed. The jumper settings are shown in Table 2-15.
2-16
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Table 2-15. Processor Core Measurement Jumpers (JP1 and JP7)
JP1 Setting
JP7 Setting
Mode
OFF
OFF
ELVIS current measurement
OFF
ON
DAQ current measurement
ON
OFF
Bypass shunt circuit. (Default)
ON
ON
Not used
ELVIS IO Current Measurement Jumper (JP2)
The processor IO current measurement jumpers (JP2) controls the
method by which IO current is measured. The feature is supported only
when the circuit connects to an NI DAQ card (see “ELVIS Interface” on
page 1-11). When is not connected to a DAQ system, the circuit must be
bypassed. The jumper settings are shown in Table 2-16.
Table 2-16. IO current Measurement Jumper (JP2)
JP2 Setting
Mode
OFF
DAQ current measurement
ON
BYPASS shunt circuit. (Default)
ELVIS Voltage Selection Jumper (JP6)
The ELVIS voltage selection jumper (JP6) is used to select the power
source for the EZ-KIT Lite. In a standard mode of operation, the board
receives its power from an external power supply. When JP6 is installed,
the board is powered from an ELVIS interface and no external power supply is required. The jumper setting is shown in Table 2-17.
external power supply must be disconnected from the board
[ The
is installed. In this case, the power supply may cause
when
JP6
damage to the EZ-KIT Lite board and ELVIS unit.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2-17
Jumper and Switch Settings
Table 2-17. ELVIS Voltage Selection Jumper (JP6)
JP6 Setting
Mode
OFF
Powered from an external power supply. (Default)
ON
Powered from ELVIS
ELVIS Select Jumper (JP8)
The ELVIS select jumper (JP8) configures the EZ-KIT Lite’s connection
to an ELVIS station (see “ELVIS Interface” on page 1-11). When JP8 is
installed, the connections to the push buttons and LED are re-directed to
the ELVIS station, instead of the processor. The jumper setting is shown
in Table 2-18.
Table 2-18. ELVIS Select Jumper (JP8)
JP8 Setting
Mode
OFF
Not connected to ELVIS. (Default)
ON
Connected to ELVIS
2-18
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
LEDs and Push Buttons
This section describes the functionality of the LEDs and push buttons.
Figure 2-3 shows the locations of the LEDs and push buttons.
Figure 2-3. LED and Push Button Locations
Reset Push Button (SW9)
The RESET push button resets all of the ICs on the board. One exception is
the USB interface chip. The chip is not being reset when the push button
is pressed after the USB cable has been plugged in and communication has
been correctly initialized with the PC. After USB communication has
been initialized, the only way to reset the USB is by powering down the
board.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2-19
LEDs and Push Buttons
Programmable Flag Push Buttons (SW13–10)
Four push buttons, SW13–10, are provided for general-purpose user input.
The buttons connect to PF5–2 programmable flag pins of the processor.
The push buttons are active HIGH and, when pressed, send a High (1) to the
processor. Refer to “LEDs and Push Buttons” on page 1-13 for more
information on how to use the PFs when programming the processor. The
push button enable switch (SW5) is capable of disconnecting the push buttons from the PF (refer to “Push Button Enable Switch (SW5)” on
page 2-11 for more information). The programmable flag signals and their
corresponding switches are shown in Table 2-19.
Table 2-19. Programmable Flag Switches
Processor Programmable Flag Pin
Push Button Reference Designator
PF2
SW13
PF3
SW12
PF4
SW11
PF5
SW10
Power LED (LED7)
When LED7 is lit (green), it indicates that power is being properly supplied
to the board.
Reset LEDs (LED8 and LED9)
When LED8 is lit, it indicates that the master reset of all the major ICs is
active. When LED9 is lit, the USB interface chip is being reset. The USB
chips reset only on power-up, or if USB communication has not been
initialized.
2-20
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
User LEDs (LED1–6)
Six LEDs connect to six general-purpose IO pins of the processor (see
Table 2-20)). The LEDs are active HIGH and are lit by writing a “1” to the
correct PF signal. Refer to “LEDs and Push Buttons” on page 1-13 for
more information about how to use the flash when programming the
LEDs.
Table 2-20. User LEDs
LED Reference Designator
Processor Programmable Flag Pin
LED1
PF6
LED2
PF7
LED3
PF8
LED4
PF9
LED5
PF10
LED6
PF11
USB Monitor LED (LED10)
The USB Monitor LED (LED10) indicates that USB communication has
been initialized successfully, and you can connect to the processor using a
VisualDSP++ EZ-KIT Lite session. This should take approximately 15
seconds. If the LED does not light, try cycling power on the board and/or
reinstalling the USB driver (see the VisualDSP++ Installation Quick Reference card).
VisualDSP++ is actively communicating with the EZ-KIT
L When
Lite target board, the LED can flicker, indicating communications
handshake.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2-21
Connectors
Connectors
This section describes the connector functionality and provides information about mating connectors. The locations of the connectors are shown
in Figure 2-4 on page 2-22.
Figure 2-4. Connector Locations
2-22
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Audio Connectors (J9 and J10)
Part Description
Manufacturer
Part Number
3.5 mm stereo jack
A/D Electronics
ST323-5
Mating Cable (shipped with EZ-KIT Lite)
3.5 mm stereo interconnect
cable
Random
0A3-01106
3.5 mm headphones
Koss
UR5
CAN Connectors (J5 and J11)
Part Description
Manufacturer
Part Number
Modular Jack
AMP
558872-1
Mating Cable
4 conductor modular jack cable
L-COM
TSP3044
Ethernet Connector (J4)
Part Description
Manufacturer
Part Number
Ethernet Jack
Pulse
JK0-0025
Mating Cable (shipped with EZ-KIT Lite)
Cat 5E patch cable
Random
PC10/100T-007
Cat 5E crossover cable
Random
PC10/100TC-007
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2-23
Connectors
RS232 Connector (J6)
Part Description
Manufacturer
Part Number
DB9,
Digi-Key
191-009-213-571-ND
Female, Vertical Mount
Mating Cable
2m Female to female cable
Digi-Key
AE1020-ND
Power Connector (J7)
The power connector provides all of the power necessary to operate the
EZ-KIT Lite board.
Part Description
Manufacturer
Part Number
2.5 mm Power Jack
SWITCHCRAFT
RAPC712
Mating Power Supply (shipped with EZ-KIT Lite)
7V Power Supply
CUI Inc.
DMS070214-P6P-SZ
The power connector supplies DC power to the EZ-KIT Lite board.
Table 2-21 shows the power supply specifications.
Table 2-21. Power Supply Specification
Terminal
Connection
Center pin
+7 [email protected] amps
Outer Ring
GND
2-24
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
Expansion Interface Connectors (J1–3)
Three board-to-board connector footprints provide signals for most of the
processor’s peripheral interfaces. The connectors are located at the bottom
of the board. For more information about the expansion interface, see
“Expansion Interface” on page 2-7. For the availability and pricing of the
J1, J12, and J3 connectors, contact Samtec.
Part Description
Manufacturer
Part Number
90 Position 0.05" Spacing,
SMT
Samtec
SFC-145-T2-F-D-A
Mating Connector
90 Position 0.05” Spacing
(Through Hole)
Samtec
TFM-145-x1 Series
90 Position 0.05” Spacing
(Surface Mount)
Samtec
TFM-145-x2 Series
90 Position 0.05” Spacing
(Low Cost)
Samtec
TFC-145 Series
JTAG Connector (P4)
The JTAG header is the connecting point for a JTAG in-circuit emulator
pod. When an emulator connects to the JTAG header, the USB debug
interface is disabled.
3 is missing to provide keying. Pin 3 in the mating connector
L Pin
should have a plug.
using an emulator with the EZ-KIT Lite board, follow the
L When
connection instructions provided with the emulator.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2-25
Connectors
SPORT0 Connector (P6)
The pinout for the P6 connector can be found in Appendix B, “Schematics” on page B-1.
Part Description
Manufacturer
Part Number
IDC Header
Digi-Key
S2012-17-ND
Mating Connector
IDC socket
Digi-Key
S4217-ND
SPORT1 Connector (P7)
The pinout for the P7 connector can be found in Appendix B, “Schematics” on page B-1.
Part Description
Manufacturer
Part Number
IDC Header
Digi-Key
S2012-17-ND
Mating Connector
IDC socket
Digi-Key
S4217-ND
PPI Connector (P8)
The pinout for the P8 connector can be found in Appendix B, “Schematics” on page B-1.
Part Description
Manufacturer
Part Number
IDC Header
Digi-Key
S2012-20-ND
Mating Connector
IDC socket
2-26
Digi-Key
S4220-ND
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
SPI Connector (P9)
The pinout for the P9 connector can be found in Appendix B, “Schematics” on page B-1.
Part Description
Manufacturer
Part Number
IDC Header
Digi-Key
S2012-10-ND
Mating Connector
IDC socket
Digi-Key
S4210-ND
Two-Wire Interface Connector (P10)
The pinout for the P10 connector can be found in Appendix B, “Schematics” on page B-1.
Part Description
Manufacturer
Part Number
IDC Header
Digi-Key
S2012-10-ND
Mating Connector
IDC socket
Digi-Key
S4210-ND
TIMERS Connector (P11)
The pinout for the P11 connector can be found in Appendix B, “Schematics” on page B-1.
Part Description
Manufacturer
Part Number
IDC Header
Digi-Key
S2012-05-ND
Mating Connector
IDC socket
Digi-Key
S4205-ND
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2-27
Connectors
UART1 Connector (P12)
The pinout for the P12 connector can be found in Appendix B, “Schematics” on page B-1.
Part Description
Manufacturer
Part Number
IDC Header
Digi-Key
S2012-05-ND
Mating Connector
IDC socket
2-28
Digi-Key
S4205-ND
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
A BILL OF MATERIALS
The bill of materials corresponds to the board schematics on page B-1.
Please check the latest schematics on the Analog Devices website,
http://www.analog.com/Processors/Processors/DevelopmentTools/tec
hnicalLibrary/manuals/DevToolsIndex.html#Evaluation%20Kit%20Manuals.
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
A-1
A-2
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
1
1
1
1
5
1
2
1
7
8
9
10
11
12
13
14
1
4
1
1
3
6
1
2
1
1
1
5
#
Ref.
U5
U46
Reference Designator
P-MOSFET
256Kx16 SRAM
12.288 MHZ OSCILLATOR
SINGLE-2-INPUT-NAND
12 MHZ CRYSTAL
128K X 8 SRAM
25 MHZ CRYSTAL
ADJ 200MA REGULATOR
NPN TRANSISTOR 200MA
USB-TX/RX MICROCONTROLLER
3.3V-OCTAL-BUFFER
U28
U8-9
U4
U39-43
Y1
U25
U7
VR2
Q1
U10
U36
HEX-INVER-SCHMITT-TRIGGER U37
10MHZ OSCILLATOR
3.3V-OCTAL-BUFFER
Description
GS74116ATP-10
SG-8002CA-PCC-ND
SN74AHC1G00DBVR
300-6027-ND
CY7C1019BV33-12VC
MA-505 25.000M-C2
ADP3331ART
MMBT4401
CY7C64603-128NC
IDT74FCT3244APY
74LVC14AD
C04310-10.00
SN74LVT244BDW
Part Number
FAIRCHILD SEMI NDS8434A
GSI TECHNOLOGY
DIG01
TI
DIG01
CYPRESS
EPSON
ANALOG
DEVICES
FAIRCHILD
CYPRESS
IDT
TI
RALTRON
TI
Manufacturer
#
1
1
1
6
2
1
1
4
1
1
1
1
1
3
Ref.
15
16
17
18
19
20
21
22
23
24
25
26
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
27
28
DUAL AUDIO OP AMP
3.3V-1.0AMP REGULATOR
VOLTAGE-SUPERVISOR
M29W320DB
DSM2150F5V
24LC32
POWER-MOSFET
Ethernet-PHY
CAN-TRANSCEIVER
8M X 8 SDRAM
SINGLE-2-INPUT-AND-GATE
SINGLE-2 INPUT OR GATE
XILINX-SPARTANIIE
32.768 CRYSTAL
Description
U29-31
VR1
U27
U24
U13
U34
U17-20
U14
U21
U15-16
U22,U47-50,U58
U52
U1
U6
Reference Designator
NATIONAL SEMI
ANALOG
DEVICES
ANALOG
DEVICES
ST MICRO
ST MICRO
ATMEL
VISHAY
SMSC
PHILIPS
MICRON
TI
TI
XILINX
EPSON
Manufacturer
LMV722M
ADP3338AKC-3.3
ADM708SAR
M29W320DB70ZA6
DSM2150F5V
24LC32
SI4820DY-T1
LAN83C185-JD
TJA1041T
MT48LC32M8A2TG-75
SN74LVC1G08DBVR
SN74LVC1G32DBVR
XC2S150E-7FT256C
MC-156 32.768KA-A2
Part Number
Bill Of Materials
A-3
A-4
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2
1
1
1
1
5
3
2
34
35
36
37
38
39
40
1
31
33
1
30
2
1
29
32
#
Ref.
DIP SWITCH
SMT SOCKET
PUSH BUTTON SWITCH
USB CONNECTOR
POWER JACK
REGULAOR
DSP
OP-amp
Instrumentation-amp
RS232-TXRX
STERO-ADC
STERO-DAC
Description
SW1, SW7
J1, J2, J3
SW9-13
J8
J7
U26
U35
U11,U23
U2-3
U32
U33
U38
Reference Designator
C&K
SAMTEC
PANASONIC
MILL-MAX
SWITCHCRAFT
ANALOG
DEVICES
ANALOG
DEVICES
ANALOG
DEVICES
ANALOG
DEVICES
ANALOG
DEVICES
ANALOG
DEVICES
ANALOG
DEVICES
Manufacturer
CKN1365-ND
SFC-145-T2-F-D-A
EVQ-PAD04M
897-30-004-90-0000
SC1152-ND12
ADP3025JRU-REEL
ADSP-BF537SKBC1ENG
AD820AR
AD623ARM-REEL
ADM3202ARN
AD1871YRS
AD1854JRS
Part Number
#
1
5
1
1
1
2
7
2
3
7
1
1
1
1
2
Ref.
41
42
43
44
45
46
47
48
49
50
51
52
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
53
54
55
68uF 25V 20% CAP003
698K 1/8W 1% 805
340K 1/8W 1% 805
68uF 6.3V 20% D
SILICON RECTIFIER
FERRITE BEAD
100 100MW 5% 805
10uF 16V 10% C
LED
MODULAR CONNECTOR
DB9 CONNECTOR
Rotary-Switch
POE-Builtin-magnetics
DIP SWITCH
DIP SWITCH
Description
CT1-2
R167
R166
CT5
D4
FER2-6,FER9
R100-101,R103
CT7 AND CT8
LED1-6,10
J5, J11
J6
SW16
J4
SW2-6
SW8
Reference Designator
PANASONIC
DALE
DALE
PANASONIC
VISHAY
MURATA
AVX
SPRAGUE
PANASONIC
AMP
NORCOMP INC
GRAYHILL
PULSE ENG.
DIG01
DIG01
Manufacturer
EEV-FC1E680P
CRCW0805-6983FT
CRCW0805-3403FT
ECS-TOJD686R
S2A/52
BLM11A601SPT
CR21-101J-T
293D106X9016C2T
LN1461C-TR
558872-1
191-009-213-571
94HAB08
JK0-0025
CKN1363-ND
CKN1364-ND
Part Number
Bill Of Materials
A-5
A-6
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2
5
19
43
83
62
63
64
65
66
5
59
1
2
58
61
1
57
1
1
56
60
#
Ref.
0.01UF 16V 10% 402
0.1UF 10V 10% 402
10UF 6.3V 10% 805
1UF 10V 10% 805
0.47UF 16V 10% 805
SCHOTTKY DIODE
190 100MHZ 5A FER002
10K 31MW 5% RNET8
270 1/10W 5% 805
10uH 47 +/-20 IND001
332K 1/10W 1% 805
Description
AVX
AVX
AVX
AVX
ZETEX
MURATA
CTS
PHYCOMP
DIG01
PHILIPS
Manufacturer
C1-25,C30-46,C96-105, AVX
C107-110,C141-145,
C159-167,C177-181,
C202-205,C211, C225,
C226, C227
C55-57,C59-60,
C111-114,C139-140,
C146-149,C152-157,
C168-175,C185-198
C158,C176,C182-184,
C206-209, C212-219
C134,C210, C220-222
C199-200
D5
FER7
RN1-5
R99,R136
L1
R164
Reference Designator
0402YC103KAT2A
0402ZD104KAT2A
080560106KAT2A
0805ZC105KAT2A
0805YC474KAT2A
ZHCS1000
DLW5BSN191SQ2
746X101103J
9C08052A2700JLHFT
445-1202-2-ND
9C08052A3323FKRT/R
Part Number
#
59
1
3
20
2
4
2
1
2
1
12
Ref.
67
68
69
70
71
72
73
74
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
75
76
77
0.1UF 16V 10% 603
0.022UF 50V 5% 805
1.5K 1/10W 5% 603
34.8K 1/10W 1% 805
1000PF 50V 5% 402
18PF 50VDC 5% 805
33 1/16W 5% 402
22 1/16W 5% 402
0 1/16W 5% 402
4.7k 1/16w 5% 402
10K 1/16W 5% 402
Description
Manufacturer
C64,C72-74,C87-89,
C123-125,C130,C133
C95
R206, R124
R113
C127-128
C26-29
R1, R54
R187-R202,R122-123,
R137-138
R3,R163,R207
R4
AVX
AVX
DIGIKEY
YAGEO
AVX
PANASONIC
PANASONIC
PANASONIC
PANASONIC
PANASONIC
R2,R5,R7-9,R12-16,
DALE
R24-25,R72-74,R78-80,
R82,R84-90,R97,
R126-130,R139-147,
R162,R169,
R170-172,R174,
R176-178,R179,
R181-186,R205
Reference Designator
0603YC104KAT2A
08055C223JAT2A
P1.5KCFCT-ND
9C08052A3482FKHFT
04025C102JAT2A
ECJ-2VC1H180J
ERJ-2GEJ330X
ERJ-2GEJ220X
ERJ-2GE0R00X
ERJ-2GEJ472X
CRCW0402103JRT7
Part Number
Bill Of Materials
A-7
A-8
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
1
1
1
1
2
2
2
2
84
85
86
87
88
89
90
91
2
81
1
1
80
83
4
79
4
5
78
82
#
Ref.
10UH 17 20% IND005
1A 10BQ040 SMB
220UF 6.3V 20% D2E
33000PF 25V 10% 0603
68000PF 25V +80/-20% 0603
22000PF 16V 10% 0603
470PF 50V 5% 0603
4.7UF 6.3V 20% 0603
150PF 50V 5% 0603
330PF 50V 5% 0603
68PF 50V 5% 0603
4.7UF 25V 205 0805
10UF 25V +80/-20% 1210
0.01UF 16V 10% 0603
Description
L2-3
D8-9
CT3-4
C126,C129
C131
C132
C119
C135
C120
C79,C84,C118,C121
C116-117
C122
C115,C136-138
C50-51,C62-63,C93
Reference Designator
COILCRAFT
IR
SANYO
AVX
PANASONIC
PANASONIC
PANASONIC
PANASONIC
AVX
AVX
PANASONIC
PANASONIC
PANASONIC
KEMET
Manufacturer
MSS1278-103MXB
10BQ040
10TPE220ML
06033C333KAT2A
ECJ-1VF1E683Z
ECJ-1VB1C223K
ECJ-1VC1H471J
ECJ-1VB0J475M
06035A151JAT2A
06035A331JAT2A
ECJ-1VC1H680J
ECJ-2FB1E475M
ECJ-4YF1E106Z
C0603C103K4RAC
Part Number
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2
2
2
10
1
12
4
8
1
1
4
1
93
94
95
96
97
98
99
100
101
102
103
104
1
6
92
105
#
Ref.
6.2K 1/10W 1% 0603
75K 1/16W 1% 0603
10K 1/16W 1% 0603
4.7 1/10W 5% 0603
130K 1/16W 1% 0603
10 1/10W 5% 0603
49.9 1/16W 1% 0603
0 1/10W 5% 0603
1M 1/10W 5% 0603
330 1/10W 5% 0603
100K 1/10W 5% 0603
10M 1/10W 5% 0603
4.7K 1/10W 5% 0603
10K 1/10W 5% 0603
Description
VISHAY
VISHAY
VISHAY
VISHAY
Manufacturer
R109
R108
R64,R102,R106,R110
R119
R107
R6,R55-57,R59,R62,
R69,R111
R67-68,R70-71
R27,R115,R117-118,
R149-154,R165,R168
R135
DIGI-KEY
DALE
PHYCOMP
PHYCOMP
VISHAY
DALE
VISHAY
PHYCOMP
VISHAY
R75-76,R83,R91-96,R98 VISHAY
R20,R26
R10-11
R155,R161
R37,R53,R105,
R156-158
Reference Designator
311-6.20KHTR-ND
CRCW06037502FRT1
9C06031A1002FKHFT
9C06031A4R70JLHFT
CRCW06031303FRT1
CRCW0603100JRT1
CRCW060349R9FRT1
9C06031A0R00JLHFT
CRCW0603105JRT1
CRCW0603331JRT1
CRCW0603104JRT1
CRCW0603106JRT1
CRCW0603472JRT1
CRCW0603103JRT1
Part Number
Bill Of Materials
A-9
A-10
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
2
3
4
3
2
2
2
2
2
112
113
114
115
116
117
118
119
120
2
109
4
1
108
111
1
107
1
3
106
110
#
Ref.
0.1 1/10W 1% 0603
90.9K 1/10W 1% 0603
604 1/10W 1% 0603
49.9K 1/10W 1% 0603
1.65K 1/10W 1% 0603
3.32K 1/10W 1% 0603
5.49K 1/10W 1% 0603
11K 1/10W 1% 0603
750K 1/10W 1% 0603
237 1/10W 1% 0603
4.7NF 16V 10% 0603
6.8NF 16V 10% 0603
1K 1/10W 5% 0603
25.5K 1/16W 1% 0603
200K 1/16W 1% 0603
Description
R61,R148
R58,R63
R50-51
R38,R41
R45,R49
R44,R48,R132
R42-43,R46-47
R39-40,R60
R30,R32
R23,R29,R31,R33
C90
C91-92
R125
R104
R112,R114,R116
Reference Designator
YAGEO
DIGI-KEY
DIGI-KEY
DIGI-KEY
DIGI-KEY
DIGI-KEY
DIGI-KEY
DIGI-KEY
DIGI-KEY
DIGI-KEY
DIG01
DIG01
YAGEO
YAGEO
VISHAY
Manufacturer
ERJ-3RSFR10V
311-90KHTR-ND
311-604HTR-ND
311-49.9KHTR-ND
311-1.65KHTR-ND
311-3.32KHTR-ND
311-5.49KHTR-ND
311-11KHTR-ND
311-750KHTR-ND
311-237HTR-ND
311-1083-2-ND
311-1084-2-ND
9C06031A1001JLHFT
9C06031A2552FKHFT
CRCW06032003FRT1
Part Number
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
8
4
12
4
2
2
1
2
2
2
2
2
122
123
124
125
126
127
128
129
130
131
132
133
2
2
121
134
#
Ref.
DIODE
2.74K 1/10W 1% 0603
2200pF 50V 5% 0603
680pF 50V 5% 0603
220PF 50V 5% 0603
62.0 1/10W 1% 0603
12.4K 1/10W 1% 0603
2.21K 1/10W 1% 0603
33PF 50V 5% 0603
0.001UF 50V 5% 0603
100PF 50V 5% 0603
120PF 50V 5% 0603
5.76K 1/10W 1% 0603
10K 1/10W 1% 0603
Description
PANASONIC
DIGI-KEY
DIGI-KEY
Manufacturer
D1 & D2
R36,R52
C76,C78
C80,C83
C82,C86
R65-66
R77
R133-134
C150-151
C66-67,C69-70
DIODES INC
DIGI-KEY
PANASONIC
PANASONIC
PANASONIC
DIGI-KEY
DIGI-KEY
DIGI-KEY
PANASONIC
PANASONIC
C52-54,C61,C65,C68,
PANASONIC
C75,C77,C81,C85,C94,
C106
C47-49,C71
R17-19,R21-22,R28,
R34-35
R159-160
Reference Designator
MMBD4148W
311-2.74KHTR-ND
ECJ-1VB1H222K
ECJ-1VC1H681J
ECJ-1VC1H221J
311-62.0HTR-ND
311-12.4KHTR-ND
311-2.21KHTR-ND
ECJ-1VC1H300J
ECJ-1VC1H102J
ECJ-1VC1H101J
ECJ-1VC1H121J
311-5.76KHTR-ND
311-10.0KHTR-ND
Part Number
Bill Of Materials
A-11
A-12
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
#
2
1
6
8
2
2
1
2
2
1
1
2
2
Ref.
135
136
137
138
139
140
141
142
143
144
145
146
147
1.2K 1/16W 1% 402
AUDIO CONNECTOR
FUSE
IDC 20X2
IDC 17X2
IDC 10X2
IDC 7X2
IDC 5X2
IDC 3X1
IDC 2X1
QUICKSWITCH-257
LED
LED
Description
R173, R175
J9, J10
F1
P8
P6-7
P9-10
P4
P11-12
JP3,JP10
JP1-2, JP5-9, JP12
U44-45,U54-57
LED7
LED8-9
Reference Designator
DIGIKEY
AD ELECTRONICS
RAYCHEM CORP.
BERG
BERG
BERG
BERG
BERG
BERG
BERG
ANALOG
DEVICES
PANASONIC
PANASONIC
Manufacturer
P1.2KJTR-ND
ST-323-5
SMD250-2
54102-T08-20
54102-T08-17
54102-T08-10
54102-T08-07
54102-T08-05
54101-T08-03
54101-T08-02
ADG774ABRQ
LN1361C
LN1261C
Part Number
A
B
C
D
1
1
2
2
ADSP-BF537 EZ-KIT LITE
SCHEMATIC
3
3
ANALOG
DEVICES
4
Approvals
Date
Engineering
A
B
C
Size
Board No.
C
Date
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF537 EZ-KIT LITE
TITLE
Title
Drawn
Checked
20 Cotton Road
Rev
A0188-2004
1.1
Sheet
1-21-2005_16:26
D
1
of
11
A
B
C
D
U35
A[1:19]
A1
J14
A2
K14
A3
L14
A4
1
A2
A3
J13
A4
A5
K13
A6
L13
A7
A5
A6
K12
L12
A9
M12
A10
M13
A11
M14
A7
A8
A12
A13
A14
A15
A16
A17
A18
A19
M9
D0
N9
D1
P9
D2
M8
D3
N8
D4
P8
D5
M7
D6
N7
D7
P7
D8
M6
D9
N6
D10
P6
D11
M5
D12
N5
D13
P5
D14
P4
D15
A1
A8
A9
A10
A11
N14
A12
N13
A13
N12
A14
M11
A15
N11
A16
P13
A17
P12
A18
P11
A19
ARDY
D3
PJ1_MDIO
D4
PJ2_SCL
D5
PJ3_SDA
D6
PJ4_CAN_RX
D7
PJ5_CAN_TX
D8
PJ6_RSCLK0
D9
PJ7_RFS0
D10
PJ8_DR0PRI
D11
PJ9_TSCLK0
D12
PJ10_TFS0
D13
PJ11_DT0PRI
AMS0
AMS1
ARDY
AMS3
RTXI
D15
E14
F14
F13
ARE
H14
AWE
SRAS
SCAS
H13
ABE0~/SDQM0
H12
ABE1~/SDQM1
ABE0
ABE1
D14
BR
P10
BG
N10
BGH
BR
BG
BGH
B10
NMI
N4
U35
PF4_PB3
BMODE0
P3
BMODE1
L5
BMODE0
BMODE1
BMODE2
G1
PG0_ELVIS_TRIGGER
PF5_PB4
G2
PG1_ELVIS_PF1
PF6_LED1
GPIO/PPI_D0
GPIO/ETXD0
GPIO/PPI_D1
GPIO/ETXD1
G3
PG2_ELVIS_PF2
GPIO/PPI_D2
F1
GPIO/PPI_D3
F2
GPIO/PPI_D4
F3
GPIO/PPI_D5
E1
GPIO/PPI_D6
E2
GPIO/PPI_D7
E3
GPIO/PPI_D8/DR1SEC
E4
GPIO/PPI_D9/DT1SEC
D1
GPIO/PPI_D10/RSCLK1
D2
GPIO/PPI_D11/RFS1
D3
GPIO/PPI_D12/DR1PRI
D5
GPIO/PPI_D13/TSCLK1
D6
GPIO/PPI_D14/TFS1
C1
GPIO/PPI_D15/DT1PRI
PF7_LED2
PG3_ELVIS_PF5
PF8_LED3
PG4_ELVIS_PF6
PF9_LED4
PG5_ELVIS_PF7
PF10_LED5
PG6_UART0_CTS
PF11_LED6
PG7_UART0_RTS
PF12_AUDIO_RESET
PG8
PF13_CAN_ERR
PG9
PF14_CAN_EN
PG10
PF15_CAN_STB~
M2
EMU
N2
TMS
P2
TCK
N1
TRST
M3
TDI
N3
TDO
SCAS
D12
SWE
B13
SCKE
B14
CLKOUT
E12
SA10
C13
SMS
PF3_PB2
PG12
SRAS
C14
PF2_PB1
PG11
AMS3
D13
PF1_UART0_RX
AMS1
AMS2
G12
PF0_UART0_TX
AMS0
BMODE2
G14
ARE
M1
GPIO/UART0_TX/DMAR0
L1
MDIO
GPIO/UART0_RX/DMAR1/TACI1
B11
L2
SCL
GPIO/UART1_TX/TMR7
C11
L3
SDA
GPIO/UART1_RX/TMR6/TACI6
D7
L4
DR0SEC/CAN_RX/TACI0
GPIO/TMR5/SPI_SSEL6
D8
K1
DT0SEC/CAN_TX/SPI_SSEL7
GPIO/TMR4/SPI_SSEL5
C8
K2
RSCLK0/TACLK2
GPIO/TMR3/SPI_SSEL4
B8
K3
RFS0/TACLK3
GPIO/TMR2/PPI_FS3
D9
K4
DR0PRI/TACLK4
GPIO/TMR1/PPI_FS2
C9
J1
TSCLK0/TACLK1
GPIO/TMR0/PPI_FS1
D10
J2
TFS0/SPI_SSEL3
GPIO/SPI_SSEL1
D11
J3
DT0PRI/SPI_SSEL2
GPIO/SPI_MOSI
H1
GPIO/SPI_MISO
A9
H2
RTXI
GPIO/SPI_SCK
A8
H3
RTXO
GPIO/SPI_SS/TACLK0
H4
GPIO/PPI_CLK/TMRCLK
MDC
B7
D14
AOE
AWE
C7
PJ0_MDC
D2
G13
AOE
2
U35
D1
RTXO
AMS2
E13
D[0:15]
D0
EMU
PG13
TMS
PG14_FLASH_UNPROTECT
TCK
PG15_USB_IRQ
GPIO/ETXD3
GPIO/ETXEN
GPIO/MII_TXCLK/RMII_REF_CLK
GPIO/MII_PHYINT/RMII_MDINT
SCLK
R4
4.7K
402
SA10
SMS
PH6_PHYINT
PH7_COL
PH8_ERXD0
PH9_ERXD1
PH10_ERXD2
PH11_ERXD3
PH12_ERXDV
PH13_ERXCLK
PH14_ERXER
PH15_CRS
When designing your JTAG interface please refer to the
2
Engineer to Engineer Note EE-68 which can be found at
VDDINT
VDDEXT
U35
CLKIN
A1
XTAL
C12
BUF_XTAL
C1
0.01UF
402
C6
0.01UF
402
C5
0.01UF
402
C7
0.01UF
402
VDDEXT1
GND1
VDDEXT2
GND2
E6
D3
DNP
C4
0.01UF
402
C3
0.01UF
402
C2
0.01UF
402
C8
0.01UF
402
CLKIN
3V_BP
LABEL "VDDRTC"
R10
10M
0603
TP1
VDDEXT
VROUT
R2
10K
402
VDDEXT3
E11
VDDEXT4
F4
VDDEXT5
F12
VDDEXT6
H5
VDDEXT7
H10
VDDEXT8
J11
VDDEXT9
J12
VDDEXT10
K7
VDDEXT11
K9
VDDEXT12
L7
VDDEXT13
L9
VDDEXT14
L11
VDDEXT15
P1
VDDEXT16
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
2
4
3
U51
25MHZ
OSC005
C27
18PF
805
R1
33
402
4
VDD
1
C26
18PF
805
PH5_TXCLK
B2
ADSP-BF537
MINI_BGA182
SCKE
C206
10UF
805
3
PH4_ETXEN
B1
TDO
http://www.analog.com
U7
PH3_ETXD3
C6
ADSP-BF537
MINI_BGA182
TDI
ADSP-BF537
MINI_BGA182
1
PH2_ETXD2
C5
TRST
C10
RESET
XTAL
OE
B9
GND17
VDDRTC
GND18
3
OUT
CLKIN
C209
10UF
805
GND
2
DNP
C15
0.01UF
402
C10
0.01UF
402
C11
0.01UF
402
C9
0.01UF
402
C12
0.01UF
402
C13
0.01UF
402
C14
0.01UF
402
A13
VROUT0
B12
VROUT1
C16
0.01UF
402
GND19
GND20
3V_BP
GND21
E5
VDDINT1
GND22
VDDINT2
E10
VDDINT3
G10
VDDINT4
K5
VDDINT5
K8
VDDINT6
K10
VDDINT7
GND23
E8
R3
0
402
3V_BP
VDDINT
RTXI
1
PH1_ETXD1
C4
B3
GPIO/COL
B4
GPIO/ERXD0
B5
GPIO/ERXD1
B6
GPIO/ERXD2
A2
GPIO/ERXD3
A3
GPIO/ERXDV/TACLK5
A4
GPIO/ERXCLK/TACLK6
A5
GPIO/ERXER/TACLK7
A6
GPIO/MII_CRS/RMII_CRS_DV
VDDEXT
RESET
PH0_ETXD0
C3
SWE
A12
CLKIN
A11
XTAL
A7
BUF_XTAL
NMI
GPIO/ETXD2
C2
C25
0.01UF
402
RTXO
GND24
GND25
A10
A14
D4
E7
E9
F5
F6
F10
F11
G4
G5
G11
H11
J4
J5
J9
J10
3
K6
K11
L6
L8
L10
M4
M10
P14
ADSP-BF537
MINI_BGA182
R11
10M
0603
R170
10K
402
R171
10K
402
R172
10K
402
R173
1.2K
402
R174
10K
402
R175
1.2K
402
R176
10K
402
C208
10UF
805
C207
10UF
805
C18
0.01UF
402
C23
0.01UF
402
C22
0.01UF
402
C24
0.01UF
402
C21
0.01UF
402
C20
0.01UF
402
C19
0.01UF
402
C17
0.01UF
402
U6
1
2
4
PJ8_DR0PRI
3
NMI
TERM1 TERM2
NC1
NC2
ANALOG
DEVICES
BR
4
C28
18PF
805
32.768KHZ
OSC008
C29
18PF
805
PJ3_SDA
PJ4_CAN_RX
PJ2_SCL
ARDY
Approvals
Date
RTC
Engineering
A
B
C
Size
Board No.
C
Date
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF537 EZ-KIT LITE
DSP
Title
Drawn
Checked
20 Cotton Road
Rev
A0188-2004
1.1
Sheet
1-21-2005_16:26
D
2
of
11
A
B
C
D
3V_BP
A[1:19]
D[0:15]
U24
1
A1
A1
23
A0
A2
24
A3
25
26
29
A6
2
D0
5
DQ2
11
DQ4
D3
A4
D4
A5
R198 22 402
47
A5
A3
R202 22 402
44
30
A2
D2
R199 22 402
DQ3
A4
D1
R195 22 402
8
A3
A1
R197 22 402
DQ1
A2
A5
R196 22 402
DQ0
A1
A4
U16
DQ5
D5
A6
R201 22 402
A7
31
A8
32
50
A9
33
A9
A10
34
A10
A6
DQ6
A7
D6
A7
D7
A8
R200 22 402
53
DQ7
A8
A9
22
SA10
A10
SA10
A12
35
A12
A13
36
A13
A18
20
A18
A11
A12
23
A0
24
A1
25
A2
26
A3
29
A4
30
A5
31
A6
32
A7
33
A8
34
A9
22
A10
35
A11
36
A12
ADDRESS RANGE
MEMORY
A3
R187 22 402
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
2
D8
R188 22 402
5
D9
R189 22 402
8
D10
R192 22 402
11
D11
R190 22 402
44
D12
ASYNC BANK 3
0x2020 0000 - 0x202F FFFF
ASYNC BANK 2
0x2010 0000 - 0x201F FFFF
ASYNC BANK 1
0x2000 0000 - 0x200F FFFF
ASYNC BANK 0
0x0000 0000 - 0x03FF FFFF
R193 22 402
47
0x2030 0000 - 0x203F FFFF
A4
A5
A6
A7
A8
SDRAM
D13
A9
D14
A10
D15
A11
R191 22 402
50
R194 22 402
53
A12
A13
3V_BP
A14
A15
A16
A17
A19
2
BA0
21
A19
BA1
16
SWE
19
CS
37
CKE
38
CLK
WE
17
SCAS
CAS
18
SRAS
RAS
SMS
SWE
SCKE
SCAS
SCLK
20
BA0
21
BA1
A18
R12
10K
402
16
WE
17
CAS
18
RAS
SRAS
CS
CKE
19
37
38
CLK
R13
10K
402
R14
10K
402
R15
10K
402
R16
10K
402
A19
SMS
A0
F2
A1
E2
A2
C2
A3
D2
A4
F3
A5
E3
A6
C3
A7
D6
A8
C6
A9
E6
A10
F6
A11
D7
A12
C7
A13
E7
A14
F7
A15
G7
A16
D3
A17
E4
A18
F5
A19
F4
A20
SCLK
D5
U22
4
H7
2
6
12GND1
28GND2
41GND3
46GND4
52GND5
54GND6
GND7
ON
MT48LC32M8A2
TSOP54
2
AMS1
3
AMS2
8
1
C4
U49
4
H2
2
6
1
4
5
J2
SN74LVC1G08
SOT23-5
U39
4
4
AMS3
SN74LVC1G08
SOT23-5
7
3
MT48LC32M8A2
TSOP54
1
AMS0
2
ABE1
39
DQM
1
DQM
6
12GND1
28GND2
41GND3
46GND4
52GND5
54GND6
GND7
SW6
39
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15/A-1
D0
K3
D1
G4
D2
K4
D3
K5
D4
G5
D5
K6
D6
G6
D7
H3
D8
J3
D9
H4
D10
J4
D11
H5
D12
J6
D13
H6
D14
J7
D15
2
SCKE
1
ABE0
1
G3
C5
2
D4
SN74AHC1G00
SOT23-5
SWT018
DIP4
FLASH Enable Switch
1
RESET
BYTE
RY/BY~
CE
OE
WE
VPP/WP~
M29W320DB
TFBGA63_80
U48
K2
K7GND1
GND2
U15
1
VDD13
VDD29
VDD314
VDD427
VDD543
VDD649
VDD7
1
VDD13
VDD29
VDD314
VDD427
VDD543
VDD649
VDD7
A2
G2
J5
3V_BP
VDD
3V_BP
4
2
SN74LVC1G08
SOT23-5
ARE
64 MB SDRAM
(8M x 8 x 4 banks) x 2 chips
AWE
JP10
1
PG14_FLASH_UNPROTECT
4 MB FLASH
(2M x 16)
2
3
RESET
IDC3X1
3X1
3
3
SHORTING
JUMPER
DEFAULT=2 & 3
FLASH Unprotect Jumper
3V_BP
3V_BP
3V_BP
C35
0.01UF
402
C30
0.01UF
402
C31
0.01UF
402
C32
0.01UF
402
C33
0.01UF
402
C34
0.01UF
402
C42
0.01UF
402
C43
0.01UF
402
C41
0.01UF
402
C44
0.01UF
402
C45
0.01UF
402
C46
0.01UF
402
C37
0.01UF
402
C38
0.01UF
402
C39
0.01UF
402
C40
0.01UF
402
C36
0.01UF
402
ANALOG
DEVICES
4
Approvals
Date
Engineering
A
B
C
Size
Board No.
C
Date
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF537 EZ-KIT LITE
SDRAM AND FLASH
Title
Drawn
Checked
20 Cotton Road
Rev
A0188-2004
1.1
Sheet
1-21-2005_16:26
D
3
of
11
A
B
C
D
3.3V
R169
10K
402
C216
10UF
805
FER3
600
603
1
R20
100K
0603
R21
5.76K
0603
1
PF12_AUDIO_RESET
R28
5.76K
0603
U47
4
AUDIO_RESET
2
RESET
1
SN74LVC1G08
SOT23-5
C71
120PF
0603
C53
100PF
0603
3.3V
R23
237
0603
U29
2
1
AGND
3
LMV722M
SOIC8
R17
5.76K
0603
C70
0.001UF
0603
R35
5.76K
0603
C68
100PF
0603
LABEL "LINE IN"
J9
ADC LEFT
ADC
C47
120PF
0603
1
5
LEFT_IN
AGND
AMP_LEFT_IN
4
R32
750K
0603
LOOPBACK_LEFT
3
RIGHT_IN
C67
0.001UF
0603
13
12
7
AMP_RIGHT_IN
CON001
STEREO_JACK
11
5
10
LMV722M
SOIC8
2
18
AGND
19
16
C215
10UF
805
FER4
600
603
R34
5.76K
0603
R22
5.76K
0603
17
CASC
CAPLP
XCTRL
VINLP
VINLN
VINRP
C49
120PF
0603
24
AUDIO_RESET
21
8
2
CCLK/{256~/512}
3
COUT/{DF0}
4
CIN/{DF1}
5
CLATCH/{M~/S}
2
ADC_M~/S
VINRN
CAPRN
CAPRP
LRCLK
BCLK
DOUT
AGND
C52
100PF
0603
CAPLN
1
MCLK
MCLK
R26
100K
0603
R25
10K
402
U33
R33
237
0603
U29
6
LOOPBACK_RIGHT
2
R24
10K
402
RESET
DIN
28
PJ7_RFS0_S
27
PJ6_RSCLK0_S
26
PJ8_DR0PRI_S
25
14
VREF
VREF_AUDIO
AD1871YRS
SSOP28
2
C64
0.1UF
603
R31
237
0603
U30
C54
100PF
0603
1
AGND
C214
10UF
805
C61
100PF
0603
3
LMV722M
SOIC8
R19
5.76K
0603
C69
0.001UF
0603
R18
5.76K
0603
C51
0.01UF
0603
C65
100PF
0603
C50
0.01UF
0603
C63
0.01UF
0603
C62
0.01UF
0603
AGND
ADC RIGHT
C48
120PF
0603
AGND
R30
750K
0603
3
3
AGND
SW7
1
15
3
14
4
13
5
12
6
11
7
10
3
PJ7_RFS0
LMV722M
SOIC8
4
PJ9_TSCLK0
5
PJ10_TFS0
6
AGND
7
8
8
ADC_M~/S
16
2
2
PJ6_RSCLK0
5
VREF_AUDIO
1
PJ8_DR0PRI
7
ON
R29
237
0603
U30
6
C66
0.001UF
0603
PJ8_DR0PRI_S
PJ6_RSCLK0_S
PJ7_RFS0_S
PJ9_TSCLK0_S
PJ10_TFS0_S
9
SWT016
DIP8
A5V
A5V
5V
3.3V
5V
FER2
Audio Selection Switch
R27
0
0603
C55
0.1UF
402
C56
0.1UF
402
C57
0.1UF
402
C212
10UF
805
C213
10UF
805
C59
0.1UF
402
C60
0.1UF
402
AGND
4
AGND
ANALOG
DEVICES
AGND
LMV722
LMV722
AD1871
AD1871
AD1871
Approvals
Date
Engineering
A
B
C
Size
Board No.
C
Date
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF537 EZ-KIT LITE
ADC AND AUDIO IN
Title
Drawn
Checked
20 Cotton Road
Rev
A0188-2004
1.1
Sheet
1-21-2005_16:26
D
4
of
11
A
B
C
D
1
1
C81
100PF
0603
R43
5.49K
0603
R40
11K
0603
R44
3.32K
0603
3.3V
DAC LEFT
DAC
R54
33
402
U4
1
OE
OUT
3
12.288MHZ
OSC003
PJ9_TSCLK0_S
PJ10_TFS0_S
PJ11_DT0PRI
2
3.3V
4
CCLK
3
CLATCH
5
CDATA
CT2
68UF
CAP003
U31
R50
604
0603
1
3
U38
10
96/48~
6
384/256~
7
X2MCLK
2
MCLK
26
BCLK
25
LRCLK
27
SDATA
2
C77
100PF
0603
MCLK
R53
10K
0603
C79
330PF
0603
R42
5.49K
0603
16
OUTL17
OUTL+
13
OUTR12
OUTR+
C80
680PF
0603
LMV722M
SOIC8
R45
1.65K
0603
R52
2.74K
0603
C82
220PF
0603
14
FILTR
19
FILTB
LABEL "LINE OUT"
AGND
C218
10UF
805
8
ZEROR
C87
0.1UF
603
C217
10UF
805
R47
5.49K
0603
5
LEFT_OUT
C85
100PF
0603
4
LOOPBACK_LEFT
3
LOOPBACK_RIGHT
AUDIO_RESET
R37
10K
0603
2
J10
1
22
ZEROL
R41
49.9K
0603
C78
2200PF
0603
24
RESET
R39
11K
0603
9
DEEMP
23
MUTE
R48
3.32K
0603
CON001
STEREO_JACK
C84
330PF
0603
AGND
21
IDPM0
20
IDPM1
2
RIGHT_OUT
6
CT1
68UF
CAP003
U31
C75
100PF
0603
R51
604
0603
7
5
AD1854JRS
SSOP28
R46
5.49K
0603
DAC RIGHT
C83
680PF
0603
LMV722M
SOIC8
R49
1.65K
0603
R36
2.74K
0603
C76
2200PF
0603
R38
49.9K
0603
C86
220PF
0603
AGND
3
3
VREF_AUDIO
5V
A5V
C72
0.1UF
603
C73
0.1UF
603
C74
0.1UF
603
AGND
AD1854
AD1854
ANALOG
DEVICES
LMV722
4
Approvals
Date
Engineering
A
B
C
Size
Board No.
C
Date
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF537 EZ-KIT LITE
DAC AND AUDIO OUT
Title
Drawn
Checked
20 Cotton Road
Rev
A0188-2004
1.1
Sheet
1-21-2005_16:26
D
5
of
11
A
B
C
D
3.3V
5V
1
2
2
PF15_CAN_STB~
6
7
14
6
4
5
4
PJ4_CAN_RX
8
3
3
PF13_CAN_ERR
1
ON
SW2
1
PF14_CAN_EN
EN
3
VDD
10
VBAT
U21
5
R79
10K
402
VIO
R80
10K
402
3.3V
7
INH
9
WAKE
STB
C106
100PF
0603
R65
62.0
0603
R81
DNP
0603
R55
10
0603
J11
1
8
ERR
2
1
13
CANH
11
SPLIT
12
CANL
TXD
SWT018
DIP4
4
RXD
CAN Enable Switch
2
GND
PJ5_CAN_TX
TJA1041
SOIC14
1
3
4
C90
4.7NF
0603
R66
62.0
0603
CON039
4PIN
R62
10
0603
LABEL "CAN"
J5
1
2
3
3.3V
5V
3V_BP
C94
100PF
0603
4
CON039
4PIN
C103
0.01UF
402
Ethernet Loopback Jumper
CAN
C104
0.01UF
402
JP11
1
2
3
4
LABEL "ETHERNET"
FER5
600
603
3V_BP
IDC2X2
2X2
DNP
FER9
600
603
R206
1.5K
603
ACTIVITY
R76
330
0603
J4
R67
49.9
0603
LAN_AVDD
R68
49.9
0603
R70
49.9
0603
R71
49.9
0603
R69
10
0603
13
14
2
2
PJ1_MDIO
PJ0_MDC
PH11_ERXD3
PH10_ERXD2
PH9_ERXD1
PH8_ERXD0
PH12_ERXDV
PH13_ERXCLK
PH14_ERXER
PH5_TXCLK
PH4_ETXEN
LAN_AVDD
PH0_ETXD0
3V_BP
PH1_ETXD1
PH2_ETXD2
PH3_ETXD3
C102
0.01UF
402
C99
0.01UF
402
C98
0.01UF
402
C97
0.01UF
402
PH7_COL
PH15_CRS
13
53
AVDD157
AVDD261
AVDD363
AVDD4
26
MDIO
27
MDC
29
RXD3
30
RXD2
31
RXD1
32
RXD0
33
RX_DV
34
RX_CLK
35
RX_ER
37
TX_ER
38
TX_CLK
39
TX_EN
41
TXD0
42
TXD1
44
TXD2
45
TXD3
47
COL
48
CRS
VREG
U14
8
VDD118
VDD243
VDD3
RJ45
XMIT
51
TXP
50
TXN
7
TX+
1
1
TXCT
8
TX-
2
RX+
9
RXCT
3
RX-
6
5
VCC-
4
6
VCC+
5
C91
6.8NF
0603
55
RXP
54
RXN
C92
6.8NF
0603
16
SPEED100/PHYAD0
17
LINKON/PHYAD1
19
ACTIVITY/PHYAD2
20
FDUPLEX/PHYAD3
2
GPO1/PHYAD4
2
RCV
C93
0.01UF
0603
46
INT
C95
0.022UF
805
PH6_PHYINT
POE_VCCPOE_VCC+
1
3
GPO0
7
3
GPO2
8
3
12
REG_EN
R72
10K
402
R73
10K
402
R74
10K
402
3
14
VDD_CORE
9
TEST0
10
TEST1
LINKON
ACTIVITY
R97
10K
402
11
CLK_FREQ
3V_BP
R177
10K
402
R178
10K
402
R185
10K
402
R186
10K
402
3V_BP
10
SHIELD
SW3
8
4
2
7
5
3
6
6
4
5
1
ON
1
2
C101
0.01UF
402
C100
0.01UF
402
4
C96
0.01UF
402
3
Ethernet Mode Select Switch
MODE0
MODE1
SHGND
MODE2
15
16
CON033
16PIN
SWT018
DIP4
R75
330
0603
25
RESET
LINKON
RESET
23
CLKIN/XTAL1
22
XTAL2
BUF_XTAL
C219
10UF
805
C105
0.01UF
402
4
R77
12.4K
0603
LAN83C185
TQFP64
ANALOG
DEVICES
49
52AGND1
58AGND2
60AGND3
62AGND4
AGND5
R78
10K
402
7
15GND1
21GND2
24GND3
28GND4
36GND5
40GND6
GND7
59
EXRES1
TQFP64
LAN83C185
Approvals
Date
Engineering
A
B
C
Size
Board No.
C
Date
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF537 EZ-KIT LITE
ETHERNET AND CAN
Title
Drawn
Checked
20 Cotton Road
Rev
A0188-2004
1.1
Sheet
1-21-2005_16:26
D
6
of
11
A
B
C
D
U54
3V_BP
2
WS_P0_1
3
PF6_LED1
3V_BP
WS_P2_1
R100
100
805
3
1
SW13
SWT013
SPST-MOMENTARY
4
PF8_LED3
R179
10K
402
R6
10
0603
U37
WS_P3_1
RS_P0
PF9_LED4
74LVC14A
SOIC14
YA
4
I1A
I0B
YB
6
I1B
11
I0C
10
I1C
14
I0D
13
I1D
PF7_LED2
R87
10K
402
LABEL "PB1"
5
WS_P1_1
I0A
7
U36
YC
9
2
4
YD
12
6
8
1
S
15
E
ELVIS_SELECT
C222
1UF
805
U55
2
3
PF10_LED5
R88
10K
402
LABEL "PB2"
5
WS_P5_1
R101
100
805
5
SW12
SWT013
SPST-MOMENTARY
6
RS_P1
74LVC14A
SOIC14
C221
1UF
805
1
ON
1
1Y2
1A3
1Y3
1A4
1Y4
4
YB
YC
YD
2Y2
2Y3
2Y4
14
12
1
9
7
5
3V_BP
3
1
OE1
19
OE2
I1A
I0B
2Y1
16
LED6
AMBER-SMT
LED001
7
LED5
AMBER-SMT
LED001
LED4
AMBER-SMT
LED001
LED3
AMBER-SMT
LED001
LED2
AMBER-SMT
LED001
POWER
LED7
GREEN-SMT
LED001
LED1
AMBER-SMT
LED001
IDT74FCT3244APY
SSOP20
9
R83
330
0603
12
R91
330
0603
R92
330
0603
R93
330
0603
R94
330
0603
R95
330
0603
R96
330
0603
S
15
E
8
7
3
6
4
5
2
2
PF2_PB1
ADG774A
QSOP16
PF3_PB2
3
PF4_PB3
4
PF5_PB4
SWT018
DIP4
R89
10K
402
LABEL "PB3"
1A2
18
1
SW5
2
YA
I1B
11
I0C
10
I1C
14
I0D
13
I1D
R56
10
0603
U37
I0A
6
PF11_LED6
1Y1
11
2A1
13
2A2
15
2A3
17
2A4
ADG774A
QSOP16
WS_P4_1
1A1
2
Push Button Enable Switch
R103
100
805
R57
10
0603
U37
9
SW11
SWT013
SPST-MOMENTARY
8
RS_P2
3V_BP
74LVC14A
SOIC14
C220
1UF
805
SW16
4
2
3 4 5
5
6
C2 2
1 07
6
8
SWT019
ROTARY
BMODE1
R90
10K
402
LABEL "PB4"
R59
10
0603
U37
1
SW10
SWT013
SPST-MOMENTARY
2
RESET
LED8
RED-SMT
LED001
3
R8
10K
402
R9
10K
402
3V_BP
1
U50
4
POSITION
RESET
8
7
1
5
PFO
2
RESET
RESET
U58
4
RESET
SN74LVC1G08
SOT23-5
ADM708SAR
SOIC8
2
AS_P3_1
R5
10K
402
SN74LVC1G08
SOT23-5
11
74LVC14A
SOIC14
PG15_USB_IRQ
1
C211
0.01UF
402
JP12
1
1
BOOT FROM 16-BIT MEMORY
2
RESERVED
3
BOOT FROM SPI MEMORY
4
BOOT FROM SPI HOST
5
BOOT FROM SERIAL TWI MEMORY
6
BOOT FROM TWI HOST
7
BOOT FROM UART HOST
2
SN74LVC1G32
SOT23-5
IDC2X1
SHORTING
JUMPER
DEFAULT=NOT INSTALLED
Push Button Enable Switch
ANALOG
DEVICES
C225
0.01UF
402
Approvals
Date
Title
Drawn
IDT74FCT3244
QS3257
Checked
QS3257
Engineering
A
EXECUTE FROM 16-BIT EXTERNAL MEMORY
2
R205
10K
402
C108
0.01UF
402
U52
4
3V_BP
ADM708
0
10
PF7_LED2
74LVC14A
3
BOOT MODE
U37
12
74LVC14A
SOIC14
4
1
MR
4
PFI
SW9
SWT013
SPST-MOMENTARY
SOFT_RESET
C107
0.01UF
402
R86
10K
402
R182
10K
402
U27
C109
0.01UF
402
R85
10K
402
Boot Mode Select Switch
R181
10K
402
R98
330
0603
R7
10K
402
RESET
U37
BMODE0
RS_P3
C210
1UF
805
13
BMODE2
R84
10K
402
3V_BP
74LVC14A
SOIC14
R162
10K
402
3
4
2
C1
1
1
B
C
Size
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF537 EZ-KIT LITE
PUSH BUTTONS, LEDS AND BOOT MODE
Board No.
C
Date
20 Cotton Road
Rev
A0188-2004
1.1
Sheet
1-21-2005_16:26
D
7
of
11
A
B
C
R163
0
402
SW8
VDDINT
6
7
4
13
5
12
8
RG+
RG-
R160
10K
0603
6
6
11
7
10
8
9
ACH4+
ACH0+
Function Generator Switch
3
AD820
SOIC8
8
1
2
SWT017
DIP6
U11
7
IDC2X1
14
R102
10K
0603
C205
0.01UF
402
ELVIS Select Jumper
16
AMP_LEFT_IN
AMP_RIGHT_IN
1
LEFT_OUT
RIGHT_OUT
SWT016
DIP8
Core Current Measurement Jumper
AD623
USOIC8
ON
IN-
R61
0.1
0603
3
6
2
2
8
5
7
V+
4
V6
OUT
5
REF
IN+
1
5
4
3
SHORTING
JUMPER
DEFAULT=INSTALLED
15
SW1
1
ACH3+
3
U2
JP1
2
6
IDC2X1
9
5
FUNC_OUT
2
4
AMP_RIGHT_IN
2
DAC1
1
10
4
SHORTING
JUMPER
DEFAULT=NOT INSTALLED
3
3
JP7
DAC0
AMP_LEFT_IN
11
1
R58
90.9K
0603
12
2
2
RIGHT_IN
A5V
1
1
LEFT_IN
ON
ACH2+
1
VDDINT_SHUNT
D
Oscilloscope Select Switch
A5V
R60
11K
0603
C88
0.1UF
603
C202
0.01UF
402
ELVIS_5V
P16
1
2
3
4
AGND
U56
V_UNREG
PG0_ELVIS_TRIGGER_S
IDC2X2
2X2
P5
JP6
AGND
1
DSP CORE VOLTAGE & CURRENT
2
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
IDC2X1
SHORTING
JUMPER
DEFAULT=NOT INSTALLED
2
JP1
JP7
MODE
OFF
OFF
ELVIS DMM CURRENT MEASUREMENT
OFF
ON
DAQ DMM CURRENT MEASUREMENT
ON
OFF
BYPASS SHUNT CIRCUITS
ON
ON
NOT USED
RS_P2
RS_P0
ELVIS Voltage Selection Jumper
WS_P4_1
WS_P2_1
WS_P0_1
ELVIS_5V
A5V
R63
90.9K
0603
PG3__ELVIS_PF5_S
PG2_ELVIS_PF2_S
PG0_ELVIS_TRIGGER_S
VDDEXT_SHUNT
VDDEXT
U3
3
IN+
2
SHORTING
JUMPER
DEFAULT=INSTALLED
IN-
JP2
1
8
2
1
RG+
RG-
7
V+
4
V6
OUT
5
REF
2
U23
VDDINT
R159
10K
0603
6
ACH1+
3
AD820
SOIC8
ACH4+
ACH3+
ACH2+
ACH1+
ACH0+
IDC2X1
3
AD623
USOIC8
IO Current Measurement Jumper
R148
0.1
0603
C204
0.01UF
402
R64
10K
0603
A5V
R104
25.5K
0603
FUNC_OUT
INSTALL JUMPER TO BYPASS SHUNT
C89
0.1UF
603
VDDINT
VDDINT_SHUNT
C203
0.01UF
402
AGND
DAC0
+15_P_1
+15_P_2
+5_P_1
+5_P_2
+5_P_3
GND5
RS_P[6]
RS_P[4]
RS_P[2]
RS_P[0]
GND7
KEY2
KEY4
WS_P[6]_1
WS_P[4]_1
WS_P[2]_1
WS_P[0]_1
GND9
ID6
ID4
ID2
ID0
GND11
NC1
AS_P[6]_1
AS_P[4]_1
AS_P[2]_1
AS_P[0]_1
PB_PRES_1
UPDATE
CONVERT
SCANCLK
TRIG1_2
GATE1_1
GPCTR0_SOURCE
GPCTR0_OUT_1
GND13
VH_1
AIGND2
ACH7_1
ACH6_1
ACH5_1
ACH4
AIGND4
ACH3
ACH2
ACH1
ACH0
AISENSE_1
KEY6
KEY8
NC4
FG_SYNC_1
FG_SIG_1
GND14
NC5
ZL_1
ZH_1
NC8
DAC0_2
GND17
VDCA_1
-15_P_1
-15_P_2
GND1
GND2
GND3
GND4
RS_P[7]
RS_P[5]
RS_P[3]
RS_P[1]
GND6
KEY1
KEY3
WS_P[7]_1
WS_P[5]_1
WS_P[3]_1
WS_P[1]_1
GND8
ID7
ID5
ID3
ID1
GND10
AS_P[7]_1
AS_P[5]_1
AS_P[3]_1
AS_P[1]_1
+5V2
WFTRIG
STARTSCAN
EXTSRTOBE
TRIG2
SOURCE1_1
GPCRT1_OUT
GPCTR0_GATE
FREQ_OUT
GND12
VL_1
AIGND1
ACH15_1
ACH14_1
ACH13_1
ACH12
AIGND3
ACH11
ACH10
ACH9
ACH8
NC2
KEY5
KEY7
NC3
FM_1
AM_1
+5V3
GND15
NC6
ZM_1
NC7
DAC1_2
GND16
VDCB_1
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
PG1_ELVIS_PF1_S
PG2_ELVIS_PF2_S
RS_P3
RS_P1
WS_P5_1
WS_P3_1
WS_P1_1
ELVIS_SELECT
2
I0A
3
I1A
5
I0B
6
I1B
11
I0C
10
I1C
14
I0D
13
I1D
YA
YB
YC
4
7
9
PG0_ELVIS_TRIGGER
PG1_ELVIS_PF1
PG2_ELVIS_PF2
2
YD
12
1
S
15
E
ADG774A
QSOP16
ELVIS_5V
U57
PG3_ELVIS_PF5
AS_P3_1
PG4_ELVIS_PF6
PG4_ELVIS_PF6_S
PG5_ELVIS_PF7_S
PG5_ELVIS_PF7
PG1_ELVIS_PF1_S
2
I0A
3
I1A
5
I0B
6
I1B
11
I0C
10
I1C
14
I0D
13
I1D
YA
YB
YC
YD
4
7
9
PG3__ELVIS_PF5_S
PG4_ELVIS_PF6_S
PG5_ELVIS_PF7_S
12
1
S
15
E
ADG774A
QSOP16
3
PFI
3.3V
DAC1
PCI32B
C227
0.01UF
402
AGND
C226
0.01UF
402
DSP IO CURRENT
JP8
1
2
ELVIS_SELECT
AGND
IDC2X1
SHORTING
JUMPER
DEFAULT=NOT INSTALLED
ELVIS CONNECTOR
NI ELVIS ID 30 (0001 1110)
ELVIS Select Jumper
ANALOG
DEVICES
4
Approvals
Date
Engineering
A
B
C
Size
Board No.
C
Date
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF537 EZ-KIT LITE
ELVIS INTERFACE
Title
Drawn
Checked
20 Cotton Road
Rev
A0188-2004
1.1
Sheet
1-21-2005_16:26
D
8
of
11
A
B
C
D
EXPANSION INTERFACE (TYPE B)
5V_EI
1
3V_BP
5V_EI
3V_BP
1
All USB interface circuitry is considered proprietary and has
D[0:15]
been omitted from this schematic.
A[1:19]
1
2
1
J3
2
1
4
3
4
3
4
3
6
5
6
5
6
5
A3
8
7
A2
8
7
A5
10
9
A4
10
9
A7
12
11
A6
12
11
A1
PF11_LED6
PF12_AUDIO_RESET
PF0_UART0_TX
PF2_PB1
PF13_CAN_ERR
PF14_CAN_EN
PJ3_SDA
PH1_ETXD1
8
7
10
9
12
11
14
13
16
15
18
17
A9
14
13
A8
14
13
A11
16
15
A10
16
15
A13
18
17
A12
18
17
A15
20
19
A14
20
19
20
19
A17
22
21
A16
22
21
22
21
A19
24
23
A18
24
23
24
23
26
25
26
25
26
25
28
27
28
27
28
27
30
29
30
29
30
29
32
31
32
31
32
31
34
33
34
33
34
33
36
35
36
35
36
35
2
D1
D3
38
37
40
39
42
D5
41
44
D7
43
46
D9
3
J2
When designing your JTAG interface please refer to the
J1
2
45
48
47
PG9
PG15_USB_IRQ
PG14_FLASH_UNPROTECT
PG13
PJ5_CAN_TX
PJ11_DT0PRI
D0
52
51
D12
D15
54
53
D14
56
55
58
57
60
59
62
61
64
63
66
65
68
67
70
69
72
71
74
73
76
75
78
77
80
79
82
81
84
83
86
85
88
90
PF2_PB1
R168
0
0603
PG7_UART0_RTS
D8
D13
PF4_PB3
PG5_ELVIS_PF7
D6
D10
PF7_LED2
PJ9_TSCLK0
D4
49
POE_VCC+
PJ10_TFS0
D2
50
PG2_ELVIS_PF2
PF8_LED3
PF6_LED1
D11
PG0_ELVIS_TRIGGER
PF0_UART0_TX
PG9
38
37
40
39
42
44
46
48
41
43
45
47
PJ6_RSCLK0
PJ1_MDIO
39
42
44
PG4_ELVIS_PF6
46
PG6_UART0_CTS
48
PG8
71
72
71
74
73
74
73
76
75
76
75
78
77
78
77
80
79
80
79
82
81
82
81
84
83
84
83
86
85
86
85
87
88
87
88
87
89
90
89
90
89
SA10
SWE
45X2
CON019
PF14_CAN_EN
PF2_PB1
AMS3
AMS2
AMS1
AMS0
ARDY
ARE
ABE1
SCKE
SCAS
SCLK
45X2
CON019
3V_BP
PH0_ETXD0
PH2_ETXD2
PH4_ETXEN
PF6_LED1
R105
10K
0603
EMULATOR_SELECT
PH6_PHYINT
P4
PH8_ERXD0
1
2
PH10_ERXD2
3
4
PH12_ERXDV
5
6
PH14_ERXER
7
8
PJ0_MDC
9
10
11
12
13
14
EMULATOR_EMU
EMULATOR_TMS
EMULATOR_TCK
EMULATOR_TRST
EMULATOR_TDI
EMULATOR_TDO
IDC7X2
7X2
3
BR
BG
BGH
45X2
CON019
4
Approvals
Date
Checked
Engineering
C
Size
Board No.
C
Date
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF537 EZ-KIT LITE
EXPANSION INTERFACE
Title
Drawn
B
2
BUF_XTAL
ANALOG
DEVICES
A
DSP JTAG HEADER
47
69
PG14_FLASH_UNPROTECT
PJ2_SCL
45
67
PG12
PF3_PB2
43
70
PG10
http://www.analog.com
PF1_UART0_RX
41
68
PF3_PB2
72
PH15_CRS
37
40
65
PF5_PB4
69
PJ7_RFS0
38
63
SRAS
67
70
PH13_ERXCLK
66
PF6_LED1
68
PJ8_DR0PRI
PH11_ERXD3
64
ABE0
65
PJ4_CAN_RX
61
POE_VCC-
63
66
PH9_ERXD1
62
PG3_ELVIS_PF5
64
PG10
59
SMS
61
PH7_COL
57
PG1_ELVIS_PF1
62
PG11
60
PF15_CAN_STB~
59
RESET
58
AWE
57
60
PG12
55
AOE
58
RESET
53
ABE0
55
PG8
56
ABE1
53
56
PF9_LED4
54
PF3_PB2
54
PF7_LED2
51
PF4_PB3
51
PF10_LED5
52
PG15_USB_IRQ
52
NMI
49
PG13
49
PH5_TXCLK
50
PG11
50
PH3_ETXD3
Engineer to Engineer Note EE-68 which can be found at
Rev
A0188-2004
1.1
Sheet
1-21-2005_16:26
D
9
of
11
A
B
5V
3.3V
5V
V_UNREG
PJ8_DR0PRI
1
PJ4_CAN_RX
PJ5_CAN_TX
PJ11_DT0PRI
PJ6_RSCLK0
PF11_LED6
PF12_AUDIO_RESET
PF13_CAN_ERR
PJ3_SDA
PJ2_SCL
P7
2
1
4
3
4
3
6
5
6
5
8
7
8
7
10
9
10
9
12
11
12
11
14
13
14
13
16
15
16
15
18
17
18
17
20
19
20
19
22
21
22
21
24
23
24
23
26
25
26
25
28
27
28
27
30
29
30
29
32
31
32
31
34
33
34
33
RESET
PG13
PJ7_RFS0
PG12
PG8
PJ10_TFS0
PG9
PG15_USB_IRQ
PG10
PG0_ELVIS_TRIGGER
PG1_ELVIS_PF1
PG2_ELVIS_PF2
PG3_ELVIS_PF5
PG4_ELVIS_PF6
PF11_LED6
PF12_AUDIO_RESET
PF13_CAN_ERR
PJ3_SDA
PJ2_SCL
PG5_ELVIS_PF7
PF9_LED4
PG6_UART0_CTS
PF8_LED3
PG7_UART0_RTS
PF7_LED2
IDC17X2
17X2
RESET
3V_BP
PG11
1
C112
0.1UF
402
PG14_FLASH_UNPROTECT
U32
C114
0.1UF
402
1
C1+
3
C1PG0_ELVIS_TRIGGER
PG1_ELVIS_PF1
4
C2+
5
C2-
C113
0.1UF
402
PG2_ELVIS_PF2
J6
2
V+
1
6
6
V-
2
7
PG3_ELVIS_PF5
PG4_ELVIS_PF6
PG5_ELVIS_PF7
PG6_UART0_CTS
PG7_UART0_RTS
11
PF0_UART0_TX
SW4
1
PG6_UART0_CTS
8
10
PF1_UART0_RX
2
7
12
3
6
PG7_UART0_RTS
IDC17X2
17X2
4
5
ON
1
4
P6
2
3
PF7_LED2
SPORT 1
2
PF8_LED3
3.3V
1
PF9_LED4
D
V_UNREG
SPORT 0
PJ9_TSCLK0
C
T1IN
T2IN
T1OUT
T2OUT
14
3
7
8
13
R1OUT
R1IN
9
8
R2OUT
R2IN
ADM3202ARN
SOIC16
4
9
5
C111
0.1UF
402
SWT018
DIP4
CON038
9PIN
UART Enable Switch
JP9
SERIAL PORT
(UART 0)
V_UNREG
1
2
IDC2X1
5V 3.3V
SHORTING
JUMPER
DEFAULT=NOT INSTALLED
2
PPI
2
UART 0 Loop Jumper
V_UNREG
PF15_CAN_STB~
PG0_ELVIS_TRIGGER
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
3.3V
5V
TWI
P10
PG2_ELVIS_PF2
PG4_ELVIS_PF6
PG6_UART0_CTS
PG8
PG10
PG12
PG14_FLASH_UNPROTECT
PF9_LED4
PF14_CAN_EN
RESET
PF11_LED6
PF12_AUDIO_RESET
PF13_CAN_ERR
3
P8
2
36
PJ3_SDA
PJ2_SCL
PG1_ELVIS_PF1
PG3_ELVIS_PF5
PG5_ELVIS_PF7
PJ3_SDA
PG7_UART0_RTS
PG9
PG11
PG13
PG15_USB_IRQ
PG0_ELVIS_TRIGGER
PG2_ELVIS_PF2
PG4_ELVIS_PF6
PG6_UART0_CTS
PF10_LED5
PF15_CAN_STB~
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
PJ2_SCL
RESET
PG1_ELVIS_PF1
PG3_ELVIS_PF5
V_UNREG
PG5_ELVIS_PF7
PG7_UART0_RTS
3.3V
SPI
IDC10X2
10X2
P9
2
1
PF8_LED3
4
3
PF7_LED2
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
PF9_LED4
PF12_AUDIO_RESET
35
38
37
40
39
5V
R204
DNP
402
PF13_CAN_ERR
PF14_CAN_EN
PJ11_DT0PRI
IDC20X2
20X2
PF6_LED1
PF4_PB3
3
PF11_LED6
RESET
PF10_LED5
R203
DNP
402
PJ10_TFS0
PF5_PB4
PJ5_CAN_TX
IDC10X2
10X2
3.3V
5V
5V
3.3V
UART 1
TIMERS
P12
P11
2
4
PF9_LED4
PF8_LED3
4
PF7_LED2
6
8
10
1
3
5
PF2_PB1
PF3_PB2
PF2_PB1
PF4_PB3
2
1
4
3
6
5
8
7
10
9
PF2_PB1
PF4_PB3
ANALOG
DEVICES
7
9
PF3_PB2
IDC5X2
5X2
IDC5X2
5X2
Approvals
Date
Engineering
A
B
C
Size
Board No.
C
Date
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF537 EZ-KIT LITE
STAMP CONNECTORS
Title
Drawn
Checked
20 Cotton Road
Rev
A0188-2004
1.1
Sheet
1-21-2005_16:26
D
10
of
11
A
B
C
5V_EI
3.3V
TP9
LABEL "3.3V_BP"
LABEL "7.5V"
F1
2.5A
FUS001
D4
2A
DO-214AA
FER7
CHOKE_COIL
4
3
1
2
V_UNREG
JP3
1
S2A_RECT
J7
R117
0
0603
VR1
1
C127
1000PF
402
2
1
3V_BP
D
CT7
10UF
C
C130
0.1UF
603
3
INPUT
2
2
OUTPUT
3
GND
1
ADP3338AKC-33
SOT-223
3
7.5V_POWER
CON005
2.5MM_JACK
C134
1UF
805
SHORTING
JUMPER
DEFAULT=1 & 2
IDC3X1
3X1
CT8
10UF
C
C133
0.1UF
603
3V Selection Jumper
1
C128
1000PF
402
V_UNREG
SHGND
U20
V_UNREG
DA
R183
10K
402
R112
200K
0603
C118
330PF
0603
R184
10K
402
R107
130K
0603
DB
C120
150PF
0603
DC
DD
R106
10K
0603
R119
4.7
0603
R110
10K
0603
8
7
C136
10UF
1210
6
5
LABEL "5V"
4
G
C116
68PF
0603
[email protected]
SA
SB
SC
U26
R113
34.8K
805
C135
4.7UF
0603
2
6
7
3
L2
10UH
IND005
C126
33000PF
0603
R114
200K
0603
C131
68000PF
0603
C129
33000PF
0603
C132
22000PF
0603
D1
MMBD4148W
200MA
SOT323
C123
0.1UF
603
DC
DD
SB
35
31
11
INTVCC2
SC
R111
10
0603
18
CS3
27
DRVH3
26
BST3
28
SW3
DA
DB
DC
DD
C124
0.1UF
603
ADJ/FX5~
14
ADJ/FX3~
SA
3.3V
17
FB3
SC
15
EAO3
C119
470PF
0603
16
EAN3
25
DRV2
24
FB2
23
COMP2/SD2~
U12
3
8
1
7
2
6
3
5
R108
75K
0603
R109
6.2K
0603
C121
330PF
0603
4
IRF7403
SOIC8
DNP
R120
25.5K
0603
DNP
R180
47.5K
0603
DNP
1
D8
10BQ040
SMB
1A
2
EI Voltage Selection Jumper
1
2
3
8
7
C138
10UF
1210
6
C115
10UF
1210
5
LABEL "3.3V"
1
[email protected]
3.3V
TP7
2
3
L3
10UH
IND005
U17
DA
C117
68PF
0603
DB
DD
ADP3025JRU
TSSOP38
8
CT3
220UF
D2E
7
6
2
1
D9
10BQ040
SMB
1A
3
5
4
G
SA
C201
33PF
0603
DNP
C58
270PF
805
DNP
5
SI4820DY
SOIC8
DC
CT6
33UF
B
R121
DNP 51.1K
0603
DNP
CT4
220UF
D2E
6
4
G
SB
5
7
SHORTING
JUMPER
DEFAULT=INSTALLED
U18
29
DRVL3
2
SI4820DY
SOIC8
D2
MMBD4148W
200MA
SOT323
C122
4.7UF
0805
8
4
G
SA
10
CLSET3
13
SS3
R116
200K
0603
DB
SS5
INTVCC1
2
2X1
DA
2
1
CS5
37
DRVH5
38
BST5
36
SW5
22
CPOR
8
REF
12
SYNC
9
AGND
32
PGND2
JP5
1
U19
EAN5
DRVL5
TP8
IDC2X1
3
FB5
5V_EI
2
4
EAO5
CLSET5
5V
1
SI4820DY
SOIC8
30
VIN
33
SD
34
PGND
19
PFI
20
PFO
21
PWRGD
C137
10UF
1210
SB
SC
1
2
3
SI4820DY
SOIC8
LABEL "GND"
3V_BP
VDDINT_SHUNT
TP10
VROUT
JP4
TP3
TP4
TP5
TP6
R115
0
0603
1
U28
4
TP2
LABEL "VDDINT"
R118
0
0603
3V_BP
R207
10K
402
VDDEXT_SHUNT
L1
10UH
IND001
1
5
2
6
3
7
4
8
NDS8434A
SO-8
2
3
IDC3X1
3X1
3
1
D5
ZHCS1000
SOT23D
1A
CT5
68UF
D
ANALOG
DEVICES
SHORTING
JUMPER
DEFAULT=2 & 3
Core Voltage Selection Jumper
C125
0.1UF
603
Approvals
Date
Engineering
A
B
C
Size
Board No.
C
Date
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF537 EZ-KIT LITE
POWER
Title
Drawn
Checked
20 Cotton Road
Rev
A0188-2004
1.1
Sheet
1-21-2005_16:26
D
11
of
11
I
INDEX
A
AD1854, 1-12
AD1871, 1-12
ADSP-BF537 processor
audio interface (SPORT0), 2-3
boot modes, 2-13
clock out (CLK OUT), 2-3
core voltage, 2-2
Ethernet MAC peripheral, 1-11
ETXD/ERXD signals, 2-6
External Bus Interface Unit (EBIU), 2-3
general-purpose IO pins, 2-4, 2-9, 2-10, 2-11,
2-12, 2-21
input clock, 2-3
internal memory (SRAM), 1-6
IO voltage, 2-2
memory select pins, 1-6
peripheral ports, xv
PPI signals, 2-5
programmable flag pins (PFs), 1-13, 2-20
real time clock (RTC), 2-3
SPI signals, 2-5
SPORT0, 1-12
TMR signals, 2-4
UART1 signals, 2-4
~AMS0-3, flash select pins, 1-6, 1-9, 2-3, 2-11
ASYNC, external memory, 1-7
audio
applications, xv
circuit, 1-12, 2-3, 2-15
connectors (J9-10), 2-23
DAC/CAD (see also AD1854 & AD1871)
enable (SW7) switch, 2-12
input configuration switch (SW8), 2-16
interface, see also SPORT0 interface, 2-3
reset (PF12), 2-5
B
background telemetry channel (BTC), 1-14
bill of materials, A-1
boot
modes, 2-13
mode select switch (SW16), 2-13
breakpoints, restrictions, 1-18
C
clock frequency, 1-8, 1-9
COL signal, 2-6
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
I-1
INDEX
connectors, 1-4, 2-22
DB9 (UART), 2-7
J11 (CAN), 2-23
J1-3 (expansion), 2-3, 2-8, 2-25
J4 (ethernet), 2-23
J5 (CAN), 2-23
J6 (RS232), 2-24
J7 (power), 2-24
J9-10 (audio), 2-23
P10 (TWI), 2-27
P11 (timers), 2-27
P12 (UART1), 2-28
P4 (JTAG), 2-8, 2-25
P6 (SPOT0), 1-12
P6 (SPOTR0), 2-3
P7 (SPORT1), 2-26
P8 (PPI), 2-26
P9 (SPI), 2-4, 2-27
PJ4 (CAN), 1-10
PJ5 (CAN), 1-10
SPORT0 (P6), 2-26
contents, EZ-KIT Lite package, 1-2
Controller Area Network (CAN)
connectors (J5, J11), 2-23
enable switch (SW2), 2-9
interface, 1-10
signals, 2-5, 2-10
transceiver, 1-10
core current measurement jumpers (JP1, JP7),
2-16
customer support, xvii
EBIU_SDBCTL, 1-8
EBIU_SDGCTL, 1-8
EBIU_SDRRC, 1-8
ELVIS interface, 1-11, 2-15, 2-16
select jumper (JP8), 2-18
signals, 2-5
voltage select jumper (JP6), 2-17
enable control input (EN), 1-10
enabling debugger, 1-18
error/power indication output (ERR), 1-10
ERXD signals, 2-6
ethernet
connector (J4), 2-23
interface, 1-11, 2-6
select switch (SW3), 2-10
ETXD signals, 2-6
evaluation license restrictions, 1-6
example programs, 1-13
expansion interface, 1-12, 2-3, 2-4, 2-7, 2-11,
2-25
voltage select jumper (JP5), 2-14
external bus interface unit (EBIU), 2-3
external memory, 1-7, 2-3, 2-8
ASYNC memory banks 0-3, 1-7
flash, see flash memory
SDRAM, see SDRAM
EZ-KIT Lite board
architecture, 2-2
features, xiii
F
D
data acquisition (DAQ) device, 1-12, 2-17
DB9 (UART) connector, 2-7
DIP switches
see SW
disabling interrupts, 1-18
I-2
E
features, EZ-KIT Lite board, xiii
flag pins, see programmable flags (PFs), 2-4
flash memory, xiv, 1-9, 2-3, 2-13
enable (SW6) switch, 2-11
frame sync signals, 1-12
frequency, 1-8, 1-9
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
INDEX
G
general-purpose IO, 1-13
H
Help, online, xxii
I
IEEE 802.3-2002 standard, 1-11
interfaces
audio, 1-12
Controller Area Network (CAN), 1-10
ELVIS, 1-11
Ethernet, 1-11
expansion (J1-3), 2-25
graphical user interface (GUI), 1-14
SDRAM, 1-8
internal memory, 1-7, 2-8
core MMRs, 1-7
data bank A SRAM, 1-7
data bank A SRAM/CACHE, 1-7
data bank B SRAM, 1-7
data bank B SRAM/CACHE, 1-7
instruction bank A SRAM, 1-7
instruction bank B SRAM, 1-7
instruction SRAM/CACHE, 1-7
reserved, 1-7
scratch pad SRAM, 1-7
system MMRs, 1-7
internal regulator, 2-2
IO
current measurement jumper (JP2), 2-17
voltage, 2-2
J
JTAG
connector (P4), 2-25
emulation port, 2-8
jumpers, 1-4, 2-9
JP10 (flash unprotect), 1-10
JP1 (core current), 2-16
JP2 (IO current), 2-17
JP3 (power), 2-13
JP4 (voltage select), 2-13
JP5 (expansion voltage), 2-14
JP6 (ELVIS voltage), 2-17
JP7 (core current), 2-16
JP8 (ELVIS select), 2-18
JP9 (UART), 2-15
L
LabVIEW virtual instruments, 1-12
LEDs, 1-4, 1-13, 2-19
LED10 (USB monitor), 1-5, 2-21
LED1-6 (PF6-11), 2-5, 2-21
LED7 (power), 2-20
LED8-9 (reset), 2-20
M
Medium Access Controller (MAC), 1-11
address, 1-7, 1-10
memory, 1-8
flash, configuration, 1-10
map, 1-6
SDRAM, configuration, 1-8
select pins, see ~AMS0-3 & ~SMS0
N
notation conventions, xxv
O
oscilloscope, 2-15
configuration switch (SW1), 2-15
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
I-3
INDEX
P
S
package contents, 1-2
PG0-15 pins, 2-5
PH0-15 signals, 2-6
power
connector (J7), 2-24
LED (LED7), 2-20
regulator circuit, 2-13, 2-14
select jumper (JP3), 2-13
specifications, 2-24
supply, 2-24
Power-over-Ethernet (PoE), 1-11, 2-13, 2-14
PPI connector (P8), 2-26
programmable flags (PFs), 2-4
PF0-1 (UART), 2-4
PF12 (audio), 2-5
PF13-15 (CAN), 1-10, 2-5
PF2-5, 1-13, 2-4, 2-20
PF6-11 (IO), 2-5, 2-21
push buttons, 2-19, 2-20
see also switches
SCLK, 1-8, 1-9
SDRAM, xiv, 1-6, 1-7, 1-8, 1-9, 2-3
serial clock (SCL), 1-8
Serial Peripheral Interconnect (SPI), 2-4
connector (P9), 2-27
setting
EZ-KIT Lite hardware, 1-3
target options, 1-16
~SMS0, SDRAM select pin, 1-6, 2-3
SMSC device, 1-11
software breakpoints, 1-18
SPORT0
connector (P6), 2-26
interface, xv, 1-12, 2-3
SPORT1
connector (P7), 2-26
standby control input (~STB), 1-10
starting EZ-KIT Lite, 1-5
stereo input/output channels, 1-12
switches, 2-9
see also push buttons
SW10-13 (PF2-5), 2-4, 2-20
SW16 (boot mode select) switch, 2-13
SW1 (audio/oscilloscope) switch, 2-15
SW2 (CAN enable) switch, 1-10, 2-9
SW3 (Ethernet) switch, 2-10
SW4 (UART) switch, 2-10
SW5 (push button enable) DIP switch, 1-13,
2-11, 2-20
SW6 (flash enable) switch, 1-9, 2-11
SW7 (audio enable) switch, 1-12, 2-12
SW8 (audio input) switch, 2-16
SW9 (reset), 2-19
system
architecture, EZ-KIT Lite board, 2-2
clock, 1-8
R
receive data output (RXD), 1-10
registering, this product, 1-3
regulators, 2-2
reset
cycles counters on run, 1-17
options, 1-16
processor, 2-20
push button (SW9), 2-19
service routines, 1-15
values, 1-18
RJ45 connector, 1-11
RS232 connector (J6), 2-24
I-4
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
INDEX
T
target options
dialog box, 1-16
miscellaneous, 1-17
on emulator exit, 1-17
reset, 1-16
timers connector (P11), 2-27
trace
buffer, 1-14, 1-15
destination, 1-15
instruction addresses, 1-15
number, 1-15
source, 1-15
Trace window, 1-14, 1-15
transmit data input (TXD), 1-10
TWI connector (P10), 2-27
two-wire interface (TWI), 1-12, 2-27
U
UART
enable switch (SW4), 2-10
loop jumper (JP9), 2-15
port, 2-7
UART0
signals, 2-6
transmit/receive pins, 2-4
UART1 connector (P12), 2-28
Universal Asynchronous Receiver Transmitter
(UART), xiv, xv
USB
bus power, 2-6, 2-13, 2-14
cable, 1-3
connector (P7), 2-24
interface, 2-8, 2-25
interface chip, 2-19, 2-20
monitor LED (LED10), 2-21
USB-LAN EZ-Extender, 1-11, 2-13, 2-14
user LEDs (LED1-6), 2-21
V
validating memory writes, 1-17
VisualDSP++
documentation, xxiii
interface, 1-14
online Help, xxii
voltage
regulators, 2-2
select jumper (JP4), 2-13
X
XML
file, 1-18
reset values, 1-18
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
I-5
INDEX
I-6
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
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