Datasheet

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ams AG
The technical content of this austriamicrosystems datasheet is still valid.
Contact information:
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8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
e-Mail: [email protected]
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AS3517 V17
Data Sheet, Confidential
Data Sheet, Confidential
AS3517
Stereo Audio Codec with enhanced System Power Management
• Power Management
– step down for CPU core (0.65V-3.4V, 250mA)
– step down for peripheral (0.65V-3.4V, 250mA)
– step down for harddisk (0.65V-3.4V, 500mA)
– step up for backlight (15V (25V), 38mA),
– LDO for digital supply (2.9V, 200mA)
– LDO for analog supply (2.9V, 200mA)
– LDO for peripherals (1.2V-3.5V, 200mA)
– LDO for peripherals (1.2V-3.5V, 200mA)
– LDO for RTC (1.0V-2.5V, 2mA)
– power supply supervision
– hibernation modes
– 5sec and 10sec emergency shut-down
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Further the device offers advanced power management
functions. All necessary ICs and peripherals in a Digital Audio
Player with flash or harddisk memory are supplied by the
AS3517. The different regulated supply voltages are
programmable via the serial control interface. The power
management block generates 11 different supply voltages out
of a single battery supply. CPU, NAND flash, SRAM, memory
cards, harddisk, LCD, LCD backlight, USB-HOST and USBOTG can be powered. AS3517 also contains a charger. The
single supply voltage may vary from 3.0V to 5.5V.
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The AS3517 is a low power stereo audio codec and is
designed for Portable Digital Audio Applications. It allows
playback and recording in CD quality. It has a variety of audio
inputs and outputs to directly connect electret microphones,
16Ω/32Ω headsets and auxiliary signal sources via a 10channel mixer. It only consumes 20mW in playback mode.
• High Efficiency Headphone Amplifier
– volume control via serial interface
– 32 steps @1.5dB and MUTE
– 2x60mW @16Ω driver capability
– headphone and over-current detection
– phantom ground eliminates large capacitors
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1 General Description
The AS3517 has an on-chip, phase locked loop (PLL)
controlled, clock generator. It generates 44.1kHz, 48kHz and
other sample rates defined in MP3, AAC, WMA, OGG VORBIS
etc. No additional external crystal or PLL is needed in slave
mode. Further the AS3517 has an independent 32kHz real time
clock (RTC) on chip which allows a complete power down of
the system CPU.
2 Key Features
• Multi-bit Sigma Delta Converters
– DAC: 94dB SNR (‘A’ weighted) @ 2.9V
– ADC: 90dB SNR (‘A’ weighted) @ 2.9V
– Sampling Frequency: 8-48kHz
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• 2 Microphone Inputs
– 3 gain pre-setting (28dB/34dB/40dB) and AGC
– 32 gain steps @1.5dB and MUTE
– supply for electret microphone
– microphone detection
– remote control by switch
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• 2 Line Inputs
– volume control via serial interface
– 32 steps @1.5dB and MUTE
– stereo or 2x mono or mono differential
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• Audio Mixer
– 10 channel input/output mixer with AGC
– mixes line inputs and microphones with DAC
– left and right channels independent
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• 2 Line Outputs
– volume control via serial interface
– 32 steps @1.5dB and MUTE
– 1Vp @10kΩ
– Stereo 2*5mW to 16ohm
– Differential 10mW to 32ohm (earpiece)
• Battery Charger
– automatic trickle charge (50mA)
– prog. constant current charging (50-460mA)
– prog. constant voltage charging (3.9V-4.25V)
• Real Time Clock
– ultra low power 32kHz oscillator
– 32bit RTC sec counter, 96 days auto wake-up
– selectable alarm (seconds or minutes)
– 128bit free SRAM for random settings
– 32kHz clock output to peripheral
• Auxiliary Oscillator (only for master clock mode)
– low power 12-24MHz oscillator
– master clock input/output (e.g. from/to CPU)
• General Purpose ADC
– 10bit resolution
– 21 inputs analog multiplexer
• Interfaces
– I²S digital audio interface and SPDIF
– 2 wire serial control interface
– reset pin, watchdog, power good pin
– PWM output
– 128bit unique ID (OTP)
– 30 different interrupts
• Package CTBGA81 [9.0x9.0x1.15mm] 0.8mm pitch
3 Application
Portable Digital Audio Player and Recorder
PDA, Smartphone
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
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AS3517 V17
Data Sheet, Confidential
4 Functional Overview
AS3517
USB
Host / OTG
PMU = Voltage Supply + Supply Supervision + Power-up + Hibernation
SPDIF Out
µController
Keys
De/Encoder
HD
PWM Out
DRM ID
Audio DAC
Reset & WD
Headphone
Amplifier
RTC
OSC/PLL
I²S
LCD
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MMC,
SD etc
Application Processor
Audio ADC
Microphone
Amplifier
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2w Interface
Line
Outputs
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SDRAM
Flash
Line
Inputs
FMRadio
PMU = Voltage Supply + Supply Supervision + Power-up + Hibernation
DC/DCs - LDOs
Charger
Voltage Supply
Digital Interface
3V-5V Battery
5V Charger
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Audio Signal
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
2 - 93
AS3517 V17
Data Sheet, Confidential
5 Block Diagram
AS3517 Block Diagram
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Figure 1
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
3 - 93
AS3517 V17
Data Sheet, Confidential
Contents
General Description ......................................................................................................................................... 1
Key Features.................................................................................................................................................... 1
Application ....................................................................................................................................................... 1
Functional Overview ........................................................................................................................................ 2
Block Diagram.................................................................................................................................................. 3
Pinout and Packaging ...................................................................................................................................... 6
6.1
Pin Description.......................................................................................................................................... 6
6.2
Ball Assignment ........................................................................................................................................ 8
6.2.1
CTBGA81 .......................................................................................................................................... 8
6.3
Package Drawings .................................................................................................................................... 9
6.3.1
CTBGA81 .......................................................................................................................................... 9
7 Ordering Information ...................................................................................................................................... 10
8 Absolute Maximum Ratings (Non-Operating)................................................................................................. 11
8.1
Operating Conditions .............................................................................................................................. 12
8.1.1
Supply Voltages............................................................................................................................... 12
8.1.2
Operating Currents .......................................................................................................................... 13
8.1.3
Temperature Range......................................................................................................................... 13
8.1.4
Audio Specification .......................................................................................................................... 14
9 Detailed Functional Description ..................................................................................................................... 16
9.1
Audio Functions ...................................................................................................................................... 16
9.1.1
Audio Line Inputs (2x)...................................................................................................................... 16
9.1.2
Microphone Inputs (2x) .................................................................................................................... 18
9.1.3
Audio Line Outputs (2x) ................................................................................................................... 20
9.1.4
Headphone Output .......................................................................................................................... 21
9.1.5
DAC, ADC and I2S Digital Audio Interface ...................................................................................... 23
9.1.6
Audio Output Mixer .......................................................................................................................... 28
9.1.7
2-Wire-Serial Control Interface ........................................................................................................ 29
9.2
Power Management Functions ............................................................................................................... 32
9.2.1
Low Drop Out Regulators ................................................................................................................ 32
9.2.2
DCDC Step-Down Converter (3x).................................................................................................... 35
9.2.3
Charger............................................................................................................................................ 39
9.2.4
15V Step-Up Converter ................................................................................................................... 41
9.2.5
USB VBUS Supply........................................................................................................................... 43
9.3
SYSTEM Functions ................................................................................................................................ 46
9.3.1
SYSTEM.......................................................................................................................................... 46
9.3.2
Hibernation ...................................................................................................................................... 49
9.3.3
Supervisor ....................................................................................................................................... 50
9.3.4
Interrupt Generation......................................................................................................................... 51
9.3.5
Real Time Clock .............................................................................................................................. 52
9.3.6
10-Bit ADC....................................................................................................................................... 53
9.3.7
Unique ID Code (64 bit OTP ROM) ................................................................................................. 54
9.4
Register Description ............................................................................................................................... 55
10
Copyright .................................................................................................................................................... 91
11
Disclaimer................................................................................................................................................... 93
12
Contact Information .................................................................................................................................... 93
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1
2
3
4
5
6
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
4 - 93
AS3517 V17
Data Sheet, Confidential
Revision History
Revision
0.99
1.0
Date
Owner
6.10.2006 pkm
12.10.2006 pkm
Description
Corrected version
Changed block diagram of DCDC15
Inserted register overview
Corrected some typos
1.1
26.1.2007
pkm
Corrected block diagram (DAC mute)
Corrected start-up sequence (VPROG1 and VPROG2 exchange)
6.4.2007
pkm
Added Typical Application Information
Changed chip version for V17
RTCT register reset corrected to RVDD-POR
USB & CHGIN 0ms de-bounce time changed to 8ms
24.9.2008
pkm
Updated marking and ordering information
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1.2
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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Revision 1v3
5 - 93
AS3517 V17
Data Sheet, Confidential
6 Pinout and Packaging
Table 1
Pinlist CTBGA81
PinName
AGND
AVDD
AVSS
BATTEMP
BVDD
BVDD
BVDDH
Type
Analog I/O
Supply
Supply
Analog I/O
Supply
Supply
Supply
A8
A4
B4
F2
F1
E1
C1
BVDDC1
BVDDC2
BVDDC3
BVDDR
CHG_IN
CHG_OUT
CN_GEXT
Supply
Supply
Supply
Supply
Analog Input
Analog Output
Digital output
C2
G3
H3
B7
B5
B3
A6
B6
A2
B2
G1
J2
H2
F3
C8
D9
A9
C9
B1
D7
D6
F8
F7
C7
C6
D8
E7
G4
A7
A5
A3
CP_CP
CSCL
CSDA
CVDD1
CVDD2
CVDD3
CVSS1
CVSS2
CVSS3
CVSS15
DVDD
DVSS
FVDD
HBT
HPCM
HPGND
HPL
HPR
ISINK
LIN1L
LIN1R
LIN2L
LIN2R
LOUT1L
LOUT1R
LOUT2L
LOUT2R
LRCLK
LXC1
LXC2
LXC3
Digital output
Digital input with pull up
Digital I/O with pull up
Analog Input
Analog Input
Analog Input
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Digital input with pull down
Analog Output
Analog I/O
Analog Output
Analog Output
Analog Output
Analog Input
Analog Input
Analog Input
Analog Input
Analog Output
Analog Output
Analog Output
Analog Output
Digital I/O with pull down
Digital output
Digital output
Digital output
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Function
Analog Reference Voltage (AVDD/2) buffer cap terminal
Analog Circuit VDD, connected to LDO1 on BGA substrate
Analog Circuit VSS
Charger Battery Temperature Sensor input (100kΩ NTC)
Positive (Battery) Supply Terminal, 5.5V max.
Positive (Battery) Supply Terminal, 5.5V max.
Positive (Battery) Supply Terminal of Headphone Amplifier, 5.5V
max.
Positive (Battery) Supply Terminal of DCDC1, 5.5V max.
Positive (Battery) Supply Terminal of DCDC2, 5.5V max.
Positive (Battery) Supply Terminal of DCDC3, 5.5V max.
RTC Positive (Battery) Supply terminal, 5.5V max
Charger Positive Supply Terminal, 5.5V max
Charger Output prog. for Ichg 50-400mA or Vchg 3.9-4.25V
USB charge pump CN of flying cap / Output to control USB-Host
DCDC N-Switch
USB charge pump CP of flying cap
Clock Input of two wire interface
Data I/O of two wire interface
CVDD1 and Feedback pin
CVDD2 and Feedback Pin
CVDD3 and Feedback Pin
CVDD1 StepDown Neg. Supply terminal
CVDD2 StepDown Neg. Supply terminal
CVDD3 Stepdown Neg. Supply terminal
DCDC15V Neg. Supply terminal
Digital Circuit VDD, connected to LDO2 on BGA substrate
Digital Circuit VSS
ADC&DAC Digital Circuit VDD (1.8-3.6V)
Heartbeat Input for CPU supervision
Headphone Common GND Output for DC-coupled speakers
Headphone Amplifier reference buffer cap terminal
Headphone Amplifier Output Left Channel
Headphone Amplifier Output Right Channel
DCDC15V Load Current Sink terminal (e.g. white LED)
Line Input 1 Left Channel
Line Input 1 Right Channel
Line Input 2 Left Channel
Line Input 2 Right Channel
Line Output Left Channel
Line Output Right Channel
Line Output Left Channel
Line Output Right Channel
I2S Left/Right Clock
CVDD1 StepUp switch output to coil
CVDD2 StepUp switch output to coil
CVDD3 StepUp switch output to coil
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Ball
G7
H7
J9
E2
D3
E3
B8
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Pin Description
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6.1
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
6 - 93
AS3517 V17
Data Sheet, Confidential
J6
J4
PWRUP
Q24M
Digital input with pull down
Digital output multiplexed
J3
Q32K
Digital output multiplexed
G2
F4
H4
G5
A1
D4
RVDD
SCLK
SDI
SDO
SW15
USBH_CSN
Analog Output
Digital I/O with pull down
Digital input with pull down
Digital output
Analog Output
Analog Input
C4
USBH_CSP
Analog Input
C5
G6
H6
H8
C3
USBH_PG
VPRG1
VPRG2
VREF
VBUS
Digital output
Analog Input
Analog Input
Analog I/O
Analog I/O
B9
J7
H1
H5
VSSH
XIN24
XIN32
XIRQ
Supply
Analog I/O
Analog I/O
Digital output
J8
J1
J5
XOUT24
XOUT32
XRES
Analog I/O
Analog I/O
Digital output open drain
Function
Microphone Input 1N
Microphone Input 1P
Microphone Supply 1 (2.95V) / Remote Input 1
Microphone Input 2N
Microphone Input 2P
Microphone Supply 2 (2.95V) / Remote Input 2
LDO3 Regulator Output
LDO4 Regulator Output
Power Good, SPDIF, PLL clock, PWM digital output.
Configurable as open drain or push pull.
Master CLK digital input (e.g. from CPU)
Power Up input
12-24MHz Clock output, PLL clock. Configurable as open drain
or push pull.
32kHz Clock output, SPDIF, PLL clock, PWM. Configurable as
open drain or push pull.
RTC Supply Regulator Output prog. to 1.0-2.5V
I2S Shift Clock
I2S Data Input to DAC
I2S Data output from ADC
DCDC15V switch terminal
USB-Host Step Up neg. Current sense terminal to 100mΩ
resistor
USB-Host Step Up pos. Current sense term. to 100mΩ resistor
(BVDD)
Output to control USB-Host DCDC high Side P-Switch
5 State Prog Input to define power up sequence
5 State Prog Input to define default regulator voltages
Analog Reference ( filtered AVDD) decoupling cap terminal
USB supply terminal for supervision and charge pump or StepUp
feedback
Headphone Amplifier Neg. Supply terminal
24MHz Oscillator Crystal terminal
32kHz RTC Oscillator Crystal terminal
Interrupt Request Output. Configurable as open drain or push
pull, active high or active low
24MHz Oscillator Crystal terminal
32kHz RTC Oscillator Crystal terminal
Reset Output
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Type
Analog Input
Analog Input
Analog I/O
Analog Input
Analog Input
Analog I/O
Analog Output
Analog Output
Digital I/O multiplexed
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PinName
MIC1N
MIC1P
MIC1S
MIC2N
MIC2P
MIC2S
PVDD1
PVDD2
PWGD
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Ball
H9
G9
G8
E9
F9
E8
D2
D1
F6
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
7 - 93
AS3517 V17
Data Sheet, Confidential
6.2
Ball Assignment
6.2.1
CTBGA81
Figure 2 Ball Assignment CTBGA81
2
3
4
5
6
7
8
9
A
SW15
CVSS3
LXC3
BVDDC2
LXC2
CVSS1
LXC1
BVDDC1
HPL
A
B
ISINK
CVSS15
CVDD3
BVDDC3
CVDD2
CVSS2
CVDD1
BVDDH
VSSH
B
C
CN_GEXT
CP_CP
VBUS
USBH_CSP USBH_PG
LOUT1R
LOUT1L
HPCM
HPR
C
D
PVDD2
PVDD1
BVDD
USBH_CSN
nc
LIN1R
LIN1L
LOUT2L
HPGND
D
E
CHG_OUT
BATTEMP
BVDD
nc
nc
nc
LOUT2R
MIC2S
MIC2N
E
F
CHG_IN
BVDDR
HBT
SCLK
nc
PWGD
LIN2R
LIN2L
MIC2P
F
G
DVDD
RVDD
CSCL
LRCLK
SDO
VPRG1
AGND
MIC1S
MIC1P
G
H
XIN32
FVDD
CSDA
SDI
XIRQ
VPRG2
AVDD
VREF
MIC1N
H
J
XOUT32
DVSS
Q32K
Q24M
XRES
PWRUP
XIN24
XOUT24
AVSS
J
1
2
3
4
5
6
7
8
9
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© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
8 - 93
AS3517 V17
Data Sheet, Confidential
6.3
6.3.1
Package Drawings
CTBGA81
Marking
A
A … for PB free
Dimensions
Y
Year
WWW
Working week assembly/packaging
ZZZ
Free choice
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Package Code AYWWZZZ
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Table 2
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Figure 3 CTBGA81 Marking
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Figure 4 CTBGA81 9x9mm 0.8mm pitch
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
9 - 93
AS3517 V17
Data Sheet, Confidential
7 Ordering Information
Version
Temperature Range
AS3517H-ECTP
V17
-20 to +85 °C
AS3517H-ECTS
V17
-20 to +85 °C
Package Type
CTBGA81; 9x9mm package size,
0.8mm ball pitch
CTBGA81; 9x9mm package size,
0.8mm ball pitch
Delivery Form
Tape & Reel
DryPack
Tray
DryPack
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Device ID
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
10 - 93
AS3517 V17
Data Sheet, Confidential
8 Absolute Maximum Ratings (Non-Operating)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The device should be
operated under recommended operating conditions.
Table 3
Absolute Maximum Ratings
Parameter
5V pins
Min
-0.5
Max
7.0
Unit
V
V IN_SW15
15V pin
-0.5
17
V
V IN_VSS
-0.5
0.5
V
V IN_DVDD
Voltage difference at VSS
terminals
3.3V pins with diode to DVDD
-0.5
5.0
DVDD+0.5
V
V IN_xDVDD
pins with no diode to DVDD
-0.5
7.0V
V
V IN_AVDD
3.3V pins with diode to AVDD
-0.5
5.0
AVDD+0.5
V
V IN_REG
voltage regulator pins with
diodes to BVDD
voltage regulator pin with
diode to BVDD
pins with diode to BVDD
-0.5
5.0
BVDD+0.5
3.6
BVDD+0.5
7.0
BVDD+0.5
100
V
mA
Norm: JEDEC 17
+/-1
kV
Norm: JEDEC JESD22-A114C
1000
mW
BGA81, T amb =70°C
5
85
%
Min
Max
260
Unit
°C
235
245
°C
30
45
s
V IN_BVDD
I scr
Input Current (latchup
immunity)
Electrostatic Discharge HBM
ESD
Pt
Total Power Dissipation (all
supplies and outputs)
Humidity non-condensing
H
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Parameter
-0.5
-100
Package Body Temperature
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T body
D well
-0.5
Applicable for pins HPR/L, CHG_OUT
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V
Soldering Conditions
Symbol
T peak
V
Applicable for pins CVSS3, CVSS15,
CVSS1, CVSS2, VSSH, AVSS, DVSS
Applicable for pins LRCK, SCLK, SDI,
VPRG1, VPRG2, BATTEMP, ISINK,
XIN32, XOUT32, XIN24, XOUT24, XIRQ,
XRES, PWGD, Q32K, Q24M, HBT
Applicable for pins
CSCL, CSDA, PWRUP
Applicable for pins HPCM, HPGND,
LOUT1L/R, LOUT2L/R, VREF, AGND,
LIN1L/R, LIN2L/R, MIC1P/N, MIC2P/N,
MIC1S, MIC2S
Applicable for pins AVDD, DVDD,
PVDD1/2, CVDD1/2/3, UVDD
Applicable for pins RVDD
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V IN_RVDD
Table 4
Note
Applicable for pins BVDD, BVDDH,
BVDDC1, BVDDC2, BVDDC3, BVDDR,
CHG_IN, VBUS
Applicable for pin SW15
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Symbol
V IN_5V
Solder Profile*
Note
Norm IPC/JEDEC J-STD-020C, reflects
moisture sensitivity level only
above 217 °C
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* austriamicrosystems AG strongly recommends to use underfill.
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
11 - 93
AS3517 V17
Data Sheet, Confidential
8.1
Operating Conditions
8.1.1
Supply Voltages
Table 5
Operating conditions for supply voltages
Max
5.5
Unit
V
4.0
5.5
V
CHG_IN
Charger Supply Voltage
4.5
5.5
V
DVDD
Digital Supply Voltage
2.8
3.6
V
Digital Audio Supply Voltage (LDO2)
AVDD
Analogue Supply Voltage
2.8
3.6
V
Analog Audio Supply Voltage (LDO1)
AGND
Analogue Ground Voltage
V DELTA -
Difference of Negative
Supplies
CVSS1, CVSS2, CVSS3,
CVSS15, VSSH, AVSS, DVSS
Difference of Positive Supplies
V
To achieve good performance, the
negative supply terminals should be
connected to low impedance ground
plane.
AVDD-DVDD
V DELTA +
Table 6
Parameter
Power-on Reset Activation
Level
V POR_OFF
Power-on Reset Release
Level
Power-on Hysterisis
LRCLK Frequency
Watchdog
Delay Time of pin PWRUP
Digital Output Driver
Capability (drive LOW)
Digital Output Driver
Capability (drive HIGH)
Internal Pull-up Current
Source
Digital Input Level LOW,
BVDD>3V
Digital Input Level HIGH,
BVDD>3V
Digital Input Level HIGH,
BVDD<=3V
Internal Pull-down resistor
Digital Input Level LOW
V POR_HY
f LRCLK_WD
t ON_DELAY
V DO_L
V DO_H
I PU
0.1
lv
-0.1
-0.25
0.25
V
ch
R PWRUP
V DI_L
ni
V PWRUP_H
V PWRUP_H
Min
Typ
2.15
Max
2.0
2
100
4.1
Te
V DI_H
Digital Input Level HIGH
Internal Pull-down current
source
Audio Clock Frequency
Unit
V
V
8
mV
kHz
0.3
ms
V
10
2.6
V
10
µA
0.5
Note
Power-on Reset activation
level when DVDD
decreases
Power-on Reset release
when DVDD increases
Minimum key press time
Pins XRES, XIRQ,
PWGD @ 8mA, SDO
Pins XRES, XIRQ @ 8mA,
push/pull mode only, SDO
Pins XRES, XIRQ, PWGD
V
Pin PWRUP
BVVD/3
V
Pin PWRUP
1
V
Pin PWRUP
ca
V PWRUP_L
f CLK
AVDD/2
Electrical Specification of other function blocks
Symbol
V POR_ON
I PD
Note
al
id
Min
3.0
VBUS
Parameter
Battery Supply Voltage
BVDD, BVDDH, BVDDC1,
BVDDC2, BVDDC3, BVDDR
USB VBUS Voltage
am
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Symbol
BVDDx
1.02
8
360
DVDD/2
*0.3
DVDD/2
*0.7
10
0.42
kΩ
V
V
µA
48
kHz
Pin PWRUP
Pin HBT, SDI, SCLK,
MCLK, LRCK
Pin HBT, SDI, SCLK,
MCLK, LRCK
Pin HBT
LRCK according to
streamed audio data
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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Revision 1v3
12 - 93
AS3517 V17
Data Sheet, Confidential
8.1.2
Operating Currents
Table 7
Supply currents
Parameter
Headphone current from BVDDH
Typ
1
I DAC->HP
DAC playback current
6.4
mA
no load, including PMU
I Line->HP
Line Input playback current
1.9
mA
no load, including PMU
Temperature Range
Table 8
Temperature Range
Parameter
Operating temperature range
Tj
Junction temperature range
R th
Thermal Resistance
Min
-20
Typ
25
0
Max
85
110
39
Unit Note
°C
°C
°C/W For CTBGA81 package
Te
ch
ni
ca
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Symbol
T amb
Unit Note
mA quiescent current, no load
lv
8.1.3
Max
al
id
Symbol
I HPH
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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Revision 1v3
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AS3517 V17
Data Sheet, Confidential
Table 9
Audio Parameters
Symbol
Parameter
DAC Input to Line Output
FS
Full Scale Output
SNR
Signal to Noise Ratio
DR
Dynamic Range
THD
SINAD
Min
Typ
Max
Unit
Note
0.97
91
V RMS
dB
88
dB
1kHz FS input
A-weighted, no load,
silence input
A-weighted, no load,
-60dB FS 1kHz input
1kHz FS input
A-weighted, 1kHz FS input
Total Harmonic Distortion
Signal to Noise and
Distortion
Line Input to Line Output
FS
Full Scale Output
SNR
Signal to Noise Ratio
-90
85
dB
dB
0.96
92
V RMS
dB
THD
SINAD
-90
86
dB
dB
89
dB
0.895
0.89
94
V RMS
V RMS
dB
SNR
Signal to Noise Ratio
DR
Dynamic Range
90
dB
THD
Total Harmonic Distortion
-95
-75
dB
dB
-69
CS
Signal to Noise and
Distortion
ca
SINAD
Channel Separation
ch
ni
Line Input to HP Output
FS
Full Scale Output
-60
dB
91
dB
73
dB
68
dB
74
68
dB
dB
0.875
V RMS
0.87
V RMS
Signal to Noise Ratio
95
dB
DR
Dynamic Range
95
dB
-91
-75
dB
dB
Te
SNR
THD
Total Harmonic Distortion
-70
SINAD
1kHz 1V RMS (FS) input
A-weighted, no load,
silence input
1kHz 1V RMS (FS) input
A-weighted, 1kHz FS input
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Total Harmonic Distortion
Signal to Noise and
Distortion
CS
Channel Separation
DAC Input to HP Output
FS
Full Scale Output
al
id
Audio Specification
lv
8.1.4
Signal to Noise and
Distortion
87
-60
dB
dB
R L = 32Ω
R L = 16Ω
A-weighted, no load,
silence input
A-weighted, no load,
-60dB FS 1kHz input
no load, 1kHz FS input
Pout=20mW, R L = 32Ω,
f=1kHz FS input
Pout=40mW, R L = 16Ω,
f=1kHz FS input
A-weighted, no load, 1kHz
FS input
A-weighted,Pout=20mW,
R L = 32Ω, f=1kHz FS input
A-weighted,Pout=40mW,
R L = 16Ω, f=1kHz FS input
R L = 32Ω
R L = 16Ω
R L = 32Ω, 1kHz 1V RMS (FS)
input
R L = 16Ω, 1kHz 1V RMS (FS)
input
A-weighted, no load,
silence input
A-weighted, no load,
-60dB FS 1kHz (FS) input
no load, 1kHz 1V RMS input
Pout=20mW, R=32Ω, 1kHz
1V RMS (FS) input
Pout=40mW, R=16Ω, 1kHz
1V RMS (FS) input
A-weighted, no load, 1kHz
1V RMS input
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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Revision 1v3
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AS3517 V17
Data Sheet, Confidential
Channel Separation
MIC Input to Line Output
FS
Full Scale Output
SNR
Signal to Noise Ratio
Min
Typ
74
Max
Unit
dB
68
dB
75
70
dB
dB
0.97
81
V RMS
dB
DR
Dynamic Range
83
dB
THD
Total Harmonic Distortion
-78
dB
Signal to Noise and
Distortion
Line Input to ADC Output
SNR
Signal to Noise Ratio
75
dB
90
dB
DR
Dynamic Range
90
dB
THD
Total Harmonic Distortion
-78
dB
SINAD
Signal to Noise and
Distortion
78
dB
1kHz FS input
A-weighted, no load,
silence input
A-weighted, no load,
-60dB FS 1kHz input
1kHz 27mV RMS (-3dB FS)
input
A-weighted, 1kHz 27mV RMS
(-3dB FS) input
A-weighted, no load,
silence input
A-weighted, no load,
-60dB FS 1kHz input
1kHz 1V RMS (-3dB FS)
input
A-weighted, 1kHz 1V RMS (3dB FS) input
Te
ch
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ca
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SINAD
Note
A-weighted, Pout=20mW,
R=32Ω, 1kHz 1V RMS (FS)
input
A-weighted, Pout=40mW,
R=16Ω, 1kHz 1V RMS (FS)
input
R L = 32Ω
R L = 16Ω
al
id
CS
Parameter
lv
Symbol
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
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AS3517 V17
Data Sheet, Confidential
9 Detailed Functional Description
9.1
Audio Functions
9.1.1
Audio Line Inputs (2x)
General
The chip features includes two identical line inputs. The blocks can work in mono differential, 2x mono single ended or in stereo single
ended mode.
al
id
The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each and MUTE. The gain can be
set from –34.5dB to +12dB. The stage is set to mute by default. If the line input is not enabled, the volume settings are set to their default
values. Changing the volume and mute control can only be done after enabling the input.
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lv
Figure 5 Line Inputs
Mono Single Ended Mode
ni
ca
Stereo Mode
Te
ch
Mono Differential Mode
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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Revision 1v3
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AS3517 V17
Data Sheet, Confidential
Parameter
Table 10 Line Input Parameter
Parameter
Input Signal Level
R LIN
Δ RLIN
C LIN
A LIN
Input Impedance
Input Impedance Tolerance
Input Capacitance
Programmable Gain
Gain Steps
Min
Max
Unit
V PEAK
20-100
±15
5
1.5
kΩ
%
pF
dB
dB
±0.25
100
dB
dB
-34.5
Gain Step Accuracy
Mute Attenuation
A LINMUTE
Typ
1.0
+12
Register Description
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Table 11 Line Input Related Register
Name
LINE_IN1_R
LINE_IN1_L
LINE_IN2_R
LINE_IN2_L
AudioSet_1
AudioSet_3
discrete logarithmic gain
steps
lv
BVDD = 3.3V, TA= 25oC, fs=48kHz unless otherwise mentioned
Note
Pls observe gain settings.
Max. peak levels at any
node within the circuit shall
not exceed AVDD
depending on gain setting
al
id
Symbol
V LIN
Base
2-wire
2-wire
2-wire
2-wire
2-wire
2-wire
serial
serial
serial
serial
serial
serial
Offset
0Ah
0Bh
0Ch
0Dh
14h
16h
Description
Right Line Input 1 settings
Left Line Input 1 settings
Right Line Input 2 settings
Left Line Input 2 settings
Enable/disable driver stage
Enable/disable mixer input
Te
ch
ni
ca
Line Inputs have to be enabled in register 14h first before other settings in register 0Ah to 0Dh can be programmed.
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
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AS3517 V17
Data Sheet, Confidential
9.1.2
Microphone Inputs (2x)
General
The AFE offers two microphone inputs and 2 low noise microphone voltage supply (microphone bias), voice activation, microphone
connect detection and push button remote control.
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Figure 6 Microphone Input
Microphone Preamplifier and Gain Stage
Gain Stage & Limiter
The integrated pre-amplifier allows 3 preset gain settings. There is also a limiter which attenuates high input signals from e.g. electrete
microphones signal to 1Vp. The AGC has 15 steps with a dynamic range of about 29dB. The AGC is ON by default but can be disabled by
a microphone register bit.
Apart from the microphone pre-amplifier the microphone input signal can further be amplified with 32 @1.5dB programmable logarithmic
gain steps and MUTE. All gains and MUTE are independently programmable. The gain can be set from –40.5dB to +6dB.
The stage is set to mute by default. If the microphone input is not enabled, the volume settings are set to their default values. Changing
the volume and mute control can only be done after enabling the input.
Supply & Detection
Each microphone input generates a supply voltage of 1.5V above HPHCM. The supply is designed for ≤2mA and has a 10mA current
limit. In OFF mode the MICS terminal is pulled to AVDD with 30kOhm. A current of typically 50uA generates an interrupt to inform the
CPU, that a circuit is connected. When using HPCM as headset ground the HP–stage gives the interrupt. After enabling the HP-stage
through the CPU the microphone detection interrupt will follow.
Remote Control
ca
When using the MICxS terminals as ADC-10 input to monitor external voltages the 30kOhm pull-up can be disabled.
ni
Fast changes of the supply current of typically 500uA are detected as a remote button press, and an interrupt is generated. Then the CPU
can start the measurement of the microphone supply current with the internal 10-bit ADC to distinguish which button was pressed. As the
current measurement is done via an internal resistor, only two buttons generating a current of about 0.5mA and 1mA can be detected.
With this 1mA as microphone bias is still available.
Voice Activation
Te
ch
Further a built-in voice activation comparator can actuate an interrupt if microphone input voltage of about 5mVRMS is detected.
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
18 - 93
AS3517 V17
Data Sheet, Confidential
Parameter
Table 12 Microphone Inputs Parameter
Min
Input Signal Level
Input Impedance
Input Impedance Tolerance
Input Capacitance
Microphone Preamplifier Gain
A MIC
Programmable Gain
Gain Steps
1.5
Unit
mV PEAK
mV PEAK
mV PEAK
kΩ
%
pF
dB
dB
dB
dB
dB
±0.25
1
15*2
50
120
100
dB
V PEAK
dB
µs/6dB
ms/6dB
dB
-40.5
Max
+6
V MICSUP
I MICMAX
Microphone Supply Voltage
Max. Microphone Supply
Current
2.9
10
V
mA
V NOISE
Microphone Supply Voltage
Noise
Microphone Detection
Current
Max. Remote Detection
Current
5
µV
50
µA
500
µA
I MICDET
I REMDET
Note
A MICPRE = 28dB; A MIC = 0dB
A MICPRE = 34dB; A MIC = 0dB
A MICPRE = 40dB; A MIC = 0dB
MICP, MICN to AGND
Preamplifier has 3
selectable (fixed) gain
settings
discrete logarithmic gain
steps
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Gain Step Precision
Limiter Activation Level
Limiter Gain Overdrive
Limiter Attack Time
Limiter Decay Time
Mute Attenuation
V MICLIMIT
A MICLIMIT
t ATTACK
t DECAY
A MICMUTE
Typ
40
20
10
15
±15
5
28
34
40
al
id
Parameter
lv
Symbol
V MICIN 0
V MICIN 1
V MICIN 2
R MICIN
Δ MICIN
C MICIN
A MICPRE
microphones nominally
need a bias current of
0.5mA-1mA
BVDD = 3.3V, TA= 25oC unless otherwise mentioned
Register Description
Table 13 Microphone Related Register
serial
serial
serial
serial
serial
serial
serial
serial
serial
Offset
06h
07h
08h
09h
14h
16h
24h
26h
27h
ca
Base
2-wire
2-wire
2-wire
2-wire
2-wire
2-wire
2-wire
2-wire
2-wire
ch
ni
Name
MIC1_R
MIC1_L
MIC2_R
MIC2_L
AudioSet_1
AudioSet_3
IRQ_ENRD_1
IRQ_ENRD_3
IRQ_ENRD_4
Description
Right Microphone Input 1 volume settings, AGC control
Left Microphone Input 1 volume settings, MIC 1 supply control
Right Microphone Input 2 volume settings, AGC control
Left Microphone Input 2 volume settings, MIC 2 supply control
Enable/disable driver stage
Enable/disable mixer input
Interrupt settings for microphone voice activation
Interrupt settings for microphone detection
Interrupt settings for remote button press detection
Te
Microphone inputs have to be enabled in register 14h first before other settings in register 06h to 09h can be programmed.
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
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AS3517 V17
Data Sheet, Confidential
9.1.3
Audio Line Outputs (2x)
General
The line outputs are designed to provide the audio signal with typical 1VPEAK at a load of minimum 10kΩ, which is a minimum value for
line inputs. If the limiters (N20/N21) are deactivated the peak output voltage is 1.45VPEAK. The load however can decrease to 64Ohm. In
addition these line output can be configured as mono differential to drive 1VPEAK @ 32Ω load (e.g. an earpiece of a mobile phone).
This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from
-40.5dB to +6dB. A zero cross detection allows to control the actual execution of new gain settings.
al
id
If the line output is not enabled, the volume settings are set to their default values. Changing of volume and mute control can only be done
after enabling the output.
If using the output in mono differential mode, the volume setting for the right channel should be set to 0dB.
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Figure 7 Line Output
Stereo Mode
Mono Differential Mode (please observe that gain of right
channel amplifier has to best to 0dB)
Parameter
Table 14 Line Output Characteristics
A LO
A LOMUTE
Min
64
Typ
Max
Unit
Ω
100
pF
+6
1.5
dB
dB
±0.25
100
dB
dB
-40.5
ca
C L_LO
Parameter
Load Impedance
(Stereo Mode)
Load Capacitance
(Stereo Mode)
Programmable Gain
Gain Steps
Gain Step Accuracy
Mute Attenuation
ni
Symbol
R L_LO
Note
line inputs nominally have
10kΩ
discrete logarithmic gain
steps
BVDD = 3.3V, TA= 25oC unless otherwise mentioned
ch
Register Description
Table 15 Line Output Related Register
Te
Name
LINE_OUT1_R
LINE_OUT1_L
LINE_OUT2_R
LINE_OUT2_L
AudioSet_1
AudioSet_3
Base
2-wire
2-wire
2-wire
2-wire
2-wire
2-wire
serial
serial
serial
serial
serial
serial
Offset
00h
01h
04h
05h
14h
16h
Description
Right Line Output 1 volume settings, MUX control
Left Line Output 1 volume settings
Right Line Output 2 volume settings, MUX control
Left Line Output 2 volume settings
Enable/disable driver stage
Enable/disable mixer input
Line output have to be enabled in register 14h first before other settings in register 00h and 01h can be programmed.
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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Revision 1v3
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AS3517 V17
Data Sheet, Confidential
9.1.4
Headphone Output
General
The headphone output is designed to provide the audio signal with 2x40mW @ 16Ω or 2x20mW @32Ω, which are typical values for
headphones. If the limiters (N20/N21) are disabled a maximum output of [email protected] or [email protected] can be achieved.
This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
43.43dB to +1.07dB. A zero cross detection allows to control the actual execution of new gain settings.
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al
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Figure 8 Headphone Output
Headphones connected via decoupling capacitors
Phantom Ground
Headphones connected to Phantom Ground
(Common Mode)
There are 2 ways to connect a headphone to the AFE. In order to spare the bulky ac/dc decoupling capacitors at pins HPR/HPL a
buffered ground (Phantom Ground) is provided. This Common Mode Buffer needs to be switched on if utilized. If form factor
considerations are less stringent, the headphones can be conventionally connected via 2x100µF capacitors.
No-Pop Function
The output is automatically set to mute when the output stage is disabled.
ca
To avoid Pop-Click noise during power-up and shut-down of the headphone amplifier, a charge/discharge control of HPGND (0V-1.45V0V) at pins HPR/HPL is incorporated into the AFE. The 100nF capacitor at pin HPGND is used to form the charge/discharge slope. Pls
observe that pin HPGND is a high impedance node which must not be connected to any other external device than the 100nF buffer
capacitor. To avoid Pop-Click noise one has to wait for 150ms in between a power-down (switch-off) and a power-up (switch-on) of the
headphone amplifier.
The output is automatically set to mute when the output stage is disabled.
ni
Figure 9 HP POP-Click Suppression
ch
HPGND [V]
MUTE OFF
HP Amps
powered down
Te
AGND
Operation
70ms
t
70ms
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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Revision 1v3
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AS3517 V17
Data Sheet, Confidential
Over-current Protection
The headphone amplifier has an over-current protection (e.g. HPR/HPL is shorted). This over-current protection will power the headphone
amplifier down for a programmable timeout period (512ms, 256ms, 128ms). The current threshold is at 150mA for HPR/HPL and 300mA
for HPCM. There is a corresponding interrupt available to be enabled.
Headphone Detection
When the headphone amplifier is powered down, one can detect the connection of a headset. It only work if the headset is connected
between pins HPR/HPL and HPCM. As long as the headphone amplifier is powered down, HPCM is biased to 150mV and acting as the
sense pin. There is a corresponding interrupt available to be enabled.
Power Save Options
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id
To save power, especially when driving 32 Ohm loads, a reduction of the bias current can be selected. Together with switching off the
phantom ground this gives 4 possible operating modes.
Table 16 Headphone Power-Save Options
IDD_HPH (typ.)
2.2mA
1.5mA
1.5mA
1.0mA
Load
16 Ohm
16 Ohm
32 Ohm
32 Ohm
lv
IBR_HPH
0
0
1
1
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HPCM_OFF
0
1
0
1
BVDD = 3.3V, TA= 25oC unless otherwise mentioned
Parameter
Table 17 Power Amplifier Block Characteristics
Symbol
R L_HP
C L_LO
P HP
Parameter
Load Impedance
Load Capacitance
Nominal Output Power
P HP_MAX
Max. Output Power
A LO
Programmable Gain
Gain Steps
Min
16
100
-45.5
A LOMUTE
Mute Attenuation
ca
Power Supply Rejection Ratio
Max
Unit
Ω
pF
40mW
20mW
60mW
30mW
Gain Step Accuracy
Over current limit
P SRRHP
Typ
1.5
+1
dB
dB
±0.25
150
300
90
dB
mA
mA
dB
100
dB
Note
stereo mode
stereo mode
RL=16Ω, limiter enabled
RL=32Ω, limiter enabled
RL=16Ω
RL=32Ω
discrete logarithmic gain
steps
HPR/HPL pins
HPCM pin
200Hz-20kHz, 720mVpp,
RL=16Ω
ni
BVDD = 3.3V, TA= 25oC unless otherwise mentioned
Register Description
ch
Table 18 Headphone Related Register
Te
Name
HPH_OUT_R
HPH_OUT_L
AudioSet_3
IRQ_ENRD_3
Base
2-wire
2-wire
2-wire
2-wire
serial
serial
serial
serial
Offset
02h
03h
16h
26h
Description
Right HP Output volume and over-current settings
Left HP Output volume settings, enable and detection control
Power save options, common mode buffer
Interrupt settings for over current and HP detection
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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Revision 1v3
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AS3517 V17
Data Sheet, Confidential
9.1.5
DAC, ADC and I2S Digital Audio Interface
Input
The AFE receives serialized audio data for the DAC via pin SDI. The output of the DAC is fed through a volume control to the mixer stage
and to the multiplexers of line output and headphone amplifiers.
This serialized audio data is a digital audio data stream with the left and the right audio channels multiplexed into one bit-stream. Via pin
LRCLK the alignment clock is input to the DAC digital filters. LRCLK (Left Right Clock) indicates whether the serial bit-stream received via
pin SDI, represents right channel or left channel audio data. Via pin SCLK the bit clock for the serial bit-stream is signalled. SDI and
LRCLK are synchronous with SCLK. SDI is an inputs; LRCLK and SCLK are either inputs or outputs depending on the master/slave
operation mode. SDO is not used.
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id
The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
40.5dB to +6dB. The stage is set to mute by default. If the DAC input is not enabled, the volume settings are set to their default values.
Changing the volume and mute control can only be done after enabling the input.
Output
lv
This block consists of an audio multiplexer where the signal, which should be recorded, can be selected. The output is then fed through a
volume control to the 20 bit ADC. The digital output is done via an I2S interface.
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The AFE sends serialized audio data from the ADC via pin SDO. This serialized audio data is a digital audio data stream with the left and
the right audio channels multiplexed into one bit-stream. Via pin LRCLK the alignment clock is signalled to the connected devices (e.g.
CPU). LRCLK (Left Right Clock) indicates whether the serial bit-stream sent via pin SDI, presents right channel or left channel audio data.
Via pin SCLK the bit clock for the serial bit-stream is signalled. SDO and LRCLK are synchronous with SCLK. SDO is an output; LRCLK
and SCLK are either inputs or outputs depending on the master/slave operation mode. SDI is not used.
The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
34.5dB to +12dB. The stage is set to mute by default. If the ADC output is not enabled, the volume settings are set to their default values.
Changing the volume and mute control can only be done after enabling the input.
The I2S output uses the same clocks as the I2S input. The sampling rate therefore depends also on the input sampling rate.
I2S Modes
The AFE can be operated either in Master Mode, Slave Mode or additionally in Slave Mode with the master clock directly signalled via pin
PWGD (pin PWGD is multiplexed for I2S Direct Mode). The difference between Master and Slave Mode is whether the AFE or the
externally attached decoder/encoder device is generating the interface clocks. The master clock (MCLK) is the necessary internal oversampling clock for the DAC and ADC (e.g. 256*fs, fs=audio sampling frequency).
Due to the internal structure left and right audio samples are exchanged in I2S Direct Mode.
In Slave Mode the PLL generates the master clock based on LRCLK. Thus the PLL needs to be preset to the expected sampling
frequency. The ranges are 8kS-12kS (8kHz-12kHz) and 16kS-48kS (16kHz-48kHz). Please refer to register 0x1Dh.
ch
ni
ca
Table 19 I2S Modes
Slave Mode, internal PLL of the AFE generates MCLK
Te
Master Mode
Slave Mode with I2S direct, the master clock is signalled
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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via pin PWGD
Power Save Options
The bias current of the DAC block can be reduced in three steps down to 50% to reduce the power consumption.
Clock Supervision
The digital audio interface automatically checks the LRCLK. An interrupt can be generated when the state of the LRCLK input changes. A
bit in the interrupt register represents the actual state (present or not present) of the LRCLK.
Signal Description
The digital audio interface uses the standard I2S format:
left justified
MSB first
one additional leading bit
al
id
•
•
•
lv
The first 18 bits are taken for DAC conversion. The on-chip synchronization circuit allows any bit-count up 32bit. When there are less than
18 bits sampled, the data sample is completed with “0”s. In I2S direct mode the data length has to be minimum 18 bits.
The ADC output is always 20 bit. If more SCLK pulses are provided, only the first 20 will be significant. All following bits will be “0”.
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SCLK has not to be necessarily synchronous to LRCLK but the high going edge has to be separate from LRCLK edges. The LRCK signal
has to be derived from a jitter-free clock source, because the on-chip PLL is generating a clock for the digital filter, which has to be always
in correct phase lock condition to the external LRCLK.
Please observe that in slave mode LRCLK has to be activated before enabling the ADC.
In Master Mode operation SCLK has 32 clock cycles for each sample word.
SCLK =
Sample Rates
MCLK LRCLK * 256
=
= LRCK * 64
4
4
In Master Mode AS3517 allows programming various sample rates. The master clock is generated by the 12-24MHz oscillator. Sampling
frequencies from 8kHz to 48kHz can be selected. For certain division ratios between master clock and sample ratio a certain deviation is
system inherent.
1
1
*
( PLLMode + 1) * 2 RD + 2
ca
LRCLK = f OSC *
f osc ................ Quarzoscillator frequency
Te
ch
ni
PLLMode ...... PLL factor (1,2)
RD ................. RateDivider (0 − 511)
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Parameter
PLL-Mode
1
1
1
1
1
1
2
2
2
PLL-Mode
1
1
1
1
1
1
2
2
2
PLL-Mode
1
1
1
1
1
1
2
2
2
RD (Rate Divider)
123
134
186
248
270
373
248
270
373
RD (Rate Divider)
81
179
123
165
179
248
165
179
248
RD (Rate Divider)
61
66
92
123
134
185
123
134
185
Deviation
0.00%
0.04%
-0.27%
0.00%
0.04%
0.00%
0.00%
0.04%
0.00%
Deviation
0.40%
-0.33%
0.00%
-0.20%
0.22%
0.00%
-0.20%
0.22%
0.00%
Deviation
-0.79%
0.04%
0.27%
0.00%
0.04%
0.27%
0.00%
0.04%
0.27%
al
id
fsample (LRCK)
48.00kS
44.10kS
32.00kS
24.00kS
22.05kS
16.00kS
12.00kS
11.025kS
8.00kS
fsample (LRCK)
48.00kS
44.10kS
32.00kS
24.00kS
22.05kS
16.00kS
12.00kS
11.025kS
8.00kS
fsample (LRCK)
48.00kS
44.10kS
32.00kS
24.00kS
22.05kS
16.00kS
12.00kS
11.025kS
8.00kS
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fOSC
24MHz
24MHz
24MHz
24MHz
24MHz
24MHz
24MHz
24MHz
24MHz
fOSC
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
16MHz
fOSC
12MHz
12MHz
12MHz
12MHz
12MHz
12MHz
12MHz
12MHz
12MHz
I2S Master clock PLL settings
lv
Table 20Table 21
Te
ch
ni
ca
Figure 10 I2S Left Justified Mode
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al
id
Figure 11 I2S Timing
Table 22 Audio Converter Parameter
T LRHD
t SDSU
t SDHD
t SDOD
t JITTER
ca
I2S Direct mode
T SCD
SCLK delay after MCLK
rising edge
T LRD
LRLCK delay after SCLK
rising edge
t SDSU
SDI setup time before SCLK
rising edge
t SDHD
SDI hold time after SCLK
rising edge
t SDOD
SDO Delay from SCLK falling
edge
Te
ch
V SDOH
V SDOL
V I2SOH
SCLK, LRCLK, SDI, MCLK
High Input Level
SCLK, LRCLK, SDI, MCLK
Low Input Level
SDO High Output Level
SDO Low Output Level
SCLK, LRCLK, High Output
Level
SCLK, LRCLK, Low Output
Level
ni
V I2SH
V I2SL
V I2SOL
Min
160
80
80
80
Typ
Max
Unit
ns
ns
ns
ns
Note
lv
Parameter
SCLK Cycle Time
SCLK Pulse Width High
SCLK Pulse Width Low
LRCLK Setup Time before
SCLK rising edge
LRCLK Hold Time after SCLK
rising edge
SDI setup time before SCLK
rising edge
SDI hold time after SCLK
rising edge
SDO Delay from SCLK falling
edge
Jitter of LRCLK
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Symbol
t SCLK
t SCLKH
t SCLKL
T LRSU
80
ns
25
ns
25
ns
25
ns
-20
20
ns
0.5
1.5
ns
0.5
1.5
ns
5
ns
5
ns
15
1.02
internal PLL generates
MCLK from LRCLK
ns
V
DVDD/2*0.7
0.42
V
DVDD/2*0.3
0.3
V
V
V
at 2mA
at 2mA
at 8mA master mode only
0.3
V
at 8mA master mode only
2.6
2.6
BVDD=3.3V, TA=25°C, Slave Mode, fS=48kHz, MCLK = 256*fS, unless otherwise specified
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Register Description
Table 23 Audio Converter Related Register
Base
2-wire
2-wire
2-wire
2-wire
2-wire
2-wire
2-wire
2-wire
2-wire
2-wire
serial
serial
serial
serial
serial
serial
serial
serial
serial
serial
Offset
0Eh
0Fh
10h
11h
1Eh
1Dh
14h
15h
16h
25h
Description
DAC input volume settings
DAC input volume settings
ADC output volume settings, source multiplexer settings
ADC output volume settings
I2S master mode settings
I2S master mode and PLL settings
Enable/disable ADC
Enable/disable DAC and power save options
Enable/disable mixer input
Interrupt settings for LRCK changes
Te
ch
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lv
DAC and ADC have to be enabled in register 14h first before other settings in register 0Eh to 11h can be programmed.
al
id
Name
DAC_R
DAC_L
ADC_R
ADC_L
I2S
I2S_PLL_OSC
AudioSet_1
AudioSet_2
AudioSet_3
IRQ_ENRD_1
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9.1.6
Audio Output Mixer
General
The mixer stage sums up the audio signals of the following stages
•
•
•
•
Microphone Input 1 & 2 (stereo microphone)
Line Input 1
Line Input 2
Digital Audio Input (DAC)
Register Description
Audio Mixer Related Register
Base
2-wire serial
2-wire serial
Offset
15h
16h
Description
Enable/disable mixer stage and AGC
Enable/disable DAC, MIC or Line Inputs to mixer stage
Te
ch
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Name
AudioSet_2
AudioSet_3
lv
This stage features an automatic gain control (AGC), which automatically avoids clipping.
al
id
The mixing ratios have to be with the volume registers of the corresponding input stages. Please be sure that the input signals of the
mixer stage are not higher than 1Vp. If summing up several signals, each individual signal has of course to be accordingly lower. This
shall insure that the output signal is also not higher than 1Vp to get a proper signal for the output amplifier.
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9.1.7
2-Wire-Serial Control Interface
General
There is an I2C slave block implemented to have access to 64 byte of setting information.
The I2C address is: Adr_Group8 - audio processors
•
•
8Ch_write
8Dh_read
Definition
Start condition after stop
Repeated start
Device address for write
Device address for read
Word address
Acknowledge
No Acknowledge
Register data/write
Register data/read
Stop condition
Increment word address internally
AS3517 (=slave) receives data
AS3517 (=slave) transmits data
Figure 12 Byte Write
Note
1 bit
1 bit
1000 1100b (8Ch)
1000 1101b 8Dh)
8 bit
1 bit
1 bit
8 bit
8 bit
1 bit
During acknowledge
ca
Figure 13 Page Write
R/W (AS3517 Slave)
R
R
R
R
R
W
R
R
W
R
R
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Symbol
S
Sr
DW
DR
WA
A
N
reg_data
data (n)
P
WA++
lv
Table 24 I2C Symbol Definitions
al
id
Protocol
ni
Byte Write and Page Write formats are used to write data to the slave.
ch
The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free). The
device-write address is followed by the word address. After the word address any number of data bytes can be sent to the slave. The
word address is incremented internally, in order to write subsequent data bytes on subsequent address locations.
Te
For reading data from the slave device, the master has to change the transfer direction. This can be done either with a repeated START
condition followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the
bus is in IDLE state. The device-read address is always followed by the 1st register byte transmitted from the slave. In Read Mode any
number of subsequent register bytes can be read from the slave. The word address is incremented internally.
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Figure 14 Random Read
Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data
transfer from the master.
al
id
The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed
by the device-write address and the word address.
am
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il
Figure 15 Sequential Read
lv
In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word
address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits
register data located by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and
issues a STOP condition on the bus.
Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subsequently. In difference
to the Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The
number of data bytes transferred in one sequence is unlimited (consider the behaviour of the word-address counter). To terminate the
transmission the master has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently.
Figure 16 Current Address Read
Te
ch
ni
ca
To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data
transfer. The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random Read, a
single byte transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an unlimited number of
data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the
transmission the master sends a not-acknowledge following the last data byte and a subsequent STOP condition.
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Parameter
al
id
Figure 17 I2C timing
Table 25 I2C Operating Conditions
Min
0
2.03
Typ
-
Max
0.87
5.5
Unit
V
V
HYST
V OL
Tsp
TH
TL
T SU
CSCL, CSDA Input Hysteresis
CSDA Low Output Level
Spike insensitivity
Clock high time
Clock low time
200
50
500
500
250
450
100
800
0.4
-
-
-
mV
V
ns
ns
ns
ns
0
-
-
ns
200
-
-
ns
Notes
(max 30%DVDD)
CSCL, CSDA (min
70%DVDD)
lv
Parameter
CSCL, CSDA Low Input Level
CSCL, CSDA High Input Level
at 3mA
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Symbol
V CSL
V CSH
T HD
TS
T PD
50
ns
max. 400kHz clock speed
max. 400kHz clock speed
CSDA has to change Tsetup
before rising edge of CSCL
No hold time needed for
CSDA relative to rising edge
of CSCL
CSDA H hold time relative to
CSDA edge for
start/stop/rep_start
CSDA prop delay relative to
lowgoing edge of CSCL
Te
ch
ni
ca
DVDD =2.9V, Tamb=25ºC; unless otherwise specified
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9.2 Power Management Functions
9.2.1
Low Drop Out Regulators
General
These LDO’s are designed to supply sensitive analogue circuits, audio devices, AD and DA converters, micro-controller and other
peripheral devices.The design is optimised to deliver the best compromise between quiescent current and regulator performance for
battery powered devices.
am
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lv
Figure 18 LDO Block Diagram
al
id
Stability is guaranteed with ceramic output capacitors of 1μF +/-20% (X5R) or 2.2μF +100/-50% (Z5U). The low ESR of these caps
ensures low output impedance at high frequencies. Regulation performance is excellent even under low dropout conditions, when the
power transistor has to operate in linear mode. Power supply rejection is high enough to suppress high ripple on the battery at the output.
The low noise performance allows direct connection of noise sensitive circuits without additional filtering networks. The low impedance of
the power device enables the device to deliver up to 150mA even at nearly discharged batteries without any decrease of performance.
LDO1
This LDO generates the analog supply voltage used for the AFE itself.
•
•
•
Input voltage is BVDD
Output voltage is AVDD (typ. 2.9V)
Driver strength: 200mA
ca
It is set to a fixed output voltage of 2.9V, 200mAmax. It supplies the analog part of the AFE. Additional external loads are possible but most
not exceed the supply ratings in total together with the operating internal blocks. Further the external load must not induce noise to the
sensitive AVDD supply pin.
LDO2
This LDO generates the digital supply voltage used for the AFE itself.
Input Voltage is BVDD
Output Voltage is DVDD (typ. 2.9V)
Driver strength: 200mA
ch
•
•
ni
•
Te
It is set to a fixed output voltage of 2.9V, 200mAmax. It supplies the digital part of the AFE. Additional external loads are possible but most
not exceed the supply ratings in total together with the operating internal blocks. Further the external load must not induce noise to the
DVDD supply pin but is not as critical as AVDD.
LDO3 & LDO4
These LDO can used to generate the periphery voltage for the digital processor or other external components (e.g. ext. DAC, USB-PHY,
SD-Cards, NAND-Flashes, FM-Tuner …)
•
•
•
•
Input Voltage BVDD
Output Voltage is PVDD1 & PVDD2 (1.2 to 3.5V)
Default value at start-up is defined by VPROG1 and VPROG2 pins
Driver strength: 200mA
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Parameter
Table 26 LDOs Block Characteristics
PSRR
Power supply rejection ratio
I OFF
I VDD
Noise
t start
V out_tol
Shut down current
Supply current
Output noise
Startup time
Output voltage tolerance
Min
Typ
Max
1
70
40
100
50
50
200
-50
50
Unit
Ω
dB
dB
nA
μA
μV rms
μs
mV
mV
mV
V LineReg
Line regulation
<1
<10
V LoadReg
Load regulation
<1
<10
mV
mV
I LIMIT
Current limitation
400
mA
f=1kHz
f=100kHz
without load
10Hz < f < 100kHz
LDO1, Static
LDO1, Transient;Slope:
t r =10μs
LDO1, Static
LDO1, Transient;Slope:
t r =10μs
LDO1, LDO2, LDO3, LDO4
am
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BVDD=4V; ILOAD=150mA; Tamb=25ºC; CLOAD =2.2μF (Ceramic); unless otherwise specified
Notes
al
id
Parameter
On resistance
lv
Symbol
R ON
Figure 19 Typical Performance Characteristics
Output noise
ca
Load regulation
Output load: 150mA
Te
ch
ni
transient load: 1mA – 100mA
slope: 1μs
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Load Regulation
output load: 150mA
transient input voltage ripple: 500mV
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output load: 10mA
transient input voltage ripple: 500mV
lv
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Load Regulation
Register Description
Table 27 LDO Related Register
Base
2-wire serial
2-wire serial
2-wire serial
Offset
17h-1
17h-2
18h
Description
PVDD1 (LDO3) control and voltage settings
PVDD2 (LDO4) control and voltage settings
Enables writings to extended registers 17h-1, 17h-2
Te
ch
ni
ca
Name
PMU PVDD1
PMU PVDD2
PMU ENABLE
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9.2.2
DCDC Step-Down Converter (3x)
General
•
•
•
•
Input Voltage BVDDC1, BVDDC2 & BVDDC3 (usually connected to the battery)
Output Voltage CVDD1, CVDD2 & CVDD3
output voltage levels can be programmed independently form 0.65V to 3.4V
the default value at start-up is defined by VPROG1 and VPROG2 pins
•
driver strength 250mA (500mA for DCDC 3)
ca
am
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nt
st
il
lv
Figure 20 DCDC Step-Down Block Diagram
al
id
These converters are meant to convert the battery voltage down to voltages which fit to the core and peripheral supply voltage
requirements for microprocessors.
ni
Functional Description
ch
The step-down converter is a high efficiency fixed frequency current mode regulator. By using low resistance internal PMOS and NMOS
switches efficiency up to 97% can be achieved. The fast switching frequency allows using small inductors, without increasing the current
ripple. The unique feedback and regulation circuit guarantees optimum load and line regulation over the whole output voltage range, up to
an output current of 250mA, with an output capacitor of only 10μF. The implemented current limitation protects the DCDC and the coil
during overload condition.
Te
To achieve optimised performance in different applications, adjustable settings allow to compromise between high efficiency and low
input, output ripple:
Low ripple, low noise operation:
In this mode there is no minimum coil current necessary before switching off the PMOS. As result, the ON time of the PMOS will be
reduced down to tmin_on at no or light load conditions, even if the coil current is very small or the coil current is inverted. This results in a
very low ripple and noise, but decreased efficiency, at light loads, especially at low input to output voltage differences. Especially in the
case of an inverted coil current the regulator will not operate in pulse skip mode.
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1: LXC1 voltage, 2:coil current (1mV=1mA) 3: output voltage
High efficiency operation:
lv
al
id
Figure 21 –DCDC buck with disabled current force / pulse skip mode
am
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nt
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il
In this mode there is a minimum coil current necessary before switching off the PMOS. As result, fewer pulses at low output loads are
necessary, and therefore the efficiency at low output load is increased. On the other hand the output voltage ripple increases, and the
noisy pulse skip operation is on up to a higher output current.
ca
Figure 22 –DCDC buck with enabled current force / pulse skip mode
1: LXC1 voltage, 2:coil current (1mV=1mA) 3: output voltage
ni
It’s also possible to switch between these two modes dynamically during operation:
Te
ch
100% PMOS ON mode for low dropout regulation:
For low input to output voltage difference the DCDC converter can use 100% duty cycle for the PMOS transistor, which is then in LDO
mode. This feature is enabled if the output voltage drops by more than 4%.
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Parameter
Table 28 DCDC Buck Typical Performance Parameter
Maximum Load current
I LIMIT
Current limit
R PSW
P-Switch ON resistance
R NSW
N-Switch ON resistance
f SW
f SWsc
C out
Lx
η eff
Switching frequency
Switching frequency
Output capacitor
Inductor
Efficiency
I VDD
Current consumption
t MIN_ON
t MIN_OFF
V LineReg
Minimum on time
Minimum off time
Line regulation
Typ
250
500
450
800
0.5
0.34
0.5
0.37
1.2
0.6
10
3.3
Max
5.5
3.4
50
0.7
0.7
0.7
0.7
4.7
Unit
V
V
mV
mA
mA
mA
mA
Ω
Ω
Ω
Ω
MHz
MHz
μF
μH
%
μA
Notes
BVDD
DCDC 1&2
DCDC 3
DCDC 1&2
DCDC 3
BVDD=3.0V;
BVDD=3.0V;
BVDD=3.0V;
BVDD=3.0V;
al
id
I LOAD
Min
3.0
0.65
-50
DCDC
DCDC
DCDC
DCDC
1&2
3
1&2
3
lv
Parameter
Input voltage
Regulated output voltage
Output voltage tolerance
in shortcut case
Ceramic, +/- 10% tolerance
+/- 10% tolerance
Iout=100mA, Vout=3.0V
Operating current without load
Low power mode current
Shutdown current
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Symbol
V IN
V OUT
V OUT_tol
V LoadReg
Load regulation
97
220
100
0.1
80
40
2
ns
ns
mV
10
mV
5
50
mV
mV
Static
Transient; Slope: t r =10μs,
100mV step, 200mA load
Static
Transient; Slope: t r =10μs,
100mA step
BVDD=3.6V; Tamb=25ºC; unless otherwise specified
Te
ch
ni
ca
Figure 23 DCDC Step-down Performance Characteristics
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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Revision 1v3
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AS3517 V17
Data Sheet, Confidential
Register Description
Te
Table 29 DCDC Buck Related Register
Name
PMU CVDD1
PMU CVDD2
PMU CVDD3
PMU ENABLE
Base
2-wire
2-wire
2-wire
2-wire
serial
serial
serial
serial
Offset
17h-3
17h-4
17h-5
18h
Description
CVDD1 (DCDC1) control and
CVDD2 (DCDC2) control and
CVDD2 (DCDC2) control and
Enables writings to extended
voltage settings
voltage settings
voltage settings
registers 17h-3, 17h-4
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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9.2.3
Charger
General
This block can be used to charge a 4V Li-Io accumulator. It supports constant current and constant voltage charging modes with
adjustable charging currents (50 to 400mA) and maximum charging voltage (3.9 to 4.25V).
Trickle Charge
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Figure 24 Charger States
If BVDD is below 3V in systems where the battery is not separated from BVDD, the charger goes automatically in trickle charge mode with
50mA charging current and 3.9V endpoint voltage. In this mode charging current and voltage are not precise, but provide a charger
function also for deep discharged batteries. The temperature supervision is not enabled in trickle charge mode.
As soon as BVDD reaches 3V the AFE switches on and starts-up the regulators with the power-up sequence selected by pins VPRG1 and
VPRG2. Afterwards the CPU can set the modes and the charging currents via the 2-wire serial interface.
ca
If the battery (CHGOUT) voltage is below 2.9V the charging current cannot be set higher than 50mA, also when using a battery separation
circuit to supply the AFE (BVDD) from USB or another voltage source.
Temperature Supervision
ni
This charger block also features a 15uA supply for an external 100k NTC resistor to measure the battery temperature while charging. If
the temperature is too high (>45°C), an interrupt can be generated. If the battery temperature drops below 42°C the charger will start
charging again. The temperature supervision is not enabled in trickle charge mode.
Te
ch
If the NTC resistor does not have 100kΩ its value can be corrected with a resistor in series or in parallel.
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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AS3517 V17
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Parameter
Table 30 Charger Parameter
Typ
68
32
0.72*
CHGIN
I NOM
V NOM
3.1
170
77
610
700
10%
I NOM
<1
Max
111
55
0.74*
CHGIN
I NOM
+20%
V NOM
+30mV
4.0
240
15%
I NOM
Unit
Notes
mA BVDD<=3V, CHGIN = 5.5V
mA BVDD<=3V, CHGIN = 4.0V
V BVDD<=3V, CHGIN = 4.4V
mA
V
BVDD > 3V
BVDD > 3V, end of charge is true
al
id
Min
37
17
V CHG_trick Charger Endpoint Voltage (trickle 0.70*
charge)
CHGIN
I CHG (0-7) Charging Current
I NOM
-20%
V CHG (0-7) Charging Voltage
V NOM
-50mV
V ON_ABS Charger On Voltage IRQ
V ON_REL Charger On Voltage IRQ
V OFF_REL Charger Off Voltage IRQ
40
V BATEMP_ON Battery Temp. high level (45°C)
V BATEMP_OFF Battery Temp. low level (42°C)
I CHG_OFF End Of Charge current level
5%
I NOM
I REV_OFF Reverse current shut down
V
mV
mV
mV
mV
mA
BVDD = 3V
CHGIN-CHGOUT
CHGIN-CHGOUT
BVDD >3V
BVDD >3V
BVDD >3V
uA
BVDD = 5V, CHGIN open
lv
Parameter
Charging Current
(trickle charge)
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Symbol
I CHG_trick
BVDD=3.6V; Tamb=25ºC; unless otherwise specified
Register Description
Table 31 Charger Related Register
Base
2-wire serial
2-wire serial
Offset
22h
25h
Description
Charger voltage, current and temp. supervision control
Enable/disable EOC and battery over-temperature interrupt
Read out charger status
Te
ch
ni
ca
Name
CHARGER
IRQ_ENRD_2
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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9.2.4
15V Step-Up Converter
General
The integrated Step-Up DC/DC Converter is a high efficiency current-mode PWM regulator, providing an output voltage up to 15V. A
constant switching-frequency results in a low noise on supply and output voltages. When using an additional transistor the output voltage
can be up to 25V to drive 6 white LED in series.
It has an adjustable sink current (1.25 to 37.5mA) to provide e.g. dimming function when driving white LEDs as back-light.
Parameter
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Figure 25 DCDC15 Block Diagram
Table 32 15V Step-Up Converter Parameter
Symbol
V SW
I VDD
V FB
V FB
Parameter
High Voltage Pin
Quiescent Current
Feedback Voltage, Transient
Feedback Voltage, during
Regulation
Current Limit
Switch Resistance
Load Current
Pulse-skip Threshold
ca
I SW_MAX
R SW
I LOAD
Typ
Max
15
140
0
0.65
350
0
1.2
Fixed Switching Frequency
Output Capacitor
I LOAD > 20mA
0.5
I LOAD < 20mA
Minimum On-Time
Maximum Duty Cycle
8
90
85
ch
F IN
C OUT
ni
V PULSESKIP
Min
0
17
0.83
510
0.85
1.33
5.5
1.0
750
1.54
45
1.5
0.55
1
22
0.6
10
27
180
98
27
L (Inductor)
Te
t MIN_ON
MDC
91
Unit
V
µA
V
V
mA
Ω
mA
V
Notes
Pin SW15
Pulse Skipping mode
Pin ISINK
Pin ISINK
V15_ON = 1
V15_ON = 0
@ 15V output voltage
Voltage at pin ISINK, pulse skips are
introduces when load current becomes
too low.
MHz
µF Ceramic
µH Use inductors with small C PARASITIC
(<100pF) for high efficency
ns
%
Guaranteed per design
Guaranteed per design
BVDD=3.6V; Tamb=25ºC; unless otherwise specified
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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AS3517 V17
Data Sheet, Confidential
Figure 26 15V Step-Up Performance Characteristics
Efficiency vs Output Current
100
VIN=3,6V
Load: 3 LED's
95
85
80
75
70
al
id
EFFICIENCY [%]
90
65
60
DCDC stepup
Current controlled 0..15V
55
50
1
10
100
lv
OUTPUT CURRENT [mA]
Register Description
am
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Table 33 15V Step-Up Related Register
Base
2-wire serial
Offset
1Bh
Description
DCDC15 current and dimming control
Te
ch
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ca
Name
DCDC15
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Data Sheet, Confidential
9.2.5
USB VBUS Supply
The VBUS voltage converter consists out of a charge pump and a DCDC converter. These 2 blocks share common pins. The charge
pump (CP) and is used as USB-OTG (on the go) supply (5V/8mA) and the DCDC step-up converter provides the USB-HOST supply (5V
/500mA). Depending on the external configuration either CP mode or DCDC mode is selected. Be aware that only one block can be used
in one application. The following description shows how each block operates and how the circuit should be configured.
Additional the USB VBUS generation block features a VBUS comparator to detect different VBUS levels thus complies to SRP (session
request protocol) and HNP (host negotiation protocol).
VBUS DCDC (USB Host Supply)
al
id
With the pin USBH_CSP connected to the battery voltage the mode USB-HOST mode is selected. This means the DCDC converter
supplies 5V and up to 500mA.
For device safety an external PMOS switch is necessary in the case of a short-circuit condition on the VBUS pin. With this PMOS the
device can shut off the path between battery and output. During start-up the PMOS switch will be opened very slowly by discharging his
gate with a small current sink. Depending on the value of the Gate-Source Capacitance and the start-up time, different current values for
the current sink can be programmed.
Te
ch
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Figure 27 VBUS DCDC Block Diagram
lv
During start-up and operation the DCDC also monitors the current over the sense resistor. If the current limit will be reached during startup the DCDC will generate an interrupt signal after 5.3usec de-bounce time. If this over-current condition is still present after 85µs the
DCDC converter will be shut off by resetting its register. During start-up, however, an interrupt will be masked until pin USBH_PG is lower
than 1V.
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VBUS Charge Pump (USB OTG Supply)
With the pin USBH_CSN and USBH_CSP connected to ground the USB-OTG mode is selected. In this mode the charge pump supplies
5V and 8mA. The charge pump uses the QLDO2 voltage as input and doubles its voltage with the help of the flying capacitor between
CP_CP and CN_GEXT to its output VBUS. If the pulse skip bit is set in the related register, the charge pump switches to pulse skip mode
for improved efficiency. Enabled pulse skip mode, however, compromises with a higher output voltage ripple.
am
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Figure 28 VBUS CP Block Diagram
Parameter
Table 34 VBUS Generation Parameter
Symbol
CP Mode
I CPOUT
I VDD
V CPOUT
F IN
C FLY
C STORE
Parameter
Output Current
Quiescent Current
Output Voltage
Switching frequency
External flying capacitor
External storage capacitor
Min
4.7
1
600
5.0
375
100
Max
Unit
Note
8
mA
µA
V
kHz
nF
@ 4.7V output voltage
5.3
2.2
uF
140
100
µA
mV
0
750
130
91
4.7
10
500
mA
KHz
ns
%
µF
µH
100
mΩ
ch
t MIN_ON
MDC
C OUT
L
Load Current
Fixed Switching Frequency
Minimum On-Time
Maximum Duty Cycle
Output Capacitor
Inductor
ni
I LOAD
f IN
ca
DCDC Mode
I VDD
Quiescent Current
V Rsense_max Current Limit at R sense
Typ
NMOS switch
Te
N SW
P SW
R sense
PMOS switch
Current Limit Sense Resistor
C FLY =100nF,I CPOUT =0..8mA
ceramic, low ESR
capacitor between CP_CP
and CN_GEXT
ceramic, low ESR
capacitor between VBUS
and VSS
Pulse Skipping mode
e.g.: 1A for 0.1 Ohm sense
resistor
@ 5V output voltage
Ceramic, +/-20%
Use inductors with small
C PARASITIC (<100pF) for
high efficiency
ON-resistance of external
switching transistor max.
1Ω
ON-resistance of external
PMOS transistor as low as
possible, because of
efficiency
e.g.: 1A for 0.1 Ohm sense
resistor
BVDD=3.3V, TA=25°C, unless otherwise specified
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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Figure 29 15V Step-Up Performance Characteristics
Efficiency vs Output Current
100
VIN=3.6V
DCDC stepup
5V USB Host supply
95
100mA
85
80
75
al
id
EFFICIENCY [%]
90
500mA
70
65
60
lv
OUTPUT CURRENT [mA]
Register Description
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Table 35 USB VBUS Related Registers
Base
2-wire serial
Offset
1Ah
Description
DCDC and CP control, VBUS comparator settings
Te
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Name
PMU VBUS
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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9.3
SYSTEM Functions
9.3.1
SYSTEM
General
The system block handles the power up, power down and regulator voltage settings of the AFE.
Power Up Conditions
The chip powers up when on of the following condition is true:
•
High signal on the PWR_UP pin (>80ms, >1V & >1/3 BVDD)
Rising edge on the VBUS pin (USB plug in: >80ms, BVDD>3V, VBUS>4.5V)
Rising edge on the CHGIN pin (charger plug in: >80ms, BVDD>3V, CHGIN>4.0V)
Rising edge on the RTCSUP and consequently on RVDD pin (RTCSUP > 1.35V, BVDD >3V)
•
RTC wake-up: The auto wake-up timer is internally connected to the Power-up and Hibernation Control block.
Power Down Conditions
The chip automatically shuts off if one of the following conditions arises:
•
LDO or step down converter output voltage drop below a programmable level (has to be enabled)
Junction temperature reaches maximum threshold, set in SUPERVISOR register (0x24h)
High signal on the PWR_UP pin for more than (>5.4s, >1V & >1/3 BVDD).
With setting SD_TIME bit in register 24h the time can be doubled.
Te
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ca
•
•
•
Clearing the PWR_HOLD bit in SYSTEM register (0x20h)
I2C watchdog power down(no serial reading for >1s, has to be enabled)
Heartbeat watchdog via pin HBT(no watchdog reset via HBT pin for > 500ms, has to be enabled)
Please note, that when using power-up sequence 16 to 25 no power down is performed but a reset puls (86us typ,
60us min) will be performed.
BVDD drops below the minimum threshold voltage (<2.7V)
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•
•
•
lv
To hold the chip in power up mode the PWR_HOLD bit in the SYSTEM register (0x20h) is set.
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•
•
•
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Data Sheet, Confidential
Start-up Sequence
The AFE offers 25 different power-up sequences. The specific start-up sequence can be selected via VPRG1 and VPROG2 pin. Each pin
detects 5 logical input states which shall come from an external resistor divider network.
At first, LDO1 (AVDD) and LDO2 (DVDD) is powering up. This cannot be influenced with the selection of specific sequences below. LDO1
and LDO2 are necessary for the internal supply of the AFE.
After power-up sequence selected by pin VPRG1, all voltage settings and power on/off conditions of the described regulators can be
programmed via the serial interface.
Table 36 Start-up Modes
1
2
3
4
5
open
open
open
open
open
DCDC1
CVDD1
open
1,2V 3rd
vdd
1,2V 3rd
150k-vdd 1,2V 3rd
150k-vss 1,2V 3rd
vss
1,2V 3rd
150k-vdd open
1,5V
150k-vdd
vdd
1,5V
150k-vdd 150k-vdd 1,5V
150k-vdd 150k-vss 1,5V
150k-vdd
vss
1,5V
DCDC2
CVDD2
3,3V 2nd
2,5V 2nd
2,5V 2nd
1,8V 2nd
x
DCDC3
CVDD3
3,3V 1st
3,3V 1st
x
x
x
3rd
3rd
3nd
3rd
3rd
3,3V
2,5V
2,5V
1,8V
2nd
2nd
2nd
2nd
x
3,3V
3,3V
DCDC4
VBUS
x
x
x
x
x
DCDC15 LDO3
LDO4
VLED
PVDD1
PVDD2
x
x
x
x
x
x
x 3,3V 1st
x
x 3,3V 1st
x
x 3,3V 1st 2,5V 2nd
XRES/
PWGD
4th
4th
4th
4th
4th
8th
8th
8th
8th
8th
1st
1st
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
3,3V 1st
x
3,3V 1st
x
3,3V 1st 2,5V 2nd
4th
4th
4th
4th
4th
8th
8th
8th
8th
8th
x
x
x
x
x
x
x
x
x
x
x
x
x
x
3,3V 1st
x
3,3V 1st
x
3,3V 1st 2,5V 2nd
4th
4th
4th
4th
4th
8th
8th
8th
8th
8th
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6
7
8
9
10
VPRG1
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VPRG2
lv
#
11
12
13
14
15
vdd
vdd
vdd
vdd
vdd
open
vdd
150k-vdd
150k-vss
vss
1,8V
1,8V
1,8V
1,8V
1,8V
3rd
3rd
3nd
3rd
3rd
3,3V
2,5V
2,5V
1,8V
2nd
2nd
2nd
2nd
x
3,3V
3,3V
1st
1st
x
x
x
16
17
18
19
20
vss
vss
vss
vss
vss
open
vdd
150k-vdd
150k-vss
vss
1,2V
1,2V
1,2V
1,8V
1,8V
1st
1st
1st
1st
1st
1,8V
1,8V
2,5V
2,5V
3,3
2nd
2nd
2nd
2nd
2nd
3,3V
3,0V
3,3V
3,3V
3,3V
3rd
3rd
3rd
3rd
3rd
5,0V
5,0V
5,0V
5,0V
5,0V
5th
5th
5th
5th
5th
5mA
5mA
5mA
5mA
5mA
5th
5th
5th
5th
5th
3,0V
3,0V
3,0V
3,0V
3,0V
6th
6th
6th
6th
6th
3,0V
3,0V
3,0V
3,0V
3,0V
7th
7th
7th
7th
7th
*
*
*
*
*
8th
8th
8th
8th
8th
150k-vss
open
1,2V
150k-vss
vdd
1,2V
150k-vss 150k-vdd 1,2V
150k-vss 150k-vss 1,8V
150k-vss
vss
1,8V
3rd
3rd
3rd
3rd
3rd
1,8V
1,8V
2,5V
2,5V
3,3
2nd
2nd
2nd
2nd
2nd
3,3V
3,0V
3,3V
3,3V
3,3V
1st
1st
1st
1st
1st
5,0V
5,0V
5,0V
5,0V
5,0V
5th
5th
5th
5th
5th
5mA
5mA
5mA
5mA
5mA
5th
5th
5th
5th
5th
3,0V
3,0V
3,0V
3,0V
3,0V
6th
6th
6th
6th
6th
3,0V
3,0V
3,0V
3,0V
3,0V
7th
7th
7th
7th
7th
*
*
*
*
*
8th
8th
8th
8th
8th
ca
21
22
23
24
25
*… in Special Mode the XRES is going High 85us (min 60us) after PwrUp key is released
Te
ch
ni
x … means that this regulator is not started with the start-up sequencer but has to be turned on by the 2-wire serial interface when
needed.
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AS3517 V17
Data Sheet, Confidential
am
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Figure 30 Power Up Timing
Register Description
Table 37 System Related Register
Offset
20h
24h
26h
ca
Base
2-wire serial
2-wire serial
2-wire serial
Description
Watchdog and Over-temperature control, Power down enable
Enable/disable wake-up interrupts, set shut-down time
Enable/disable junction temperature interrupt
Te
ch
ni
Name
SYSTEM
IRQ_ENRD_1
IRQ_ENRD_3
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Data Sheet, Confidential
9.3.2
Hibernation
General
Hibernation allows shutting down a part or the complete system. Hibernation can be terminated by every possible
interrupt of the AFE. E.g. one can use the RTC for a time triggered wake-up. The interrupt has to be enabled before
going to hibernation
Table 38 Hibernation Modes
VSS
150kVSS
KeepBit
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
ON
ON
LDOs
OFF
Default
OFF
As Before
No Change
No Change
OFF
Default
OFF
As Before
No Change
No Change
DCDCs
OFF
Default
OFF
As Before
No Change
No Change
OFF
Default
OFF
As Before
No Change
No Change
VBUS
OFF
OFF
No Change
No Change
No Change
No Change
Stays ON
Default
No Change
ON
No Change
No Change
DCDC15V
OFF
OFF
No Change
No Change
No Change
No Change
OFF
Default
OFF
As Before
No Change
No Change
al
id
16-25
Action
Hib. with Default
Cancel Hibernation
Hib. with Modif Settings
Cancel Hibernation
Hib. with Modif Settings
Cancel Hibernation
Hib. with Default
Cancel Hibernation
Hib. with Modif Settings
Cancel Hibernation
Hib. with Modif Settings
Cancel Hibernation
lv
VPRG2
VDD
150kVDD
OPEN
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Modes
1-15
“Hibernation with Default” means that, the voltage of the power supply is determined by VPROG1 pin.
“Hibernation with Modified Settings” means, that the voltage of the power supply is controlled by register settings.
Te
ch
ni
ca
Figure 31 Hibernate Timing
Register Description
Table 39 Hibernation Related Register
Name
PMU Hibernate
PMU ENABLE
Base
2-wire serial
2-wire serial
Offset
17h-6
18h
Description
Hibernation control
Enables writings to extended register 17h-6
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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AS3517 V17
Data Sheet, Confidential
9.3.3
Supervisor
General
This supervisor function can be used for automatic detection of BVDD brown out or junction over-temperature condition.
BVDD Supervision
The supervision level can be set in 8 steps @ 60mV from 2.74 to 3.16V. If the level is reached an interrupt can be generated. If BVDD
reaches 2.7V the AFE shuts down automatically.
Junction Temperature Supervision
al
id
The temperature supervision level can also be set by 5 bits (120 to –15oC). If the temperature reaches this level, an interrupt can be
generated. The over-temperature shutdown level is always 20oC higher.
Power Rail Monitoring
lv
The 4 main regulators have an extra monitor which measures the output voltage of the regulator. This power rail monitors are independent
from the 10bit ADC. To activate these please see related registers.
Register Description
Base
2-wire
2-wire
2-wire
2-wire
2-wire
serial
serial
serial
serial
serial
Offset
21h
23h
24h
25h
26h
Description
Battery and junction temperature supervision threshold levels
Enable/disable PVDD/CVDD monitoring interrupt and shutdown
Enable/disable PVDD/CVDD monitoring interrupt and shutdown
Enable/disable battery brown out interrupt
Enable/disable junction temperature interrupt
Te
ch
ni
ca
Name
SUPERVISOR
IRQ_ENRD_0
IRQ_ENRD_1
IRQ_ENRD_2
IRQ_ENRD_3
am
lc s
on A
te G
nt
st
il
Table 40 Supervisor Related Register
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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AS3517 V17
Data Sheet, Confidential
9.3.4
Interrupt Generation
General
All interrupt sources can get enabled or disabled by corresponding bits in the 5 IRQ-bytes. By default no interrupt source is enabled.
The XIRQ output can get configured to be PUSH/PULL or OPEN_DRAIN and ACTIVE_HIGH or ACTIVE LOW with 2 bits in IRQ_ENRD_4
register (27h). Default state is open drain and active_low.
IRQ Source Interpretation
LEVEL
The IRQ output is kept active as long as the interrupt source is present and this IRQ-Bit is enabled
EDGE
al
id
There are 3 different modules to process interrupt sources:
lv
The IRQ gets active with a high going edge of this source. The IRQ stays active until the corresponding IRQ-Register gets read.
STATUS CHANGE
De-bouncer
am
lc s
on A
te G
nt
st
il
The IRQ gets active when the source-state changes. The change bit and the status can be read to notice which interrupt was the source.
The IRQ stays active until the corresponding interrupt register gets read.
There is a de-bounce function implemented for USB and CHARGER. Since these 2 signals can be unstable for the phase of plug-in or
unplug, a de-bounce time of 512ms/256ms/128ms can be selected by 2 bits in the IRQ_ENRD_4 register (27h).
Interrupt Sources
18 IRQ events will activate the XIRQ pin:
headphone connected
Microphone 1 connected
Microphone 2 connected
Microphone 1 remote control
•
•
•
Microphone 2 remote control
Voice activation threshold reached
RTC sec/min elapsed
•
•
•
•
10bit ADC end of conversion
I²S changed
USB changed
Charger changed
•
End of charge (at 10% of programmed current )
•
Battery temperature high (at 42°C and 45°C with 100kΩ NTC)
•
RVDD low (e.g. after battery was changed)
•
•
•
Battery low (Brown-out voltage reached)
wake-up from hibernation
power-up key (pin PWRUP) pressed
•
power rail monitor: PVDD1, PVDD2, CVDD1, CVDD2
Te
ch
ni
ca
•
•
•
•
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Data Sheet, Confidential
9.3.5
Real Time Clock
General
The real time clock block is an independent block, which is still working even when the chip is shut down. The only condition for this
operation is that BVDDR has a voltage of above 1.0V. The block uses a standard 32kHz crystal that is connected to a low power
oscillator. The total power consumption is typ. 12µA. (Q32k clock buffer not operating)
The RTC seconds counter is 32bit wide and can be programmed via the 2-wire serial interface. The RTC can deliver a seconds or minutes
interrupt.
al
id
Another 23bit wide counter allows auto wake-up (max. after 96 days). This counter is internally connected to the power-up and hibernation
control block.
The RTC voltage regulator (RVDD) further supplies a 128bit SRAM. It can be used to store settings or data before shutdown.
Clock adjustment
lv
The RTC clock is adjustable in steps of 7.6ppm which allows the use of inexpensive 32kHz crystals. The nominal frequency shall be
32.768Hz. This frequency is divided down to 0.25Hz:
f = 32.768 / (4*32*1024)
am
lc s
on A
te G
nt
st
il
At the input of this divider one can add corrective counts, which allow to correct an inaccurate crystal in a range from –64 counts (=488ppm) to +63 counts (=+480ppm):
fcorrected = fcrystal / [(4*32*1024)-64+RTC_TBC]
Register Description
Table 41 RTC Related Register
Base
2-wire
2-wire
2-wire
2-wire
2-wire
2-wire
serial
serial
serial
serial
serial
serial
Offset
28h
29h
2Ah to 2Dh
19h
25h
27h
Description
RTC oscillator and counter enable
RTC interrupt and time correction settings
RTC time-base seconds registers
RTC wake-up settings and SDRAM access
Interrupt settings for RVDD under-voltage detection
Interrupt settings for getting a second or minute interrupt
Te
ch
ni
ca
Name
RTCV
RTCT
RTC_0 to RTC_3
RTC_WakeUp
IRQ_ENRD_2
IRQ_ENRD_4
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Data Sheet, Confidential
9.3.6
10-Bit ADC
General
This general purpose ADC can be used for measuring several voltages and currents to perform functions like battery monitor, temperature
supervision, button press detection, etc..
Input Sources
Table 42 ADC10 Input Sources
Range
5.120V
5.120V
2
3
4
5
6
CHGIN
VBUS
BatTemp
MIC1S
5.120V
5.120V
5.120V
2.560V
2.560V
5mV
5mV
5mV
2.5mV
2.5mV
7
MIC2S
2.560V
2.5mV
8
VBE_1uA
1.024
1mV
9
VBE_2uA
1.024
1mV
10
11
12
13..15
I_MIC1S
I_MIC2S
RVDD
Reserved
1.024mA typ.
1.024mA typ.
2.560V
1.024V
2.0uA
2.0uA
2.5mV
1mV
Reference
LSB
5mV
5mV
Description
check battery voltage of 4V LiIo accumulator
check RTC backup battery voltage (connected to BVDD inside the
package)
Source defined by DC_TEST in register 0x18
check charger input voltage
check USB input voltage
check battery charging temperature
check voltage on MIC1S for remote control or external voltage
measurement
check voltage on MIC1S for remote control or external voltage
measurement
measuring basis-emitter voltage of temperature sense transistor;
Tj = 0.5*[ADC_bit0:bit9] – 565/2
measuring basis-emitter voltage of temperature sense transistor;
Tj = 0.5*[ADC_bit0:bit9] – 575/2
check current of MIC1S for remote control detection
check current of MIC2S for remote control detection
check RTC supply voltage
for testing purpose only
al
id
Source
CHGOUT
BVDDR
lv
0
1
am
lc s
on A
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nt
st
il
Nr.
AVDD=2.9V is used as reference to the ADC. AVDD is trimmed to +/-20mV with over all precision of +/-29mV. So the absolute accuracy is
+/-1%.
Parameter
Table 43 ADC10 Parameter
Min
138k
2.534
0.198
0.396
2.475
0.7
ni
ca
Parameter
Input Divider Resistance
ADC Full Scale Range
Division Factor 1
Division Factor 2
ADC Gain Stage
Conversion Time
I_MICS Full Scale Range
Typ
180k
2.56
0.2
0.4
2.5
34
1.0
Max
234k
2.586
0.202
0.404
2.525
50
1.4
Unit
Ω
V
1
1
V
µs
mA
Notes
CHGOUT, BVDDR, VBUS, CHGIN
CHGOUT, BVDDR, VBUS, CHGIN
RVDD, BATTEMP, MIC1S, MIC2S
ch
Symbol
R DIV
ADC FS
Ratio1
Ratio2
Gain
T CON
I_MIC FS
BVDD=3.6V; Tamb=25ºC; unless otherwise specified
Register Description
Te
Table 44 ADC10 Related Register
Name
ADC_0
ADC_1
IRQ_ENRD_4
PMU_ENABLE
Base
2-wire serial
2 wire serial
2-wire serial
2-wire serial
Offset
2Eh
2Fh
27h
18h
Description
ADC source selection, ADC result<9:8>
ADC result <7:0>
Interrupt settings for end of conversion interrupt
Extended ADC source selection
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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9.3.7
Unique ID Code (64 bit OTP ROM)
General
This fuse array is used to store a unique identification number, which can be used for DRM issues. The number is generated and
programmed during the production process.
Register Description
Base
2-wire serial
Offset
38h to 3Fh
Description
Unique ID register 0 to 7
Te
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ca
am
lc s
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nt
st
il
lv
Name
UID_0 to UID_7
al
id
Table 45 UID Related Register
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Revision 1v3
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Data Sheet, Confidential
9.4
Register Description
Table 46 I2C Register Overview
Name
D<7>
D<6>
LINE_OUT1_R LO1_MUX_B
0:SUM_Stereo;1:SUM_MDiff
2:ADC_IN; 3:DAC_OUT
0
0
LINE_OUT1_L -
02h
HPH_OUT_R
0: 256ms; 1: 128ms
2: 512ms; (3: 0ms)
0
0
HPR_VOL
Gain from MUX_C to HPR= (-45.43dB … +1.07dB)
0
0
MUTE_ON_ HP_ON
K
HPDET_ON HPL_VOL
Gain from MUX_C to HPL= (-45.43dB … +1.07dB)
0
0
0
-
LO2R_VOL
Gain from MUX_D to LOUT2R= (-40.5dB … +6dB)
0
0
0
LINE_OUT2_L -
06h
MIC1_R
0
Line_IN1_R
0Bh
Line_IN1_L
0
2: 40dB
0
DAC_L
10h
ADC_R
0
0
0
0
0
0
0
0
M1R_VOL
Gain from MicAmp (N6) to Mixer (N15) = (-40.5dB … +6.0dB)
0
0
0
0
0
0
0
0
0
0
0
0
0
MIC2_AGC PRE2_GAIN
0: 28dB; 1: 34dB
_OFF
M2R_VOL
Gain from MicAmp (N4) to Mixer (N12) = (-40.5dB … +6.0dB)
0
0
M2SUP
_OFF
-
2: 40dB
0
0
0
0
0
0
MUTE_OFF RDET2_
_D
OFF
M2L_VOL
Gain from MicAmp (N4) to Mixer_In (N13)= (-40.5dB … +6.0dB)
0
0
0
-
MUTE_OFF LI1R_VOL
_B
Gain from LIN1R to Mixer (N10)= (-34.5dB … +12dB)
0
0
LI1_MODE
0
0
0
0
0
0
0
0
0
ca
MUTE_OFF LI1L_VOL
_G
Gain from LIN1L to Mixer (N17)= (-34.5dB … +12dB)
0
0
0
0
0
0
-
-
MUTE_OFF LI2R_VOL
_C
Gain from LIN2R to Mixer (N11)= (-34.5dB … +12dB)
0
0
0
LI2_MODE
0
0
0
0
0
MUTE_OFF LI2L_VOL
_F
Gain from LIN2L to Mixer (N16)= (-34.5dB … +12dB)
0
0
-
-
-
DAR_VOL
Gain from DAC (N19) to Mixer/MUX (N23)= (-40.5dB … +6dB)
0
0
0
-
MUTE_OFF _H
DAL_VOL
Gain from DAC (N22) to Mixer/MUX (N26) = (-40.5dB … +6dB)
0
0
ch
0Fh
Te
DAC_R
0
M1L_VOL
Gain from MicAmp (N6) to Mixer (N14) = (-40.5dB … +6.0dB)
00: SE_Sterep; 01: MonoDiff
10: SE_Mono
0
0
0Eh
0
0
ni
Line_IN2_L
0
0
LO2L_VOL
Gain from MUX_D to LOUT2L= (-40.5dB … +6dB)
00: SE_Sterep; 01: MonoDiff
10: SE_Mono
0
0
0Dh
0
0
0
0
MUTE_OFF RDET1_
_E
OFF
0
Line_IN2_R
0
0
0
M1SUP
_OFF
0
0Ch
0
0
MUTE_OFF _L
MIC1_AGC PRE1_GAIN
0: 28dB; 1: 34dB
_OFF
0
0
am
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on A
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nt
st
il
05h
0Ah
0
0
0: MIC1; 2: MIC2
1:MIC1_MDiff; 3: Stereo_MIC
0
0
MIC2_L
0
DAC_
DIRECT
LINE_OUT2_R LO2_MUX_D
09h
0
0
04h
MIC2_R
0
0
HP_OVC_TO
HPH_OUT_L
08h
0
LO1L_VOL
Gain from MUX_B to LOUT1L= (-40.5dB … +6dB)
03h
MIC1_L
0
MUTE_OFF _J
0
07h
D<4>
D<3>
D<2>
D<1>
D<0>
LO1R_VOL
Gain from MUX_B to LOUT1R= (-40.5dB … +6dB)
al
id
01h
D<5>
-
lv
Addr
00h
0
0
0
0
0
0
0
0
0
0
-
0: Stereo_Mic; 1:LineIN_1
2: LineIN_2; 3: AudioSUM
0
0
ADR_VOL
Gain from MUX_A to ADC (N9) = (-34.5dB … +12dB)
0
0
0
0
0
ADC_MUX_A
0
0
0
0
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Revision 1v3
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0
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AS3517 V17
Data Sheet, Confidential
Name
ADC_L
12h-1
OutContr1
D<6>
D<5>
MUTE_OFF _A
D<4>
D<3>
D<2>
D<1>
D<0>
ADL_VOL
Gain from MUX_A to ADC (N18) = (-34.5dB … +12dB)
0
0
0
14h
AudioSet_1
0: PWGD; 1: PWM
2: SPDIF; 3: PLL clock
0
0
0: 12mA PP; 1: 12mA OD
2: 4mA PP; 3: 2mA PP
0
0
0: Q32K; 1: PWM
2: SPDIF; 3: PLL clock
0
0
MUX_Q24M SPDIF_
COPY_OK
SPDIF_
SPDIF_
MCLK_INV INVALID
SPDIF_CNTR
16h
AudioSet_3
17h-1
PMU PVDD1
0
0
LIN1_ON
MIC2_ON
MIC1_ON
0
PMU PVDD2
PMU CVDD1
PMU CVDD2
PMU CVDD3
0
0
0
0
DAC_ON
-
0
0
0
0
0
0
0
BIAS_OFF SUM_OFF
AGC_OFF
IBR_DAC
0
0
0
0
0
0
0
0
0
LIN1MIX_O LIN2MIX_O MIC1MIX_O MIC2MIX_O DACMIX_O ZCU_OFF
FF
FF
FF
FF
FF
IBR_HPH
HPCM_ON
0
0
0
0
LDO_PVDD 1_OFF
0
LDO_PVDD 2_OFF
0
0
PROG_
PVDD1
VSEL_PVDD1
0
0
0h – Fh:1.2V+VSEL*50mV (1.2V – 1.95V)
10h – 1Fh: 2.0V+(VSEL-10h)*100mV (2.0V – 3.5V)
0
0
0
0
0
0
PROG_
PVDD2
0
0h – Fh:1.2V+VSEL*50mV (1.2V – 1.95V)
10h – 1Fh: 2.0V+(VSEL-10h)*100mV (2.0V – 3.5V)
0
0
0
0
VSEL_CVDD1
0
0
0
0
0h: OFF; 1h - 38h …. 0.6V+VSEL*50mV Î 0.65V – 3.40V; (38h – 3Fh …. 3.4V)
0
SKIP_OFF_ PROG_
CVDD2
CVDD2
VSEL_CVDD2
0
0
0
0
VSEL_PVDD2
SKIP_OFF_ PROG_
CVDD1
CVDD1
0
0
0
0
0h: OFF; 1h - 38h …. 0.6V+VSEL*50mV Î 0.65V – 3.40V; (38h – 3Fh …. 3.4V)
0
0
0
0
0
SKIP_OFF_ PROG_
CVDD3
CVDD3
VSEL_CVDD3
0
0
0
0
0
0
0
0
KEEP_
PVDD2
KEEP_
PVDD1
KEEP_
VLED
KEEP_
VBUS
KEEP_
CVDD3
KEEP_
CVDD2
KEEP_
CVDD1
0
0
0
0
0
0
0
17h-6
PMU Hibernate -
18h
PMU Enable
0
-
0h: OFF; 1h - 38h …. 0.6V+VSEL*50mV Î 0.65V – 3.40V; (38h – 3Fh …. 3.4V)
DC_TEST
PMU_GATE PMU_WR_ENABLE
ca
0: unused; 1: AVDD; 2: DVDD; 3: PVDD1
4: PVDD2; 5: CVDD1; 6; CVDD2; 7: CVDD3
0
0
0
0
0
1:
2:
3:
4:
6:
0
prog
prog
prog
prog
prog
17h-1
17h-2
17h-3
17h-4
17h-6
/ 12h-1 (PVDD1, OutContr1)
/ 12h-2 (PVDD2, OutContr2)
/ 12h-3 (CVDD1, PWM)
(CVDD2); 5: prog 17h-5 (CVDD3)
(Hibernate); 0,7: unused
0
0
16s
8s
4s
2s
1s
4ks
2ks
1ks
512s
256s
1k*1Ks
512ks
256ks
128ks
64ks
RTC_WakeUp 1 st write/read: WAKEUP_BYTE_1
ni
19h
0
0
0
17h-5
0
0: OFF; 1: 32kS
2: 44.1kS; 3: 48kS
0
0
ADC_R_ON ADC_L_ON LOUT2_ON LOUT1_ON LIN2_ON
0
17h-4
0: Q24
1: PLL clock
0
am
lc s
on A
te G
nt
st
il
AudioSet_2
0
0: 12mA OD; 1: 12mA PP
2: 4mA PP; 3: 2mA PP
0
0
PWM_
PWM_CYCLE
INVERTED 0: no pulses; DytyCycle = PWM_CYCLE * 0.3937%
15h
17h-3
0
MUX_Q32K
0
17h-2
0
DRIVE_Q32K
2: 4mA PP; 3: 2mA PP
0
0
PWM
0
MUX_PWGD
OutContr2_SP DRIVE_Q24M
0: 12mA PP; 1: 12mA OD
DIF
12h-3
0
DRIVE_PWGD
lv
12h-2
D<7>
-
al
id
Addr
11h
128s
64s
32s
2 nd write/read: WAKEUP_BYTE_2
32ks
16ks
8ks
ch
3 rd wirte/read: WAKEUP_BYTE_3
EnableWakeup 4k*1ks
Te
1Ah
1Bh
2k*1ks
4 th to 19 th write/read: SRAM_128
USB_UTIL_DC I_PMOS_GATE
DCDC_PS_ DCDC_
VBUS_COMP_TH
0: 1µA; 1: 2µA
DC
OFF
PMOS_OFF 0: 4.5V; 1: 3.18V
DCDC15
2: 3µA; 3: 4µA
0
0
0
DIM_UP_D DIM_RATE
0: no dimming; 1: 150ms
OWN
0
2: 300ms; 3: 500ms
0
0
0
2: 1.5V; 3: 0.6V
0
0
VBUS_SKIP VBUS_ON
_ON
0
0
I_BACKLIGHT
0 … OFF
1-31 … LED current = 1.25mA*I_BACKLIGHT (1.25mA … 38.75mA)
0
0
0
0
0
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Revision 1v3
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AS3517 V17
Data Sheet, Confidential
Addr
1Ch
Name
I2S
D<7>
D<6>
D<5>
D<4>
Please see master clock divider table
D<3>
D<2>
D<1>
D<0>
1Dh
I2S_PLL_OSC I2S_MASTE OSC24_PD I2S_
R_ON
DIRECT
0
0
0
0
0
0
0
21h
SUPERVISOR BVDD_SUP
0
1
1
IRQ_ENRD_0
24h
IRQ_ENRD_1
26h
IRQ_ENRD_3
27h
IRQ_ENRD_4
28h
RTCV
RTCT
2Ah
RTC_0
2Bh
RTC_1
2Ch
RTC_2
2Dh
RTC_3
2Eh
ADC_0
0
0
1
Temp_ShutDown = 140C – JTEMP_SUP*5C (+140C..—15C)
Temp_IRQ = 120C – JTEMP_SUP*5C (+120C .. –35C)
0
0
0
0
CHG_V
0
CHG_OFF
0
CVDD2_
EN_SD
CVDD2_
UNDER
CVDD2_
EN_IRQ
CVDD2_
OVER
CVDD1_
EN_SD
CVDD1_
UNDER
CVDD1_
EN_IRQ
CVDD1_
OVER
PDD2_
EN_SD
PDD2_
UNDER
PDD2_
EN_IRQ
PDD2_
OVER
0
0
-
0
0
0
0
PWRUP_
IRQ
WAKEUP_ VOXM2_
IRQ
IRQ
VOXM1_
IRQ
0
0
0
PDD1_
EN_SD
PDD1_
UNDER
0
PDD1_
EN_IRQ
PDD1_
OVER
0
0
CVDD3_
EN_SD
CVDD3_
UNDER
CVDD3_
EN_IRQ
CVDD3_
OVER
0
0
0
0
BATTEMP_ CHG_
HIGH
EOC
CHG_
STATUS
CHG_
USB_
CHANGED STATUS
USB_CHAN RVDD_LOW BVDD_LOW
GED
0
0
0
0
0
0
0
JTEMP_HI GH
HPH_
OVC
I2S_
STATUS
I2S_
MIC2_
MIC1_
CHANGED CONNECT CONNECT
HPH_
CONNECT
0
0
0
0
0
XIRQ_AH
XIRQ_PP
ADC_EOC
0: 512ms; 1: 256ms
2: 128ms; 3: 0ms
0
0
REM2_DET REM1_DET RTC_
UPDATE
0
0
0
0
0
RTC_ON
OSC32_ON
0
-
0
0
0
V_RVDD
0
0
T_DEB
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
ADC<9:8>
0: CHGOUT; 1: BVDDR; 2: DC_TEST; 3: CHG_IN; 4: VBUS;
5: BatTemp; 6: MSUP1; 7: MSUP2; 8: VBE_1uA; 9: VBE_2uA;
10: I_MSUP1; 11: I_MSUP2; 12; RVDD; 13, 14, 15: reserved
0
0
0
0
0
0
X
X
X
X
X
IRQ_MIN
TRTC<6:0>
0
QRTC<7:0>
ca
0
QRTC<15:8>
0
0
QRTC<23:16>
0
ni
0
QRTC<31:24>
0
0
ADC_Source<3:0>
ch
ADC_1
Te
2Fh
0
(50mA … 400mA)
0
0
SD_TIME
0
WATCHDO PWR_HOLD
G_ON
0
V(RVDD)=1V+V_RVDD*0.1V
Default is 1.2V.
0
0
29h
0
I2S_DIVIDE
R_8
HEARTBEA JTEMP_
T_ON
OFF
Vchg=3.9V+50mV*CHG_V
(3.9V … 4.25V)
0
0
0
IRQ_ENRD_2
1
BAT_TEMP CHG_I
Ichg=50mA+50mA*CHG_I
_OFF
0: 5.4s
1: 10.9s
25h
0: reserved; 1: 16-48kS
2: 8-12kS; 3: reserved
0
0
am
lc s
on A
te G
nt
st
il
23h
0: /1; 1: /2
2: /4; 3:OFF
0
JTEMP_SUP
V_BrownOut = 2..74V+BVDD_SUP*60mV
(2.74V .. 3.16V)
0
0
1
CHARGER
PLL_MODE
Design_Version<3:0>
1
22h
Q24M_DIVIDER
al
id
SYSTEM
0
lv
0
20h
0
38-3F UID_0 .. 7
ADC<7:0>
X
X
X
X
X
ID<7:0>
…
ID<63:56>
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
57 - 93
AS3517 V17
Data Sheet, Confidential
Table 47 LINE_OUT1_R Register
Name
LINE_OUT1_R
Base
Default
2-wire serial
00h
Right Line Output 1 Register
Configures MUX_B and the audio gain from MUX_B output to LOUT1R output.
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
Access Bit Description
00
R/W
Multiplexes the analog audio inputs of MUX_B to LOUT1R and
at LOUT1L
00: SUM Stereo
01: SUM mono differential (The gain of LOUT1R shall be 0dB
to hold signals in symmetry)
10: ADC (N9/N18)
11: DAC (N23/N26)
0
n/a
00000
R/W
volume settings for right line output 1, adjustable in
32 steps @ 1.5dB; gain from MUX_B to LOUT1R
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
Offset: 00h
Bit Name
LO1_MUX_B
5
4:0
LO1R_VOL
am
lc s
on A
te G
nt
st
il
lv
al
id
Bit
7:6
Table 48 LINE_OUT1_L Register
Name
LINE_OUT1_L
Offset: 01h
MUTE_OFF_J
LO1L_VOL
Te
ch
ni
5
4:0
Bit Name
ca
Bit
7
6
Base
Default
2-wire serial
00h
Left Line Output 1 Register
Configures the audio gain from MUX_B output to LOUT1L output and controls
MUTE switch J
This register is reset when the stage is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
Access Bit Description
0
n/a
0b
R/W
Control of MUTE switch J
0:line output set to mute
1: normal operation
0
n/a
00000
R/W
volume settings for left line output 1, adjustable in
32 steps @ 1.5dB; gain from MUX_B to LOUT1L
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
58 - 93
AS3517 V17
Data Sheet, Confidential
Table 49 HPH_OUT_R Register
Name
HPH_OUT_R
5
DAC_DIRECT
4:0
HPR_VOL
lv
Bit Name
HP_OVC_TO
am
lc s
on A
te G
nt
st
il
Bit
7:6
al
id
Offset: 02h
Base
Default
2-wire serial
00h
Right Headphone Output Register
Configures MUX_C and the audio gain from MUX_C output to HPR output.
This register is reset at a DVDD-POR.
Default
Access Bit Description
00
R/W
Headphone amplifier over current time out. The headphone
amplifier is powered down if an over-current is detected. The
current thresholds are 150mA at pins HPR / HPL pin or 300mA
at pin HPCM (e.g. shorted headphone outputs)
11: 0 ms ( no power down)
10: 512ms
01: 128ms
00: 256 ms
0
R/W
0: MUX_C output connected to limiter (N24/N25)
1: MUX_C output connected to DAC (N23/N26)
00000
R/W
volume settings for right headphone output, adjustable in 32
steps @ 1.5dB; gain from MUX_C to HPR output
11111: 1.07 dB gain
11110: -0.43 dB gain
..
00001: -43.93 dB gain
00000: -45.43 dB gain
Table 50 HPH_OUT_L Register
Offset: 03h
Bit Name
MUTE_ON_K
6
HP_ON
5
HPDET_ON
4:0
HPL_VOL
Te
ch
ni
Bit
7
Base
Default
2-wire serial
00h
Left Headphone Output Register
Configures the audio gain from MUX_C output to HPL output and controls
MUTE switch K
This register is reset at a DVDD-POR.
Default
Access Bit Description
0
R/W
Control of MUTE switch K
0: normal operation
1: headphone output set to mute (mute is on during power-up)
0
R/W
0: headphone stage not powered
1: power up headphone stage
0
R/W
Enables the detection when a headset gets connected. HPCM
is used as a sense pin and is biased to 150mV
0: no headphone detection
1: enable headphone detection
00000
R/W
volume settings for left headphone output, adjustable in 32
steps @ 1.5dB; gain from MUX_C output to HPL output
11111: 1.07 dB gain
11110: -0.43 dB gain
..
00001: -43.93 dB gain
00000: -45.43 dB gain
ca
Name
HPH_OUT_L
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
59 - 93
AS3517 V17
Data Sheet, Confidential
Table 51 LINE_OUT2_R Register
Name
LINE_OUT2_R
Base
Default
2-wire serial
00h
Right Line Output 2 Register
Configures MUX_B and the audio gain from MUX_B output to LOUT2R output.
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
Access Bit Description
00
R/W
Multiplexes the analog audio inputs of MUX_D to LOUT2R and
at LOUT2L
00: MIC1
01: MIC1 mono differential (The gain of LOUT2R shall be 0dB
to hold signals in symmetry)
10: MIC2
11: Stereo MIC
0
n/a
00000
R/W
volume settings for right line output 2, adjustable in
32 steps @ 1.5dB; gain from MUX_D to LOUT2R
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
Offset: 04h
Bit Name
LO2_MUX_D
5
4:0
LO2R_VOL
am
lc s
on A
te G
nt
st
il
lv
al
id
Bit
7:6
Table 52 LINE_OUT2_L Register
Name
LINE_OUT2_L
Offset: 05h
MUTE_OFF_L
LO2L_VOL
Te
ch
ni
5
4:0
Bit Name
ca
Bit
7
6
Base
Default
2-wire serial
00h
Left Line Output 2 Register
Configures the audio gain from MUX_B output to LOUT2L output and controls
MUTE switch J
This register is reset when the stage is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
Access Bit Description
0
n/a
0b
R/W
Control of MUTE switch L
0:line output set to mute
1: normal operation
0
n/a
00000
R/W
volume settings for left line output 2, adjustable in
32 steps @ 1.5dB; gain from MUX_D to LOUT2L
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
60 - 93
AS3517 V17
Data Sheet, Confidential
Table 53 MIC1_R Register
Name
MIC1_R
Offset: 06h
Bit Name
MIC1_AGC_OFF
6:5
PRE1_Gain
4:0
M1R_VOL
am
lc s
on A
te G
nt
st
il
lv
al
id
Bit
7
Base
Default
2-wire serial
00h
Right Microphone Input 1 Register
Configures the gain from microphone 1 amplifier output up to mixer input (Σ).
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
Access Bit Description
0
R/W
Control of limiter AGC (automatic gain control). Limits high
dynamic range of electrete/MEMS microphone (e.g. user
shouts or blows into microphone)
0: automatic gain control enabled
1: automatic gain control disabled
00
R/W
Sets the gain of the microphone 1 preamplifier (gain from
microphone inputs to N5)
00: gain set to 28 dB
01: gain set to 34 dB
10: gain set to 40 dB
11: reserved, do not use.
00000
R/W
volume settings for right microphone input 1, adjustable in 32
steps @ 1.5dB; gain from microphone amplifier (N6) to mixer
input (N15)
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
Table 54 MIC1_L Register
Name
MIC1_L
Offset: 07h
Bit Name
M1SUP_OFF
6
MUTE_OFF_E
5
RDET1_OFF
ch
ni
ca
Bit
7
M1L_VOL
Te
4:0
Base
Default
2-wire serial
00h
Left Microphone Input 1 Register
Configures the gain from microphone 1 amplifier output up to mixer input (Σ) and
controls MUTE switch D.
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
Access Bit Description
0
R/W
0: microphone 1 supply enabled
1: microphone supply disabled
0
R/W
Control of MUTE switch E
0: microphone input 1 set to mute
1: normal operation
0
R/W
Disables the microphone 1 detect function (30kOhm pull-up
from MIC1S to AVDD) to use the terminal as ADC-10 input
0: microphone 1 detection enabled
1: microphone detection disabled
00000
R/W
volume settings for left microphone 1 input, adjustable in 32
steps @ 1.5dB; gain from microphone amplifier (N6) to mixer
input (N14)
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
61 - 93
AS3517 V17
Data Sheet, Confidential
Table 55 MIC2_R Register
Name
MIC2_R
Offset: 08h
Bit Name
MIC2_AGC_OFF
6:5
PRE2_Gain
4:0
M2R_VOL
am
lc s
on A
te G
nt
st
il
lv
al
id
Bit
7
Base
Default
2-wire serial
00h
Right Microphone Input 2 Register
Configures the gain from microphone 2 amplifier output up to mixer input (Σ).
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
Access Bit Description
0
R/W
Control of limiter AGC (automatic gain control). Limits high
dynamic range of electrete/MEMS microphone (e.g. user
shouts or blows into microphone)
0: automatic gain control enabled
1: automatic gain control disabled
00
R/W
Sets the gain of the microphone 2 preamplifier (gain from
microphone inputs to N5)
00: gain set to 28 dB
01: gain set to 34 dB
10: gain set to 40 dB
11: reserved, do not use.
00000
R/W
volume settings for right microphone input 2, adjustable in 32
steps @ 1.5dB; gain from microphone amplifier (N4) to mixer
input (N12)
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
Table 56 MIC2_L Register
Name
MIC2_L
Offset: 09h
Bit Name
M1SUP_OFF
6
MUTE_OFF_D
5
RDET2_OFF
ch
ni
ca
Bit
7
M2L_VOL
Te
4:0
Base
Default
2-wire serial
00h
Left Microphone Input 2 Register
Configures the gain from microphone 2 amplifier output up to mixer input (Σ) and
controls MUTE switch E.
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
Access Bit Description
0
R/W
0: microphone 2 supply enabled
1: microphone supply disabled
0
R/W
Control of MUTE switch D
0: microphone input 2 set to mute
1: normal operation
0
R/W
Disables the microphone 2 detect function (30kOhm pull-up
from MIC1S to AVDD) to use the terminal as ADC-10 input
0: microphone 1 detection enabled
1: microphone detection disabled
00000
R/W
volume settings for left microphone 2 input, adjustable in 32
steps @ 1.5dB; gain from microphone amplifier (N4) to mixer
input (N13)
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
62 - 93
AS3517 V17
Data Sheet, Confidential
Table 57 LINE_IN1_R Register
Name
LINE_IN1_R
Bit
7:6
5
Bit Name
4:0
LI1R_VOL
al
id
Offset: 0Ah
Base
Default
2-wire serial
00h
Right Line Input 1 Registers
Configures the gain from analog line input pin LIN1R to mixer input (Σ) and controls
MUTE switch B.
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
Access Bit Description
00
n/a
0
R/W
Control of MUTE switch B
0: right line input is set to mute
1: normal operation
00000
R/W
volume settings for right line input 1, adjustable in 32 steps @
1.5dB; gain from line input pin (LIN1R) to mixer input (N10)
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
am
lc s
on A
te G
nt
st
il
lv
MUTE_OFF_B
Table 58 LINE_IN1_L Register
Name
LINE_IN1_L
Offset: 0Bh
Bit Name
LI1_MODE
5
MUTE_OFF_G
4:0
LI1L_VOL
Te
ch
ni
ca
Bit
7:6
Base
Default
2-wire serial
00h
Left Line Input 1 Registers
Configures the gain from analog line input pin LIN1L to mixer input (Σ) and controls
MUTE switch G.
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
Access Bit Description
00
R/W
Configures Line Input 1 (right and left channel) in accordance
with the connected input sources
00: inputs switched to single ended stereo
01: inputs switched to differential mono
10: inputs switched to single ended mono
11: reserved, do not use.
0
R/W
Control of MUTE switch G
0: left line input is set to mute
1: normal operation
00000
R/W
volume settings for right line input 1, adjustable in 32 steps @
1.5dB; gain from line input pin (LIN1L) to mixer input (N17)
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
63 - 93
AS3517 V17
Data Sheet, Confidential
Table 59 LINE_IN2_R Register
Name
LINE_IN2_R
Bit
7:6
5
Bit Name
4:0
LI2R_VOL
al
id
Offset: 0Ch
Base
Default
2-wire serial
00h
Right Line Input 2 Register
Configures the gain from analog line input pin LIN2R to mixer input (Σ) and controls
MUTE switch C.
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
Access Bit Description
00
n/a
0
R/W
Control of MUTE switch C
0: right line input is set to mute
1: normal operation
00000
R/W
volume settings for right line input, adjustable in 32 steps @
1.5dB; gain from line input pin (LIN2R) to mixer input (N11)
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
am
lc s
on A
te G
nt
st
il
lv
MUTE_OFF_C
Table 60 LINE_IN2_L Register
Name
LINE_IN2_L
Offset: 0Dh
Bit Name
LI2_MODE
5
MUTE_OFF_F
4:0
LI2L_VOL
Te
ch
ni
ca
Bit
7:6
Base
Default
2-wire serial
00h
Left Line Input 2 Registers
Configures the gain from analog line input pin LIN2L to mixer input (Σ) and controls
MUTE switch F.
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
Access Bit Description
00
R/W
Configures Line Input 2 (right and left channel) in accordance
with the connected input sources
00: inputs switched to single ended stereo
01: inputs switched to differential mono
10: inputs switched to single ended mono
11: reserved, do not use.
0
R/W
Control of MUTE switch F
0: left line input is set to mute
1: normal operation
00000
R/W
volume settings for right line input, adjustable in 32 steps @
1.5dB; gain from line input pin (LIN2L) to mixer input (N16)
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
64 - 93
AS3517 V17
Data Sheet, Confidential
Table 61 DAC_R Register
Name
DAC_R
Base
Default
2-wire serial
00h
Right DAC Output Registers
Configures the gain from DAC output to mixer input (Σ) / MUX input.
This register is reset when the block is disabled in AudioSet2 register (15h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
Access Bit Description
000
n/a
00000
R/W
Volume settings for right DAC output, adjustable in 32 steps @
1.5dB; gain from DAC output (N19) to mixer/MUX input (N23).
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
Offset: 0Eh
Bit Name
DAR_VOL
Table 62 DAC_L Register
Offset: 0Fh
Bit
7
6
MUTE_OFF_H
DAL_VOL
Te
ch
ni
ca
5
4:0
Bit Name
Base
Default
2-wire serial
00h
Left DAC output Registers
Configures the gain from DAC output to mixer input (Σ) / MUX input and controls MUTE
switch H.
This register is reset when the block is disabled in AudioSet2 register (15h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
Access Bit Description
0
n/a
0
R/W
Control of MUTE switch H
0: DAC output is set to mute
1: normal operation
0
n/a
00000
R/W
Volume settings for left DAC output, adjustable in 32 steps @
1.5dB: gain from DAC output (N22) to mixer/MUX input (N26).
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
am
lc s
on A
te G
nt
st
il
Name
DAC_L
lv
al
id
Bit
7:5
4:0
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
65 - 93
AS3517 V17
Data Sheet, Confidential
Table 63 ADC_R Register
Name
ADC_R
Base
Default
2-wire serial
00h
Right ADC input Registers
Configures MUX_A and the gain from MUX_A output to the ADC input
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
Access Bit Description
00
R/W
Connect MUX A output to following inputs
00: Microphone (N4/N6)
01: Line_IN1 (N1/N8)
10: Line_IN2 (N2/N7)
11: Audio SUM (N24/N25)
0
n/a
00000
R/W
Volume settings for right ADC input, adjustable in 32 steps @
1.5dB; gain from MUX_A output to ADC input (N9).
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
Bit Name
ADC_MUX_A
5
4:0
ADR_VOL
am
lc s
on A
te G
nt
st
il
lv
Bit
7:6
al
id
Offset: 10h
Table 64 ADC_L Register
Name
ADC_L
Offset: 11h
Bit
7
6
MUTE_OFF_A
ADL_VOL
Te
ch
ni
ca
5
4:0
Bit Name
Base
Default
2-wire serial
00h
Left ADC input Registers
Configures the gain from MUX_A output to the ADC input and controls MUTE switch A.
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
Access Bit Description
0
n/a
0
R/W
Control of MUTE switch A
0: ADC input is set to mute
1: normal operation
0
n/a
00000
R/W
Volume settings for left ADC input, adjustable in 32 steps @
1.5dB, gain from MUX_A output to ADC input (N18).
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
66 - 93
AS3517 V17
Data Sheet, Confidential
Table 65 Output Control Register
Name
OutContr1
Offset: 12h-1
Bit Name
DRIVE_PWGD
5:4
MUX_PWGD
3:2
DRIVE_Q32K
1:0
MUX_Q32K
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
lv
al
id
Bit
7:6
Base
Default
2-wire serial
00h
Q32k and PWGD Output Control Register
Configures PWGD pin (Power Good) and Q32k pin (output of 32kHz oscillator).
This is an extended register and needs to be enabled by writing 001b to Reg. 18h first.
This register is reset at a DVDD-POR.
Default
Access Bit Description
00
R/W
Enables the PWGD output pin either to open-drain or push-pull
and sets various driving strengths
00: 12mA push-pull output
01: 12mA open-drain output
10: 4mA push-pull output
11: 2mA push-pull output
00
R/W
Multiplexes various digital signals to the PWGD output pin
00: PowerGood control signal
01: PWM signal to dim LEDs etc.
10: SPDIF converted from SDI to DAC
11: PLL output clock
00
R/W
Enables the Q32k output pin either to open-drain or push-pull
and sets various driving strengths
00: 12mA push-pull output
01: 12mA open-drain output
10: 4mA push-pull output
11: 2mA push-pull output
00
R/W
Multiplexes various digital signals to the Q32k output pin
00: 32kHz RTC clock
01: PWM signal to dim LEDs etc.
10: SPDIF converted from SDI to DAC
11: PLL output clock
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
67 - 93
AS3517 V17
Data Sheet, Confidential
Table 66 SPDIF Register
Name
OutContr2_SPDIF
Offset: 12h-2
Bit Name
DRIVE_Q24M
5
MUX_Q24M
4
SPDIF_COPY_OK
3
SPDIF_MCLK_INV
2
SPDIF_INVALID
1:0
SPDIF_CNTR
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Bit
7:6
Base
Default
2-wire serial
00h
SPDIF and Q24M Output Control Register
Adds status bits to the SPDIF bit-stream, configures the SPDIF output and the Q24M
pin (output of 24MHz oscillator)
This is an extended register and needs to be enabled by writing 010b to Reg. 18h first.
This register is reset at a DVDD-POR.
Default
Access Bit Description
00
R/W
Enables the Q24M output pin either to open-drain or push-pull
and sets various driving strengths
00: 12mA push-pull output
01: 12mA open-drain output
10: 4mA push-pull output
11: 2mA push-pull output
0
R/W
Multiplexes various digital signals to the Q24M output pin
0: 24MHz oscillator clock
1: PLL output clock
0
SPDIF copy control bit
0: copy not permitted
1: copy permitted
0
SPDIF master clock control bit
0: master clock
1: master clock inverted
0
SPDIF sample status bit
0: sample valid
1: sample invalid
00
R/W
SPDIF output ON/OFF control and sample rate status bits
00: SPDIF output OFF
01: SPDIF output ON (32kS)
10: SPDIF output ON (44.1kS)
11: SPDIF output ON (48kS)
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
68 - 93
AS3517 V17
Data Sheet, Confidential
Table 67 PWM Register
Offset: 12h-3
Bit
7
Bit Name
PWM_INVERTED
6:0
PWM_CYCLE
Base
Default
2-wire serial
00h
PWM Output Control Register
Sets the PWM output duty cycle and signal polarity.
This is an extended register and needs to be enabled by writing 011b to Reg. 18h first.
This register is reset at a DVDD-POR.
Default
Access Bit Description
0
R/W
PWM output polarity
0: not inverted
1: inverted
0000000
R/W
Sets the PWM duty cycle
Duty Cycle = PWM_CYCLE * 0.3937%
PWM_CYCLE = 0 means no pulse
al
id
Name
PWM
lv
Table 68 AudioSet_1 Register
Bit Name
ADC_R_ON
6
ADC_L_ON
5
LOUT2_ON
4
LOUT1_ON
3
LIN2_ON
2
LIN1_ON
1
MIC2_ON
0
MIC1_ON
Te
ch
ni
Bit
7
ca
Offset: 14h
Base
Default
2-wire serial
00h
First Audio Set Register
Powers the various audio inputs and outputs UP or DOWN.
Attention: This control register resets and holds microphone, line out, and ADC related
registers in reset. After activation the required register settings need to be reprogrammed.
This register is reset at a DVDD-POR.
Default
Access Bit Description
0
R/W
0: ADC right channel powered down
1: ADC right channel enabled for recording
0
R/W
0: ADC left channel powered down
1: ADC left channel enabled for recording
0
R/W
0: Line output 2 powered down
1: Line output enabled
0
R/W
0: Line output 1 powered down
1: Line output enabled
0
R/W
0: Line input 2 powered down
1: Line input 2 enabled
0
R/W
0: Line input 1 powered down
1: Line input 1 enabled
0
R/W
0: Microphone input 2 powered down
1: Microphone input 1 enabled
0
R/W
0: Microphone input 1 powered down
1: Microphone input 1 enabled
am
lc s
on A
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nt
st
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Name
AudioSet_1
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
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AS3517 V17
Data Sheet, Confidential
Table 69 AudioSet_2 Register
Name
AudioSet_2
Offset: 15h
Bit Name
BIAS_OFF
6
SUM_OFF
5
AGC_OFF
4:3
IBR_DAC<1:0>
2
DAC_ON
lv
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Te
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1:0
al
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Bit
7
Base
Default
2-wire serial
00h
Second Audio Set Register
Powers various internal audio blocks UP or DOWN and controls bias current.
Attention: This control register resets and holds DAC related registers in reset. After
activation the required register settings need to be re-programmed.
This register is reset at a DVDD-POR.
Default
Access Bit Description
0
R/W
Power-down of the AGND bias. This bit can be set, if the AFE
is used for digital data transfer and PMU functions only and all
the analog audio blocks are not used.
0: bias enabled
1: bias disabled, for power saving in non audio mode
0
R/W
Power-down of ΣR and ΣL
0: Mixer stage enabled (limits output signal to 1Vp)
1: Mixer stage powered down
0
R/W
Switches the signal limiter OFF (N20/N21)
0: automatic gain control for summing stage enabled
1: automatic gain control for summing stage disabled
00
R/W
Bias current settings for DAC:
00: 50%
01: 60%
10: 75%
11: 100%
0
R/W
0: DAC powered down
1: DAC enabled
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
70 - 93
AS3517 V17
Data Sheet, Confidential
Table 70 AudioSet_3 Register
Name
AudioSet_3
LIN2MIX_OFF
5
MIC1MIX_OFF
4
MIC2MIX_OFF
3
DACMIX_OFF
2
ZCU_OFF
1
IBR_HPH
0
HPCM_ON
lv
6
am
lc s
on A
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nt
st
il
Bit Name
LIN1MIX_OFF
Te
ch
ni
ca
Bit
7
al
id
Offset: 16h
Base
Default
2-wire serial
00h
Third Audio Set Register
Sets headphone output bias currents and operation modes and enables audio signal
inputs to ΣR and ΣL.
This register is reset at a DVDD-POR.
Default
Access Bit Description
0
R/W
Input from line input 1 to ΣR and ΣL
0: ON
1: OFF
0
R/W
Input from line input 2 to ΣR and ΣL
0: ON
1: OFF
0
R/W
Input from microphone 1 to ΣR and ΣL
0: ON
1: OFF
0
R/W
Input from microphone 2 to ΣR and ΣL
0: ON
1: OFF
0
R/W
Input from DAC to ΣR and ΣL
0: ON
1: OFF
0
R/W
Zero cross gain update of audio outputs. Audio gain settings
changes will only be executed when the signal level is close to
zero
0: zero cross update enabled
1: zero cross update disabled
0
R/W
Bias current increase for the headphone amplifier depending
on load conditions
0: 100%
1: 150%
0
R/W
Power-up of the headphone common mode buffer:
0: headphone CM buffer is switched off
1: headphone CM buffer is switched on
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
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AS3517 V17
Data Sheet, Confidential
Table 71 PMU PVDD1 Register
Name
PMU PVDD1
Offset: 17h-1
Bit Name
LDO_PVDD1_OFF
6
5
PROG_PVDD1
4:0
VSEL_PVDD1
am
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al
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Bit
7
Base
Default
2-wire serial
00h
PVDD1 Low Drop-Out Regulator (LDO3) Control Register
This is an extended register and needs to be enabled by writing 001b to Reg. 18h first.
This register is reset at a DVDD-POR.
Default
Access Bit Description
0
R/W
Power-down of LDO for PVDD1
0: PVDD1 (LDO3) enable
1: PVDD1 (LDO3) power-down
0
n/a
0
R/W
Enables settings either selected by external pins (VPRGx) or
settings stored in the 17h-1 register
0: VPRGx pins controlled
1: Register controlled
00000
R/W
The voltage select bits set the LDO output in 2 different
resolution ranges
Range: 00h until 0Fh in 50mV steps
PVDD1=1.2V+VSEL_PVDD1*50mV
(1.2V until 1.95V)
Range: 10h until 1Fh in 100mV steps
PVDD1=2.0V+VSEL_PVDD1*100mV
(2.0V until 3.5V)
Table 72 PMU PVDD2 Register
Name
PMU PVDD2
Offset: 17h-2
Bit Name
LDO_PVDD2_OFF
6
5
PROG_PVDD2
4:0
VSEL_PVDD2
Te
ch
ni
ca
Bit
7
Base
Default
2-wire serial
00h
PVDD2 Low Drop-Out Regulator (LDO4) Control Register
This is an extended register and needs to be enabled by writing 010b to Reg. 18h first.
This register is reset at a DVDD-POR.
Default
Access Bit Description
0
R/W
Power-down of LDO for PVDD2
0: PVDD2 (LDO4) enable
1: PVDD2 (LDO4) power-down
0
n/a
0
R/W
Enables settings either selected by external pin (VPRGx) or
settings stored in the 17h-2 register
0: VPRGx pins controlled
1: Register controlled
00000
R/W
The voltage select bits set the LDO output in 2 different
resolution ranges
Range: 00h until 0Fh in 50mV steps
PVDD2=1.2V+VSEL_PVDD1*50mV
(1.2V until 1.95V)
Range: 10h until 1Fh in 100mV steps
PVDD2=2.0V+VSEL_PVDD1*100mV
(2.0V until 3.5V)
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
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AS3517 V17
Data Sheet, Confidential
Table 73 PMU CVDD1 Register
Name
PMU CVDD1
Offset: 17h-3
Bit Name
SKIP_OFF_CVDD1
6
PROG_CVDD1
5:0
VSEL_CVDD1
am
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al
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Bit
7
Base
Default
2-wire serial
00h
CVDD1 DC/DC Buck Regulator Control Register
This is an extended register and needs to be enabled by writing 011b to Reg. 18h first.
This register is reset at a DVDD-POR.
Default
Access Bit Description
0
R/W
Disables pulse skip mode
0: 170mA current force / pulse skip mode enabled
1: current force / pulse skip mode disabled (only ON without
load)
0
R/W
Enables settings either selected by external pin (VPRGx) or
settings stored in the 17h-3 register
0: VPRGx pins controlled
1: Register controlled
00000
R/W
The voltage select bits set the DC/DC output voltage level and
power the DC/DC converter down.
00000: DC/DC powered down
01h until 38h in 50mV steps
CVDD1=0.6V+VSEL_CVDD1*50mV
(0.65V until 3.4V)
38h until 3Fh = 3.4V (no change)
Table 74 PMU CVDD2 Register
Name
PMU CVDD2
Offset: 17h-4
Bit Name
SKIP_OFF_CVDD2
6
PROG_CVDD2
5:0
VSEL_CVDD2
Te
ch
ni
ca
Bit
7
Base
Default
2-wire serial
0x00
CVDD2 DC/DC Buck Regulator Control Register
This is an extended register and needs to be enabled by writing 100bto Reg. 18h first.
This register is reset at a DVDD-POR.
Default
Access Bit Description
0
R/W
Disables pulse skip mode
0: 170mA current force / pulse skip mode enabled
1: current force / pulse skip mode disabled (only ON without
load)
0
R/W
Enables settings either selected by external pin (VPRGx) or
settings stored in the 17h-4 register
0: VPRGx pins controlled
1: Register controlled
00000
R/W
The voltage select bits set the DC/DC output voltage level and
power the DC/DC converter down.
00000: DC/DC powered down
01h until 38h in 50mV steps
CVDD2=0.6V+VSEL_CVDD1*50mV
(0.65V until 3.4V)
38h until 3Fh = 3.4V (no change)
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
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AS3517 V17
Data Sheet, Confidential
Table 75 PMU CVDD3 Register
Name
PMU CVDD3
Offset: 17h-5
Bit Name
SKIP_OFF_CVDD3
6
PROG_CVDD3
5:0
VSEL_CVDD3
am
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Bit
7
Base
Default
2-wire serial
0x00
CVDD3 DC/DC Buck Regulator Control Register
This is an extended register and needs to be enabled by writing 101bto Reg. 18h first.
This register is reset at a DVDD-POR.
Default
Access Bit Description
0
R/W
Disables pulse skip mode
0: 170mA current force / pulse skip mode enabled
1: current force / pulse skip mode disabled (only ON without
load)
0
R/W
Enables settings either selected by external pin (VPRGx) or
settings stored in the 17h-5 register
0: VPRGx pins controlled
1: Register controlled
00000
R/W
The voltage select bits set the DC/DC output voltage level and
power the DC/DC converter down.
00000: DC/DC powered down
01h until 38h in 50mV steps
CVDD2=0.6V+VSEL_CVDD1*50mV
(0.65V until 3.4V)
38h until 3Fh = 3.4V (no change)
Table 76 PMU Hibernate Register
Name
PMU Hibernate
Offset: 17h-6
Bit
7
6
Bit Name
5
KEEP_PVDD1
4
KEEP_VLED
3
KEEP_VBUS
2
KEEP_CVDD3
ch
ni
ca
KEEP_PVDD2
KEEP_CVDD2
Te
1
0
Base
Default
2-wire serial
00h
PMU Hibernation Control Register (PVDD1/2, CVDD1/2/3, VLED)
Hibernation is started when writing to this register.
This is an extended register and needs to be enabled by writing 110b to Reg. 18h first.
This register is reset at a DVDD-POR.
Default
Access Bit Description
0
n/a
0
R/W
Keeps the programmed PVDD2 level during hibernation
0: power down PVDD2
1: keep PVDD2
0
R/W
Keeps the programmed PVDD1 level during hibernation
0: power down PVDD1
1: keep PVDD1
0
R/W
Keeps the 15V DC/DC step-up for backlight switched on
0: power down CVDD1
1: keep CVDD1
0
R/W
Keeps the programmed VBUS level during hibernation
0: power down CVDD2
1: keep CVDD2
0
R/W
Keeps the programmed CVDD3 level during hibernation
0: power down CVDD3
1: keep CVDD3
0
R/W
Keeps the programmed CVDD2 level during hibernation
0: power down CVDD2
1: keep CVDD2
0
R/W
Keeps the programmed CVDD1 level during hibernation
0: power down CVDD1
1: keep CVDD1
KEEP_CVDD1
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
74 - 93
AS3517 V17
Data Sheet, Confidential
Table 77 PMU ENABLE Register
Name
PMU ENABLE
Offset: 18h
Bit Name
DC_TEST
3
PMU_GATE
0:2
PMU_WR_ENABLE
Te
ch
ni
ca
am
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nt
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al
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Bit
7
6:4
Base
Default
2-wire serial
00h
PMU Extension Enable Register
Enables 12h and 17h to write into extended registers and allows multiplexing supply
voltages for monitoring via ADC10. This register is reset at a DVDD-POR.
Default
Access Bit Description
0
n/a
000
R/W
Allows multiplexing internal and external supply voltages to
one DC test node which can be further multiplexed to ADC10.
The accuracy is 5mV/LSB (see reg. 2Eh)
000: not used
001: AVDD
010: DVDD
011: PVDD1
100: PVDD2
101: CVDD1
110: CVDD2
111: CVDD3
0
R/W
Enables all settings made in registers 0x17-x at once. If this
bit is set, changes are activated as soon as they are written to
the related register.
0: no change
1: change at once
000
R/W
Enables extended registers 12h-x and 17h-x
000: not used
001: enables 17h-1 for PVDD1 settings
enables 12h-1 for OutCntr1 settings
010: enables 17h-2 for PVDD2 settings
enables 12h-2 for OutCntr2_SPDIF settings
011: enables 17h-3 for CVDD1 settings
enables 12h-3 for PWM settings
100: enables 17h-4 for CVDD2 settings
101: enables 17h-5 for CVDD3 settings
110: enables 17h-6 for hibernation settings
111: not used
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
75 - 93
AS3517 V17
Data Sheet, Confidential
Table 78 RTC_WakeUp Register
Byte Name
WAKE_UP_BYTE0
(1 st write to 0x19 is
byte 0)
7:0
WAKE_UP_BYTE1
(2 nd write to 0x19
is byte 1)
7:0
WAKE_UP_BYTE2
(3 rd write to 0x19 is
byte 2)
7:0
SRAM_128
(4 th … 19 th write to
0x19 programs the
128bit static SRAM)
Te
ch
ni
ca
am
lc s
on A
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nt
st
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Adr.
7:0
al
id
Offset: 19h
Base
Default
2-wire serial
n/a
RTC Wake-Up and SRAM Register
Sets and enables the RTC wake-up counter and programs the 128bit SRAM. 3 bytes
need to be written in a sequence to set the counter. The 3-byte sequence allows to set
the counter to every value between 1sec and 8388608sec (=97 days). The MSB of the
3 rd byte enables the wake-up counter. Byte 4 …19 will program the static 128bit SRAM
which is supplied by RVDD. This register is reset at a RVDD-POR.
Default
Access Bit Description
00h
R/W
0000 0001: 1sec
0000 0010: 2sec
0000 0100: 4sec
0000 1000: 8sec
0001 0000: 16sec
0010 0000: 32sec
0100 0000: 64sec
1000 0000: 128sec
00h
R/W
0000 0001: 256sec
0000 0010: 512sec
0000 0100: 1 024sec
0000 1000: 2 048sec
0001 0000: 4 096sec
0010 0000: 8 192sec
0100 0000: 16 384sec
1000 0000: 32 768sec
00h
R/W
000 0001: 65 536sec
000 0010: 131 072sec
000 0100: 262 144sec
000 1000: 524 288sec
001 0000: 1 048 576sec
010 0000: 2 097 152sec
100 0000: 4 194 304sec
0xxx xxxxxb = wake-up disabled
1xxx xxxxxb = wake-up enabled
00000000 R/W
xxxx xxxxb = byte 4
:
xxxx xxxxb = byte 19
lv
Name
RTC_WakeUp
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
76 - 93
AS3517 V17
Data Sheet, Confidential
Table 79 USB_UTIL Register
Name
USB_UTIL_DCDC
Offset: 1Ah
Bit Name
I_PMOS_GATE
5
DCDC_PS_OFF
4
DCDC_PMOS_OFF
3:2
VBUS_COMP_TH
1
VBUS_SKIP_ON
0
VBUS_ON
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
lv
al
id
Bit
7:6
Base
Default
2-wire serial
00h
USB Utility Register
Controls VBUS output voltage and the external transistor as well as special mode bits
for the DCDC step-down converters
This register is reset at a DVDD-POR.
Default
Access Bit Description
00
R/W
Sets the gate current level into the external PMOS transistor to
control the inrush current to VBUS
00: 1µA
01: 2µA
10: 3µA
11: 4µA
0
R/W
Disables 200uA power saving in skip mode
0: Power savings ON
1: Power savings OFF
0
R/W
Disables the PMOS of DCDC step down 1, 2 and 3 to be
switched fully on, if the regulator cannot achieve the
programmed output voltage anymore.
0: PMOS fully ON
1: PMOS switching
00
R/W
Sets the threshold for the VBUS comparator. The output can
be read in register 25h.
00: 4.5V
01: 3.18V
10: 1.5V
11: 0.6V
0
R/W
Enables the skip mode for the VBUS 1:2 charge pump which
increases efficiency for small loads connected to VBUS supply,
but increases VBUS supply ripple
0
R/W
Switches the VBUS output voltage ON and OFF
0: VBUS output voltage disabled
1: VBUS output voltage enabled
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
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AS3517 V17
Data Sheet, Confidential
Table 80 DCDC15 Register
Name
DCDC15
Offset: 1Bh
Bit Name
DIM_UP_DOWN
6:5
DIM_RATE
4:0
I_BACKLIGHT
Name
I2S
Offset: 1Ch
Bit Name
I2S_DIVIDER
lv
Base
Default
2-wire serial
00h
I2S Mode Control Register (Master Mode only)
Contains lower 8 bits for I2S master mode clock generation divider.
This register is reset at a DVDD-POR.
Default
Access Bit Description
00h
R/W
Please see master clock divider table
Te
ch
ni
ca
Bit
7:0
am
lc s
on A
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st
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Table 81 I2S Register
al
id
Bit
7
Base
Default
2-wire serial
00h
15V DCDC Step-up Control Register
Controls the back-light current and back-light dim rate.
This register is reset at a DVDD-POR.
Default
Access Bit Description
0
R/W
Starts dimming UP/DOWN or switches LED back-light ON/OFF
when DIM_RATE = 00b
0: dim DOWN
1: dim UP
00
R/W
Sets the dim rate of the LED back-light current from 0mA to
I_BACKLIGHT and vice versa
00: no dimming (immediate ON/OFF)
01: 150ms
10: 300ms
11: 500ms
00000
R/W
Sets the current into pin ISINK in 1.25mA steps (internal
current source to control LED backlight current). Setting
11111b enables the voltage feedback mode to supply e.g.
OLEDs with a constant voltage supply.
00000: DCDC15 switched off
00001: 1.25mA
00010: 2.5mA
..
11110: 37.5mA
11111: 38.75mA
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
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AS3517 V17
Data Sheet, Confidential
Table 82 I2S_PLL_OSC Register
Name
I2S_PLL_OSC
Offset: 1Dh
Bit Name
I2S_MASTER_ON
6
OSC24_PD
5
I2S_DIRECT
4:3
Q24M_DIVIDER
2:1
PLL_MODE
0
I2S_DIVIDER_8
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
lv
al
id
Bit
7
Base
Default
2-wire serial
00h
I2S, PLL and Oscillator Mode Control Registers
This register is reset at a DVDD-POR.
Default
Access Bit Description
0
R/W
Switched the I2S master mode on
0: I2S slave mode operation
1: I2S master mode
0
R/W
Powers the 12-24MHz oscillator down. For operation a 1224MHz crystal needs to be connected to pins XIN24/XOUT24.
0: 12-24MHz oscillator enabled
1: powered down
0
R/W
Switches the PWGD pin to an input for an external master
clock (e.g. coming form the CPU). This bit overwrites prior
setting for the PWGD pin. Only valid fro I2S slave mode
operation.
0: disabled
1: enabled
00
R/W
Sets the divider for Q24M clock output or powers Q24M clock
output buffer down
00: divide by 1
01:divide by 2
10:divide by 4
11: OFF
00
R/W
Preset of PLL bias for the following sampling frequencies
00: reserved
01:16-48kS
10: 8-12kS
11: reserved
0
R/W
Bit 8 of I2S_DIVIDER (Reg. 1Ch)
Please see master clock divider table
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
79 - 93
AS3517 V17
Data Sheet, Confidential
Table 83 System Register
Offset: 20h
Bit Name
Version <3:0>
3
HEARTBEAT_ON
2
JTEMP_OFF
1
WATCHDOG_ON
0
PWR_HOLD
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
lv
Bit
7:4
Base
Default
2-wire serial
E1h
System Settings Register
Controls the powering down conditions of the AFE. The IC can also be emergency shut
down by a high level for 5.4sec (or 10.9sec see reg. 24h) at the PWRUP input pin
This register is reset at a DVDD-POR.
Default
Access Bit Description
1111
R
AFE number to identify the design version
1111: revision 7
0
R/W
Heartbeat (HBT) Watchdog
The watchdog counter will be reset by a rising edge at the HBT
input pin which has to occur at least every 500ms. If the
watchdog counter is not reset, the AFE will be powered down.
When start-up sequence #16-#25 is selected, no power down
is performed but a reset invoked via the XRES output pin
(pulse duration = 86µs typ., 60µs min)
0: HBT watchdog is disabled
1: HBT watchdog is enabled
0
R/W
Junction temperature supervision (level can be set in register
21h)
0: temperature supervision enabled
1: temperature supervision disabled
0
R/W
2-wire serial interface watchdog
To reset the watchdog counter a 2-wire serial read operation
has to be performed at least every 500ms. If the watchdog
counter is not reset, the AFE will be powered down.
0: watchdog is disabled
1: watchdog is enabled
1
R/W
0: power up hold is cleared and AFE is powered down
1: set to on after power on
al
id
Name
System
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
80 - 93
AS3517 V17
Data Sheet, Confidential
Table 84 Supervisor Register
Name
SUPERVISOR
Base
Default
2-wire serial
00h
Supervisor Register
Sets the threshold levels of battery supply and junction temperature supervision.
This register is reset at a DVDD-POR.
Default
Access Bit Description
000
R/W
Sets the threshold (brown-out voltage) at the BVDD input pin
for an interrupt at low battery condition
V_BrownOut=2.74+BVDD_Sup*60mV
000: 2.74V
001: 2.80V
…
110: 3.10V
111: 3.16V
00000
R/W
Sets the threshold for junction temperature emergency
shutdown and junction temperature interrupt
Invoke shutdown at: JTemp_SD=140-JTEMP_Sup*5°C
Invoke interrupt at: JTemp_IRQ=120-JTEMP_Sup*5°C
4:0
JTEMP_SUP
lv
Bit Name
BVDD_SUP
am
lc s
on A
te G
nt
st
il
Bit
7:5
al
id
Offset: 21h
Table 85 Charger Register
Name
CHARGER
Offset: 22h
Bit Name
BAT_TEMP_OFF
6:4
CHG_I
ch
ni
ca
Bit
7
Base
Default
2-wire serial
00h
Charger Control Register
Sets the charging current, end of charge voltage and battery temp. supervision.
This register is reset at a DVDD-POR.
Default
Access Bit Description
0
R/W
0: enables 15uA supply for external 100k NTC resistor
1: disables supply
000
R/W
set maximum charging current
111: 400 mA
110: 350 mA
101: 300 mA
100: 250 mA
011: 200 mA
010: 150 mA
001: 100 mA
000: 50 mA
000
R/W
set maximum charger voltage in 50mV steps
111: 4.25 V
110: 4.2 V
..
001: 3.95 V
000: 3.9 V
0
R/W
0: enables Charger
1: disables Charger
CHG_V
Te
3:1
0
CHG_OFF
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
81 - 93
AS3517 V17
Data Sheet, Confidential
Table 86 First Interrupt Register
CVDD1_EN_SD
0
W
CVDD1_UNDER
x
R
CVDD1_EN_IRQ
0
W
CVDD1_OVER
x
R
0
W
Offset: 23h
Bit Name
CVDD2_EN_SD
6
CVDD2_UNDER
CVDD2_EN_IRQ
5
4
PVDD2_EN_SD
2
PVDD2_UNDER
PVDD2_EN_IRQ
x
0
R
W
1
PVDD2_OVER
PVDD1_EN_SD
x
0
R
W
0
PVDD1_UNDER
PVDD1_EN_IRQ
ch
ni
ca
3
x
0
R
W
x
R
Enables interrupt for over-voltage/under-voltage supervision of
CVDD1
0: disable
1: enable
This bit is set when a +8% over-voltage at CVDD1 occurs
Invokes shut-down of AFE when a –10% under-voltage spike at
PVDD2 occurs
0: disable
1: enable
This bit is set when a –5% under-voltage at PVDD2 occurs
Enables interrupt for over-voltage/under-voltage supervision of
PVDD2
0: disable
1: enable
This bit is set when a +5% over-voltage at PVDD2 occurs
Invokes shut-down of AFE when a –10% under-voltage spike at
PVDD1 occurs
0: disable
1: enable
This bit is set when a –5% under-voltage at PVDD1 occurs
Enables interrupt for over-voltage/under-voltage supervision of
PVDD1
0: disable
1: enable
This bit is set when a +5% over-voltage at PVDD1 occurs
Te
PVDD1_OVER
Invokes shut-down of AFE when a –10% under-voltage spike at
CVDD1 occurs
0: disable
1: enable
This bit is set when a –5% under-voltage at CVDD1 occurs
am
lc s
on A
te G
nt
st
il
Bit
7
al
id
CVDD2_OVER
Base
Default
2-wire serial
00h
First Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding
interrupts, while with reading you get the actual interrupt status and will clear the
register at the same time. It is not possible to read back the interrupt enable/disable
settings. This register is reset at a DVDD-POR.
Default
Access Bit Description
0
W
Invokes shut-down of AFE when a –10% under-voltage spike at
CVDD2 occurs
0: disable
1: enable
x
R
This bit is set when a –5% under-voltage at CVDD1 occurs
0
W
Enables interrupt for over-voltage/under-voltage supervision of
CVDD2
0: disable
1: enable
x
R
This bit is set when a +8% over-voltage at CVDD1 occurs
lv
Name
IRQ_ENRD_0
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
82 - 93
AS3517 V17
Data Sheet, Confidential
Table 87 Second Interrupt Register
Name
IRQ_ENRD_1
Offset: 24h
Bit Name
SD_TIME
6
5
PWRUP_IRQ
4
WAKEUP_IRQ
3
VOXM2_IRQ
lv
am
lc s
on A
te G
nt
st
il
VOXM1_IRQ
0
W
x
R
0
W
x
R
ca
2
al
id
Bit
7
Base
Default
2-wire serial
00h
Second Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding
interrupts, while with reading you get the actual interrupt status and will clear the
register at the same time. It is not possible to read back the interrupt enable/disable
settings. This register is reset at a DVDD-POR.
Default
Access Bit Description
0
R/W
Control bit which sets the emergency shut-down time from
5.4sec to 10.9sec. The shut-down of AS3517 is invoked by a
high signal at the PWRUP input pin.
0: 5.4sec
1: 10.9sec
0
n/a
0
W
Enables interrupt which is invoked whenever a high signal at
the PWRUP input pin occurs
0: disable
1: enable
x
R
This bit is set whenever a high level of min. BVDD/3 at the
PWRUP input pin occurs (PWRUP pin is commonly connected
to the power-up button)
0
W
Enables interrupt which is invoked whenever a wake-up from
RTC wake-up counter occurs
0: disable
1: enable
X
R
This bit is set when a wake-up has been invoked by the RTC
wake-up counter.
CVDD3_EN_SD
0
CVDD3_UNDER
CVDD3_EN_IRQ
0
ch
ni
1
Te
CVDD3_OVER
W
x
0
R
W
x
R
Enables interrupt which is invoked by reaching a voltage
threshold at MIC2 input (voice activation)
0: disable
1: enable
This bit is set when a voltage threshold of 5mV RMS (unfiltered)
at MIC2 has been reached (voice activation)
Enables interrupt which is invoked by reaching a voltage
threshold at MIC1 input (voice activation)
0: disable
1: enable
This bit is set when a voltage threshold of 5mV RMS (unfiltered)
at MIC1 has been reached (voice activation)
Invokes shut-down of AFE when a –10% under-voltage spike at
CVDD2 occurs
0: disable
1: enable
This bit is set when a –5% under-voltage at CVDD1 occurs
Enables interrupt for over-voltage/under-voltage supervision of
CVDD2
0: disable
1: enable
This bit is set when a +8% over-voltage at CVDD1 occurs
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
83 - 93
AS3517 V17
Data Sheet, Confidential
Table 88 Third Interrupt Register
Offset: 25h
Bit Name
BATTEMP_HIGH
(level)
6
CHG_EOC
(level)
5
CHG_STATUS
4
CHG_CHANGED
(status change)
3
USB_STATUS
2
USB_CHANGED
(status change)
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
lv
Bit
7
Base
Default
2-wire serial
00h
Third Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding
interrupts, while with reading you get the actual interrupt status and will clear the
register at the same time. It is not possible to read back the interrupt enable/disable
settings. This register is reset at a DVDD-POR.
Default
Access Bit Description
0
W
Battery over-temperature interrupt setting.
0: disable
1: enable interrupt if battery temperature exceeds 45°C
The interrupt must not be enabled if the charger block and
battery temperature supervision is disabled
x
R
Battery over-temperature interrupt reading
0: battery temperature below 45°C
1: battery temperature was too high and the charger was
turned off. The charger will be turned on again, when the
temperature gets below 42°C
0
W
Battery end of charge interrupt setting
0: disable
1: enable
The interrupt must not be enabled if the charger block is
disabled
x
R
Battery end of charge interrupt reading
0: battery charging in progress
1: charging is complete, charging current is below 10% of
nominal current, turn off charger
To check end of charge again the charger has to be turned on.
x
R
0: no charger input source connected
1: charger input source connected, also valid if charger is
connected during wakeup
0
W
Charger input status change interrupt setting
0: disable
1: enables an interrupt on a low to high or high to low change
of CHGIN pin.
x
R
Charger input status change interrupt reading
0: charger input status not changed
1: charger input status changed, check CHG_STATUS
x
R
0: no USB input connected
1: USB input connected, also valid if USB is connected during
wakeup. The threshold can be set in the USB_UTIL register
(1Ah)
0
W
USB input status change interrupt setting
0: disable
1: enables an interrupt on a low to high or high to low change
of VBUS pin. The threshold can be set in the USB_UTIL
register (1Ah)
x
R
USB input status change interrupt reading
0: USB input status not changed
1: USB input status changed, check USB_STATUS
al
id
Name
IRQ_ENRD_2
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
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AS3517 V17
Data Sheet, Confidential
Name
IRQ_ENRD_2
Base
Default
2-wire serial
00h
Third Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding
interrupts, while with reading you get the actual interrupt status and will clear the
register at the same time. It is not possible to read back the interrupt enable/disable
settings. This register is reset at a DVDD-POR.
Default
Access Bit Description
0
W
Real time clock supply (RVDD) under-voltage interrupt setting
0: disable
1: enable
x
R
Real time clock supply interrupt reading
0: RTC supply o.k.
1: RTC supply (RVDD) was low, RTC not longer valid
The interrupt gets set in hibernation or during power-up even if
the interrupt is not enabled thus allowing to recognise a
change of the battery connected to BVDDR during hibernation
or shutdown. For a valid reading, the interrupt has to be
enabled first.
0
W
BVDD under-voltage supervisor interrupt setting
0: disable
1: enable
x
R
BVDD supervisor interrupt setting
0: BVDD is above brown out level
1: BVDD has reached brown out level
The threshold can be set in the SUPERVISOR register (24h)
Offset: 25h
Bit Name
RVDD_LOW
(level)
0
BVDD_LOW
(level)
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
lv
al
id
Bit
1
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
85 - 93
AS3517 V17
Data Sheet, Confidential
Table 89 Fourth Interrupt Register
Name
IRQ_ENRD_3
Offset: 26h
al
id
lv
6
5
Bit Name
JTEMP_HIGH
(level)
HPH_OVC
(level)
am
lc s
on A
te G
nt
st
il
Bit
7
Base
Default
2-wire serial
0x00
Fourth Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding
interrupts, while with reading you get the actual interrupt status and will clear the
register at the same time. It is not possible to read back the interrupt enable/disable
settings. This register is reset at a DVDD-POR.
Default
Access Bit Description
0
W
Supervisor junction over-temperature interrupt setting
0: disable
1: enable
x
R
Supervisor junction over-temperature interrupt reading
0: chip temperature below threshold
1: chip temperature has reached the threshold
The threshold can be set in the SUPERVISOR register (21h)
0
n/a
0
W
Headphone over-current interrupt setting
0: disable
1: enable
The interrupt must not be enabled if the headphone block is
disabled
x
R
Headphone over-current interrupt reading
0: no over-current detected
1: headphone over-current detected, headphone amplifier was
shut down. The current thresholds are 150mA at HPR / HPL
pin or 300mA at HPCM pin. The shut-down time can be set in
HPH_OUT_R register (0x02)
x
R
0: no LRCK on I2S interface detected
1: LRCK on I2S interface present
0
W
I2S input status change interrupt setting
0: disable
1: enable
x
R
I2S input status change interrupt reading
0: I2S input status not changed
1: I2S input status changed, check I2S_status
0
W
Microphone 2 connect detection interrupt setting
0: disable
1: enable
x
R
Microphone 2 connect detection interrupt reading
0: no microphone connected to MIC input
1: microphone connected at MIC input.
This interrupt is only invoked when the microphone stage is
powered down. The IRQ will be released after enabling the
microphone stage.
Detecting a microphone during operation has to be done by
measuring the supply current.
0
W
Microphone 1 connect detection interrupt setting
0: disable
1: enable
x
R
Microphone 1 connect detection interrupt reading
0: no microphone connected to MIC input
1: microphone connected at MIC input.
This interrupt is only invoked when the microphone stage is
powered down. The IRQ will be released after enabling the
microphone stage.
Detecting a microphone during operation has to be done by
measuring the supply current.
I2S_STATUS
3
I2S_CHANGED
(status change)
2
MIC2_CONNECT
(level)
ch
ni
ca
4
MIC1_CONNECT
(level)
Te
1
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
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AS3517 V17
Data Sheet, Confidential
Name
IRQ_ENRD_3
Offset: 26h
Bit Name
HPH_CONNECT
(level)
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
lv
al
id
Bit
0
Base
Default
2-wire serial
0x00
Fourth Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding
interrupts, while with reading you get the actual interrupt status and will clear the
register at the same time. It is not possible to read back the interrupt enable/disable
settings. This register is reset at a DVDD-POR.
Default
Access Bit Description
0
W
Headphone connect detection interrupt setting
0: disable
1: enable
x
R
Headphone connect detection interrupt reading
0: no headphone connected
1: headphone connected
This interrupt is only invoked when the headphone stage is
powered down. The IRQ will be released after enabling the
headphone stage.
Detecting a headphone during operation is not possible.
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
87 - 93
AS3517 V17
Data Sheet, Confidential
Table 90 Fifth Interupt Register
Name
IRQ_ENRD_4
Offset: 27h
Bit Name
T_DEB<1:0>
5
XIRQ_AH
4
XIRQ_PP
3
REM2_DET
(edge)
2
REM1_DET
(edge)
1
RTC_UPDATE
(edge)
0
ADC_EOC
(edge)
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
lv
al
id
Bit
7:6
Base
Default
2-wire serial
0x00
Fifth Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding
interrupts, while with reading you get the actual interrupt status and will clear the
register at the same time. It is not possible to read back the interrupt enable/disable
settings. This register is reset at a DVDD-POR.
Default
Access Bit Description
00
R/W
Sets the USB and Charger connect de-bounce time:
00: 340ms
01: 170ms
10: 85ms
11: 4ms
0
R/W
Sets the active output state of the XIRQ line:
0: IRQ is active low
1: IRQ is active high
0
R/W
Sets the XIRQ output buffer type:
0: IRQ output is open drain
1: IRQ output is push pull
0
W
Microphone 2 remote key press detection interrupt setting
0: disable
1: enable
x
R
Microphone 2 remote key press detection interrupt reading
0: no key press detected
1: Microphone 2 supply current got increased, remote key
press detected -> measure MICS supply current
0
W
Microphone 1 remote key press detection interrupt setting
0: disable
1: enable
x
R
Microphone 1 remote key press detection interrupt reading
0: no key press detected
1: Microphone 1 supply current got increased, remote key
press detected -> measure MICS supply current
0
W
RTC timer interrupt setting
0: disable
1: enable
x
R
RTC timer interrupt reading
0: no RTC interrupt occurred
1: RTC timer interrupt occurred. Selecting minute or second
interrupt can be done via RTCT register (29h)
0
W
ADC end of conversion interrupt setting
0: disable
1: enable
x
R
ADC end of conversion interrupt reading
0: ADC conversion not finished
1: ADC conversion finished. Read out ADC_0 and ADC_1
register to get the result (2Eh & 2Fh)
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
88 - 93
AS3517 V17
Data Sheet, Confidential
Table 91 RTCV Register
Base
Default
2-wire serial
23h
RTC Voltage Register
This register is reset at a DVDD-POR.
Default
Access Bit Description
0010
R/W
Selects the RVDD output voltage level (1V to 2.5V)
Default: 1.2V
RVDD= 1V + V_RVDD*0.1V
Offset: 28h
Bit Name
V_RVDD
3:2
1
RTC_ON
1
R/W
0
OSC32_ON
1
R/W
Table 92 RTCV Register
Offset: 29h
Bit
7
Bit Name
IRQ_MIN
6:0
RTC_TBC<6:0>
Base
Default
2-wire serial
40h
RTC Timing Register
This register is reset at a RVDD-POR.
Default
Access Bit Description
0
R/W
0: generates an interrupt every second
1: generates an interrupt every minute
The interrupt has to be enable in IRQ_ENRD_4 (27h)
1000000
R/W
These bits are used to correct the inaccuracy of the used
32kHz crystal.
am
lc s
on A
te G
nt
st
il
Name
RTCT
RTC counter clock control:
0: Disable clock for RTC counter
1: Enables clock for RTC counter
Switches the 32kHz oscillator ON A 32kHz watch crystal need
to be connected to pins XIN32/XOUT32
0: Disable 32kHz oscillator
1: Enables 32kHz oscillator
lv
Bit
7:4
al
id
Name
RTCV
Trimming register for RTC, 128 steps @ 7.6ppm
000000: 1 (7.6ppm)
000001: 2 (15.2ppm)
…
100000: 64 (488ppm)
…
111110: 126 (960.8ppm)
111111: 127 (968.4ppm)
Offset: 2Ah to 2Dh
Byte Name
RTC_0
RTC_1
RTC_2
RTC_3
Te
ch
Adr.
2Ah
2Bh
2Ch
2Dh
Base
Default
2-wire serial
00 00 00 00h
RTC Time-base Seconds Register
This register is reset at a RVDD-POR.
Default
Access Bit Description
00h
R/W
QRTC<7:0>; RTC seconds bits 0 to 7
00h
R/W
QRTC<15:8>; RTC seconds bits 8 to 15
00h
R/W
QRTC<23:9>; RTC seconds bits 9 to 23
00h
R/W
QRTC<31:24>; RTC seconds bits 24 to 31
ni
Name
RTC_0 to RTC_3
ca
Table 93 RTC_0 to RTC_3 Register
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
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AS3517 V17
Data Sheet, Confidential
Name
ADC_0
Base
Default
2-wire serial
0000 00xx
First 10-bit ADC Register
Writing to this register will start the measurement of the selected source.
This register is reset at a DVDD-POR, exception are bit 8 and 9.
Default
Access Bit Description
00000000 R/W
Selects ADC input source
0000: CHGOUT
0001: BVDDR
0010: defined by DC_TEST in register 0x18
0011: CHGIN
0100: VBUS
0101: BatTemp
0110: MIC1S
0111: MIC2S
1000: VBE_1uA
1001: VBE_2uA
1010: I_MIC1S
1011: I_MIC1S
1100: RVDD
1101: reserved
1110: reserved
1101: reserved
00
n/a
xx
R/W
ADC result bit 9 to 8
Offset: 2Eh
Bit Name
ADC_Source
3:2
1:0
ADC<9:8>
am
lc s
on A
te G
nt
st
il
lv
Bit
7:4
al
id
Table 94 ADC_0 Register
Table 95 ADC_1 Register
Name
ADC_1
Offset: 2Fh
Bit
7:0
Bit Name
ADC<7:0>
Base
2-wire serial
Second 10-bit ADC Register
This register is not reset.
Default
Access Bit Description
xxxx xxxx
R/W
ADC result bit 7 to 0
Default
xxxx xxxx
Base
2-wire serial
Unique ID Register
This register is read only and is not reset.
Default
Access Bit Description
n/a
R
Unique ID byte 0
n/a
R
Unique ID byte 1
n/a
R
Unique ID byte 2
n/a
R
Unique ID byte 3
n/a
R
Unique ID byte 4
n/a
R
Unique ID byte 5
n/a
R
Unique ID byte 6
n/a
R
Unique ID byte 7
Default
n/a
Name
UID_0 to UID_7
Offset: 38h to 3Fh
ni
Byte Name
UID_0
UID_1
UID_2
UID_3
UID_4
UID_5
UID_6
UID_7
Te
ch
Adr.
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
ca
Table 96 UID_0 to UID_7 Register
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
90 - 93
AS3517 V17
Data Sheet, Confidential
10 Typical Application
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ca
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Figure 32 Typical Application Schematic 1
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
91 - 93
AS3517 V17
Data Sheet, Confidential
Te
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am
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Figure 33 Typical Application Schematic 2
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
92 - 93
AS3517 V17
Data Sheet, Confidential
11 Copyright
Copyright © 2008, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written
consent of the copyright owner.
All products and companies mentioned are trademarks of their respective companies.
12 Disclaimer
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al
id
Devices sold by austriamicrosystems AG are covered by the warranty and patent identification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or
regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change
specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check
with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications
requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical lifesupport or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each
application.
am
lc s
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The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG
shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of
profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or
arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall
arise or flow out of austriamicrosystems AG rendering of technical or other services.
13 Contact Information
Headquarters:
austriamicrosystems AG
Business Unit Communications
A 8141 Schloss Premstätten, Austria
T. +43 (0) 3136 500 0
F. +43 (0) 3136 5692
[email protected]
For Sales Offices, Distributors and Representatives, please visit:
Te
ch
ni
ca
www.austriamicrosystems.com
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1v3
93 - 93
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