LTC3876 Dual DC/DC Controller for DDR Power with Differential VDDQ Sensing and ±50mA VTT Reference DESCRIPTION FEATURES n n n n n n n n n n n n Complete DDR Power Solution with VTT Reference Wide VIN Range: 4.5V to 38V, VDDQ: 1V to 2.5V ±0.67% VDDQ Output Voltage Accuracy VDDQ and VTT Termination Controllers ±1.2% ±50mA Linear VTTR Reference Output Controlled On-Time, Valley Current Mode Control Frequency Programmable from 200kHz to 2MHz Synchronizable to External Clock tON(MIN) = 30ns, tOFF(MIN) = 90ns RSENSE or Inductor DCR Current Sensing Power Good Output Voltage Monitor Overvoltage Protection and Current Limit Foldback Thermally Enhanced 38-Pin (5mm × 7mm) QFN and TSSOP Packages The LTC®3876 is a complete DDR power solution, compatible with DDR1, DDR2, DDR3 and future DDRX lower voltage standards. The LTC3876 includes VDDQ and VTT DC/DC controllers and a precision linear VTT reference. A differential output sense amplifier and precision internal reference combine to offer an accurate VDDQ supply. The VTT controller tracks the precision VTTR linear reference with less than 20mV total DC error. The precision VTTR reference maintains 1.2% regulation accuracy tracking onehalf VDDQ over temperature for a ±50mA reference load. The LTC3876 allows operation from 4.5V to 38V maximum at the input. The VDDQ output can range from 1.0V to 2.5V, with a corresponding VTT and VTTR output range of 0.5V to 1.25V. Voltage tracking soft-start, PGOOD and fault protection features are provided. APPLICATIONS n n L, LT, LTC, LTM, Linear Technology, OPTI-LOOP, and the Linear logo are registered trademarks and Hot Swap and No RSENSE are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5487554, 6580258, 6304066, 6476589, 6774611. Motherboard Memory Servers TYPICAL APPLICATION DDR3 1.5V VDDQ/20A 0.75VTT/±10A 4.5V to 14V Input VIN 4.5V TO 14V SENSE1+ 15k L1 0.47μH 0.1μF SENSE2+ 0.1μF BOOST1 3.57k MT1 TG1 SW1 DB1 1μF MT2 4.7μF 30.1k MB1 COUT4 330μF INTVCC BG1 COUT3 100μF VOUTSENSE1+ 100k VOUTSENSE1– PGOOD 0.1μF 15k 1000pF PGOOD TRACK/SS1 80 3.0 2.5 70 2.0 1.5 60 1.0 50 1μF VTTRVCC 40 0.1 VTTSNS VTTR 2.2μF 1000pF ITH1 DISCONTINUOUS MODE MB2 BG2 PGND 20k 4.0 3.5 VTT 0.75V ±10A SW2 DRVCC2 4.5 VIN = 12V VDDQ = 1.5V 90 3.57k L2 0.47μH DB2 DRVCC1 COUT2 330μF w2 BOOST2 TG2 100 15k 0.1μF POWER LOSS (W) COUT1 100μF 0.1μF EFFICIENCY (%) CIN1 180μF w2 1.5V, 20A VDDQ Efficiency/Power Loss VDDR Channel 1 VIN LTC3876 SENSE1– SENSE2– VTTR ±50mA FORCED CONTINUOUS MODE 1 LOAD CURRENT (A) 0.5 0 10 3876 TA01b 15k ITH2 100k RT SGND RUN 3876 TA01a 3876f 1 LTC3876 ABSOLUTE MAXIMUM RATINGS (Note 1) Input Supply Voltage (VIN) ......................... –0.3V to 40V BOOST1, BOOST2 Voltages ....................... –0.3V to 46V SW1, SW2 Voltages ...................................... –5V to 40V INTVCC, DRVCC1, DRVCC2, EXTVCC, PGOOD, RUN, (BOOST1-SW1), (BOOST2-SW2), MODE/PLLIN Voltages ....................................................... –0.3V to 6V VOUTSENSE1+, VOUTSENSE1– , SENSE1+, SENSE1–, SENSE2+, SENSE2– Voltages ....................... –0.6V to 6V TRACK/SS1 Voltage ..................................... –0.3V to 5V DTR1, CVCC, PHASMD, RT, VRNG1, VRNG2, VTTSNS, VDDQSNS, VTTR, ITH1, ITH2 Voltages ................................ ..–0.3V to (INTVCC + 0.3V) Operating Junction Temperature Range (Notes 2, 3, 4) ....................................... –40°C to 125°C Storage Temperature Range .................. –65°C to 150°C Lead Temperature (Soldering, 10 sec) FE Package ...................................................... 300°C PIN CONFIGURATION TOP VIEW BOOST2 VTTSNS VRNG2 CVCC SENSE2– SENSE2+ PHASMD TOP VIEW 38 37 36 35 34 33 32 ITH2 1 31 TG2 VDDQSNS 2 30 SW2 VTTR 3 29 BG2 VTTRVCC 4 28 DRVCC2 MODE/PLLIN 5 27 EXTVCC CLKOUT 6 26 INTVCC PGND 39 SGND 7 38 VRNG2 2 37 VTTSNS SENSE2+ 3 36 BOOST PHASMD 4 35 TG2 ITH2 5 34 SW2 VDDQSNS 6 33 BG2 VTTR 7 32 DRVCC VTTRVCC 8 31 EXTVCC MODE/PLLIN 9 30 INTVCC PGND 39 SGND 11 24 VIN RT 12 23 DRVCC1 VRNG1 9 1 CLKOUT 10 25 PGND RT 8 CVCC SENSE2– 29 PGND 28 VIN 27 DRVCC1 ITH1 10 22 BG1 VRNG1 13 TRACK/SS1 11 21 SW1 ITH1 14 25 SW1 VOUTSENSE1+ 12 20 TG1 TRACK/SS1 15 24 TG1 BOOST1 PGOOD RUN DTR1 SENSE1– SENSE1+ VOUTSENSE1– 13 14 15 16 17 18 19 UHF PACKAGE 38-LEAD (5mm × 7mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB PGND 26 BG1 VOUTSENSE1+ 16 23 BOOST1 VOUTSENSE1– 17 22 PGOOD SENSE1+ 18 21 RUN SENSE1– 19 20 DTR1 FE PACKAGE 38-LEAD PLASTIC TSSOP TJMAX = 125°C, θJA = 28°C/W EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3876EUHF#PBF LTC3876EUHF#TRPBF 3876 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C LTC3876IUHF#PBF LTC3876IUHF#TRPBF 3876 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C LTC3876EFE#PBF LTC3876EFE#TRPBF LTC3876FE 38-Lead Plastic TSSOP –40°C to 125°C LTC3876IFE#PBF LTC3876IFE#TRPBF LTC3876FE 38-Lead Plastic TSSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3876f 2 LTC3876 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise noted. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 4.5 38 V VDDQ Regulates Differentially with Respect to VOUTSENSE1–, VTTSNS and VTTR Regulate Differentially to One-Half VDDQ with Respect to VOUSTSENSE1– 1.0 0.5 0.5 2.5 1.25 1.25 V V V Main Control Loop VIN Input Voltage Operating Range VDDQ(REG) VTTR(REG) VTTSNS(REG) VDDQ Regulated Operating Range VTTR Regulated Operating Range VTTSNS Regulated Operating Range IQ Input DC Supply Current Both Channels Enabled Shutdown Supply Current VDFB1(REG) MODE/PLLIN = 0V, No Load RUN1 = RUN2 = 0V Regulated Differential Feedback Voltage on ITH1 = 1.2V (Note 5) Channel 1, VDDQ TA = 25°C (VOUTSENSE1+ – VOUTSENSE1–) TA = 0°C to 85°C TA = –40°C to 125°C 5000 20 μA μA l l 0.5985 0.596 0.594 0.6 0.6 0.6015 0.604 0.606 V V V 0.6 0.6 0.606 0.609 V V Regulated Differential Feedback Voltage on Channel 1, VDDQ Over Line, Load and Common Mode VIN = 4.5V to 38V, ITH1 = 0.5V to 1.9V, VOUTSENSE1– = ±500mV (Notes 5, 7) TA = 0°C to 85°C TA = –40°C to 125°C l l 0.594 0.591 Regulated Voltage Error on Channel 2, VTTSNS (Referenced to VTTR) ITH2 = 1.4V (Note 5) TA = 0°C to 85°C TA = –40°C to 125°C l l –10 –15 10 15 mV mV Regulated Voltage Error on Channel 2, VTTSNS Over Line, Load and Common Mode. (Referenced to VTTR) VIN = 4.5V to 38V, ITH1 = 0.5V to 1.9V, (Notes 5, 7) TA = 0°C to 85°C TA = –40°C to 125°C l l –15 –20 15 20 mV mV IVOUTSENSE1+ VOUTSENSE1+ Input Bias Current VDFB1 [VOUTSENSE1+ – VOUTSENSE1–] = 0.6V ±5 ±25 nA IVOUTSENSE1– VOUTSENSE1– Input Bias Current VDFB1 [VOUTSENSE1+ – VOUTSENSE1–] = 0.6V –25 –50 μA IVTTSNS IVTTSNS Input Bias Current IVTTSNS = 750mV ±5 ±50 nA gm(EA)1,2 Error Amplifier Transconductance ITH = 1.2V (Note 3) 1.7 mS tON(MIN)1,2 Minimum On-Time VIN = 38V, RT = 20k, VDDSNS = 1.2V, VSENSE– = 0.6V 30 ns tOFF(MIN)1,2 Minimum Off-Time 90 ns VTTSNS(REG) Current Sensing VSENSE1(MAX) Maximum Valley Current Sense Threshold VRNG = 2V, VDFB1 = 0.57V, VSENSE1– = 1.5V (VSENSE1+ – VSENSE1–) VRNG = 0V, VDFB1 = 0.57V, VSENSE1– = 1.5V VRNG = INTVCC, VDFB1 = 0.57V, VSENSE1– = 1.5V VSENSE1(MIN) Minimum Valley Current Sense Threshold (VSENSE1+ – VSENSE1–) (Forced Continuous Mode) VSENSE2(MAX) Maximum Valley Current Sense Threshold VRNG = 2V, VTTSNS = 0.72V, VSENSE2– = 0.75V (VSENSE2+ – VSENSE2–) VRNG = 0V, VTTSNS = 0.72V, VSENSE2– = 0.75V VRNG = INTVCC, VTTSNS = 0.72V, VSENSE2– = 0.75V VSENSE2(MIN) Minimum Valley Current Sense Threshold (VSENSE1+ – VSENSE1–) (Forced Continuous Mode) VRNG = 2V, VTTSNS = 0.78V, VSENSE2– = 0.75V VRNG = 0V, VTTSNS = 0.78V, VSENSE2– = 0.75V VRNG = INTVCC, VTTSNS = 0.78V, VSENSE2– = 0.75V ISENSE1,2+ SENSE1,2+ Pins Input Bias Current VSENSE+ = 0.6V VSENSE+ = 2.5V ±5 1 ISENSE1,2– SENSE2– Pins Input Bias Current (Internal 500k Resistor to SGND) VSENSE1– = 0.6V VSENSE1– = 2.5V 1.2 5 l l l 80 21 39 VRNG = 2V, VDFB1 = 0.63V, VSENSE1– = 1.5V VRNG = 0V, VDFB1 = 0.63V, VSENSE1– = 1.5V VRNG = INTVCC, VDFB1 = 0.63V, VSENSE1– = 1.5V 100 30 50 120 40 61 –50 –15 –25 l l l 80 21 39 100 30 50 mV mV mV mV mV mV 120 40 61 –120 –36 –60 mV mV mV mV mV mV ±50 ±2 nA μA μA μA 3876f 3 LTC3876 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise noted. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 1.15 1.2 1.25 V Start-Up and Shutdown l VRUN(TH) RUN Pin On Threshold VRUN Rising VRUN(HYS) RUN Pin On Hysteresis VRUN Falling from VRUN(TH) 100 mV IRUN(OFF) RUN Pin Pull-Up Current When Off RUN = SGND 2.5 μA IRUN(HYS) RUN Pin Pull-Up Current Hysteresis IRUN(HYS) = IRUN(ON) – IRUN(OFF) 10 μA VUVLO(INTVCC) INTVCC Undervoltage Lockout INTVCC Falling INTVCC Rising ITRACK/SS Soft-Start Pull-Up Current l l 3.3 0V < TRACK/SS < 0.6V 3.7 4.2 4.5 1 V V μA Frequency and Clock Synchronization Clock Output Frequency (Steady-State Switching Frequency) RT = 205k RT = 80.6k RT = 18.2k φVTT VTT Channel 2 Phase (Relative to Channel 1) VPHASMD = SGND VPHASMD = Floating VPHASMD = INTVCC 180 180 240 Deg Deg Deg φCLKOUT CLKOUT Phase (Relative to Channel 1) VPHASMD = SGND VPHASMD = Floating VPHASMD = INTVCC 60 90 120 Deg Deg Deg VCLKOUT(H) Clock Output Voltage High Pulling to INTVCC VCLKOUT(L) Clock Output Voltage Low Pulling to SGND 0 VPLLIN(H) Clock Input Voltage High fMODE/PLLIN >100kHz 2 VPLLIN(L) Clock Input Voltage Low fMODE/PLLIN >100kHz RMODE/PLLIN MODE/PLLIN Input DC Resistance fCLKOUT 450 200 500 2000 550 VINTVCC kHz kHz kHz V V V –0.5 V 600 kΩ Gate Drivers RTG(UP)1,2 TG Driver Pull-Up On-Resistance TG High 2.5 Ω RTG(DOWN)1,2 TG Driver Pull-Down On-Resistance TG Low 1.2 Ω RBG(UP)1 BG Driver 1 Pull-Up On-Resistance BG1 High 2.5 Ω RBG(UP)2 BG Driver 2 Pull-Up On-Resistance BG2 High 1.6 Ω RBG(DOWN)1,2 BG Driver Pull-Down On-Resistance BG Low 0.8 Ω TD(TG/BG)1,2 Top Gate Off to Bottom Gate On Delay Time (Note 6) 20 ns TD(BG/TG)1,2 Bottom Gate Off to Top Gate On Delay Time (Note 6) 15 ns VTT Reference VTTR(IVTTR) VTTR Load Regulation –50mA < IVTTR < 50mA; TA = –40°C to 125°C (VTTR(IVTTR) is Measured Through an 1.5 < VDDQ < 2.5 1.0 < VDDQ < 1.5 Internal Kelvin Connection to the VTTR Pin and is Specified as the Ratio (VTTR(IVTTR)/ VDDQ) l l 0.4940 0.4930 0.5060 0.5070 V/V V/V Internal VCC Regulator VDRVCC1 Internal Regulated DRVCC1 Voltage 6V < VIN < 38V ∆VDRVCC1 DRVCC1 Load Regulation ICC = 0mA to 100mA VEXTVCC(TH) EXTVCC Switchover Voltage EXTVCC Rising VEXTVCC(HYS) EXTVCC Switchover Hysteresis ∆VDRVCC2 EXTVCC to DRVCC2 Voltage Drop VEXTVCC = 5V, IDRVCC2 = 100mA 5.0 4.4 5.3 5.6 V –1.5 –3 % 4.6 4.8 V 200 mV 200 mV 3876f 4 LTC3876 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise noted. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX PGDOV PGOOD Overvoltage Threshold PGDUV UNITS VOUTSENSE, VTTSNS Rising, with Respect to Reference Voltage 5 7.5 10 % PGOOD Undervoltage Threshold VOUTSENSE, VTTSNS Falling, with Respect to Reference Voltage –5 –7.5 –10 % PGDHYS PGOOD Threshold Hysteresis VOUTSENSE, VTTSNS Returning to Reference Voltage 2.0 VPGD(LO) PGOOD Low Voltage IPGOOD = 2mA 0.1 tPGD(FALL) tPGD(RISE) Delay from OV/UV Fault to PGOOD Falling Delay from OV/UV Recovery to PGOOD Rising PGood Output Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC3876UHF: TJ = TA + (PD • 34°C/W) LTC3876FE: TJ = TA + (PD • 28°C/W) Note 3: The LTC3876 is tested under pulsed load conditions such that TJ ≈ TA. The LTC3876E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3876I is guaranteed to meet performance specifications over the full –40°C to 125°C operating junction temperature range. The maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the package thermal impedance and other environmental factors. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. 50 20 % 0.3 V μs μs Continuous operation above the specified absolute maximum operating junction temperature may impair the device reliability or permanently damage the device. Note 5: The LTC3876 is tested in a feedback loop that adjusts (VOUTSENSE1+ VOUTSENSE1–) and VTTSNS to achieve specified error amplifier output voltages (ITH1,2). Note 6: Delay times are measured using 50% levels. Note 7: In order to simplify the total system error computation, the regulated voltage is defined in one combined specification which includes the effects of line, load and common mode variation. The combined regulated voltage specification is tested by independently varying line, load, and common mode, which by design do not significantly affect one another. For any combination of line, load, and common mode variation, the regulated voltage should be within the limits specified that are tested in production to the following conditions: a. Line: VIN = 4.5V to 38V, ITH = 1V, VOUTSENSE1– = 0V b. Load: VIN = 15V, ITH = 0.5V to 1.9V, VOUTSENSE1– = 0V c. Common mode: VIN = 15V, ITH = 1V, to VOUTSENSE1– = ±500mV, (Ch1) 3876f 5 LTC3876 TYPICAL PERFORMANCE CHARACTERISTICS Transient Response VDDQ (Forced Continuous Mode) Load Step VDDQ (Forced Continuous Mode) ILOAD 20A/DIV VSW 20V/DIV Load Release VDDQ (Forced Continuous Mode) ILOAD 20A/DIV VSW 20V/DIV ILOAD 20A/DIV VSW 20V/DIV VOUT 50mV/DIV VOUT 50mV/DIV VOUT 50mV/DIV IL 20A/DIV IL 20A/DIV IL 20A/DIV 10μs/DIV LOAD TRANSIENT = 0A TO 15A VIN = 12V VOUT = 1.5V FIGURE 10 CIRCUIT, VDDQ CHANNEL 1 3876 G01 5μs/DIV LOAD STEP = 0A TO 15A VIN = 12V VOUT = 1.5V FIGURE 10 CIRCUIT, VDDQ CHANNEL 1 Transient Response VDDQ (Discontinuous Mode) 3876 G02 Load Step VDDQ (Discontinuous Mode) ILOAD 20A/DIV VSW 20V/DIV VOUT 50mV/DIV VOUT 50mV/DIV IL 20A/DIV VOUT 50mV/DIV IL 20A/DIV IL 20A/DIV 3876 G04 5μs/DIV LOAD STEP = 500mA TO 15A VIN = 12V VOUT = 1.5V FIGURE 10 CIRCUIT, VDDQ CHANNEL 1 Transient Response VTT (Forced Continuous Mode) ILOAD 20A/DIV VSW 20V/DIV VOUT 50mV/DIV VOUT 50mV/DIV IL 20A/DIV IL 10A/DIV 10μs/DIV LOAD TRANSIENT = 0A TO 15A VIN = 12V VOUT = 1.5V FIGURE 10 CIRCUIT, VDDQ CHANNEL 1 3876 G05 5μs/DIV LOAD RELEASE = 15A TO 500mA VIN = 12V VOUT = 1.5V FIGURE 10 CIRCUIT, VDDQ CHANNEL 1 Load Step VTT (Forced Continuous Mode) ILOAD 20A/DIV VSW 20V/DIV 3876 G07 3876 G03 Load Release VDDQ (Discontinuous Mode) ILOAD 20A/DIV VSW 20V/DIV ILOAD 20A/DIV VSW 20V/DIV 10μs/DIV LOAD TRANSIENT = 0A TO 15A VIN = 12V VOUT = 1.5V FIGURE 10 CIRCUIT, VDDQ CHANNEL 1 5μs/DIV LOAD RELEASE = 15A TO 500mA VIN = 12V VOUT = 1.5V FIGURE 10 CIRCUIT, VDDQ CHANNEL 1 3876 G06 Load Release VTT ILOAD 20A/DIV VSW 20V/DIV VOUT 50mV/DIV IL 10A/DIV 5μs/DIV LOAD STEP = 0A TO 10A VIN = 12V VOUT = 0.75V FIGURE 10 CIRCUIT, VTT CHANNEL 2 3876 G08 5μs/DIV LOAD RELEASE = 10A TO 0A VIN = 12V VOUT = 0.75V FIGURE 10 CIRCUIT, VTT CHANNEL 2 3876 G09 3876f 6 LTC3876 TYPICAL PERFORMANCE CHARACTERISTICS Regular Soft Start-Up (Forced Continuous Mode) Output Tracking (Forced Continuous Mode) Soft Start-Up Into Prebiased Output RUN 5V/DIV VIN 5V/DIV VDDQ 500mV/DIV TRACK/SS 200mV/DIV VTT 500mV/DIV VDDQ 500mV/DIV VTT 500mV/DIV TRACK/SS 200mV/DIV Overcurrent Protection (Forced Continuous Mode) LOAD CURRENT 20A/DIV IL 10A/DIV VOUT 50mV/DIV SHORTCIRCUIT TRIGGER 1V/DIV VOUT 1V/DIV 24A IL 20A/DIV 0A COUT DISCHARGE COUT RECHARGE 3876 G13 500μs/DIV BG STAYS ON UNTIL VOUT 20μs/DIV PULLED BELOW VIN = 12V CURRENT LIMIT OVERVOLTAGE VDDQ = 1.5V FOLDBACK VOUT THRESHOLD ILOAD = 0A DROPS BELOW HALF REGULATED FIGURE 10 CIRCUIT, SET POINT VDDQ CHANNEL 1 VIN = 12V VDDQ = 1.5V CURRENT LIMIT = 23A OVERLOAD = 10A TO 17.5A FICURE 10 CIRCUIT, VDDQ CHANNEL 1 VIN = 12V VDDQ = 1.5V ILOAD = 0A, SHORT = 50A FIGURE 10 CIRCUIT, VDDQ CHANNEL 1 Phase Relationship: PHASMD = Ground (Forced Continuous Mode) Phase Relationship: PHASMD = Float (Forced Continuous Mode) SW1 5V/DIV CLKOUT 5V/DIV 60° 500ns/DIV PHASMD = GND VIN = 6V VDDQ = 1.5V, VTT = 0.75V LOAD = 0A FIGURE 10 CIRCUIT 3876 G16 OVERVOLTAGE CREATED BY APPLYING A CHARGED CAPACITOR TO VOUT Phase Relationship: PHASMD = INTVCC (Forced Continuous Mode) PLLIN 5V/DIV SW1 5V/DIV 0° SW2 5V/DIV 180° 3876 G15 3876 G14 PLLIN 5V/DIV 0° VOUT 200mV/DIV BG1 5V/DIV IL 20A/DIV SW2 5V/DIV CLKOUT 5V/DIV Overvoltage Protection (Forced Continuous Mode) 50A FULL CURRENT LIMIT VOUT GREATER THAN HALF REGULATED SETTING PLLIN 5V/DIV 3876 G12 10ms/DIV VIN = 12V VDDQ = 1.5V, VTT - 0.75V FIGURE 10 CIRCUIT Short-Circuit Protection (Forced Continuous Mode) 10A 5ms/DIV SW1 5V/DIV 3876 G11 1ms/DIV CSS = 10nF VIN = 12V VDDQ = 1.5V, VTT = 0.75V VDDQ PREBIASED TO 0.75V VTT PREBIASED TO 0.6V FIGURE 10 CIRCUIT 3876 G10 2ms/DIV CSS = 10nF VIN = 12V VDDQ = 1.5V, VTT = 0.75V FIGURE 10 CIRCUIT TRACK/SS 200mV/DIV VDDQ 500mV/DIV VTT 500mV/DIV SW2 5V/DIV 180° 90° 500ns/DIV PHASMD = FLOAT VIN = 6V VDDQ = 1.5V, VTT = 0.75V LOAD = 0A FIGURE 10 CIRCUIT 0° 3876 G17 CLKOUT 5V/DIV 240° 120° 500ns/DIV PHASMD = INTVCC VIN = 6V VDDQ = 1.5V, VTT = 0.75V LOAD = 0A FIGURE 10 CIRCUIT 3876 G18 3876f 7 LTC3876 TYPICAL PERFORMANCE CHARACTERISTICS Output Regulation vs Input Voltage VDDQ Channel 1 Output Regulation vs Load Current VDDQ Channel 1 0.2 Output Regulation vs Temperature VDDQ Channel 1 0.6 0.2 0 –0.1 VOUT = 1.5V ILOAD = 5A VOUT NORMALIZED AT VIN = 15V –0.2 0 5 10 15 20 25 30 NORMALIZED ΔVOUT (%) NORMALIZED ΔVOUT (%) 0.1 0 –0.1 VIN = 15V VOUT = 1.5V VOUT NORMALIZED AT ILOAD = 4A –0.2 35 0 40 2 VIN (V) 4 6 ILOAD (A) –0.2 1 1 1 NORMALIZED Δf (%) 2 NORMALIZED Δf (%) 2 0 –1 VOUT = 1.6V ILOAD = 5A f = 200kHz FREQUENCY NORMALIZED AT VIN = 15V 5 10 15 20 25 VIN (V) 30 35 0 40 2 4 6 ILOAD (A) 8 VIN = 15V, VOUT = 1.5V ILOAD = 0A, f = 200kHz FREQUENCY NORMALIZED AT TA = 25°C –40°C 25°C 85°C 125°C 0.510 0.505 0.500 0.495 0.490 0.515 VTTR(IVTTR)/VDDQ (V/V) VIN = 15V f = 400kHz 0.520 VIN = 15V f = 400kHz –40°C 25°C 85°C 125°C 0.510 0.505 0.500 0.495 0.490 0.485 0.485 –25 0 IVTTR (mA) 25 50 3876 G24 25 50 75 100 125 150 TEMPERATURE (°C) VTTR Load Regulation VDDQ = 1V 0.520 0.520 0 3876 G24 VTTR Load Regulation VDDQ = 1.5V VTTR Load Regulation VDDQ = 2.5V 0.480 –50 –2 –50 –25 10 3876 G23 3876 G22 0.515 0 –1 VIN = 15V VOUT = 1.5V f = 200kHz FREQUENCY NORMALIZED AT ILOAD = 4A –2 –2 0 25 50 75 100 125 150 TEMPERATURE (°C) CLKOUT/Switching Frequency vs Temperature 2 –1 0 3876 G21 CLKOUT/Switching Frequency vs Load Current 0 VIN = 15V VOUT = 1.5V ILOAD = 0A VOUT NORMALIZED AT TA = 25°C 3876 G20 CLKOUT/Switching Frequency vs Input Voltage NORMALIZED Δf (%) 0 –0.6 –50 –25 10 8 3876 G19 VTTR(IVTTR)/VDDQ (V/V) 0.2 –0.4 0.480 –50 0.515 VTTR(IVTTR)/VDDQ (V/V) NORMALIZED ΔVOUT (%) 0.4 0.1 VIN = 15V f = 400kHz –40°C 25°C 85°C 125°C 0.510 0.505 0.500 0.495 0.490 0.485 –25 0 IVTTR (mA) 25 50 3876 G26 0.480 –50 –25 0 IVTTR (mA) 25 50 3876 G27 3876f 8 LTC3876 TYPICAL PERFORMANCE CHARACTERISTICS Error Amplifier Transconductance vs Temperature 1.75 1.70 1.65 1.60 1.55 120 120 100 90 80 60 40 20 0 –20 VRNG = 2V VRNG = 1V VRNG = 0.6V –40 1.50 –50 –25 –60 0 25 50 75 100 125 150 TEMPERATURE (°C) 0 1.6 1.2 0.8 ITH VOLTAGE (V) 0.4 2 –30 –60 0 0.6 1.20 14 1.15 10 8 6 0.4 4 0.2 2 0 –50 –25 0 RUN PIN BELOW SWITCHING THRESHOLD 40 4.5 0 3.8 25 20 15 10 3.5 3.3 –50 –25 130°C 25°C –45°C 5 0 25 50 75 100 125 150 TEMPERATURE (°C) 3876 G34 25 50 75 100 125 150 TEMPERATURE (°C) Quiescent Current Into VIN Pin vs Temperature with EXTVCC = 0V 3.7 QUIESCENT CURRENT (mA) UVLO LOCK (INTVCC FALLING) 0 3876 G33 Shutdown Current into VIN Pin vs Voltage on VIN Pin 30 CURRENT (μA) 3.7 0.80 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) 35 UVLO RELEASE (INTVCC RISING) 3.9 0.95 3876 G32 INTVCC Undervoltage Lockout Thresholds vs Temperature 4.1 1.00 0.90 3876 G31 4.3 1.05 0.85 0 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) 1.10 RUN PIN ABOVE SWITCHING THRESHOLD SHUTDOWN REGION 2.4 2 TRACK/SS Pull-Up Current vs Temperature 16 12 0.8 1.6 1.2 0.8 ITH VOLTAGE (V) 0.4 3876 G30 CURRENT (μA) 1.2 STAND-BY REGION VRNG = 2V VRNG = 1V VRNG = 0.6V –120 SWITCHING REGION CURRENT (μA) RUN PIN THRESHOLDS (V) 0 RUN Pull-Up Currents vs Temperature 1.6 UVLO THRESHOLD (V) 30 3876 G29 RUN Pin Thresholds vs Temperature 1.0 60 –90 2.4 3876 G28 1.4 CURRENT SENSE VOLTAGE (mV) VDDQ CH2 VTT CH2 CURRENT SENSE VOLTAGE (mV) TRANSCONDUCTANCE (mS) 1.80 VTT Current Sense Voltage vs ITH Voltage VDDQ Current Sense Voltage vs ITH Voltage 5 10 15 20 25 30 35 3.5 3.4 3.3 3.2 3.1 0 0 3.6 40 VIN (V) 3876 G35 3.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3876 G36 3876f 9 LTC3876 PIN FUNCTIONS (QFN/TSSOP) ITH2 (Pin 1/Pin 5): Channel 2 VTT Current Control Threshold. This pin is the output of the error amplifier and the switching regulator’s compensation point. The current comparator threshold increases with this control voltage. This voltage ranges from 0V to 2.2V. ITH2 has been optimized to support a symmetric range of positive and negative current by moving the zero sense voltage to 1.2V. (zero inductor valley current). VDDQSNS (Pin 2/Pin 6): VDDQ Sense. VDDQSNS provides the VDDQ regulation reference point to the VTT differential reference resistor divider. The positive Input to the VTT differential reference resistor divider is VDDQSNS and negative input is VOUTSENSE–. The resistor divider is connected internally between VDDQSNS and VOUTSENSE– and is composed of two equally sized 105k resistors in series for 210K total resistance. When VDDQSNS is tied to INTVCC, the VTTR linear reference outputs are three-stated and VTTR becomes the VTTSNS reference input. This allows the option to tie the VTTR reference input to the VTTR output of a second LTC3876 in a multiphase application. VTTR (Pin 3/Pin 7): VTT Reference. VTTR is the buffered output of the VTT differential reference resistor divider. VTTR is specifically designed for large DDR memory systems by providing superior accuracy and load regulation specified for up to ±50mA. Connect VTTR directly to the DDR memory VREF input. VTTR is a high output linear reference which tracks the VTT differential reference resistor divider and is equal to 0.5 • (VDDQSNS – VOUTSENSE–). Power is supplied through VTTRVCC. Internally the VTTR connection is connected to VDDQSNS reference in order to provide Kelvin sensing of VTTR. The output capacitor minimum should be 2.2μF. VTTRVCC (Pin 4/Pin 8): VTTR Supply Input for VTTR Reference. Connect to DRVCC through an RC decoupling filter of 2.2μF and 1Ω typically. MODE/PLLIN (Pin 5/Pin 9): Operation Mode Selection or External Clock Synchronization Input. When this pin is tied to INTVCC forced continuous mode operation is selected. Typing this pin to SGND allows discontinuous mode operation on channel 1, VDDQ while channel 2, VTT operates in forced continuous mode. When an external clock is applied at this pin, both channels operate in forced continuous mode and are synchronized to the external clock. Channel 2 VTT operates in forced continuous mode only; permitting it to accurately track VTTR when sourcing and sinking load current. CLKOUT (Pin 6/Pin 10): Clock Output of Internal Clock Generator. Its output level swings between INTVCC and SGND. If clock input is present at the MODE/PLLIN pin, it will be synchronized to the input clock, with phase set by the PHASMD pin. If no clock is present at the MODE/ PLLIN pin, its frequency will be set by the RT pin. To synchronize other controllers, CLKOUT can be connected to their MODE/PLLIN pins. SGND (Pin 7/Pin 11): Signal Ground. All small-signal analog components should be connected to this ground. Connect SGND to the exposed pad and PGND pin using a single PCB trace. RT (Pin 8/Pin 12): Clock Generator Frequency Programming Pin. Connect an external resistor from RT to SGND to program the switching frequency between 200kHz and 2MHz. An external clock applied to MODE/PLLIN should be within ±30% of this programmed frequency to ensure frequency lock. When the RT pin is floating, the frequency is internally set to be slightly under 200kHz. VRNG1, VRNG2 (Pin 9, Pin 34/Pin 13, Pin 38): Current Sense Voltage Range Inputs. When programmed between 0.6V and 2V, the voltage applied to VRNG1,2 is twenty times (20x) the maximum sense voltage between SENSE1,2+ and SENSE1,2–, i.e., for either channel, (VSENSE+ – VSENSE–) = 0.5 • VRNG. If a VRNG is tied to SGND the channel operates with a maximum sense voltage of 30mV, equivalent to a VRNG of 0.6V; If tied to INTVCC, a maximum sense voltage of 50mV, equivalent to a VRNG of 1V. Do not float these pins. ITH1 (Pin 10/Pin 14): Channel 1 VDDQ Current Control Threshold. This pin is the output of the error amplifier and the switching regulator’s compensation point. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V, with 0.8V corresponding to the zero sense voltage (zero inductor valley current). 3876f 10 LTC3876 PIN FUNCTIONS (QFN/TSSOP) TRACK/SS1 (Pin 11/Pin 15): External Tracking and SoftStart Input for Channel 1 VDDQ . An internal 1μA temperature-independent pull-up current source is connected to the TRACK/SS1 pin. A capacitor to ground at this pin sets the ramp time to the final regulated output voltage. The LTC3876 regulates VDFB1, the differential feedback voltages (VOUTSENSE1+ – VOUTSENSE1–) to the smaller of 0.6V or the voltage on the TRACK/SS1 pin. Alternatively, another voltage supply connected to this pin allows the output to track the outer supply during start-up. VOUTSENSE1+ (Pin 12/Pin 16): VDDQ Differential Output Sense Amplifier (+) Input of Channel 1. Connect this pin to a feedback resistor divider between the positive and negative output capacitor terminals of VOUT1. In nominal operation the LTC3876 will attempt to regulate the differential output voltage VOUT1 to 0.6V multiplied by the feedback resistor divider ratio. VOUTSENSE1– (Pin 13/Pin 17): Differential Output Sense Amplifier (–) Input of Channel 1. Connect this pin to the negative terminal of the output load capacitor. This pin is the remote ground connection for VDDQSNS which provides the input to the VTT reference (VTTR) resistor divider. SENSE1+, SENSE2+ (Pin 14, Pin 37/Pin 18, Pin 3): Differential Current Comparator (+) Input. The ITH pin voltage and controlled offsets between the SENSE+ and SENSE– pins set the current trip threshold. The comparator can be used for RSENSE sensing or inductor DCR sensing. For RSENSE sensing Kelvin (4-wire) connect the SENSE+ pin to the (+) terminal of RSENSE. For DCR sensing tie the SENSE+ pin to the connection between the DCR sense capacitor and sense resistor connected across the inductor. SENSE1–, SENSE2– (Pin 15, Pin 36/Pin 19, Pin 2): Differential Current Comparator(–) Input. The comparator can be used for RSENSE sensing or inductor DCR sensing. For RSENSE current sensing Kelvin (4-wire) connect the SENSE– pin to the (–) terminal of RSENSE. For DCR sensing tie the SENSE– pin to the DCR sense capacitor tied to the inductor VOUT node connection. These pins also function as output voltage sense pins for the top MOSFET on-time adjustment. The impedance looking into these pins is different from the SENSE+ pins because there is an additional 500k internal resistor from each of the SENSE– pins to SGND. DTR1 (Pin 16/Pin 20): Detect Load Transient Transient for Overshoot Reduction. When load current suddenly drops, if voltage on this DTR pin drops below half of INTVCC, the bottom gate (BG) will turn off and allow the inductor current to drop to zero faster, thus reducing the VOUT overshoot. (Refer to Load-Release Transient Detection in the Applications Information section for more details.) To disable the DTR feature, simply tie the DTR pin to INTVCC. RUN (Pin 17/Pin 21): Run Control Input. An internal proportional-to-absolute temperature (PTAT) pull-up current source (~2.5μA at 25°) is constantly connected to this pin. Taking RUN below a threshold (~0.8V at 25°) shuts down all bias of INTVCC and DRVCC and places the LTC3876 into micropower shutdown mode. Allowing the RUN pin to rise above this threshold turns on the internal bias supply and all circuitry while forcing TG and BG off. When the RUN pin rises above 1.2V the TG and BG drivers are turned on and an additional 10μA temperature-independent pull-up current is connected internally to the RUN pin. The RUN pin can sink up to 50μA or be forced as high as 6V. PGOOD (Pin 18/Pin 22): Power Good Indicator Output. This open-drain logic output is pulled to ground when VDDQ goes out of a ±7.5% or VTT goes out of a ±10% window around the regulation point, after a 50μs power-bad masking delay. Returning to the regulation point, there is a much shorted delay to power good, and a hysteresis of around 15mV on both sides of the window. BOOST1, BOOST2 (Pin 19, Pin 32/Pin 23, Pin 36): Boosted Floating Driver Supply for Top MOSFET Drivers. The (+) terminal of the bootstrap capacitor CB connects to this pin. The BOOST pins swings between (DRVCC – VSCHOTTKY) and (VIN + DRVCC – VSCHOTTKY). TG1, TG2 (Pin 20, Pin 31/Pin 24, Pin 35): Top Gate Driver Outputs. The TG pins drive the gates of the top N-channel power MOSFET with a voltage swing of DRVCC between SW and BOOST. SW1, SW2 (Pin 21, Pin 30/Pin 25, Pin 34): Switch Node Connection to Inductors. Voltage swings are from a diode voltage below ground to VIN. The (–) terminal of the bootstrap capacitor, CB connects to this node. 3876f 11 LTC3876 PIN FUNCTIONS (QFN/TSSOP) BG1, BG2 (Pin 22, Pin 29/Pin 26, Pin 33): Bottom Gate Driver Outputs. The BG pins drive the gates of the bottom N-channel power MOSFET between PGND and DRVCC. DRVCC1, DRVCC2 (Pin 23, Pin 28/Pin 27, Pin 32): Supplies of Bottom Gate Drivers. DRVCC1 is also the output of an internal 5.3V regulator, DRVCC2 is also the output of the EXTVCC switch. Normally the two DRVCC pins are shorted together on the PCB, and decoupled to PGND with a minimum of 4.7μF ceramic capacitor, CDRVCC. VIN (Pin 24/Pin 28): Input Voltage Supply. The supply voltage can range from 4.5V to 38V. For increased noise immunity decouple this pin to SGND with an RC filter. Voltage at this pin is also used to adjust top gate on-time, therefore it is recommended to tie this pin to the main power input supply through an RC filter. PGND (Pin 25, Exposed Pad Pin 39/Pin 29, Exposed Pad Pin 39): Power Ground. Connect this pin as close as practical to the source of the bottom N-channel power MOSFET, the (–) terminal of CDRVCC and the (–) terminal of CIN. Connect the exposed pad and PGND pin to SGND pin using a single PCB trace under the IC. The exposed pad must be soldered to the circuit board for electrical and rated thermal performance. INTVCC (Pin 26/Pin 30): Supply Input for Internal Circuitry (Not Including Gate Drivers). Normally powered from the DRVCC pins through a decoupling RC filter to SGND (typically 2.2Ω and 1μF) EXTVCC (Pin 27/Pin 31): External Power Input. When EXTVCC exceeds 4.7V, an internal switch connects this pin to DRVCC2 and shuts down the internal regulator so that INTVCC and gate-drive power is drawn from EXTVCC. The VIN pin still needs to be powered up but draws minimum current. VTTSNS (Pin 33/Pin 37): VTT Sense, Channel 2 Error Amplifier Feedback Input. Kelvin-connect this pin directly to desired regulation point on the VTT supply, VTTSNS provides the inverting regulation feedback signal for the VTT termination supply. Internally the VTT error amplifier positive input connects to the VTTR output for accurate VTTR reference tracking. VTTSNS will regulate channel 2 VTT termination supply to the differential reference voltage 0.5 • (VDDQSNS – VOUTSENSE1–). PHASMD (Pin 38/Pin 4): Phase Selector Input. This pin determines the relative phases of channels and the CLKOUT signal. With zero phase being defined as the rising edge of TG1: Pulling this pin to SGND locks TG2 to 180° and CLKOUT to 60°, Connecting this pin to INTVCC locks TG2 to 240° and CLKOUT to 120° and floating this pin locks TG2 to 180° and CLKOUT to 90°. CVCC (Pin 35/Pin 1): Connect VCC. This pin should always be connected to INTVCC. 3876f 12 LTC3876 FUNCTIONAL DIAGRAM VIN VIN IN EN LDO OUT SD 2μA TO 5μA PTAT 10μA + UVLO 4.2V + 1.2V BOOST TG DRV – RUN TG VTT CHANNEL 2 MT L SW EN_DRV – CB DB RSENSE DRVCC + 0.7V – – LOGIC CONTROL SENSE– VIN 250k 4.7V INTVCC COUT CINTVCC DRVCC2 DRVCC1 START ONE-SHOT TIMER VDDQ CHANNEL 1 EXTVCC + CDRVCC STOP RFB1 BG DRV 250k BG FORCED CONTINUOUS MODE ON-TIME ADJUST MODE/PLLIN IREV ICMP + + – – CLK1 CLOCK PLL/ GENERATOR RT CLK2 SENSE+ SENSE– TO CHANNEL 2 CLKOUT CVCC gm INTVCC INTVCC 1μA gm EA1 TRACK/SS + + – RPGD PGOOD 0.6V CSS OV DELAY RFB2 PHASE DETECTOR MODE/CLK DETECT RT MB PGND + DIFFAMP (A = 1) CH1 – UV VOUTSENSE1+ VOUTSENSE1– 105k 105k VDDQSNS DRVCC VTTRVCC CVTTR(VCC) OV VTTR CH2 CVTTR EA2 UV + – INTVCC 1/2 INTVCC DUPLICATE DASHED LINE BOX FOR CHANNEL 2 + LOAD RELEASE DETECTION VTTSNS 3876 FD CHANNEL 2 TO LOGIC CONTROL – VRNG ITH INTVCC DTR INTVCC CITH1 CITH2 RITH2 RITH1 3876f 13 LTC3876 OPERATION (Refer to Functional Diagram) DDR Operation The LTC3876 is a dual channel, current mode step-down controller designed to provide high efficiency power conversion for high power DDR memory and bus termination supplies. Its unique controlled on-time architecture allows extremely low step-down ratio’s while maintaining a fast, constant switching frequency. The LTC3876 is a complete DDR power solution with one master RUN pin, TRACK/SS input and PGOOD output. The RUN pin enables all supplies. The TRACK/SS pin determines the VDDQ soft-start characteristics and VTT tracks 0.5 • VDDQ. PGOOD monitors both VDDQ and VTT to ensure regulation within a ±7.5% typical window. The current limit settings are set independently on both VDDQ and VTT channels. The VDDQ, VTT and CLKOUT phase relationships are set by the PHASMD pin to permit multiphase operation in high power DDR solutions which require more than one VDDQ or VTT channel. VDDQ Supply The LTC3876 is designed to support any DDR application where VDDQ can range from 2.5V down to 1V. The LTC3876 supports high power applications by differentially regulating the VDDQ supply, VTTR reference and VTT supply. The channel 1 feedback resistor divider, VDDQSNS and VOUTSENSE– should be tied directly to the differential VDDQ regulation points. For best results these connections should be routed separately and Kelvin connected. VDDQSNS is the VDDQ regulation sense point or positive input and VOUTSENSE– is the remote ground sense point or negative input to the VTT differential reference resistor divider. The resistor divider is connected internally between VDDQSNS and VOUTSENSE– and is composed of two equally sized 105k resistors in series for 210K total resistance. VTT Supply The VTT supply reference is connected internally to the output of the VTTR VTT reference output. VTTSNS provides the inverting regulation feedback signal for the VTT termination supply. Kelvin-connect the VTTSNS pin directly to desired regulation point on the VTT supply. By sensing VTTSNS the channel 2 VTT supply regulates to VTTR. The VTT supply operates in forced continuous mode and tracks VDDQ in start-up and in normal operation regardless of the MODE/PLLIN settings. In start-up the VTT supply is enabled coincident with the VDDQ supply. Operating the VTT supply in forced continuous allows accurate tracking in startup and under all operating conditions. VTT Reference (VTTR) The linear VTT reference, VTTR, is specifically designed for large DDR memory systems by providing superior accuracy and load regulation for up to ±50mA output load. VTTR is the buffered output of the VTT differential reference resistor divider. VTTR is a high output linear reference which tracks the VTT differential reference resistor divider and is equal to 0.5 • (VDDQSNS – VOUTSENSE–). Connect VTTR directly to the DDR memory VREF input. Power is supplied through VTTRVCC. Internally the VTTR connection is connected to VDDQSNS reference to provide Kelvin sensing of VTTR. Both input and output supply decoupling is important to performance and accuracy. A 2.2μF output capacitor is recommended for most typical applications. It is suggested to use no less than 1μF and no more than 47μF on the VTTR output. The typical recommended input VTTRVCC RC decoupling filter is 2.2μF and 1Ω. When VDDQSNS is tied to INTVCC, the VTTR linear reference output is three-stated and VTTR becomes the VTTSNS reference input. This allows the option to tie the VTTR reference input to the VTTR output of a second LTC3876 in a multiphase application. Main Control Loop The LTC3876 is a controlled on-time, valley current mode step-down DC/DC dual controller with two channels operating out of phase. Each channel drives both main and synchronous N-channel MOSFETs. The two channels operate independently where channel 1 is VDDQ and channel 2 is the VTT termination supply which tracks 0.5 • VDDQ. The top MOSFET is turned on for a time interval determined by a one-shot timer. The one-shot timer or the top MOSFET ’s on-time is controlled to maintain a fixed switch3876f 14 LTC3876 OPERATION (Refer to Functional Diagram) ing frequency. As the top MOSFET is turned off, the bottom MOSFET is turned on after a small delay. The delay, or dead time, is to avoid both top and bottom MOSFETs being on at the same time, causing shoot-through current from VIN directly to power ground. The next switching cycle is initiated when the current comparator, ICMP, senses that inductor current falls below the trip level set by voltages at the ITH and VRNG pins. The bottom MOSFET is turned off immediately and the top MOSFET on again, restarting the one-shot timer and repeating the cycle. Again in order to avoid shoot-through current, there is a small dead-time delay before the top MOSFET turns on. At this moment, the inductor current hits its “valley” and starts to rise again. Inductor current is determined by sensing the voltage between SENSE+ and SENSE–, either by using an explicit resistor connected in series with the inductor or by implicitly sensing the inductor’s DC resistive (DCR) voltage drop through an RC filter connected across the inductor. The trip level of the current comparator, ICMP , is proportional to the voltage at the ITH pin, with a zero-current threshold corresponding to an ITH of 0.8V for channel 1 and 1.2V for channel 2. forward-conduction voltage. This creates a more negative differential voltage (VSW – VOUT) across the inductor, allowing the inductor current to drop faster to zero, thus creating less overshoot on VOUT. See Load-Release Transient Detection in Applications Information for details. Differential Output Sensing This dual controller’s first channel, VDDQ features differential output voltage sensing. The output voltage is resistively divided externally to create a feedback voltage for the controller. The internal difference amplifier (DIFFAMP) senses this feedback voltage with respect to the output’s remote ground reference to create a differential feedback voltage. This scheme eliminates any ground offsets between local ground and remote output ground, resulting in a more accurate output voltage. Channel 1 allows remote output ground deviate as much as ±500mV with respect to local ground (SGND). Channel 2 VTT is referenced to VTTR internally which differentially tracks 0.5 • (VDDQSNS – VOUTSENSE–). DRVCC/EXTVCC/INTVCC Power DRVCC1,2 are the power for the bottom MOSFET drivers. Normally the two DRVCC pins are shorted together on the PCB, and decoupled to PGND with a minimum 4.7μF ceramic capacitor, CDRVCC. The top MOSFET drivers are biased from the floating bootstrap capacitors (CB) which are recharged during each cycle through an external Schottky diode when the top MOSFET turns off and the SW pin swings down. The error amplifier (EA) adjusts this ITH voltage by comparing the feedback signal to the internal reference voltage. On channel 1, the difference amplifier (DA) converts the differential feedback signal (VOUTSENSE1+ – VOUTSENSE1–) to a single-ended input for the EA; channel 2 uses VTTSNS directly. Output voltage is regulated so that the feedback voltage is equal to the internal reference. If the load current increases/decreases, it causes a momentary drop/rise in the differential feedback voltage relative to the reference. The EA then moves ITH voltage, or inductor valley current setpoint, higher/lower until the average inductor current again matches the load current, so that the output voltage comes back to the regulated voltage. The DRVCC can be powered on two ways: an internal lowdropout (LDO) linear voltage regulator that is powered from VIN and can output 5.3V to DRVCC1. Alternatively, an internal EXTVCC switch (with on-resistance of around 2Ω) can short the EXTVCC pin to DRVCC2. The LTC3876 features a detect transient (DTR) pin on channel 1 to detect “load-release”, or a transient where the load current suddenly drops, by monitoring the first derivative of the ITH voltage. When detected, the bottom gate (BG) is turned off and inductor current flows through the body diode in the bottom MOSFET, allowing the SW node voltage to drop below PGND by the body diode’s If the EXTVCC pin is below the EXTVCC switchover voltage (typically 4.7V with 200mV hysteresis, see the Electrical Characteristics Table), then the internal 5.3V LDO is enabled. If the EXTVCC pin is tied to an external voltage source greater than this EXTVCC switchover voltage, then the LDO is shut down and the internal EXTVCC switch shorts the EXTVCC pin to the DRVCC2 pin, thereby powering DRVCC 3876f 15 LTC3876 OPERATION (Refer to Functional Diagram) and INTVCC with the external voltage source and helping to increase overall efficiency and decrease internal self heating from power dissipated in the LDO. This external power source could be the output of the step-down converter itself, given that the output is programmed to higher than 4.7V. The VIN pin still needs to be powered up but now draws minimum current. Power for most internal control circuitry other than gate drivers is derived from the INTVCC pin. INTVCC can be powered from the combined DRVCC pins through an external RC filter to SGND to filter out noises due to switching. Shutdown and Start-Up The RUN pin has an internal proportional-to-absolute temperature (PTAT) current source (around 2.5μA at 25°C) to pull up the pin. Taking the RUN pin below a certain threshold voltage (around 0.8V at 25°C) shuts down all bias of INTVCC and DRVCC and places the LTC3876 into micropower shutdown mode with a minimum IQ at the VIN pin. The LTC3876’s DRVCC (through the internal 5.3V LDO regulator or EXTVCC) and the corresponding channel’s internal circuitry off INTVCC will be biased up when either or both RUN pins are pulled up above the 0.8V threshold, either by the internal pull-up current or driven directly by external voltage source such as logic gate output. No channel of the LTC3876 will start switching until the RUN pin is pulled up to 1.2V. When the RUN pin rises above 1.2V, the TG and BG drivers are enabled, and TRACK/SS released. An additional 10μA temperatureindependent pull-up current is connected internally to the RUN pin. To turn off TG, BG and the additional 10μA pull-up current, RUN needs to be pulled down below 1.2V by about 100mV. These built-in current and voltage hystereses prevent false jittery turn-on and turn-off due to noise. Such features on the RUN pin allows input undervoltage lockout (UVLO) to be set up using external voltage dividers from VIN. At start-up channel 1 is controlled by the voltage on the TRACK/SS pin and channel 2 tracks 0.500 • (VDDQSNS – VOUTSENSE1–). When the voltage on the TRACK/SS pin is less than the 0.6V internal reference, the (differential) feedback voltage is regulated to the TRACK/SS voltage instead of the 0.6V reference. The TRACK/SS pin can be used to program the output voltage soft-start ramp-up time by connecting an external capacitor from a TRACK/SS pin to signal ground. An internal temperature-independent 1μA pull-up current charges this capacitor, creating a voltage ramp on the TRACK/SS pin. As the TRACK/SS voltage rises linearly from ground to 0.6V, the switching starts, VDDQ ramps up smoothly to its final value and the feedback voltage to 0.6V. TRACK/SS will keep rising beyond 0.6V, until being clamped to around 3.7V. Alternatively, the TRACK/SS pin can be used to track an external supply like in a master slave configuration. Typically, this requires connecting a resistor divider from the master supply to the TRACK/SS pin (see the Applications Information section). TRACK/SS1 is pulled low internally when the corresponding channel’s RUN pin is pulled below the 1.2V threshold (hysteresis applies), or when INTVCC or either of the DRVCC1,2 pins drop below their respective undervoltage lockout (UVLO) thresholds. Channel 1 VDDQ Light Load Operation If the MODE/PLLIN pin is tied to INTVCC or an external clock is applied to MODE/PLLIN, the LTC3876 will be forced to operate in continuous mode. With load current less than one-half of the full load peak-to-peak ripple, the inductor current valley can drop to zero or become negative. This allows constant-frequency operation but at the cost of low efficiency at light loads. If the MODE/PLLIN pin is left open or connected to signal ground, channel 1 will transition into discontinuous mode operation, where a current reversal comparator (IREV) shuts off the bottom MOSFET (MB) as the inductor current approaches zero, thus preventing negative inductor current and improving light-load efficiency. Only VDDQ channel 1 is allowed to operate in discontinuous mode. The VTT channel 2 operates in forced continuous mode at all times independent of the MODE/PLLIN setting. In this mode, both channel 1 switches remain off. As the output capacitor discharges by load current and the output voltage droops lower, channel 1 EA will eventually move the ITH voltage above the zero current level (0.8V) to initiate another switching cycle. 3876f 16 LTC3876 OPERATION (Refer to Functional Diagram) Power Good and Fault Protection The PGOOD pin is connected to an internal open-drain N-channel MOSFET. An external resistor or current source can be used to pull this pin up to 6V (e.g., VDDQ/VTT or DRVCC). Overvoltage or undervoltage comparators (OV, UV) turn on the MOSFET and pull the PGOOD pin low when the feedback voltage is outside the ±7.5% window of the 0.6V reference voltage. The PGOOD pin is also pulled low when the channel’s RUN pin is below the 1.2V threshold (hysteresis applies), or in undervoltage lockout (UVLO). Note that feedback voltage of channel 1 is sensed differentially through VOUTSENSE1+ with respect to VOUTSENSE1–, while channel 2 is sensed through VTTSNS. PGOOD is only high when both channels are within window. When the feedback voltage of channel 1 is within the ±7.5% window and channel 2 within the ±10% window, the open-drain NMOS is turned off and the pin is pulled up by the external source. The PGOOD pin will indicate power good immediately after the feedback is within the window. But when a feedback voltage of a channel goes out of the window, there is an internal 50μs delay before its PGOOD is pulled low. In an overvoltage (OV) condition, MT is turned off and MB is turned on immediately without delay and held on until the overvoltage condition clears. Foldback current limiting is provided if the output is below one-half of the regulated voltage, such as being shorted to ground. As the feedback drops below one-half of the normal regulation point approaching 0V, the internal ITH clamp voltage gradually drops 2.4V to 1.3V for VDDQ channel 1 and 2.2V to 1.8V for VTT channel 2. This reduces the inductor valley current level to about one-third of its maximum value as the feedback approaches 0V. Foldback current limiting is disabled at start-up. Frequency Selection and External Clock Synchronization An internal oscillator (clock generator) provides phaseinterleaved internal clock signals for individual channels to lock up to. The switching frequency and phase of each switching channel is independently controlled by adjust- ing the top MOSFET turn-on time (on-time) through the one-shot timer. This is achieved by sensing the phase relationship between a top MOSFET turn-on signal and its internal reference clock through a phase detector. The time interval of the one-shot timer is adjusted on a cycleby-cycle basis, so that the rising edge of the top MOSFET turn-on is always trying to synchronize to the internal reference clock signal for the respective channel. The frequency of the internal oscillator can be programmed from 200kHz to 2MHz by connecting a resistor, RT, from the RT pin to signal ground (SGND). The RT pin is regulated to 1.2V internally. For applications with stringent frequency or interference requirements, an external clock source connected to the MODE/PLLIN pin can be used to synchronize the internal clock signals through a clock phase-locked loop (Clock PLL). The LTC3876 operates in forced continuous mode of operation when it is synchronized to the external clock. The external clock frequency has to be within ±30% of the internal oscillator frequency for successful synchronization. The clock input levels should be no less than 2V for “high” and no greater than 0.5V for “low”. The MODE/ PLLIN pin has an internal 600k pull-down resistor. Multichip Operations The PHASMD pin determines the relative phases between the internal reference clock signals for the two channels as well as the CLKOUT signal, as shown in Table 1. The phases tabulated are relative to zero degree (0°) being defined as the rising edge of the internal reference clock signal of channel 1. The CLKOUT signal can be used to synchronize additional power stages in a multiphase power supply solution feeding either a single high current output, or separate outputs. Table 1 PHASMD SGND FLOAT INTVCC VDDQ Channel 1 0° 0° 0° VTT Channel 2 180° 180° 240° CLKOUT 60° 90° 120° 3876f 17 LTC3876 APPLICATIONS INFORMATION Once the required output voltage and operating frequency have been determined, external component selection is driven by load requirement, and begins with the selection of inductors and current sense method (either sense resistors RSENSE or inductor DCR sensing). Next, power MOSFETs are selected. Finally, input and output capacitors are selected. Output Voltage Programming As shown in Figure 1, external resistor dividers are used from the regulated outputs to their respective ground references to program the output voltages. On channel 1, the resistive divider is tapped by the VOUTSENSE1+ pin, and the ground reference is remotely sensed by the VOUTSENSE1– pin, this voltage is sensed differentially. Connect the VTTSNS pin directly to the VTT output. By regulating the tapped (differential) feedback voltages to the internal reference 0.6V, the resulting output voltages are: V(VDDQ) – VOUTSENSE1– = 0.6V • (1 + RFB2/RFB1) and V(VTT) = 0.500 • (VDDQ – VOUTSENSE1–) For example, if VOUT1 is programmed to 1.5V and the output ground reference is sitting at –0.5V with respect to SGND, then the absolute value of the output will be 2.0V with respect to SGND. The minimum (differential) output voltages are limited to the internal reference 0.6V, and the maximum are 5.5V. VOUT LTC3876 CFF (OPT) RFB2 COUT VOUTSENSE1+ RFB1 VOUTSENSE1– 3876 F01 The VOUTSENSE1+ pin is a high impedance pin with no input bias current other than leakage in the nA range. The VOUTSENSE1– pin has about 30μA of current flowing out of the pin. The VTTSNS pin is quasi-high impedance pin with minimum bias current out of the pin. Differential output sensing allows for more accurate output regulation in high power distributed systems having large line losses. Figure 2 illustrates the potential variations in the power and ground lines due to parasitic elements. The variations may be exacerbated in multi-application systems with shared ground planes. Without differential output sensing, these variations directly reflect as an error in the regulated output voltage. The LTC3876 channel 1’s differential output sensing can correct for up to ±500mV of variation in the output’s power and ground lines. The LTC3876 channel 1’s differential output sensing scheme is distinct from conventional schemes where the regulated output and its ground reference are directly sensed with a difference amplifier whose output is then divided down with an external resistor divider and fed into the error amplifier input. This conventional scheme is limited by the common mode input range of the difference amplifier and typically limits differential sensing to the lower range of output voltages. The LTC3876’s channel 1 allows for seamless differential output sensing by sensing the resistively divided feedback voltage differentially. This allows for differential sensing in the full output range. The difference amplifier (DIFFAMP) of the LTC3876 has a bandwidth of 8MHz, high enough so that it will not affect main loop compensation and transient behavior. To avoid noise coupling into the feedback voltage (VOUTSENSE1+), the resistor dividers should be placed close to the VOUTSENSE1+ and VOUTSENSE1–. Remote output and ground traces should be routed together as a differential pair to the remote output. For best accuracy, these traces to the remote output and ground should be connected as close as possible to the desired regulation point. Figure 1. Setting Output Voltage 3876f 18 LTC3876 APPLICATIONS INFORMATION CIN MT + – VIN POWER TRACE PARASITICS L LTC3876 VOUTSENSE1+ VOUTSENSE1– RFB2 ±VDROP(PWR) MB RFB1 COUT1 ILOAD COUT2 I LOAD GROUND TRACE PARASITICS ±VDROP(GND) OTHER CURRENTS FLOWING IN SHARED GROUND PLANE 3876 F02 Figure 2. Differential Output Sensing Used to Correct Line Loss Variations in a High Power Distributed System with a Shared Ground Plane Switching Frequency Programming Inductor Value Calculation The choice of operating frequency is a trade-off between efficiency and component size. Lowering the operating frequency improves efficiency by reducing MOSFET switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. Conversely, raising the operating frequency degrades efficiency but reduces component size. The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. A higher frequency generally results in lower efficiency because of MOSFET gate charge losses. In addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. The switching frequency of the LTC3876 can be programmed from 200kHz to 2MHz by connecting a resistor from the RT pin to signal ground. The value of this resistor can be chosen according to: The inductor value has a direct effect on ripple current. The inductor ripple current ∆IL decreases with higher inductance or frequency and increases with higher VIN: R T [kΩ] = 41550 – 2.2 f (kHz ) The overall controller system, including the clock PLL and switching channels, has a synchronization range of no less than ±30% around this programmed frequency. Therefore, during external clock synchronization be sure that the external clock frequency is within this ±30% range of the RT programmed frequency. It is advisable that the RT programmed frequency be equal the external clock for maximum synchronization margin. Refer to the “Phase and Frequency Synchronization” section for more details. ⎛V ⎞⎛ V ⎞ ΔIL = ⎜ OUT ⎟ ⎜ 1– OUT ⎟ ⎝ f •L ⎠ ⎝ VIN ⎠ Accepting larger values of ∆IL allows the use of low inductances, but results in higher output voltage ripple, higher ESR losses in the output capacitor, and greater core losses. A reasonable starting point for setting ripple current is ∆IL = 0.4 • IMAX. The maximum ∆IL occurs at the maximum input voltage. To guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: ⎛ V ⎞⎛ VOUT ⎞ OUT L=⎜ ⎟ ⎜ 1– ⎟ ⎝ f • ΔIL(MAX) ⎠ ⎝ VIN(MAX) ⎠ 3876f 19 LTC3876 APPLICATIONS INFORMATION Inductor Core Selection Current Limit Programming Once the value for L is known, the type of inductor must be selected. The two basic types are iron powder and ferrite. The iron powder types have a soft saturation curve which means they do not saturate hard like ferrites do. However, iron powder type inductors have higher core losses. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. The current sense comparators’ maximum trip voltage between SENSE+ and SENSE– (or “sense voltage”), when ITH is clamped at its maximum, is set by the voltage applied to the VRNG pin and is given by: Core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. This results an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! A variety of inductors designed for high current, low voltage applications are available from manufacturers such as Sumida, Panasonic, Coiltronics, Coilcraft, Toko, Vishay, Pulse and Würth. Current Sense Pins Inductor current is sensed through voltage between SENSE+ and SENSE– pins, the inputs of the internal current comparators. The input voltage range of the SENSE pins is –0.5V to 5.5V. Care must be taken not to float these pins during normal operation. The SENSE+ pins are quasi-high impedance inputs. There is no bias current into a SENSE+ pin when its corresponding channel’s SENSE– pin ramps up from below 1.1V and stays below 1.4V. But there is a small (~1μA) current flowing into a SENSE+ pin when its corresponding SENSE– pin ramps down from 1.4V and stays above 1.1V. Such currents also exist on SENSE– pins. But in addition, each SENSE– pin has an internal 500k resistor to SGND. The resulted current (VOUT/500k) will dominate the total current flowing into the SENSE– pins. SENSE+ and SENSE– pin currents have to be taken into account when designing either RSENSE or DCR inductor current sensing. VSENSE(MAX) = 0.05VRNG The valley current mode control loop does not allow the inductor current valley to exceed 0.05VRNG. In practice, one should allow sufficient margin, to account for tolerance of the parts and external component values. Note that ITH is close to 2.4V for channel 1 and 2.2V for channel 2 when in positive current limit. An external resistive divider from INTVCC can be used to set the voltage on a VRNG pin between 0.6V and 2V, resulting in a maximum sense voltage between 30mV and 100mV. Such wide voltage range allows for variety of applications. The VRNG pin can also be tied to either SGND or INTVCC to force internal defaults. When VRNG is tied to SGND, the device has an equivalent VRNG of 0.6V. When the VRNG pin is tied to INTVCC, the device has an equivalent VRNG of 2V. RSENSE Inductor Current Sensing The LTC3876 can be configured to sense the inductor currents through either low value series current sensing resistors (RSENSE) or inductor DC resistance (DCR). The choice between the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. DCR sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. However, current sensing resistors provide the most accurate current limits for the controller. A typical RSENSE inductor current sensing scheme is shown in Figure 3a. The filter components (RF , CF) need to be placed close to the IC. The positive and negative sense traces need to be routed as a differential pair close together and (4-wire) Kelvin connected underneath the sense resistor, as shown in Figure 3b. Sensing current elsewhere can effectively add parasitic inductance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. 3876f 20 LTC3876 APPLICATIONS INFORMATION RSENSE RESISTOR AND PARASITIC INDUCTANCE R ESL VOUT LTC3876 SENSE+ CF SENSE– CFt3F ≤ ESL/RS POLE-ZERO CANCELLATION RF RF 3876 F03a FILTER COMPONENTS PLACED NEAR SENSE PINS Figure 3a. RSENSE Current Sensing TO SENSE FILTER, NEXT TO THE CONTROLLER COUT RSENSE 3876 F03b Figure 3b. Sense Lines Placement with Sense Resistor RSENSE is chosen based on the required maximum output current. Given the maximum current, IOUT(MAX), maximum sense voltage, VSENSE(MAX), set by VRNG, and maximum inductor ripple current ∆IL(MAX), the value of RSENSE can be chosen as: VSENSE(MAX) RSENSE = ΔIL(MAX) IOUT(MAX) – 2 Conversely, given RSENSE and IOUT(MAX), VSENSE(MAX) and thus VRNG voltage can be determined from the above equation. To ensure the maximum output current, sufficient margin should be built in the calculations to account for variations of LTC3876 under different operating conditions and tolerances of external components. Because of possible PCB noise in the current sensing loop, the current sensing voltage ripple ∆VSENSE = ∆IL • RSENSE also needs to be checked in the design to get a good signal-to-noise ratio. In general, for a reasonably good PCB layout, 10mV of ∆VSENSE is recommended as a conservative number to start with, either for RSENSE or inductor DCR sensing applications. For today’s highest current density solutions the value of the sense resistor can be less than 1mΩ and the peak sense voltage can be as low as 20mV. In addition, inductor ripple currents greater than 50% with operation up to 2MHz are becoming more common. Under these conditions, the voltage drop across the sense resistor’s parasitic inductance becomes more relevant. A small RC filter placed near the IC has been traditionally used to reduce the effects of capacitive and inductive noise coupled in the sense traces on the PCB. A typical filter consists of two series 10Ω resistors connected to a parallel 1000pF capacitor, resulting in a time constant of 20ns. This same RC filter, with minor modifications, can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. For example, Figure 4a illustrates the voltage waveform across a 2mΩ sense resistor with a 2010 footprint for a 1.2V/15A converter operating at 100% load. The waveform is the superposition of a purely resistive component and a purely inductive component. It was measured using two scope probes and waveform math to obtain a differential measurement. Based on additional measurements of the inductor ripple current and the on-time and off-time of the top switch, the value of the parasitic inductance was determined to be 0.5nH using the equation: ESL = VESL(STEP) tON • tOFF • ΔIL tON + tOFF where VESL(STEP) is the voltage step caused by the ESL and shown in Figure 4a, and tON and tOFF are top MOSFET on-time and off-time respectively. If the RC time constant is chosen to be close to the parasitic inductance divided by the sense resistor (L/R), the resulting waveform looks resistive again, as shown in Figure 4b. For applications using low VSENSE(MAX), check the sense resistor manufacturer’s data sheet for information about parasitic inductance. In the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the ESL step and use the equation above to determine the ESL. However, do not over filter. Keep the RC time constant less than or equal to the inductor time constant to maintain a high enough ripple voltage on VRSENSE. 3876f 21 LTC3876 APPLICATIONS INFORMATION VSENSE 20mV/DIV VESL(STEP) 500ns/DIV 3876 F04a Figure 4a. Voltage Waveform Measured Directly Across the Sense Resistor The previous discussion generally applies to high density/ high current applications where IOUT(MAX) > 10A and low inductor values are used. For applications where IOUT(MAX) < 10A, set RF to 10Ω and CF to 1000pF. This will provide a good starting point. The filter components need to be placed close to the IC. The positive and negative sense traces need to be routed as a differential pair and Kelvin (4-wire) connected to the sense resistor. DCR Inductor Current Sensing For applications requiring higher efficiency at high load currents, the LTC3876 is capable of sensing the voltage drop across the inductor DCR, as shown in Figure 5. The DCR of the inductor represents the small amount of DC winding resistance, which can be less than 1mΩ for today’s low value, high current inductors. VSENSE 20mV/DIV 500ns/DIV 3876 F04b Figure 4b. Voltage Waveform Measured After the Sense Resistor Filter. CF = 1000pF, RF = 100Ω Note that the SENSE1– and SENSE2– pins are also used for sensing the output voltage for the adjustment of top gate on time, tON. For this purpose, there is an additional internal 500k resistor from each SENSE– pin to SGND, therefore there is an impedance mismatch with their corresponding SENSE+ pins. The voltage drop across the RF causes an offset in sense voltage. For example, with RF = 100Ω, at VOUT = VSENSE– = 5V, the sense-voltage offset VSENSE(OFFSET) = VSENSE– • RF/500k = 1mV. Such small offset may seem harmless for current limit, but could be significant for current reversal detection (IREV), causing excess negative inductor current at discontinuous mode. Also, at VSENSE(MAX) = 30mV, a mere 1mV offset will cause a significant shift of zero-current ITH voltage by (2.4V – 0.8V) • 1mV/30mV = 53mV. Too much shift may not allow the output voltage to return to its regulated value after the output is shorted due to ITH foldback. Therefore, when a larger filter resistor RF value is used, it is recommended to use an external 500k resistor from each SENSE+ pin to SGND, to balance the internal 500k resistor at its corresponding SENSE– pin. In a high current application requiring such an inductor, conduction loss through a sense resistor would cost several points of efficiency compared to DCR sensing. The inductor DCR is sensed by connecting an RC filter across the inductor. This filter typically consists of one or two resistors (R1 and R2) and one capacitor (C1) as shown in Figure 5. If the external (R1||R2) • C1 time constant is chosen to be exactly equal to the L/DCR time constant, the voltage drop across the external capacitor is equal to the voltage drop across the inductor DCR multiplied by R2/ (R1 + R2). Therefore, R2 may be used to scale the voltage across the sense terminals when the DCR is greater than INDUCTOR L DCR VOUT COUT L/DCR = (R1||R2) C1 LTC3876 R1 SENSE+ C1 – R2 (OPT) SENSE 3876 F05 C1 NEAR SENSE PINS Figure 5. DCR Current Sensing 3876f 22 LTC3876 APPLICATIONS INFORMATION the target sense resistance. With the ability to program current limit through the VRNG pin, R2 may be optional. C1 is usually selected in the range of 0.01μF to 0.47μF. This forces R1||R2 to around 2k to 4k, reducing error that might have been caused by the SENSE pins’ input bias currents. Resistor R1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. Capacitor C1 should be placed close to the IC pins. The first step in designing DCR current sensing is to determine the DCR of the inductor. Where provided, use the manufacturer’s maximum value, usually given at 25°C. Increase this value to account for the temperature coefficient of resistance, which is approximately 0.4%/°C. A conservative value for inductor temperature TL is 100°C. The DCR of the inductor can also be measured using a good RLC meter, but the DCR tolerance is not always the same and varies with temperature; consult the manufacturers’ data sheets for detailed information. From the DCR value, VSENSE(MAX) is easily calculated as: VSENSE(MAX) = DCRMAX(25°C) ( ) • ⎡1+ 0.4% TL(MAX) – 25°C ⎤ ⎣ ⎦ ΔI ⎞ ⎛ • ⎜ IOUT(MAX) – L ⎟ ⎝ 2 ⎠ If VSENSE(MAX) is within the maximum sense voltage (30mV to 100mV) of the LTC3876 as programmed by the VRNG pin, then the RC filter only needs R1. If VSENSE(MAX) is higher, then R2 may be used to scale down the maximum sense voltage so that it falls within range. The maximum power loss in R1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: PLOSS (R1) = (V IN(MAX) – VOUT )• V OUT R1 Ensure that R1 has a power rating higher than this value. If high efficiency is necessary at light loads, consider this power loss when deciding whether to use DCR sensing or RSENSE sensing. Light load power loss can be modestly higher with a DCR network than with a sense resistor due to the extra switching losses incurred through R1. However, DCR sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at heavy loads. Peak efficiency is about the same with either method. To maintain a good signal-to-noise ratio for the current sense signal, start with a ∆VSENSE of 10mV. For a DCR sensing application, the actual ripple voltage will be determined by: ΔVSENSE = VIN – VOUT VOUT • R1• C1 VIN • f Power MOSFET Selection Two external N-channel power MOSFETs must be selected for each channel of the LTC3876 controller: one for the top (main) switch and one for the bottom (synchronous) switch. The gate drive levels are set by the DRVCC voltage. This voltage is typically 5.3V. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic-level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the onresistance, RDS(ON), Miller capacitance, CMILLER, input voltage and maximum output current. Miller capacitance, CMILLER, can be approximated from the gate charge curve usually provided on the MOSFET manufacturers’ data sheet. CMILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat, divided by the specified VDS test voltage. When the IC is operating in continuous mode, the duty cycles for the top and bottom MOSFETs are given by: VOUT VIN V DBOT = 1– OUT VIN DTOP = 3876f 23 LTC3876 APPLICATIONS INFORMATION The MOSFET power dissipations at maximum output current are given by: a single-phase application. The maximum RMS capacitor current is given by: PTOP = DTOP •IOUT(MAX)2 •RDS(ON)(MAX) (1+ δ ) + VIN 2 IRMS ≅IOUT(MAX) • VOUT • VIN VIN –1 VOUT R TG(HI) R TG(LO) ⎤ ⎛ IOUT(MAX) ⎞ ⎡ • CMILLER ⎢ •⎜ + ⎥•f ⎟ 2 V – V V ⎝ ⎠ MILLER ⎦ ⎣ DRVCC MILLER This formula has a maximum at VIN = 2VOUT , where IRMS = IOUT(MAX)/2. This simple worst-case condition PBOT = DBOT • IOUT(MAX)2 • RDS(ON)(MAX) • (1 + δ ) is commonly used for design because even significant where δ is the temperature dependency of RDS(ON), RTG(HI) deviations do not offer much relief. Note that capacitor is the TG pull-up resistance, and RTG(LO) is the TG pull- manufacturers’ ripple current ratings are often based on down resistance. VMILLER is the Miller effect VGS voltage only 2000 hours of life. This makes it advisable to further and is taken graphically from the MOSFET ’s data sheet. derate the capacitor or to choose a capacitor rated at a Both MOSFETs have I2R losses while the topside N-channel higher temperature than required. Several capacitors may equation includes an additional term for transition losses, also be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the which are highest at high input voltages. For VIN < 20V, the high current efficiency generally improves with larger LTC3876, additional ceramic capacitors should also be MOSFETs, while for VIN > 20V, the transition losses rapidly used in parallel for CIN close to the IC and power switches increase to the point that the use of a higher RDS(ON) device to bypass the high frequency switching noises. Typically with lower CMILLER actually provides higher efficiency. The multiple X5R or X7R ceramic capacitors are put in parallel with either conductive-polymer or aluminum-electrolytic synchronous MOSFET losses are greatest at high input types of bulk capacitors. Because of its low ESR, the cevoltage when the top switch duty factor is low or during ramic capacitors will take most of the RMS ripple current. short-circuit when the synchronous switch is on close to Vendors do not consistently specify the ripple current 100% of the period. rating for ceramics, but ceramics could also fail due to The term (1 + δ) is generally given for a MOSFET in the excessive ripple current. Always consult the manufacturer form of a normalized RDS(ON) vs temperature curve in the if there is any question. power MOSFET data sheet. For low voltage MOSFETs, 0.5% per degree (°C) can be used to estimate δ as an Figure 6 represents a simplified circuit model for calculating the ripple currents in each of these capacitors. The approximation of percentage change of RDS(ON): input inductance (LIN) between the input source and the δ = 0.005/°C • (TJ – TA) input of the converter will affect the ripple current through where TJ is estimated junction temperature of the MOSFET LIN 1μH and TA is ambient temperature. CIN Selection In continuous mode, the source current of the top N-channel MOSFET is a square wave of duty cycle VOUT/ VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The worst-case RMS current occurs by assuming + – VIN ESR(BULK) ESR(CERAMIC) ESL(BULK) ESL(CERAMIC) IPULSE(PHASE1) IPULSE(PHASE2) + CIN(BULK) CIN(CERAMIC) 3876 F06 Figure 6. Circuit Model for Input Capacitor Ripple Current Simulation 3876f 24 LTC3876 APPLICATIONS INFORMATION the capacitors. A lower input inductance will result in less ripple current through the input capacitors since more ripple current will now be flowing out of the input source. For simulating positive output current loading using this model, look at the ripple current during steady-state for the case where one phase is fully loaded and the other is not loaded. This will in general be the worst-case for ripple current since the ripple current from one phase will not be cancelled by ripple current from the other phase. The LTC3876 is more complex than this example because the VTT channel can provide significant negative current. For the LTC3876 steady state worst-case, look at the condition where VDDQ channel is fully loaded and the VTT channel is supplying maximum negative current. This will in general be the worst-case for ripple current since the ripple current from VTT will add with ripple current from VDDQ when the VTT channel sinks or provides negative current. Note that the bulk capacitor also has to be chosen for RMS rating with ample margin beyond its RMS current per simulation with the circuit model provided. For a lower VIN range, a conductive-polymer type (such as Sanyo OS-CON) can be used for its higher ripple current rating and lower ESR. For a wide VIN range that also require higher voltage rating, aluminum-electrolytic capacitors are more attractive since it can provide a larger capacitance for more damping. An aluminum-electrolytic capacitor with a ripple current rating that is high enough to handle all of the ripple current by itself will be very large. But when in parallel with ceramics, an aluminum-electrolytic capacitor will take a much smaller portion of the RMS ripple current due to its high ESR. However, it is crucial that the ripple current through the aluminum-electrolytic capacitor should not exceed its rating since this will produce significant heat, which will cause the electrolyte inside the capacitor to dry over time and its capacitance to go down and ESR to go up. While it is always safest to choose the input capacitors RMS rating according to the worst-case single-phase application with negative VTT current as discussed above, it is likely not necessary. For DDR memory, the VTT output load current will statistically approach zero and should never operate at sustained negative current for any significant period of time in normal operation. There could be DDR test conditions which do exercise such extremes, but again this should not be continuous. Therefore, determine the worst-case RMS requirement for the input capacitors and reduce as appropriate for sufficient margin. The VIN sources of the top MOSFETs should be placed close to each other and share common CIN(s). Separating the sources and CIN may produce undesirable voltage and current resonances at VIN. A small (0.1μF to 1μF) bypass capacitor between the IC’s VIN pin and ground, placed close to the IC, is suggested. A 2.2Ω to 10Ω resistor placed between CIN and the VIN pin is also recommended as it provides further isolation from switching noise of the two channels. COUT Selection The selection of output capacitance COUT is primarily determined by the effective series resistance, ESR, to minimize voltage ripple. The output voltage ripple ∆VOUT , in continuous mode is determined by: ⎛ ⎞ 1 ΔVOUT ≤ ΔIL ⎜ RESR + 8 • f • COUT ⎟⎠ ⎝ where f is operating frequency, and ∆IL is ripple current in the inductor. The output ripple is highest at maximum input voltage since ∆IL increases with input voltage. Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds that required from ripple current. In single-output applications, for the same reason that LTC3876 is only truly phase interleaved at steady state, ripple current of individual channels could add up in transient, it is advisable to consider using the worst-case ∆IL, i.e., the sum of the ∆IL of all individual channels, in the calculation of ∆VOUT . The choice of using smaller output capacitance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low ESR to maintain the ripple voltage. 3876f 25 LTC3876 APPLICATIONS INFORMATION Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high-Q of ceramic capacitors with trace inductance can also lead to significant ringing. When used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. For high switching frequencies, reducing output ripple and better EMI filtering may require small value capacitors that have low ESL (and correspondingly higher self-resonant frequencies) to be placed in parallel with larger value capacitors that have higher ESL. This will ensure good noise and EMI filtering in the entire frequency spectrum of interest. Even though ceramic capacitors generally have good high frequency performance, small ceramic capacitors may still have to be parallel connected with large ones to optimize performance. High performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance. Remember also to place high frequency decoupling capacitors as close as possible to the power pins of the load. Top MOSFET Driver Supply (CB, DB) An external bootstrap capacitor, CB, connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. This capacitor is charged through diode DB from DRVCC when the switch node is low. When the top MOSFET turns on, the switch node rises to VIN and the BOOST pin rises to approximately VIN + INTVCC. The boost capacitor needs to store approximately 100 times the gate charge required by the top MOSFET. In most applications a 0.1μF to 0.47μF, X5R or X7R dielectric capacitor is adequate. It is recommended that the BOOST capacitor be no larger than 10% of the DRVCC capacitor, CDRVCC, to ensure that the CDRVCC can supply the upper MOSFET gate charge and BOOST capacitor under all operating conditions. Variable frequency in response to load steps offers superior transient performance but requires higher instantaneous gate drive. Gate charge demands are greatest in high frequency low duty factor applications under high load steps and at start-up. DRVCC Regulator and EXTVCC Power The LTC3876 features a PMOS low dropout (LDO) linear regulator that supplies power to DRVCC from the VIN supply. The LDO regulates its output at the DRVCC1 pin to 5.3V. The LDO can supply a maximum current of 100mA and must be bypassed to ground with a minimum of 4.7μF ceramic capacitor. Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers and to minimize interaction between the channels. High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3876 to be exceeded, especially if the LDO is active and provides DRVCC. Power dissipation for the IC in this case is highest and is approximately equal to VIN • IDRVCC. The gate charge current is dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equation given in Note 2 of the Electrical Characteristics. For example, when using the LDO, LTC3876’s DRVCC current is limited to less than 52mA from a 38V supply at TA = 70°C in the FE package: TJ = 70°C + (52mA)(38V)(28°C/W) = 125°C To prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode at maximum VIN. 3876f 26 LTC3876 APPLICATIONS INFORMATION When the voltage applied to the EXTVCC pin rises above 4.7V, the VIN LDO is turned off and the EXTVCC is connected to DRVCC2 pin with an internal switch. This switch remains on as long as the voltage applied to EXTVCC remains above 4.5V. Using EXTVCC allows the MOSFET driver and control power to be derived from the LTC3876’s switching regulator output VOUT during normal operation and from the LDO when the output is out of regulation (e.g., startup, short-circuit). If more current is required through the EXTVCC than is specified, an external Schottky diode can be added between the EXTVCC and DRVCC pins. Do not apply more than 6V to the EXTVCC pin and make sure that EXTVCC is less than VIN. Significant efficiency and thermal gains can be realized by powering DRVCC from the switching converter output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher efficiency). Tying the EXTVCC pin to a 5V supply reduces the junction temperature in the previous example from 125°C to: For applications where the main input power never exceeds 5.3V, tie the DRVCC1 and DRVCC2 pins to the VIN input through a small resistor, (such as 1Ω to 2Ω) as shown in Figure 7 to minimize the voltage drop caused by the gate charge current. This will override the LDO and will prevent DRVCC from dropping too low due to the dropout voltage. Make sure the DRVCC voltage exceeds the RDS(ON) test voltage for the external MOSFET which is typically at 4.5V for logic-level devices. LTC3876 DRVCC2 DRVCC1 RDRVCC VIN CDRVCC CIN 3876 F07 Figure 7. Setup for VIN ≤ 5.3V TJ = 70°C + (52mA)(5V)(28°C/W) = 77°C However, for 3.3V and other low voltage outputs, additional circuitry is required to derive DRVCC power from the converter output. The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from the internal 5.3V LDO resulting in an efficiency penalty of up to 10% at high input voltages. 2. EXTVCC connected directly to switching converter output VOUT > 4.7V. This provides the highest efficiency. 3. EXTVCC connected to an external supply. If a 4.7V or greater external supply is available, it may be used to power EXTVCC providing that the external supply is sufficient for MOSFET gate drive requirements. 4. EXTVCC connected to an output-derived boost network. For 3.3V and other low voltage converters, efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage that has been boosted to greater than 4.7V. Input Undervoltage Lockout (UVLO) The LTC3876 has two functions that help protect the controller in case of input undervoltage conditions. An internal UVLO comparator constantly monitors the INTVCC and DRVCC voltages to ensure that adequate voltages are present. The comparator enables internal UVLO signal, which locks out the switching action of both channels, until the INTVCC and DRVCC1,2 pins are all above their respective UVLO thresholds. The rising threshold (to release UVLO) of the INTVCC is typically 4.2V, with 0.5V falling hysteresis (to re-enable UVLO). The UVLO thresholds for DRVCC1,2 are lower than that of INTVCC but higher than typical threshold voltages of power MOSFETs, to prevent them from turning on without sufficient gate drive voltages. Generally for VIN > 6V, a UVLO can be set through monitoring the VIN supply by using external voltage dividers at the RUN pins from VIN to SGND. To design the voltage divider, note that both RUN pins have two levels of threshold voltages. The precision gate-drive-enable threshold voltage of 1.2V 3876f 27 LTC3876 APPLICATIONS INFORMATION can be used to set a VIN to turn on a channel’s switching. If resistor dividers are used on both RUN pins, when VIN is low enough and both RUN pins are pulled below the ~0.8V threshold, the part will shut down all bias of INTVCC and DRVCC and be put in micropower shutdown mode. The RUN pins’ bias currents depend on the RUN voltages. The bias current changes should be taken into account when designing the external voltage divider UVLO circuit. An internal proportional-to-absolute-temperature (PTAT) pull-up current source (~2.5μA at 25°C) is constantly connected to this pin. When a RUN pin rises above 1.2V, the corresponding channel’s TG and BG drives are turned on and an additional 4μA temperature-independent pull-up current is connected internally to the RUN pin. Pulling the RUN pin to fall below 1.2V by more than an 80mV hysteresis turns off TG and BG of the corresponding channel, and the additional 10μA pull-up current is disconnected. As voltage on a RUN pin increases, typically beyond 3V, its bias current will start to reverse direction and flow into the RUN pin. Keep in mind that neither of the RUN pins can sink more than 50μA; Even if a RUN pin may slightly exceed 6V when sinking 50μA, a RUN pin should never be forced to higher than 6V by a low impedance voltage source to prevent faulty conditions. Soft-Start and Tracking The LTC3876 has the ability to either soft-start by itself with a capacitor or track the output of another channel or an external supply. Note that the soft-start or tracking features are achieved not by limiting the maximum output current of the controller, but by controlling the output ramp voltage according to the ramp rate on the TRACK/SS pin. When channel 1 is configured to soft-start by itself, a capacitor should be connected to its TRACK/SS pin. TRACK/SS is pulled low until the RUN pin voltage exceeds 1.2V and UVLO is released, at which point an internal current of 1μA charges the soft-start capacitor, CSS, connected to the TRACK/SS pin. Current-limit foldback is disabled during this phase to ensure smooth soft-start or tracking. The soft-start or tracking range is defined to be the voltage range from 0V to 0.6V on the TRACK/SS pin. The total soft-start time can be calculated as: t SS(SEC) = 0.6(V)• CSS (µF) 1(µA) When one particular channel is configured to track an external supply, a voltage divider can be used from the external supply to the TRACK/SS pin to scale the ramp rate appropriately. Two common implementations are coincidental tracking and ratiometric tracking. For coincident tracking, make the divider ratio from the external supply the same as the divider ratio for the differential feedback voltage. Ratiometric tracking could be achieved by using a different ratio than the differential feedback. Note that the 1μA soft-start capacitor charging current is still flowing, producing a small offset error. To minimize this error, select the tracking resistive divider values to be small enough to make this offset error negligible. The LTC3876 allows the user to program how channel 1 VDDQ tracks an external power supply. Channel 2 VTT will always track VDDQ and be equal to 0.5 • VDDQ. By selecting different resistors, the LTC3876 can achieve different modes of tracking including the two in Figure 8a. To implement the coincident tracking, connect an additional resistive divider to the external power supply and connect its midpoint to the TRACK/SS pin of the slave channel. The ratio of this divider should be the same as that of the slave channel’s feedback divider shown in Figure 8b. In this tracking mode, the external power supply must be set higher than VDDQ. To implement the ratiometric tracking, the master channel’s feedback divider can be also used to provide TRACK/SS voltage for the slave channel, since the additional divider, if used, should be of the same ratio as the master channel’s feedback divider. 3876f 28 LTC3876 APPLICATIONS INFORMATION So which mode should be programmed? While either mode satisfies most practical applications, some tradeoffs exist. The ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. When the master channel’s output experiences dynamic excursion (under load transient, for example), the slave channel output will be affected as well. For better output regulation, use the coincident tracking mode instead of ratiometric. Phase and Frequency Synchronization For applications that require better control of EMI and switching noise or have special synchronization needs, the LTC3876 can synchronize the turn-on of the top MOSFET to an external clock signal applied to the MODE/PLLIN pin. The applied clock signal needs to be within ±30% of the RT programmed frequency to ensure proper frequency and phase lock. The clock signal levels should generally comply to VPLLIN(H) > 2V and VPLLIN(L) < 0.5V. The MODE/ PLLIN pin has an internal 600k pull-down resistor to ensure discontinuous current mode operation if the pin is left open. The LTC3876 uses the voltages on VIN and VOUT pins as well as RT to adjust the top gate on-time in order to maintain phase and frequency lock for wide ranges of VIN, VOUT and RT-programmed switching frequency f: tON ≈ VOUT VIN • f VDDQ EXTERNAL POWER SUPPLY OUTPUT VOLTAGE OUTPUT VOLTAGE EXTERNAL POWER SUPPLY VDDQ TIME TIME Coincident Tracking 3876 F08a Ratiometric Tracking Figure 8a. Two Different Modes of Output Tracking EXTERNAL POWER SUPPLY TO TRACK/SS1 PIN VDDQ RFB2(1) RFB1(1) RFB2(1) TO VOUTSENSE1+ PIN RFB1(1) TO VOUTSENSE1– PIN Coincident Tracking Setup EXTERNAL POWER SUPPLY TO TRACK/SS1 PIN R2 R1 TO VOUTSENSE1+ PIN TO VOUTSENSE1– PIN VDDQ RFB2(2) RFB1(2) 3876 F08b Ratiometric Tracking Setup Figure 8b. Setup for Coincident and Ratiometric Tracking 3876f 29 LTC3876 APPLICATIONS INFORMATION As the on-time is a function of the switching regulator’s output voltage, this output is measured by the VOUT pin to set the required on-time. Simply connecting VOUT to the regulator’s local output point is preferable for most applications, as the remotely regulated output point could be significantly different from the local output point due to line losses, and local output versus local ground is typically the VOUT required for the calculation of tON. However, there could be circumstances where this VOUT programmed on-time differs significantly different from the on-time required in order to maintain frequency and phase lock. For example, lower efficiencies in the switching regulator can cause the required on-time to be substantially higher than the internally set on-time (see Efficiency Considerations). If a regulated VOUT is relatively low, proportionally there could be significant error caused by the difference between the local ground and remote ground, due to other currents flowing through the shared ground plane. During dynamic transient conditions either in the line voltage or load current (e.g., load step or release), the top switch will turn on more or less frequently in response to achieve faster transient response. This is the benefit of the LTC3876’s controlled on-time, valley current mode architecture. However, this process may understandably lose phase and even frequency lock momentarily. For relatively slow changes, phase and frequency lock can still be maintained. For large load current steps with fast slew rates, phase lock will be lost until the system returns back to a steady-state condition (see Figure 9). It may take up to several hundred microseconds to fully resume the phase lock, but the frequency lock generally recovers quickly, long before phase lock does. For light load conditions, the phase and frequency synchronization depends on the MODE/PLLIN pin setting. If the external clock is applied, synchronization will be active and switching in continuous mode. If MODE/PLLIN is tied to INTVCC, it will operate in forced continuous mode at the RT-programmed frequency. If the MODE/PLLIN pin is tied to SGND, the LTC3876 will operate in discontinuous mode at light load and switch into continuous conduction at the RT programmed frequency as load increases. The TG on-time during discontinuous conduction is intentionally slightly extended (approximately 1.2 times the continuous conduction on-time as calculated from VIN, VOUT and f) to create hysteresis at the load-current boundary of continuous/discontinuous conduction. ILOAD CLOCK INPUT PHASE AND FREQUENCY LOCKED PHASE AND FREQUENCY LOCK LOST DUE TO FAST LOAD STEP FREQUENCY RESTORED QUICKLY PHASE LOCK RESUMED PHASE AND FREQUENCY LOCK LOST DUE TO FAST LOAD STEP FREQUENCY RESTORED QUICKLY SW VOUT 3876 F09 Figure 9. Phase and Frequency Locking Behavior During Transient Conditions 3876f 30 LTC3876 APPLICATIONS INFORMATION If an application requires very low (approaching minimum) on-time, the system may not be able to maintain its full frequency synchronization range. Getting closer to minimum on-time, it may even lose phase/frequency lock at no load or light load conditions, under which the SW on-time is effectively longer than TG on-time due to TG/BG dead times. This is discussed further under Minimum On-Time, Minimum Off-Time and Dropout Operation. Minimum On-Time, Minimum Off-Time and Dropout Operation The minimum on-time is the smallest duration that LTC3876’s TG (top gate) pin can be in high or “on” state. It has dependency on the operating conditions of the switching regulator, and is a function of voltages on the VIN and VOUT pins, as well as the value of external resistor RT. A minimum on-time of 30ns can be achieved when the VOUT pin is tied to its minimum value of 0.6V while the VIN is tied to its maximum value of 38V. For larger values of VOUT and/or smaller values of VIN, the minimum achievable on-time will be longer. The valley mode control architecture allows low on-time, making the LTC3876 suitable for high step-down ratio applications. The effective on-time, as determined by the SW node pulse width, can be different from this TG on-time, as it also depends on external components, as well as loading conditions of the switching regulator. One of the factors that contributes to this discrepancy is the characteristics of the power MOSFETs. For example, if the top power MOSFET’s turn-on delay is much smaller than the turn-off delay, the effective on-time will be longer than the TG on-time, limiting the effective minimum on-time to a larger value. Light-load operation, in forced continuous mode, will further elongate the effective on-time due to the dead times between the “on” states of TG and BG, as shown in Figure 10. During the dead time from BG turn-off to TG turn-on, the inductor current flows in the reverse direction, charging the SW node high before the TG actually turns on. The reverse current is typically small, causing a slow rising edge. On the falling edge, after the top FET turns off and before the bottom FET turns on, the SW node lingers high for a longer duration due to a smaller peak inductor current available in light load to pull the SW node low. As a result of the sluggish SW node rising and falling edges, the effective on-time is extended and not fully controlled by the TG on-time. Closer to minimum on-time, this may cause some phase jitter to appear at light load. As load current increase, the edges become sharper, and the phase locking behavior improves. The minimum on-time of the VTT channel is further limited by the fact that it must support negative current operation. Both the TG to BG and BG to TG dead-time delays add TG-SW (VGS OF TOP MOSFET) DEAD-TIME DELAYS BG (VGS OF BOTTOM MOSFET) IL 0 NEGATIVE INDUCTOR CURRENT IN FCM VIN SW 3876 F10 DURING BG-TG DEAD TIME, NEGATIVE INDUCTOR CURRENT WILL FLOW THROUGH TOP MOSFET’S BODY DIODE TO PRECHARGE SW NODE IL + – DURING TG-BG DEAD TIME, THE RATE OF SW NODE DISCHARGE WILL DEPEND ON THE CAPACITANCE ON THE SW NODE AND INDUCTOR CURRENT MAGNITUDE VIN L L SW IL TOTAL CAPACITANCE ON THE SW NODE Figure 10. Light Loading On-Time Extension for Forced Continuous Mode Operation 3876f 31 LTC3876 APPLICATIONS INFORMATION to the minimum on-time of 30ns as shown in Figure 10. Each of the dead times are in the order of 35ns. Therefore, the VTT channel minimum on time should be no less than 100ns with 150ns preferred. In continuous mode operation, the minimum on-time limit imposes a minimum duty cycle of: DMIN = f • tON(MIN) where tON(MIN) is the effective minimum on-time for the switching regulator. As the equation shows, reducing the operating frequency will alleviate the minimum duty cycle constraint. If the minimum on-time that LTC3876 can provide is longer than the on-time required by the duty cycle to maintain the switching frequency, the switching frequency will have to decrease to maintain the duty cycle, but the output voltage will still remain in regulation. This is generally more preferable to skipping cycles and causing larger ripple at the output, which is typically seen in fixed frequency switching regulators. For applications that require relatively low on-time, proper caution has to be taken when choosing the power MOSFET. If the gate of the MOSFET is not able to fully turn on due to insufficient on-time, there could be significant heat dissipation and efficiency loss as a result of larger RDS(ON). This may even cause early failure of the power MOSFET. The minimum off-time is the smallest duration of time that the TG pin can be turned low and then immediately turned back high. This minimum off-time includes the time to turn on the BG (bottom gate) and turn it back off, plus the dead-time delays from TG off to BG on and from BG off to TG on. The minimum off-time that the LTC3876 can achieve is 90ns. The effective minimum off-time of the switching regulator, or the shortest period of time that the SW node can stay low, can be different from this minimum off-time. The main factor impacting the effective minimum off-time is the top and bottom power MOSFETs’ electrical characteristics, such as Qg and turn-on/off delays. These characteristics can either extend or shorten the SW nodes’ effective minimum off-time. Large size (high Qg) power MOSFETs generally tend to increase the effective minimum off-time due to longer gate charging and discharging times. On the other hand, imbalances in turn-on and turn-off delays could reduce the effective minimum off-time. The minimum off-time limit imposes a maximum duty cycle of: DMAX = 1 – f • tOFF(MIN) where tOFF(MIN) is the effective minimum off-time of the switching regulator. Reducing the operating frequency can alleviate the maximum duty cycle constraint. If the maximum duty cycle is reached, due to a drooping input voltage for example, the output will drop out of regulation. The minimum input voltage to avoid dropout is: VIN(MIN) = VOUT DMAX At the onset of drop-out, there is a region of VIN of about 500mV that generates two discrete off-times, one being the minimum off time and the other being an off-time that is about 40ns to 60ns longer than the minimum off-time. This secondary off-time is due to the extra delay in tripping the internal current comparator. The two off-times average out to the required duty cycle to keep the output in regulation. There may be higher SW node jitter, apparent especially when synchronized to an external clock, but the output voltage ripple remains relatively small. Fault Conditions: Current Limiting and Overvoltage The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the LTC3876, the maximum sense voltage is controlled by the voltage on the VRNG pin. With valley current mode control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. The corresponding output current limit is: ILIMIT = VSENSE(MAX) RSENSE 1 + • ΔIL 2 The current limit value should be checked to ensure that ILIMIT(MIN) > IOUT(MAX). The current limit value should be greater than the inductor current required to produce maximum output power at the worst-case efficiency. 3876f 32 LTC3876 APPLICATIONS INFORMATION Worst-case efficiency typically occurs at the highest VIN and highest ambient temperature. It is important to check for consistency between the assumed MOSFET junction temperatures and the resulting value of ILIMIT which heats the MOSFET switches. To further limit current in the event of a short circuit to ground, the LTC3876 includes foldback current limiting. If the output falls by more than 50%, the maximum sense voltage is progressively lowered, to about one-fourth of its full value as the feedback voltage reaches 0V. A feedback voltage exceeding 7.5% for VDDQ channel 1 and 10% for VTT channel 2 of the regulated target of 0.6V is considered as overvoltage (OV). In such an OV condition, the top MOSFET is immediately turned off and the bottom MOSFET is turned on indefinitely until the OV condition is removed, i.e., the feedback voltage falling back below the threshold by more than a hysteresis of typical 15mV. Current limiting is not active during an OV. If the OV persists, and the BG turns on for a longer time, the current through the inductor and the bottom MOSFET may exceed their maximum ratings, sacrificing themselves to protect the load. OPTI-LOOP Compensation An additional small capacitor, CITH2, can be placed from the ITH pin to SGND to attenuate high frequency noise. Note this CITH2 contributes an additional pole in the loop gain therefore can affect system stability if too large. It should be chosen so that the added pole is higher than the loop bandwidth by a significant margin. The regulator loop response can also be checked by looking at the load transient response. An output current pulse of 20% to 100% of full-load current having a rise time of 1μs to 10μs will produce VOUT and ITH voltage transient-response waveforms that can give a sense of the overall loop stability without breaking the feedback loop. For a detailed explanation of OPTI-LOOP compensation, refer to Application Note 76. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ∆ILOAD • ESR, where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT , generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. OPTI-LOOP® compensation, through the availability of the ITH pin, allows the transient response to be optimized for a wide range of loads and output capacitors. The ITH pin not only allows optimization of the control-loop behavior but also provides a DC-coupled and AC-filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly 2nd order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. Connecting a resistive load in series with a power MOSFET, then placing the two directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. The initial output voltage step resulting from the step change in load current may not be within the bandwidth of the feedback loop, so it cannot be used to determine phase margin. The output voltage settling behavior is more related to the stability of the closed-loop system. However, it is better to look at the filtered and compensated feedback loop response at the ITH pin. The external series RITH-CITH1 filter at the ITH pin sets the dominant pole-zero loop compensation. The values can be adjusted to optimize transient response once the final PCB layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected first because their various types and values determine the loop feedback factor gain and phase. The gain of the loop increases with the RITH and the bandwidth of the loop increases with decreasing CITH1. If RITH is increased by the same factor that CITH1 is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. In addition, a feedforward capacitor, CFF , 3876f 33 LTC3876 APPLICATIONS INFORMATION can be added to improve the high frequency response, as shown in Figure 1. Capacitor CFF provides phase lead by creating a high frequency zero with RFB2 which improves the phase margin. A more severe transient can be caused by switching in loads with large supply bypass capacitors. The discharged bypass capacitors of the load are effectively put in parallel with the converter’s COUT , causing a rapid drop in VOUT . No regulator can deliver current quick enough to prevent this sudden step change in output voltage, if the switch connecting the COUT to the load has low resistance and is driven quickly. The solution is to limit the turn-on speed of the load switch driver. Hot Swap™ controllers are designed specifically for this purpose and usually incorporate current limiting, short-circuit protection and soft starting. Load-Release Transient Detection As the output voltage requirement of step-down switching regulators becomes lower, VIN to VOUT step-down ratio increases, and load transients become faster, a major challenge is to limit the overshoot in VOUT during a fast load current drop, or “load-release” transient. Inductor current slew rate diL/dt = VL/L is proportional to voltage across the inductor VL = VSW – VOUT. When the top MOSFET is turned on, VL = VIN – VOUT, inductor current ramps up. When bottom MOSFET turns on, VL = VSW – VOUT = –VOUT, inductor current ramps down. At very low VOUT, the low differential voltage, VL, across the inductor during the ramp down makes the slew rate of the inductor current much slower than needed to follow the load current change. The excess inductor current charges up the output capacitor, which causes overshoot at VOUT. If the bottom MOSFET could be turned off during the loadrelease transient, the inductor current would flow through the body diode of the bottom MOSFET, and the equation can be modified to include the bottom MOSFET body diode drop to become VL = –(VOUT + VBD). Obviously the benefit increases as the output voltage gets lower, since VBD would increase the sum significantly, compared to a single VOUT only. The load-release overshoot at VOUT causes the error amplifier output, ITH, to drop quickly. ITH voltage is proportional to the inductor current setpoint. A load transient will result in a quick change of this load current setpoint, i.e., a negative spike of the first derivative of the ITH voltage. The LTC3876 uses a detect transient (DTR) pin to monitor the first derivative of the ITH voltage, and detect the loadrelease transient. Referring to the Functional Diagram, the DTR pin is the input of a DTR comparator, and the internal reference voltage for the DTR comparator is half of INTVCC. To use this pin for transient detection, ITH compensation needs an additional RITH resistor tied to INTVCC, and connects the junction point of ITH compensation components CITH1, RITH1 and RITH2 to the DTR pin as shown in the Functional Diagram. The DTR pin is now proportional to the first derivative of the inductor current setpoint, through the highpass filter of CITH1 and (RITH1//RITH2). The two RITH resistors establish a voltage divider from INTVCC to SGND, and bias the DC voltage on DTR pin (at steady-state load or ITH voltage) slightly above half of INTVCC. Compensation performance will be identical by using the same CITH1 and make RITH1//RITH2 equal the RITH as used in conventional single resistor OPTI-LOOP compensation. This will also provide the R-C time constant needed for the DTR duration. The DTR sensitivity can be adjusted by the DC bias voltage difference between DTR and half INTVCC. This difference could be set as low as 100mV, as long as the ITH ripple voltage with DC load current does not trigger the DTR. When load current suddenly drops, VOUT overshoots, and ITH drops quickly. The voltage on the DTR pin will also drop quickly, since it is coupled to the ITH pin through a capacitor. If the load transient is fast enough that the DTR voltage drops below half of INTVCC, a load release event is detected. The bottom gate (BG) will be turned off, so that the inductor current flows through the body diode in the bottom MOSFET. This allows the SW node to drop below PGND by a voltage of a forward-conducted silicon diode. This creates a more negative differential voltage (VSW – VOUT) across the inductor, allowing the inductor current to drop at a faster rate to zero, therefore creating less overshoot on VOUT. 3876f 34 LTC3876 APPLICATIONS INFORMATION The DTR comparator output is overridden by reverse inductor current detection (IREV) and overvoltage (OV) condition. This means BG will be turned off when SENSE+ is higher than SENSE– (i.e., inductor current is positive), as long as the OV condition is not present. When inductor current drops to zero and starts to reverse, BG will turn back on in forced continuous mode (e.g., the MODE/ PLLIN pin tied to INTVCC, or an input clock is present), even if DTR is still below half INTVCC. This is to allow the inductor current to go negative to quickly pull down the VOUT overshoot. Of course, if the MODE/PLLIN pin is set to discontinuous mode (i.e., tied to SGND), BG will stay off as inductor current reverse, as it would with the DTR feature disabled. Note that it is expected that this DTR feature will cause additional loss on the bottom MOSFET, due to its body diode conduction. The bottom FET temperature may be higher with a load of frequent and large load steps. This is an important design consideration. Experiments on the demo board shows a 20°C increase when a continuous 100% to 50% load step pulse train with 50% duty cycle and 100kHz frequency is applied to the output. If not needed, this DTR feature can be disabled by tying the DTR pin to INTVCC, or simply leave the DTR pin open so that an internal 2.5A current source will pull itself up to INTVCC. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percentage efficiency can be expressed as: %Efficiency = 100% – (L1% + L2% + L3% + ...) where L1%, L2%, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce power losses, several main sources usually account for most of the losses in LTC3876 circuits: 1. I2R loss. These arise from the DC resistances of the MOSFETs, inductor, current sense resistor and is the majority of power loss at high output currents. In continuous mode the average output current flows though the inductor L, but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the inductor’s DC resistances (DCR) and the board traces to obtain the I2R loss. For example, if each RDS(ON) = 8mΩ, RL = 5mΩ, and RSENSE = 2mΩ the loss will range from 15mW to 1.5W as the output current varies from 1A to 10A. This results in loss from 0.3% to 3% a 5V output, or 1% to 10% for a 1.5V output. Efficiency varies as the inverse square of VOUT for the same external components and output power level. The combined effects of lower output voltages and higher currents load demands greater importance of this loss term in the switching regulator system. 2. Transition loss. This loss mostly arises from the brief amount of time the top MOSFET spends in the saturation (Miller) region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors, and can be significant at higher input voltages or higher switching frequencies. 3. DRVCC current. This is the sum of the MOSFET driver and INTVCC control currents. The MOSFET driver currents result from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from DRVCC to ground. The resulting dQ/dt is a current out of DRVCC that is typically much larger than the controller IQ current. In continuous mode, IGATECHG = f • (Qg(TOP) + Qg(BOT)), where Qg(TOP) and Qg(BOT) are the gate charges of the top and bottom MOSFETs, respectively. Supplying DRVCC power through EXTVCC could save several percents of efficiency, especially for high VIN applications. Connecting EXTVCC to an output-derived 3876f 35 LTC3876 APPLICATIONS INFORMATION source will scale the VIN current required for the driver and controller circuits by a factor of (duty cycle)/(efficiency). For example, in a 20V to 5V application, 10mA of DRVCC current results in approximately 2.5mA of VIN current. This reduces the mid-current loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. 4. CIN loss. The input capacitor filters large square-wave input current drawn by the regulator into an averaged DC current from the supply. The capacitor itself has a zero average DC current, but square-wave-like AC current flows through it. Therefore the input capacitor must have a very low ESR to minimize the RMS current loss on ESR. It must also have sufficient capacitance to filter out the AC component of the input current to prevent additional RMS losses in upstream cabling, fuses or batteries. The LTC3876 2-phase architecture improves the ESR loss. “Hidden” copper trace, fuse and battery resistance, even at DC current, can cause a significant amount of efficiency degradation, so it is important to consider them during the design phase. Other losses, which include the COUT ESR loss, bottom MOSFET ’s body diode reverse-recovery loss, and inductor core loss generally account for less than 2% additional loss. Power losses in the switching regulator will reflect as a higher than ideal duty cycle, or a longer on-time for a constant frequency. This efficiency accounted on-time can be calculated as: tON ≈ tON(IDEAL)/Efficiency When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If you make a change and the input current decreases, then the efficiency has increased. Design Example The following design example is the DDR3 application circuit as implemented on the standard LTC3876 QFN demo board 1631A. This DC/DC step-down converter design accommodates an input VIN range of 4.5V to 14V, with a VDDQ output of 1.5V and a VTT output of 0.75V. The DDRIII output channels are designed to produce 1.5V VDDQ at 20A, a 0.75V VTT 10A maximum average operating current with a VTT reference output (VTTR) capable of supplying up to ±50mA. (see Figure 11, LTC3876 demo circuit 1631A) The regulated channel 1 VDDQ output supply voltage is determined by: ⎛ R ⎞ VDDQ = 0.6V 1+ FB2 ⎝ RFB1 ⎠ Set VDDQ to 1.5V for DDRIII application. Using a 20k resistor for RFB1, the resulting RBF2 is 30k. The regulated channel 2 VTT termination supply is differentially referenced to an internal resistor divider connected between the VDDQSNS and the VOUTSENSE–. The resulting differential VTT reference output (VTTR) is one-half VDDQ which in this design example is 0.75V. The VTT termination supply nominally regulates to 0.75V and will track any dynamic movement of the channel 1 VDDQ supply. The switching frequency for both channels is programmed by: R T [kΩ ] = 4 • 41550 – 2.2 f [kHz ] For f = 400kHz, R T = 102kΩ. The minimum on-time occurs for maximum VIN and should be greater than the typical minimum of 30ns with adequate margin. The minimum on-time margin should allow for device variability and the extension of effective on-time at light load due to the dead times. The reason for the on-time extension at light load is that the negative inductor current causes the switch node to rise which effectively adds to the on time. This is of limited concern to the channel 1 VDDQ but is of greater concern to the channel 2 VTT supply because it supplies significant negative current. For the LTC3876 the minimum on-time without any extension is 30ns, with driver dead times of 30ns. For strong negative currents in VTT the total dead time is the total of the minimum on-time, plus both dead times for 90ns. It is therefore recommended to keep the minimum on-time greater than 100ns for channel 2 VTT to assure PLL lock under all operating conditions. 3876f 36 LTC3876 APPLICATIONS INFORMATION The minimum on-time for channel 1 VDDQ is: tON(MIN) = VOUT VIN(MAX) • f = 1.5V = 268ns 14V • 400kHz The minimum on-time for channel 2 VTT is: tON(MIN) = VOUT VIN(MAX) • f = 0.75V = 134ns 14V • 400kHz Set the channel 1 VDDQ inductor value L1 to give 35% ripple current at the maximum load to 20A for the maximum VIN of 14V using the adjusted operating frequency. ⎛ VOUT ⎞ ⎟ L1= ⎜1− ( f ) (IRIPPLE ) ⎝ VIN(MAX)⎠ VOUT ⎛ 1.5 ⎞ ⎟ = 0.47μH = ⎜1− ( 400kHz ) ( 35% t 20A ) ⎝ 14 ⎠ 1.5V Set the channel 2 VTT inductor value L2 to give 35% ripple current at the maximum load to 10A for the maximum VIN of 14V using the adjusted operating frequency. ⎛ VOUT ⎞ ⎟ ⎜1− ( f ) (IRIPPLE ) ⎝ VIN(MAX)⎠ ⎛ 0.75⎞ 0.75V = ⎟ = 0.47μH ⎜1− ( 400kHz ) ( 37.5% t 10A ) ⎝ 14 ⎠ L1= VOUT Choose the nearest standard value of 0.47μH for L2, which will result in 37.5% ripple current. The resulting channel 1 VDDQ maximum ripple current is: ΔIL1 = ⎛ 1.5V⎞ 1.5V ⎟ = 7.12A ⎜1− ( 400kHz )(0.47μH ) ⎝ 14V ⎠ The resulting channel 2 VTT maximum ripple current is: ΔIL2 = ⎛ 0.75V⎞ 0.75V ⎟ = 3.78A ⎜1− ( 400kHz )(0.47μH ) ⎝ 14V ⎠ For Figure 11, standard demo board the current limit is set using sense resistors. The VRNG is grounded which results in a maximum VSENSE voltage across the RSENSE resistor of 30mV. If we assume 50% over the nominal output of 20A this gives a starting point of 1mΩ for channel 1 VDDQ and 2mΩ for channel 2 VTT. Channel 1 VDDQ current limit for 1mΩ RSENSE. ILIMITVDDQ = VSENSE ΔIL 30mV 7.12A + = + = 33.5A 1mΩ 2 R SENSE 2 Channel 2 VTT current limit for 2mΩ RSENSE. ILIMITVTT = VSENSE ΔIL 30mV 3.78A + = + = 16.9A R SENSE 2 2mΩ 2 In high power applications, DCR current sensing is often preferred to RSENSE in order to maximize efficiency. The inductor model is selected based on its inductor and DCR value. The Würth WE7443330047 with a rated current of 20A, a saturation current of 47A and DCR of 0.8mΩ is chosen for channel 1 VDDQ. The Würth WE7443340047 with a rated current of 19A, a saturation current of 32A and DCR of 1.72mΩ is chosen for channel 2 VTT. The DCR demo board design is Figure 13. In this design example VRNG was grounded to produce an internal default value of 30mV on VSENSE. Channel 1 VDDQ DCR Current limit: V ΔI ILIMIT VDDQ = SENSE + L R SENSE 2 30mV 7.12A = + 0.8mΩ • (1+(100 ° C – 25 ° C) • 0.4% / ° C) 2 = 32.4A Channel 2 VTT DCR Current Limit: V ΔIL ILIMIT V T T = SENSE + R SENSE 2 30mV 3.78A = + 1.72mΩ • (1+(100 ° C – 25 ° C) • 0.4% / ° C) 2 = 15.3A 3876f 37 LTC3876 APPLICATIONS INFORMATION The DCR sense filter is designed using a simple RC filter across the inductor. If the inductor value and DCR is known, choose a sense filter C and calculate filter resistance. These numbers show that careful attention should be paid to proper heat sinking when operating at higher ambient temperatures. Channel 1 DCR filter resistor RDCR1: Select CIN capacitors to give ample capacitance and RMS ripple current rating. Consider worst-case duty cycles per Figure 6. If operated at steady-state with SW nodes fully interleaved, the two channels would generate not more than 7.5A RMS at full load. In this design example, 2X 10μF 25V X5R ceramic capacitors are put in parallel to take the RMS ripple current with 330μF aluminum electrolytic bulk capacitors for stability. For 10μF 1210 X5R ceramic capacitors, try to keep the ripple current less than 3A RMS through each device. The bulk capacitor is chosen for RMS rating per simulation with the circuit model provided. RDCR1 = L1 0.47μH = = 5.9k DCR •CDCR 0.8mΩ • 0.1μF Channel 2 DCR filter resistor RDCR2: RDCR1 = L1 0.47μH = = 2.74k DCR •CDCR 1.72mΩ • 0.1μF The external N-channel MOSFETs are chosen based on current capability and efficiency. The Renesas RJK0305DBP(RDS(ON)=13mΩ(maximum),CMILLER=150pF, VGS = 4.5V, VMILLER = 3V, θJA = 40°C/W, TJ(MAX) = 150°C) is chosen for the top MOSFET (main switch). The Renesas RJK0330DBP (RDS(ON) = 3.9mΩ(maximum), VGS = 4.5V, θJA = 40°C/W, TJ(MAX) =150°C) is chosen for the bottom MOSFET (synchronous switch).The power dissipation for each MOSFET can be calculated for VIN = 14V and typical TJ =125°C. The power dissipation for VIN = 14V and TJ =125°C for the top MOSFET is: The power supply output capacitor’s COUT are chosen for a low ESR. For channel 1 VDDQ, the output capacitor SANYO 2R5TPE330M9, has an ESR of 9mΩ which results in 4.5mΩ for two in parallel. For channel 2 VTT, the output capacitor SANYO 2R5TPE330M9, has an ESR of 9mΩ. The output ripple for each channel is given as: ΔVDDQ(RIPPLE) = ΔIL(MAX) (ESR) = (7.12A) • (4.5mΩ) = 32mV ΔVTT(RIPPLE) = ΔIL(MAX) (ESR) 1.5V PTOP = (20A)2 (1+0.4%(125°C–25°C)) (0.013Ω) + 14V ⎛20A⎞ ⎛ 2.5Ω 1.2Ω⎞ ⎟ (400kHz ) + (14V )2 ⎜ ⎟ (150pF ) ⎜ ⎝ 2 ⎠ ⎝5.3V – 3V 3V ⎠ = 0.78W + 0.17W = 0.95W The power dissipation for VIN = 14V and TJ =125°C for 2X bottom MOSFETs is: 14V – 1.5V ⎛20A⎞ 2 ⎜ ⎟ 14V ⎝ 2X ⎠ (1+ 0.4%(125°C – 25°C)) (0.0039Ω) = 0.4875W PBOT = The resulting junction temperatures for ambient temperature TA = 75°C are: = (3.78A) • (9mΩ) = 34mV A 0A to 10A load step in VDDQ will cause an output change of up to: ΔVDDQ(STEP) = ΔILOAD (ESR) = 10A • 0.0045mΩ = 45mV A 0A to 5A load step in VTT will cause an output change of up to: ΔVTT(STEP) = ΔILOAD (ESR) = 5A • 0.009mΩ = 45mV Optional 100μF ceramic output capacitors are included to minimize the effect of ESL in the output ripple and to improve load step response. TJ(TOP) = 75°C + (0.95W)(40°C/W) = 113°C TJ(BOT) = 75°C + (0.975W)(40°C/W) = 94.5°C 3876f 38 LTC3876 APPLICATIONS INFORMATION PCB Layout Checklist The printed circuit board layout is illustrated graphically in Figure 12. Use the following checklist to ensure proper operation of the LTC3876: • A multilayer printed circuit board with dedicated ground planes is generally preferred to reduce noise coupling and improve heat sinking. The ground plane layer should be immediately next to the routing layer for the power components, e.g., MOSFETs, inductors, sense resistors, input and output capacitors etc. • Keep SGND and PGND separate. Upon finishing the layout, connect SGND and PGND together with a single PCB trace underneath the IC from the SGND pin through the exposed PGND pad to the PGND pin. • All power train components should be referenced to PGND; all components connected to noise-sensitive pins, e.g., ITH, RT , TRACK/SS and VRNG, should return to the SGND pin. Keep PGND ample, but SGND area compact. Use a modified “star ground” technique: a low impedance, large copper area central PCB point on the same side of the as the input and output capacitors. • Place power components, such as CIN, COUT , MOSFETs, DB and inductors, in one compact area. Use wide but shortest possible traces for high current paths (e.g., VIN, VOUT , PGND etc.) to this area to minimize copper loss. • Keep the switch nodes (SW1,2), top gates (TG1,2) and boost nodes (BOOST1,2) away from noise-sensitive small-signal nodes, especially from the opposite channel’s voltage and current sensing feedback pins. These nodes have very large and fast moving signals and therefore should be kept on the “output side” of the LTC3876 (power-related pins are toward the right hand side of the IC), and occupy minimum PC trace area. Use compact switch node (SW) planes to improve cooling of the MOSFETs and to keep EMI down. If DCR sensing is used, place the top filter resistor (R1 only in Figure 5) close to the switch node. • The top N-channel MOSFETs of the two channels have to be located within a short distance from (preferably <1cm) each other with a common drain connection at CIN. Do not attempt to split the input decoupling for the two channels as it can result in a large resonant loop. • Connect the input capacitor(s), CIN, close to the power MOSFETs. This capacitor provides the MOSFET transient spike current. Connect the drain of the top MOSFET as close as possible to the (+) plate of the ceramic portion of input capacitors CIN. Connect the source of the bottom MOSFET as close as possible to the (–) terminal of the same ceramic CIN capacitor(s). These ceramic capacitor(s) bypass the high di/dt current locally, and both top and bottom MOSFET should have short PCB trace lengths to minimize high frequency EMI and prevent MOSFET voltage stress from inductive ringing. • The path formed by the top and bottom N-channel MOSFETs, and the CIN capacitors should have short leads and PCB trace. The (–) terminal of output capacitors should be connected close to the (–) terminal of CIN, but away from the loop described above. This is to achieve an effect of Kevin (4-wire) connection to the input ground so that the “chopped” switching current will not flow through the path between the input ground and the output ground, and cause common mode output voltage ripple. • Several smaller sized ceramic output capacitors, COUT , can be placed close to the sense resistors and before the rest bulk output capacitors. • The filter capacitor between the SENSE+ and SENSE– pins should always be as close as possible to these pins. Ensure accurate current sensing with Kevin (4-wire) connections to the soldering pads from underneath the sense resistors or inductor. A pair of sense traces should be routed together with minimum spacing. RSENSE, if used, should be connected to the inductor on the noiseless output side, and its filter resistors close to the SENSE+/SENSE– pins. For DCR sensing, however, filter resistor should be placed close to the inductor, and away from the SENSE+/SENSE– pins, as its terminal is the SW node. 3876f 39 LTC3876 APPLICATIONS INFORMATION VIN 4.5V TO 14V CIN1 180μF w2 CIN2 10μF w3 2.2Ω LTC3876 1μF VIN SENSE1– SENSE2– SENSE1+ SENSE2+ BOOST1 BOOST2 0.1μF 0.1μF 0.1μF 0.1μF 5.9K L1 0.47μH VDDQ 1.5V 20A MT1 COUT2 330μF w2 TG2 SW1 SW2 2.74K MT2 DB1 DB2 2.2Ω COUT1 100μF TG1 DRVCC1 INTVCC L1 0.47μH DRVCC2 EXTVCC COUT4 330μF 4.7μF 1μF MB1 BG1 BG2 1Ω VDDQSNS 1μF VOUTSENSE1+ 20k VOUTSENSE1– 100k PGOOD PGOOD 0.01μF ITH1 1500pF 12.7k VTTRVCC VTTSNS DTR1 VRNG1 100k RT SGND RUN VTTR ±50mA 2.2μF VTTR TRACK/SS1 120pF COUT3 100μF MB2 PGND 30.1k VTT 0.75V ±10A 470pF ITH2 4700pF 13.7k CVCC VRNG2 PHASMD MODE/PLLIN CLKOUT CIN1: SANYO 16SVP180M CIN2: MURATA GRM32DR61E106KA12L COUT2,COUT4: SANYO 2R5TPE330M9 COUT1, COUT3: MURATA GRM31CR60J107ME39L DB1, DB2: CENTRAL SEMI CMDSH-3 L1: WÜRTH 7443330047 L2: WÜRTH 7443340047 MT1, MB2: INFINEON BSC0901NS MB1: INFINEON BSC010NE2LS MT2: INFINEON BSC050NE2LS 3876 F11a 100 4.5 VIN = 12V VDDQ = 1.5V 4.0 90 DISCONTINUOUS MODE 3.0 2.5 70 2.0 1.5 60 POWER LOSS (W) EFFICIENCY (%) 3.5 80 1.0 50 40 0.1 FORCED CONTINUOUS MODE 1 LOAD CURRENT (A) 0.5 0 10 3876 F11b Figure 11. Design Example: 4.5V to 14V Input, VDDQ 1.5V/20A and VTT 0.75V/±10A Output, 400kHz, DCR, Step-Down Converter • Keep small-signal components connected noise-sensitive pins (give priority to SENSE+/SENSE–, VOUTSENSE1+/ VOUTSENSE1–, VFB2, RT , ITH, VRNG pins) on the left hand side of the IC as close to their respective pins as possible. This minimizes the possibility of noise coupling into these pins. If the LTC3876 can be placed on the bottom side of a multilayer board, use ground planes to isolate from the major power components on the top side of the board, and prevent noise coupling to noise sensitive components on the bottom side. 3876f 40 LTC3876 APPLICATIONS INFORMATION SENSE2– SENSE2 VTTSNS PGOOD2 BOOST2 + CB2 LTC3876 DRVCC2 EXTVCC ITH2 CITH2(2) RT CITH2(1) COUT2 PGND CVIN VIN VRNG1 CDRVCC VIN RVIN GND + CIN CERAMIC COUT1 DRVCC1 RITH1(1) DB1 ITH1 CITH1(1) MT1 MB1 BG1 SW1 TRACK/SS1 RFB2(1) CERAMIC CINTVCC + RT MB2 RINTVCC + VRNG2 PHASMD MODE/PLLIN CLKOUT SGND LOCALIZED SGND TRACE RITH2(1) MT2 INTVCC CVCC RSENSE2 VOUT2 DB2 CITH1(2) RITH1(2) L2 TG2 SW2 BG2 CSS1 RSENSE1 VOUT1 TG1 VOUTSENSE1+ RFB1(1) CB1 L1 BOOST1 VOUTSENSE1– SENSE1+ SENSE1– PGOOD1 RUN1 DTR1 3876 F12 Figure 12. Recommended PCB Layout Diagram • Place the resistor feedback divider RFB1, RFB2 close to VOUTSENSE1+ and VOUTSENSE1– pins for channel 1, or VFB2 pin for channel 2, so that the feedback voltage tapped from the resistor divider will not be disturbed by noise sources. Route remote sense PCB traces (use a pair of wires closely together for differential sensing in channel 1) directly to the terminals of output capacitors for best output regulation. • Place decoupling capacitors CITH2 next to the ITH and SGND pins with short, direct trace connections. • Use sufficient isolation when routing a clock signal into the MODE/PLLIN pin or out of the CLKOUT pin, so that the clock does not couple into sensitive pins. • Place the ceramic decoupling capacitor CINTVCC between the INTVCC pin and SGND and as close as possible to the IC. • Place the ceramic decoupling capacitor CDRVCC close to the IC, between the combined DRVCC1,2 pins and PGND. • Filter the VIN input to the LTC3876 with an RC filter. Place the filter capacitor close to the VIN pin. • If vias have to be used, use immediate vias to connect components to the SGND and PGND planes of LTC3876. Use multiple large vias for power components. 3876f 41 LTC3876 APPLICATIONS INFORMATION • Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. Connect the copper areas to DC rails only, e.g., PGND. PCB Layout Debugging Only after each controller is checked for its individual performance should both controllers be turned on at the same time. It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator output CLKOUT, or external clock if used. Probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range. The phase should be maintained from cycle to cycle in a well designed, low noise PCB implementation. Variation in the phase of SW node pulse can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PCB layout if regulator bandwidth optimization is not required. A particularly difficult region of operation is when one controller channel is turning on (right after its current comparator trip point) while the other channel is turning off its top MOSFET at the end of its on-time. This may cause minor phase-lock jitter at either channel due to noise coupling. Reduce VIN from its nominal level to verify operation of the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST, SW, TG, and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between CIN, top and bottom MOSFET components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the SGND pin of the IC. High Switching Frequency Operation At high switching frequencies there may be an increased sensitivity to noise. Special care may need to be taken to prevent cycle-by-cycle instability and/or phase-lock jitter. First, carefully follow the recommended layout techniques to reduce coupling from the high switching voltage/current traces. Additionally, use low ESR and low impedance X5R or X7R ceramic input capacitors: up to 5μF per Amp. of load current may be needed. If necessary, increase ripple sense voltage by increasing sense resistance value and VRNG setting, to improve noise immunity. 3876f 42 LTC3876 APPLICATIONS INFORMATION VIN 4.5V TO 14V CIN1 180μF w2 CIN2 10μF w3 2.2Ω LTC3876 1μF VIN SENSE1– SENSE2– SENSE1+ SENSE2+ BOOST1 BOOST2 0.1μF 0.1μF 0.1μF 0.1μF 5.9k L1 0.47μH VDDQ 1.8V 20A MT1 COUT2 330μF w2 TG2 SW1 SW2 2.74k MT2 DB1 DB2 2.2Ω DRVCC1 INTVCC DRVCC2 EXTVCC BG1 MB1 BG2 1μF VOUTSENSE1+ 20k VOUTSENSE1– PGOOD 0.01μF 12.7k PGOOD VTTRVCC VTTSNS 2.2μF VTTR TRACK/SS1 120pF 1500pF 100k ITH1 DTR1 VRNG1 RT SGND RUN COUT3 100μF 1Ω VDDQSNS 100k VTT 0.9V ±10A MB2 PGND 30.1k L1 0.47μH COUT4 330μF 4.7μF 1μF VTTR ±50mA 470pF ITH2 4700pF 13.7k CVCC VRNG2 PHASMD MODE/PLLIN CLKOUT CIN1: SANYO 16SVP180M CIN2: MURATA GRM32DR61E106KA12L COUT2,COUT4: SANYO 2R5TPE330M9 COUT1, COUT3: MURATA GRM31CR60J107ME39L DB1, DB2: CENTRAL SEMI CMDSH-3 L1: WÜRTH 7443330047 L2: WÜRTH 7443340047 MT1, MB2: INFINEON BSC0901NS MB1: INFINEON BSC010NE2LS MT2: INFINEON BSC050NE2LS 3876 F13a 100 4.5 VIN = 12V VDDQ = 1.8V 4.0 90 3.5 80 DISCONTINUOUS MODE 3.0 2.5 70 2.0 1.5 60 POWER LOSS (W) EFFICIENCY (%) COUT1 100μF TG1 1.0 50 40 0.1 FORCED CONTINUOUS MODE 1 LOAD CURRENT (A) 0.5 0 10 3876 F13b Figure 13. 4.5V to 14V Input, VDDQ 1.8V/20A and VTT 0.9V/±10A Output, 400kHz, DCR, Step-Down Converter 3876f 43 LTC3876 APPLICATIONS INFORMATION VIN 4.5V TO 28V CIN1 100μF CIN2 10μF w3 2.2Ω LTC3876 1μF VIN 100Ω SENSE1– SENSE2– SENSE1+ SENSE2+ BOOST1 BOOST2 100Ω 1nF 100Ω 1nF 100Ω 0.1μF R31 VDDQ 1V 20A L1 0.67μH COUT2 330μF w2 TG1 MT1 TG2 MT2 DB1 DB2 SW1 2.2Ω 0.002Ω COUT1 100μF 0.1μF DRVCC1 INTVCC DRVCC2 EXTVCC BG1 MB1 BG2 VDDQSNS 1μF VOUTSENSE1+ VOUTSENSE1– PGOOD 0.1μF 220pF 18.2k 113k PGOOD VTTRVCC VTTSNS 2.2μF VTTR TRACK/SS1 220pF 205k ITH1 DTR1 VRNG1 RT SGND 20k RUN COUT3 100μF 1Ω 20k 100k VTT 0.5V ±10A MB2 PGND 30.1k R32 0.003Ω COUT4 330μF 4.7μF 1μF L2 0.68μH SW2 1000pF ITH2 2700pF 2.55k CVCC VRNG2 PHASMD VTTR ±50mA CIN1: NICHICON UCJ1H101MCL1GS CIN2: MURATA GRM32ER71H106K COUT2,COUT4: SANYO 2R5TPE330M9 COUT1, COUT3: MURATA GRM31CR60J107ME39L DB1, DB2: CENTRAL SEMI CMDSH-3 L1: WÜRTH 744315067 L2: WÜRTH 744311068 MT1: INFINEON BSC035N04LS MB1, MB2: INFINEON BSC011N03LS MT2: VISHAY SiR462DP MODE/PLLIN CLKOUT 3876 F14a 100 4.0 VIN = 12V VDDQ = 1V 3.5 90 DISCONTINUOUS MODE 2.5 2.0 70 1.5 60 POWER LOSS (W) EFFICIENCY (%) 3.0 80 1.0 50 40 0.1 FORCED CONTINUOUS 0.5 MODE 0 1 10 LOAD CURRENT (A) 3876 F14b Figure 14. 4.5V to 28V Input, VDDQ 1V/20A and VTT 0.50V/±10A Output, 200kHz, RSENSE, Step-Down Converter 3876f 44 LTC3876 APPLICATIONS INFORMATION VIN 4.5V TO 38V CIN1 100μF CIN2 10μF w4 2.2Ω LTC3876 1μF VIN – SENSE1 SENSE2– SENSE1+ SENSE2+ BOOST1 BOOST2 1nF 0.1μF R31 0.002Ω VDDQ 1.2V 20A L1 0.82μH 1nF 2.49Ω TG1 MT1 COUT2 330μF w4 TG2 MT2 DB1 DB2 SW1 2.2Ω COUT1 100μF 0.1μF 1.15Ω DRVCC2 EXTVCC 4.7μF BG1 MB1 BG2 MB2 PGND 20k VOUTSENSE1– PGOOD 0.01μF 13.7k 560pF 86.6k 118k PGOOD VTTSNS 2.2μF VTTR ITH1 1800pF 4.22k CVCC VRNG2 PHASMD RT MODE/PLLIN RUN VTTR ±50mA 560pF ITH2 DTR1 VRNG1 SGND COUT3 100μF VTTRVCC TRACK/SS1 180pF COUT4 330μF w2 1μF VOUTSENSE1+ 100k VTT 0.6V ±10A 1Ω VDDQSNS 20k R32 0.002Ω SW2 DRVCC1 INTVCC 1μF L2 0.82μH CLKOUT CIN1: NICHICON UCJ1H101MCL1GS CIN3, CIN4, CIN5: MURATA GRM32ER71H106K COUT1, COUT2, COUT5: SANYO 2R5TPE330M9 COUT4, COUT7: MURATA GRM31CR60J107ME39L DB1, DB2: CENTRAL SEMI CMDSH-3 L1: WÜRTH 744315067 L2: WÜRTH 744311068 MT1: INFINEON BSC035N04LS MB1 MB2: INFINEON BSC011N03LS MT2: VISHAY SiR462DP 3876 F15a 100 5.0 VIN = 12V VDDQ = 1.2V 4.5 80 4.0 3.5 DISCONTINUOUS MODE 3.0 2.5 70 2.0 60 50 40 0.1 1.5 POWER LOSS (W) EFFICIENCY (%) 90 1.0 FORCED CONTINUOUS 0.5 MODE 0 1 10 LOAD CURRENT (A) 3876 F15b Figure 15. 4.5V to 38V Input, VDDQ 1.2V/20A and VTT 0.60V/±10A Output, 200kHz, RSENSE, Step-Down Converter 3876f 45 LTC3876 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701 Rev C) 0.70 p 0.05 5.50 p 0.05 5.15 ± 0.05 4.10 p 0.05 3.00 REF 3.15 ± 0.05 PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 5.5 REF 6.10 p 0.05 7.50 p 0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 p 0.10 0.75 p 0.05 PIN 1 NOTCH R = 0.30 TYP OR 0.35 s 45o CHAMFER 3.00 REF 37 0.00 – 0.05 38 0.40 p0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2 5.15 ± 0.10 7.00 p 0.10 5.50 REF 3.15 ± 0.10 (UH) QFN REF C 1107 0.200 REF 0.25 p 0.05 0.50 BSC R = 0.125 TYP R = 0.10 TYP BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3876f 46 LTC3876 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. FE Package 38-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1772 Rev C) Exposed Pad Variation AA 4.75 REF 38 9.60 – 9.80* (.378 – .386) 4.75 REF (.187) 20 6.60 ±0.10 2.74 REF 4.50 REF SEE NOTE 4 6.40 2.74 REF (.252) (.108) BSC 0.315 ±0.05 1.05 ±0.10 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.50 – 0.75 (.020 – .030) 0.09 – 0.20 (.0035 – .0079) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN MILLIMETERS (INCHES) 3. DRAWING NOT TO SCALE 1 0.25 REF 19 1.20 (.047) MAX 0s – 8s 0.50 (.0196) BSC 0.17 – 0.27 (.0067 – .0106) TYP 0.05 – 0.15 (.002 – .006) FE38 (AA) TSSOP REV C 0910 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3876f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 47 LTC3876 TYPICAL APPLICATION 4.5V to 5.5V Input, VDDQ 1.5V/20A and VTT 0.75V/±10A Output, 1.2MHz, RSENSE, Step-Down Converter VIN 4.5V TO 5.5V CIN1 180μF CIN2 10μF w3 2.2Ω LTC3876 1μF VIN 100Ω 1nF SENSE1– SENSE2– SENSE1+ SENSE2+ BOOST1 BOOST2 100Ω 1nF 100Ω 649Ω 100Ω 0.1μF R31 0.002Ω VDDQ 1.5V 20A L1 0.18μH 0.1μF TG1 MT1 COUT2 330μF w2 MT2 SW1 VTT 0.75A ±10A DRVCC2 EXTVCC VIN COUT4 330μF 4.7μF 1μF MB1 BG1 BG2 1Ω VDDQSNS 30.1k 1μF VOUTSENSE1+ 20k VOUTSENSE1– PGOOD 0.01μF PGOOD VTTRVCC VTTSNS 150pF 32.4k ITH1 DTR1 VRNG1 RT SGND RUN VTTR ±50mA 2.2μF VTTR TRACK/SS1 39pF COUT3 100μF MB2 PGND 68.1k R32 0.003Ω SW2 DRVCC1 INTVCC 100k L2 0.22μH DB2 2.2Ω COUT1 100μF TG2 DB1 120pF ITH2 270pF 33.2k CIN1: SANYO 16SVP180M CIN2: MURATA GRM32DR61E106KA12L COUT2, COUT4: SANYO 2R5TPE330M9 COUT1, COUT3: MURATA GRM31CR60J107ME39L DB1, DB2: CENTRAL SEMI CMDSH-3 L1: TOKO FCUL1040-H-R18M L2: TOKO FDUE0640-R22M MT1, MB1, MB2:INFINEON BSC0901NS MT2: INFINEON BSC050NE2LS CVCC VRNG2 PHASMD MODE/PLLIN CLKOUT 3876 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3776 Dual, 2-Phase, No RSENSE™, Synchronous Controller for 2.75V ≤ VIN ≤ 9.8V, VOUT Tracks One-Half VREF, 4mm × 4mm QFN-24, SSOP-24 DDR/QDR Memory Termination LTC3717 High Power DDR Memory Termination Regulator 4V ≤ VIN ≤ 36V, VOUT Tracks One-Half VIN or VREF LTC3718 Bus Termination Supply for Low Voltage VIN 1.5V ≤ VIN, Supplies 5V Gate Drive for N-Channel MOSFETs LTC3831 High Power DDR Memory Termination Regulator VOUT Tracks One-Half VIN or VREF, 3V ≤ VIN ≤ 8V LTC3413 3A Monolithic DDR Memory Termination Regulator 2.25V ≤ VIN ≤ 5.5V, TSSOP-16E LTC3833 Fast Controller On-Time, High Frequency Synchronous Step-Down Controller with Diff Amp Up to 2MHz Operating Frequency 4.5V < VIN < 38V, 0.6V < VOUT < 5.5V, 3mm × 4mm QFN-20, TSSOP-20E LTC3838 Dual, Fast, Accurate Step-Down DC/DC Controller with Differential Output Sensing Up to 2MHz Operating Frequency 4.5V < VIN < 38V, 0.6V < VOUT < 5.5V, 5mm × 7mm QFN-38, TSSOP-38E LTC3634 15V Dual 3A Monolithic DDR Memory Termination 3.6V ≤ VIN ≤ 15V, 4mm × 5mm QFN-28, TSSOP-28E LTC3617 6A Monolithic DDR Memory Termination 2.25V ≤ VIN ≤ 5.5V, 3mm × 5mm QFN-24 LTC3618 Dual 3A Monolithic DDR Memory Termination 2.25V ≤ VIN ≤ 5.5V, 4mm × 4mm QFN-24, TSSOP-24 3876f 48 Linear Technology Corporation LT 1111 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2011