Data Sheet

Freescale Semiconductor
Advance Information
Document Number: MC33909
Rev. 4.0, 7/2015
System Basis Chip with DC/DC and
Multiple Switch-to-Ground Interface
33909
This SMARTMOS IC integrates the common functionality of system basis chips
with switch detection inputs. The device works as an advanced power
management unit for the MCU and additional integrated circuits such as
sensors, CAN transceivers, and eXtreme switches. It has one built-in enhanced
high-speed CAN interface (ISO 11898-2 and -5), with local and bus failure
diagnostics, protection and fail-safe operation mode, and includes four LINs,
compatible with specification 2.1 and SAEJ2602-2.
SYSTEM BASIS CHIP
The IC starts operating when the VBATP (reverse battery protected) pin
reaches 5.3 V maximum. The device requires a reverse blocking ultrafast or
Schottky diode for operation. The VPRE supply operating in Buck/Boost mode
allows functional operation of the IC from 2.5 V to 35 V on VBATP. The VPRE
pin supplies the source voltage for the VDD, VAUX, CAN5V, and SG power
rails.
Switch-to-ground inputs are available for switch detection and supply
configurable pulsed wetting current, with low sustain current levels for
improved thermal and power management. The IC can be programmed to
wake-up when a change of state is detected on any input. The device also
implements an innovative and advanced fail-safe state machine and concept
solution.
AD SUFFIX (PB-FREE)
48 PIN LQFP-EP
98ASA00737D
Applications
• Front/rear body controllers
• Gateway modules
• Electric power steering
• Power train
Features
• VDD rail (3.3 V or 5.0 V) operates down to 2.5 V on VBATP (provided by
VPRE Buck/Boost)
• VAUX rail (3.3 V or 5.0 V) capable of surviving short-to-battery (40 V)
conditions
• Low Q current operation for low-power sleep mode, typ. 125 A
• Secured SPI and advanced watchdog
• SAFE_B pin for limp home mode
• Six switch to GND inputs with selectable wake-up in change of state
• Analog multiplexer
VSW
VBAT
PI Filter
VPRE VAUXE VAUXB VAUX
VPREGATE
BOOT
VDDE
VBAT_SMPS
VDDB
VDD
VBATP
VDD
VBAT
VBATSNS
WDI
SAFE_B
AMUX
RST_B
SG0
SG1
SG2
SG3
MOSI
MISO
SCLK
CS_B
SG4
SG5
CANH
CAN Bus
CANL
RXD_L0:RXD_L3
TXD_L0:TXD_L3
RXD_C
TXD_C
VBATP
LIN Bus
LIN_0
LIN Bus
LIN_1
LIN Bus
LIN_2
LIN Bus
LIN_3
GND LIN
MCU
INT_B
CAN5V
GND
CANGND
Figure 1. 33909AD Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2013 - 2015. All rights reserved.
SPI
Orderable Parts
1
Orderable Parts
This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are provided
on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search
for the following device numbers.
Table 1. Orderable Part Variations
Part Number
Temperature
(TA)
Package
VDD Output
Voltage
CAN
Interface(s)
MC33909N5AD
Switch to GND
Inputs
Notes
6
(1)
0
MC33909L5AD
1
5.0 V
MC33909D5AD
MC33909Q5AD
MC33909N3AD
LIN Interface(s)
-40 °C to 125 °C
7.0 x 7.0,
48 LQFP
exposed pad
1
MC33909L3AD
MC33909D3AD
MC33909Q3AD
2
3.3 V
4
0
1
2
4
Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
Internal Block Diagram
2
Internal Block Diagram
BOOT VSW VPRE VPREGATE
Power Supply
VBATP_SMPS
VPRE Regulator
POR
Sleep State
VDD Regulator
Internal rails
Bandgap
VBATP
VBATSNS
250 mV accuracy
VAUX
Regulator
Digital Control
Logic
Fail-safe
Power Management
State Machine
Inputs
VPRE
VPRE
6-20
mA
VPRE
2.0
mA
SG0
SG1
VDD
VAUXE
VAUXB
VAUX
SAFE_B
RESET_B
WDI
SG0
CANH
1.0
mA
(Low-power
mode)
3.5 V REF
comparator
VDDE
VDDB
Enhanced High
Speed CAN
Physical
Interface
To SPI
CANL
TXD_C
RXD_C
SG2
VPRE
SG3
SG4
6-20
mA
VPRE
VPRE
2.0
mA
SG5
3.5 V REF
comparator
5V CAN
Regulator
SG5
1.0
mA
(Low-power
mode)
Internal
2.5 V
To SPI
Temperature
Monitor and
Control
Internal
2.5 V
VPRE
Oscillator and
Clock Control
CANGND
CAN5V
TXD_Lx
LIN
Interface
RXD_Lx
LINx
Internal
2.5 V
VBATP
VDD
40 µA
25
SPI Interface
and Control
MUX VDD
control
GND LIN
GND1/2
Internal
2.5 V
VDD
+
-
VDD
125 k
Interrupt
Control
CS_B
SCLK
MOSI
MISO
AMUX
INT_B
Figure 2. 33909AD Simplified Internal Block Diagram
MC33909
3
Analog Integrated Circuit Device Data
Freescale Semiconductor
Internal Block Diagram
SG1
SG0
VBATSNS
VBATP
VBAT_SMPS
BOOT
VSW
GND
VPRGATE
VDD
VDDB
VDDE
47
46
45
44
43
42
41
40
39
38
37
Transparent Top View
48
Pin Connections
SG2
1
36
VAUXE
SG3
2
35
VPRE
SG4
3
34
VAUXB
LIN0
4
33
VAUX
LIN1
5
32
RXD_C
GNDLIN
6
31
TXD_C
LIN3
7
30
CANH
LIN2
8
29
CANL
SG5
9
28
GNDCAN
AMUX
10
27
CAN5V
RST_B
11
26
SAFE_B
TXD_L0
12
25
MISO
13
14
15
16
17
18
19
20
21
22
23
24
WDI
INT_B
TXD_L1
RXD_L1
RXD_L2
TXD_L2
TXD_L3
RXD_L3
MOSI
SCLK
CS_B
EP
RXD_L0
2.1
Figure 3. 33909AD Pin Connections
A functional description of each pin can be found in the Functional Device Operation section.
Table 2. 33909 Pin Definitions
Pin Number
Pin Name
Pin Function
Definition
–
EP
Ground
1-3, 9, 47, 48
SG0 - SG5
Input
4
LIN0
Input/Output
LIN0 bus input/output connected to the LIN bus
5
LIN1
Input/Output
LIN1 bus input/output connected to the LIN bus
6
GND LIN
Ground
7
LIN3
Input/Output
LIN3 bus input/output connected to the LIN bus
8
LIN2
Input/Output
LIN2 bus input/output connected to the LIN bus
11
RST_B
Input/Output
This is the device reset output whose main function is to reset the MCU. This pin has an internal pull-up
to VDD. RESET_B input voltage is also monitored in order to detect external reset and safe conditions.
10
AMUX
Output
12
TXD_L0
Input
Exposed pad – connect to the ground plane
Switch to Ground inputs
Ground for LIN 0 - 3 bus
Analog multiplex output
LIN0 bus transmit data input. Includes an internal pull-up resistor to VDD
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
Internal Block Diagram
Table 2. 33909 Pin Definitions (continued)
Pin Number
Pin Name
Pin Function
Definition
13
RXD_L0
Output
14
WDI
Input
15
INT_B
Output
16
TXD_L1
Input
17
RXD_L1
Output
LIN1 bus receive data output
18
RXD_L2
Output
LIN2 bus receive data output
19
TXD_L2
Input
LIN2 bus transmit data input. Includes an internal pull-up resistor to VDD
20
TXD_L3
Input
LIN3 bus transmit data input. Includes an internal pull-up resistor to VDD
21
RXD_L3
Output
22
MOSI
Input / SPI
SPI control data input pin from the MCU
23
SCLK
Input / SPI
SPI control clock input pin
24
CS_B
Input / SPI
SPI control chip select bar input pin. Logic [0] allows data to be transferred in.
25
MISO
Output / SPI
26
SAFE_B
Output
Output of the safe circuitry. The pin is asserted LOW in case a safe condition is detected (e.g.: software
watchdog is not triggered, VDD low, issue on reset pin, etc.). Open drain structure.
27
CAN5V
Output
Output voltage for the embedded CAN interface. A capacitor must be connected to this pin.
28
GNDCAN
Ground
Power ground for the embedded CAN interface
29
CANL
Output
CAN low output
30
CANH
Output
CAN high output
31
TXD_C
Input
32
RXD_C
Output
33
VAUX
Input
34
VAUXB
Output
Base connection for the external PNP transistor
35
VPRE
Input
Supply for VDD, VAUX, CAN5V, and SG Inputs
36
VAUXE
Input
Collector connection for the external PNP transistor
37
VDDE
Input
Emitter connection for the external LDO
38
VDDB
Output
39
VDD
Input
40
VPREGATE
Output
Gate control for low-side FET
41
GND
Ground
Ground for logic and analog (GND1 and GND2)
42
VSW
Output
Switching output
43
BOOT
Input
44
VBATP_SMPS
Power
Supply for SMPS power rail. This pin requires external reverse battery protection.
45
VBATP
Power
Battery supply input pin. This pin requires external reverse battery protection. Supplies internal voltage
except SMPS.
46
VBATSNS
Input
LIN0 bus receive data output
Watchdog inhibit
Open drain output to the MCU is used to indicate an input switch change of state.
LIN1 bus transmit data input. Includes an internal pull-up resistor to VDD
LIN3 bus receive data output
Provides digital data from 33909 to the MCU
CAN bus transmit data input. Internal pull-up to VDD
CAN bus receive data output
Output pin for the auxiliary voltage
Base connection for the external LDO
VDD supply voltage
Boot capacitor to VSW
Battery sense input. A 1.0 k external resistor required to pass battery transients.
MC33909
5
Analog Integrated Circuit Device Data
Freescale Semiconductor
Electrical Characteristics
3
Electrical Characteristics
3.1
Maximum Ratings
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Ratings
Value
Unit
-0.3 to 40
V
DC Voltage at Battery Sense Pin
-14.0 to 41
V
DC Voltage at INT_B, RST_B, MISO, MOSI, CS_B, SCLK, AMUX
-0.3 to 7.0
V
DC Voltage at SAFE_B Pin
-0.3 to 40
V
VWDI
DC Voltage at WDI Pin
-0.3 to 18
V
VSG
DC Voltage at SG0, 1, 2, 3, 4, 5
-14 to 40
V
VCAN_5V
DC Voltage on CAN_5V pin
-0.3 to 7.0
V
VBUS_CAN
DC Voltage on CANL, CANH
-32 to 40
V
VBUS_DIG
DC Voltage on TXD_C, RXD_C, TXD_Lx, RXD_Lx
-0.3 to VDD +0.3
V
VBUS_LIN
DC Voltage on LINx
-27 to 40
V
DC Voltage at VPRE Pin
-0.3 to8.0
V
DC Voltage at VPRE_GATE Pin
-0.3 to 8.0
V
VSW
DC Voltage at VSW Pin
-0.3 to 40
V
VBOOT
DC Voltage at BOOT Pin
-0.3 to 45
V
DC Voltage at VDD Pin
-0.3 to 7.0
V
DC Voltage at VDDE, VDDB Pin
-0.3 to 8.0
V
DC Voltage at VAUX Pin
-2.0 to 40
V
VAUX_E,B
DC Voltage at VAUXE, VAUXB Pin
-0.3 to 40
V
IBUS_CAN
Continuous Current Capability of CANL, CANH
200
mA
Notes
ELECTRICAL RATINGS
VBATP/VBATP_SMPS DC Voltage at Power Supply Pins
VBATSNS
VDIG
VSAFE_B
VPRE
VPRE_GATE
VDD
VDD_E,B
VAUX
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
Electrical Characteristics
Table 3. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Ratings
Value
Unit
Notes
V
(2)
V
(3)
V
(3)
V
(3)
V
(3)
ESD RATINGS
VESD1-1
VESD1-2
VESD1-3
VESD1-4
VESD2-1
VESD2-2
AEC Q100
• LINx pins versus GND
• VBAT_SMPS, VBATSNS pins versus GND
• VBATP pin versus GND
• all other pins
Charge Device Model
• Corner pins (pins 1, 12, 24, 25, 36, 37, and 48)
• All other pins (pins 2-11, 14-23, 26-35, 38-47)
±8000
±4000
3000
2000
750
500
Contact Discharge, Unpowered
• LIN0, LIN1, LIN2, and LIN3 pin with 220 pF
• LIN0, LIN1, LIN2, and LIN3 pin without capacitor
• CANH and CANL
• SGx - pins with 47-100 nF capacitor
• VBATP, VBAT_SMPS, VBATSNS
6000
6000
6000
6000
6000
Unpowered
• LIN0, LIN1, LIN2, and LIN3 pin with 220 pF and without capacitor
• CANH, CANL pin without capacitor
• VBATP (100 nF to GND)
• VBATSNS (1.0 k series resistance)
15000
15000
8000
8000
VESD6-1
VESD6-2
SGx pins with 47 nF to 100 nF capacitor
• Air discharge - unpowered and powered
• Contact discharge - unpowered and powered
15000
8000
VESD7-1
Contact Discharge, Unpowered, GND connected to ESD gun GND
• CANH, CANL without capacitor
7000
VESD4-1
VESD4-2
VESD4-3
VESD4-4
VESD4-5
VESD5-1
VESD5-2
VESD5-3
VESD5-4
THERMAL RATINGS
TA
Ambient Temperature
-40 to 125
°C
TJ
Junction Temperature
-40 to 150
°C
TSTORE
Storage Temperature
-55 to 150
°C
Notes
2. ESD testing is performed in accordance with the Human Body Model (HBM) JESD22/A114 (CZAP = 100 pF, RZAP = 1500 ) and the Charge
Device Model (CDM), Robotic (CZAP = 4.0 pF).
3.
According to Hardware requirements for LIN, CAN, and Flexray Interfaces in Automotive Applications, Revision 1.0, 2008-12-10 (IEC 61000-4-2:
CZAP = 150 pF, RZAP = 330 .
MC33909
7
Analog Integrated Circuit Device Data
Freescale Semiconductor
Electrical Characteristics
Table 4. Table of Thermal Resistance Data
Symbol
Ratings
Value
Unit
Notes
RJA
Junction to Ambient, Natural Convection, Single Layer board (1s)
72
°C/W
(4),(5)
RJA
Junction to Ambient, Natural Convection, Four layer board (2s2p)
31
°C/W
(4),(5)
RJCTOP
Junction to Case Top
23
°C/W
(6)
RJCBOTTOM
Junction to Case Bottom
1.2
°C/W
(7)
Notes
4. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
5. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board,
respectively.
6. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
7. Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any interface resistance.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
Electrical Characteristics
3.2
Static Electrical Characteristics
Table 5. Static Electrical Characteristics
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V DC to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
Full DC voltage Range
Typical DC Operating Range
2.5
7.0
–
–
35
27
V
VBATUV
VBATP Undervoltage
• VBAT Power Down Range, POR occurs
2.3
–
2.5
V
VS_HIGH
VBATP Overvoltage Detector Thresholds, at VBATP Pin
• Not active in Low-power modes
35
–
40
V
Total Supply Current, in Normal Mode, CAN in Recessive Mode, SGx
is open switch, 5.0 V CAN and VAUX ON, LINx in Recessive Mode
–
7.0
14
mA
ILPM_OFF
Low-power Mode VDD Off. Wake-up from CAN, SGx inputs at
TSCAN = 64 ms, LIN
• VBATP = 18 V and 8.0 V
–
100
190
A
ILPM_ON
Low-power Mode VDDON (5.0 V) with VDD Undervoltage and VDD
Overcurrent Monitoring, Wake-up from CAN, SGx Inputs at 
TSCAN = 64 m and LIN
• VBATP = 18 V and 8.0 V
–
125
200
A
Low-power Mode VDD OFF (no wake-up)
• VBATP = 18 V and 8.0 V
–
90
170
A
Minimum Start Up Voltage
• VBAT Power Up Range, VDD is not Operating (VBATP <
VBAT_MIN_SU)
4.5
5.0
5.3
V
VBATPTHD
Buck to Boost Mode Threshold Voltage
6.2
6.6
7.0
V
VBATPTHU
Boost to Buck Mode Threshold Voltage
6.8
7.25
7.8
V
Peak Input Current Limit
3.5
4.0
–
A
(8)
POWER INPUT
VBATP
IVBATP
IOSC
VPRE BUCK BOOST CONVERTER
VBAT_MIN_SU
IPRE_LIM
ILOAD
Transient Load Current Change
–
–
500
mA
(8)
IPRE/DT
VPRE Load regulation Variation
–
–
25
A/ms
(8)
Switching Frequency
418
440
462
kHz
(8),(9)
Continuous Output Load Current
• Buck mode
• Boost mode (VBATP = 2.5 V)
3.0
–
–
–
–
0.5
A
(8)
Current Limit Blanking Time
200
–
600
ns
Continuous Output Load Current During Low-power Mode
25
40
–
mA
fSW
ILOAD_BUCK
ILOAD_BOOST
tILIM_BT
ILPM_LOAD
Notes
8. Guaranteed by design.
9. Fixed frequency.
MC33909
9
Analog Integrated Circuit Device Data
Freescale Semiconductor
Electrical Characteristics
Table 5. Static Electrical Characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V DC to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
VPRE Overvoltage
7.2
–
8.0
V
VPRE Overvoltage Hysteresis
0.05
–
0.2
V
VPRE Undervoltage
5.5
–
6.0
V
VPRE Undervoltage Hysteresis
0.05
–
0.2
V
Notes
VPRE BUCK BOOST CONVERTER
VPREOV
VPREOVHYST
VPREUV
VPREUVHYST
VSUP_IPFF
IPFF: Input Voltage Detection
19
–
24
V
VSUP_IPFF_HYST
IPFF: Input Voltage Hysteresis
0.2
–
–
V
t_VSUP_IPFF
IPFF: Input Voltage Filter Time
1.0
–
4.0
s
IPRE_IPFF_PK
IPFF: HS Peak Current Detection
2.2
–
–
A
t_IPRE_IPFF
IPFF: HS Peak Current Filter Time
100
–
300
ns
TPRE_TWARN
VPRE Thermal Warning Threshold
–
125
–
C
(10)
TPRE_TSD
VPRE Thermal Shutdown Threshold
160
–
–
C
(10)
TPRE_TSD_HYS
VPRE Thermal Shutdown Hysteresis
10
–
–
C
(10)
CVPRE
VPRE External Capacitor
–
47
–
F
(10)
RVPRE
VPRE External Capacitor ESR
–
–
100
m
(10)
6.3
6.5
6.7
V
–
–
300
m
Output Voltage VPRE in Boost Mode
• VBATP = 2.5 V to VBATP (THD or THU), IVPRE = -550 mA
6.0
6.3
7.0
V
VPREGATE Output Voltage, Power MOSFET ON
3.5
4.0
VPRE
V
–
350
–
mA
(10)
200
350
500
mA
(10)
BUCK CONVERTER
VPREBUCK
RDS(on)
Output Voltage VPRE
• VBATP = VBATP(THD or THU) to 36 V
VSW Drain-source On-resistance
• ID = 500 mA, VBATP = 9.0 V
BOOST CONVERTER
VPREBST
VG
ISOURCE
ISINK
VPREGATE Source Continuous Current
VPREGATE Sink Continuous Current
Notes
10. Guaranteed by design.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
Electrical Characteristics
Table 5. Static Electrical Characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V DC to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
VOUT5
Output voltage (5.0 V device)
• VBATP = 2.5 V to 35 V, IOUT = 0 mA to 500 mA, Normal mode
4.9
5.0
5.1
V
VOUT3
Output voltage (3.3 V device)
• VBATP = 2.5 V to 35 V, IOUT = 0 mA to 500 mA, Normal mode
3.23
3.3
3.367
V
ISCVDD
VDD Short-circuit Current
• VDD = 1.65 V, VSCFDIFF = VPRE-VDDE
-90
–
-60
mA
IVDD_FBILIM
VDD Foldback Current Limit
• VDD = 0.5 V, VSCFDIFF = VPRE-VDDE
-60
–
-30
mA
VDD_FB
VDD Foldback Current Limit Threshold (VDD voltage when foldback
current kicks in)
0.5
1.075
1.65
V
IVDDBC
VDD Base Current Capability
25
–
–
mA
PSRR (Power supply rejection ratio)
• f = 350 kHz to 500 kHz
40
–
–
dB
(11)
Range of Decoupling Capacitor
4.7
–
100
F
(11)
External capacitor ESR
10
–
100
m
(11)
VDDLP5
Low-power Mode VDDON, output voltage (5.0 V device)
• IOUT  40 mA (time limited), VBATP  8.5 V
• IOUT  20 mA (time limited), VBATP  5.5 V
4.7
5.0
5.25
V
VDDLP3
Low-power Mode VDDON, output voltage (3.3 V device)
• IOUT  40 mA (time limited), VBATP  8.5 V
• IOUT  20 mA (time limited), VBATP  5.5 V
3.135
3.3
3.465
V
ILP-ITH
Low-power Wake-up Current Threshold, VBATP  6.0 V
2.0
5.0
9.0
mA
VDD VOLTAGE REGULATOR, VDD PIN
PSRRVDD
CEXT
R3CAPESR
VOLTAGE REGULATOR FOR CAN INTERFACE SUPPLY, CAN5V PIN
5VCANOUT
Output Voltage
• IOUT = 0 mA to 200 mA, VBATP = 5.5 V to 40 V
4.75
5.0
5.25
V
5VCANILIM
Output Current Limitation
200
–
–
mA
5VCANUV
Undervoltage Threshold Falling
4.0
–
4.7
V
5VCANUV
Undervoltage Threshold Rising
4.0
–
4.75
V
5VCANUV
Undervoltage Hysteresis
0.05
0.1
0.3
V
5VCANTS
Thermal Shutdown
160
–
–
°C
(11)
CEXT-CAN
External Capacitance
1.0
–
100
F
(11)
Notes
11. Guaranteed by design.
MC33909
11
Analog Integrated Circuit Device Data
Freescale Semiconductor
Electrical Characteristics
Table 5. Static Electrical Characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V DC to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
V AUXILIARY OUTPUT, 5.0 V AND 3.3 V SELECTABLE VB-AUX, VAUX PIN
VAUX5
VAUX Output Voltage 5.0 V
• IOUT = 0 mA to 200 mA
4.85
5.0
5.15
V
VAUX3
VAUX Output Voltage 3.3 V
• IOUT = 0 mA to 200 mA
3.2
3.3
3.4
V
VAUX-UVTH5
VAUX Undervoltage Detector 5.0 V
4.2
4.5
4.75
V
VAUX-UVTH3
VAUX Undervoltage Detector 3.3 V
2.75
3.0
3.1
V
VAUX-OVTH
VAUX-SBDL
VAUX Overvoltage
• VAUX Short to Battery Detection Level
5.6
6.0
7.0
V
VDD-15 mV
VDD
VDD+15 mv
V
VAUX Current Limit
• VAUX = 1.65 V
200
–
360
mA
VAUX Fold-back Current Limit
• VAUX < VAUX-FB
120
–
230
mA
VAUXE Fold-back Current Limit Threshold - VAUX level at which Foldback Current Kicks In
0.5
1.075
1.65
V
IAUX-SBLK
VAUX Short to Battery Leakage
0.0
–
15
µA
IVAUXBC
VAUX Base Current Capability
10
–
–
mA
External Capacitance
2.2
–
100
F
(12)
External Capacitor ESR - Includes PCB Impedance
10
–
100
m
(12)
VAUX_TRACK
IAUX-ILIM
IAUX-FBILIM
VAUX-FB
C3CAP
R3CAPESR
VAUX Tracking Supply
• VDD = 5.0 V only, IAUX = 100 mA
UNDERVOLTAGE RESET AND RESET FUNCTION, RST_B PIN
VST-TH5H
VDD Undervoltage Threshold 5H, 5.0 V device (falling)
4.25
4.5
4.75
V
VST-TH5L
VDD Undervoltage Reset Threshold 5L,5.0 V device (falling)
2.75
3.3
3.4
V
VST-TH3L
VDD Undervoltage Threshold 3L, 3.3 V device (falling)
1.85
–
2.05
V
VST-TH3H
VDD Undervoltage 3H 3.3 V device (falling)
2.75
–
3.15
V
VST-HYST
VDD Undervoltage Hysteresis, 5.0 V device
50
100
500
mV
VST-TH3L
VDD Undervoltage Hysteresis, 3.3 V device
40
100
500
mV
VSVDD-OV
VDD Overvoltage
5.5
–
6.0
V
–
–
500
mV
RST_B Sink Current - VRESET Driven Low (25 °C Only)
5.0
7.0
25
mA
Pull-up Resistor (to VDD pin)
10
20
–
k
VST-VTH
RST_B input Threshold
–
0.4
–
V
VRST-HYST
RST_B Input Hysteresis
450
–
950
mV
VOL
ISINKRESET
RPULL-UP
RST_B VOL at 1.5 mA, VBATP = 2.5 V to 35 V
Notes
12. Guaranteed by design.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
Electrical Characteristics
Table 5. Static Electrical Characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V DC to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
VBATSNS Resistor Divider (VBATP = 27 V)
• 5.0 V device, Divider 1/5.94
• 3.3 V device, Divider 1/8.9
–
–
–
–
5.0
5.0
%
Input Resistor to GND. In all modes except in Low-power modes
50
–
–
k
External Capacitor at AMUX Output
–
–
1.0
nF
(13)
Chip Temperature Sensor Coefficient
–
4.0
–
mV/°C
(13)
-10
–
10
mV
VBATSNS INPUT
VACC5
VACC3
RVBATSNS
ANALOG MUX OUTPUT
CMUX
TEMP-COEFF
VOFFSET
Input Offset Voltage when Selected as Analog
VOL
Analog Operational Amplifier Output Voltage
• Sink 250 µA
–
–
50
mV
VOH
Analog Operational Amplifier Output Voltage
• Source 250 µA
VDD -0.1
–
VDD +0.1
V
Temperature monitor
155
–
185
°C
(13)
Temperature Monitor Hysteresis
5.0
–
15
°C
(13)
TEMPERATURE LIMIT
TLIM
TLIM(HYS)
WDI INPUT
RWDIA
SAFE_B Mode A
• External Resistor to GND on WDI pin
–
–
2.5
k
RWDIB1
SAFE_B Mode B1
• External Resistor to GND on WDI pin
7.0
–
14
k
RWDIB2
SAFE_B Mode B2
• External Resistor to GND on WDI pin
29
–
40
k
RWDIB3
SAFE_B Mode B3
• External Resistor to GND on WDI pin
80
–
–
k
VWDIT
Watchdog Inhibit for Debug
• For Watchdog inhibit mode
8.0
–
–
V
SAFE_B Sink Current
• SAFE_B driven low (25 °C only)
2.5
–
–
SAFE_B Low Level
• I = 500 A
0.0
–
1.0
SAFE_B Leakage Current (VDDLOW, or device unpowered)
• VSAFE_B = 35 V
-1.0
0.0
1.0
SAFE OUTPUT
ISINKSAFE_B
VOLSAFE
ISAFE_B-IN
mA
V
A
Notes
13. Guaranteed by design.
MC33909
13
Analog Integrated Circuit Device Data
Freescale Semiconductor
Electrical Characteristics
Table 5. Static Electrical Characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V DC to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
–
0.2
1.0
V
VDD -0.5
–
VDD +0.1
V
Pull-up Resistor
10
20
25
k
Sink Current - VINT > 5.0 V, INT Driven Low (25 °C only)
2.5
7.5
25
mA
0.7 x VDD
–
Notes
INTERRUPT
VOLINT
Output Low Voltage - IOUT = 1.5 mA
VOHINT
INT_B Voltage High - INT_B = Open circuit
RPU
ISINKINT
CAN LOGIC INPUT PINS (TXD)
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
RPUCAN
Pull-up resistor - VIN = 0 V
V
–
0.3 x VDD
V
22
33
66
k
CAN DATA OUTPUT PINS (RXD)
VOUTLOW
Low Level Output Voltage - IRXD = 5.0 mA
0.0
–
0.3 x VDD
V
VOUTHIGH
High Level Output Voltage - IRXD = -3.0 mA
0.7 x VDD
–
VDD
V
IOUTHIGH
High Level Output Current - VRXD = VIO - 0.4 V
-6.0
-3.0
-1.0
mA
IOUTLOW
Low Level Output Current - VRXD = 0.4 V
2.0
5.0
12
mA
Bus Pins Common Mode Voltage for Full Functionality
(voltage range for CAN test)
-15
–
20
V
Differential Input Voltage Threshold
500
–
900
mV
Differential Input Hysteresis
100
–
-
mV
Input Resistance
5.0
–
50
k
Differential Input Resistance
10
–
100
k
Input Resistance Matching
-3.0
0.0
3.0
%
VCANH
CANH Output Voltage (45  < RBUS < 65 )
• TX dominant state
• TX recessive state
2.75
2.0
3.5
2.5
4.5
3.0
V
VCANL
CANL Output Voltage (45  < RBUS < 65 )
• TX dominant state
• TX recessive state
0.5
2.0
1.5
2.5
2.25
3.0
V
VOH-VOL
Differential Output Voltage (45  < RBUS < 65 )
• TX dominant state
• TX recessive state
1.5
-0.5
2.0
0.0
3.0
0.05
V
ICANH
CANH Output Current Capability - Dominant state
–
–
-35
mA
ICANL
CANL Output Current Capability - Dominant state
35
–
–
mA
CAN OUTPUT PINS (CANH, CANL) - RBUS = 60 For Product test
VCOM
VCANH-VCANL
VDIFF-HYST
RIN
RIN-DIFF
RIN-MATCH
ICANL-OC
CANL Overcurrent Detection - Error reported in register
-100
-85
-70
mA
ICANH-OC
CANH Overcurrent Detection - Error reported in register
70
85
100
mA
RINSLEEP
CANH, CANL Input Resistance Device Supplied and in CAN Sleep
Mode, V_CANH, V_CANL from 0 V to 5.0 V
5.0
–
50
k
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
Electrical Characteristics
Table 5. Static Electrical Characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V DC to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
-0.1
0.0
0.1
V
–
–
5.0
–
250
–
–
250
–
µA
-200
250
900
mV
4.7
5.1
5.7
V
Operating Voltage Range (voltage range for LIN testing)
8.0
–
18
V
Supply Voltage Range (voltage range for LIN testing)
7.0
–
18
V
Voltage Range within which the Device is Not Destroyed
-0.3
–
40
V
Current Limitation for Driver Dominant State Driver ON, VBUS = 18 V
40
90
200
mA
IBUS_PAS_DOM
Input Leakage Current at the Receiver Driver OFF; VBUS = 0 V; 
VBATP = 12 V
-1.0
–
–
mA
IBUS_PAS_REC
Leakage Output Current to GND Driver OFF; 7.0 V < VBATP < 17 V;
8.0 V < VBUS < 18 V
–
–
20
A
IBUS_NO_GND
Control Unit Disconnected from GND (Loss of local ground must not
affect communication in the residual network) 
GNDDEVICE = VBATP, VBATP = 12 V, 0 < VBUS < 18 V
-1.0
–
1.0
mA
IBUSNO_BAT
VBATP Disconnected, VBATP_DEVICE = GND, 0 < VBUS < 18 V (Node
has to sustain the current which can flow under this condition. Bus
must remain operational under this condition)
–
–
100
A
VBUSDOM
Receiver Dominant State
–
–
0.4
VBATP
VBUSREC
Receiver Recessive State
0.6
–
–
VBATP
VBUS_CNT
Receiver Threshold Center (VTH_DOM + VTH_REC)/2
0.475
0.5
0.525
VBATP
VHYS
Receiver Threshold Hysteresis (VTH_REC - VTH_DOM)
–
–
0.175
VBATP
Notes
CAN OUTPUT PINS (CANH, CANL) - RBUS = 60 For Product test (Continued)
VCANLP
ICAN
ILEAKGND
CANL, CANH Output Voltage in Sleep and Standby Modes 
(45  < RBUS < 65 )
CANH, CANL Input Current, Device Unsupplied, VBATP connected to
GND
• VCANH, VCANL = 5.0 V
• VCANH, VCANL = -2.0 V to + 7.0 V
Loss of Ground Leakage Current (GB CZ)
• VBATP = 12 V
A
(14)
CANH AND CANL DIAGNOSTIC INFORMATION
VLG
VHG
GND Detection Threshold
• CANL
• CANH
VLVB
VHVB
VBATP Detection Threshold
• CANL
• CANH
LIN 0-3 PIN (PARAMETERS GUARANTEED FOR 7.0 V < VBATP < 17 V)
VBATTERY
VBATP
VBATP_NON_OP
IBUS_LIM
(14)
Notes
14. Guaranteed by CZ. Parameter not tested in production.
MC33909
15
Analog Integrated Circuit Device Data
Freescale Semiconductor
Electrical Characteristics
Table 5. Static Electrical Characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V DC to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
LIN 0-3 PIN (PARAMETERS GUARANTEED FOR 7.0 V < VBATP < 17 V) (Continued)
VSERDIODE
Voltage Drop at the Serial Diode in Pull-up Path - High Z State at LINx
0.4
–
1.0
V
VSHIFT_BAT
VBATP_SHIFT (GBD)
0.0
–
11.5%
VBATP
(15)
VSHIFT_GND
GND_SHIFT (GBD)
0.0
–
11.5%
VBATP
(15)
VBUSWU
LIN Wake-up Threshold from Stop or Sleep Mode
3.2
3.5
3.8
V
RSLAVE
LIN Pull-up Resistor to VBATP
20
30
60
k
LIN Undervoltage Threshold (rising and falling) (J2602)
5.9
6.2
6.85
V
–
100
–
mV
150
160
180
°C
(15)
–
10
–
°C
(15)
–
–
0.9
V
VUVR, VUVF
VUVHSY
LIN Undervoltage Hysteresis (VUVR – VUVF) (J2602)
TLINSD
Overtemperature Shutdown
TLINSD_HYS
Overtemperature Shutdown Hysteresis
LIN RXD OUTPUT PINS
VOL_RXDL
Low Level Output Voltage - IIN  1.5 mA
VOH_RXDL5
High Level Output Voltage (VDD = 5.0 V) - IOUT  250 μA
4.25
–
5.25
V
VOH_RXDL3
High Level Output Voltage (VDD = 3.3 V) - IOUT  250 μA
3.0
–
3.5
V
LIN TXD INPUT PINS
VIL_TXDL
Low Level Input Voltage
–
–
0.3 x VDD
V
VIH_TXDL
High Level Input Voltage
0.7 x VDD
–
–
V
VINHYSTL
Input Threshold Voltage Hysteresis
450
–
950
mV
RPULLIN
Pull-up Resistor - VIN = 0.0 V
22
33
66
k
ILEAKSG_GND
Leakage (SGx pins) to GND
• Inputs tristated, analog mux selected for each input, voltage at
SGx = GND
–
–
2.0
ILEAKSG_BAT
Leakage (SGx pins) to Battery
• Inputs tristated, analog mux selected for each input, voltage at
SGx = VBATP
–
–
2.0
ILEAKSG_WE
Leakage (SGx pins) Voltage at SGx = 36 V, VBATP and VPRE = 0 V
–
–
2.0
µA
SWITCH INPUT
µA
µA
IWET1
Pulse Wetting Current 1 - Mode 1 IPULSE1 = 6.0 mA
5.4
–
6.6
mA
IWET2
Pulse Wetting Current 2 - Mode 2 IPULSE2 = 8.0 mA
7.2
–
8.8
mA
IWET3
Pulse Wetting Current 3 - Mode 3 IPULSE1 = 10 mA
9.0
–
11
mA
Notes
15. Guaranteed by design.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
Electrical Characteristics
Table 5. Static Electrical Characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V DC to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
SWITCH INPUT (Continued)
IWET4
Pulse Wetting Current 4 - Mode 4 IPULSE2 = 12 mA
10.8
–
13.2
mA
IWET5
Pulse Wetting Current 5 - Mode 5 IPULSE3 = 14 mA
12.6
–
15.4
mA
IWET6
Pulse Wetting Current 6 - Mode 6 IPULSE4 = 16 mA
14.4
–
17.6
mA
IWET7
Pulse Wetting Current 7 - Mode 7 IPULSE5 = 20 mA
18
–
22
mA
1.60
–
2.40
mA
-10
–
10
%
IWET(MAX) – IWET(MIN) X 100
IWET(AVG)
-5.0
–
5.0
%
Switch Detection Threshold - Normal mode
3.20
–
3.8
V
Low-power Polling Current
0.850
1.1
1.35
mA
100
210
350
mV
ISUSTAIN
Sustain Current
Matching Between SG Channels (2.0 mA)
ISUS(MAX) – ISUS(MIN) X 100
ISUS(AVG)
IMATCH(SUS)
Matching Between SG Channels (6, 8, 10, 12, 14, 16, and 20 mA)
IMATCH(WET)
VICTHR
ISUSTAINLP
VLPICTHR
Low-power Switch Detection Threshold
DIGITAL INTERFACE
VIH
Input Logic High Voltage Thresholds (MISO, MOSI, SCLK, CS_B)
0.7 X VDD
–
–
V
VIL
Input Logic Low Voltage Thresholds (MISO, MOSI, SCLK, CS_B)
–
–
0.2 X VDD
V
IHZ
Tri-state Leakage Current (MISO) - VDD = 0.0 V to VDD
-2.0
–
2.0
µA
ISCLK, IMOSI
SCLK/MOSI Input Current - SCLK/MOSI = 0.0 V
-3.0
–
3.0
µA
ISCLK, IMOSI
SCLK/MOSI Pull-down Current - SCLK/MOSI = VDD
-5.0
–
-15
µA
ICS_B
CS_B Input Current - CS = VDD
-10
–
10
µA
ICS_B
CS_B Pull-up Current- CS = 0.0 V
30
–
100
µA
VDD – 0.8
–
VDD + 0.3
V
VSO(HIGH)
MISO High-side Output Voltage - ISO(HIGH) = -200 µA
VSO(LOW)
MISO Low-side Output Voltage - ISO(LOW) = 1.6 mA
–
–
0.40
V
CIN
Input Capacitance on SCLK, MOSI, Tri-state MISO
–
–
20
pF
(16)
Notes
16. Guaranteed by characterization in the development phase, parameter not tested.
MC33909
17
Analog Integrated Circuit Device Data
Freescale Semiconductor
Electrical Characteristics
3.3
Dynamic Electrical Characteristics
Table 6. Dynamic Electrical Characteristics
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
Pulse Wetting Current Timer - Normal Mode
18
–
22
ms
(17)
Interrupt Delay Time - Normal Mode
–
–
16
µs
(17)
Scan Timer Accuracy - Low-power Mode
–
–
20
%
(17)
Interrupt Timer Accuracy - Low-power Mode
–
–
20
%
(17)
Tscan Timer (time actual polling takes place) - Low-power Mode
44
55
66
µs
(17)
Glitch Filter Timer - Normal Mode
–
–
9.1
µs
(18)
–
–
6.25
MHz
(18)
SWITCH INPUT
tPULSE(ON)
tINT-DLY
tSCAN TIMER
tINT TIMER
tTSCAN TIME
tGLITCH TIMER
DIGITAL INTERFACE TIMING
fOP
Transfer Frequency
tSCK
SCLK Period - 1
160
–
–
ns
(17)
tLEAD
Enable Lead Time - 2
140
–
–
ns
(17)
tLAG
Enable Lag Time - 3
50
–
–
ns
(17)
tSCKHS
SCLK High Time - 4
56
–
–
ns
(17)
tSCKLS
SCLK Low Time - 5
56
–
–
ns
(17)
tSUS
MOSI Input Setup Time - 6
16
–
–
ns
(17)
tHS
MOSI Input Hold Time - 7
20
–
–
ns
(17)
tA
MISO Access Time - 8
–
–
116
ns
(17)
tDIS
MISO Disable Time - 9
–
–
100
ns
(17)
tVS
MISO Output Valid Time - 10
–
–
116
ns
(17)
tHO
MISO Output Hold Time (No cap on MISO) - 11
20
–
–
ns
(17)
tRO
Rise Time (Design Information) - 12
–
–
30
ns
(17)
tFO
Fall Time (Design Information) - 13
–
–
30
ns
(17)
500
–
–
ns
(17)
VBATP Undervoltage Detector Threshold Deglitcher
30
50
100
µs
(17)
Deglitcher Time to Set Reset Pin Low
–
10
20
µs
(18)
VPREGATE (mode select) Time
–
150
–
µs
(17)
tCSN
CS_B Negated Time - 14
SUPPLY, VOLTAGE REGULATOR, RESET
tS_LOW1/2 DGLT
tRST-DGLT
VPREGATE
tVPREMST
Notes
17. Guaranteed by CZ. Parameter not tested in production. All SPI timing is performed with a 100 pF load on MISO, unless otherwise noted.
18. Guaranteed by design.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
Electrical Characteristics
Table 6. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
VPRE Soft start Ramp cap. = 57 µF
5.0
12
25
V/ms
VDD Soft Start Ramp - CVDD = 10 µF; I = 10 mA
5.0
12
25
V/ms
VAUX Soft Start Ramp (non-tracking mode) - CVAUX = 10 µF; I =
10 mA
5.0
12
25
V/ms
VAUX Soft Start Ramp (tracking mode) - CVAUX = 10 µF; I = 10 mA
5.0
–
25
V/ms
VDD Undervoltage (SPI selectable)
• Short, default at power ON when BATFAIL bit set
• Medium
• Medium long
• Long
–
–
–
–
1.0
5.0
10
20
–
–
–
–
Watchdog Reset
–
1.0
tAMUX-VALID
AMUX Access Time (Selected output to selected output)
• CMUX = 1.0 nF Rising edge of CS_B to selected
–
tAMUX-VALID
AMUX Access Time (Tri-state to ON)
• CMUX = 1.0 nF Rising edge of CS_B to selected
Notes
VPRE
VPRESS
VDD REGULATOR
VDD_SS
VAUX REGULATOR
VAUX_SS
VAUX_SSTR
RESET PULSE DURATION
tRST-PULSE
tRST-WD
ms
(19)
–
ms
(19)
20
–
µs
(20)
–
–
20
µs
-5.0
–
5.0
µs
AMUX OUTPUT
OSCILLATOR
tOSC-TOL
Oscillator Tolerance
INTERRUPT
Notes
19. Guaranteed by design.
20. AMUX settling time to be within 10 mV accuracy. AMUXVALID is dependent of the voltage step applied on the source SGx pin, or the difference
between the first and second channel selected as the multiplexed analog output. See Figure 10 for a typical AMUX access time versus voltage
step waveform.
MC33909
19
Analog Integrated Circuit Device Data
Freescale Semiconductor
Electrical Characteristics
Table 6. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
CAN DYNAMIC CHARACTERISTICS
tDOUT
TXD Dominant State Timeout
0.8
1.8
2.8
ms
tDOM
Bus Dominant Clamping Detection
0.8
1.6
2.8
ms
tLRD
Propagation Loop Delay TXD to RXD, recessive to dominant (Slew
rate 0)
60
120
210
ns
tTRD
Propagation Delay TXD to CAN, recessive to dominant
–
70
110
ns
tRRD
Propagation Delay CAN to RXD, recessive to dominant
–
45
140
ns
tLDR
Propagation Loop Delay TXD to RXD, dominant to recessive
100
120
255
ns
tTDR
Propagation Delay TXD to CAN, dominant to recessive
–
75
150
ns
tRDR
Propagation Delay CAN to RXD, dominant to recessive
–
50
140
ns
LIN 1-4 PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER
SPECIFICATION Bus load RBUS and CBUS 1.0 nF/1.0 k, 6. nF/660, 10 nF/500. Measurement thresholds: 50% of TXD signal to LIN signal threshold
defined at each parameter. (21)
D1
Duty Cycle 1:
• THREC (max) = 0.744 * VBATP
• THDOM (max) = 0.581 * VBATP
• D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V  VBATP 18 V
0.396
–
–
D2
Duty Cycle 2:
• THREC (min.) = 0.422 * VBATP
• THDOM (min.) = 0.284 * VBATP
• D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V  VBATP  18 V
–
–
0.581
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER
SPECIFICATION (48), (50) Bus load RBUS and CBUS 1.0 nF/1.0 k, 6.8 nF/660, 10 nF/500. Measurement thresholds: 50% of TXD signal to LIN signal
threshold defined at each parameter. (22)
D3
Duty Cycle 3:
• THREC (max) = 0.778 * VBATP
• THDOM (max) = 0.616 * VBATP
• D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V  VBATP  18 V
0.417
–
–
D4
Duty Cycle 4:
• THREC (min.) = 0.389 * VBATP
• THDOM (min.) = 0.251 * VBATP
• D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V  VBATP  18 V
–
–
0.59
–
20
100
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE
BRFAST
LIN Fast Slew Rate (Programming mode)
kBits/s
Notes
21. See Figure 4.
22. See Figure 5.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
Electrical Characteristics
Table 6. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions TCASE = -40 °C to 125 °C, Battery Voltage = 3.5 V to 28 V DC (VBATP = 2.5 V to 27 V DC),
unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS VBATP from 7.0 V to 18 V, bus load RBUS and CBUS 1.0 nF/1.0 k, 6.8 nF/
660, 10 nF/500. Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. (23)
tREC_PD
tREC_SYM
tPROPWL
tWAKE_SLEEP
tWAKE_STOP
tTXDDOM
Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF)
–
4.2
6.0
µs
-2.0
–
2.0
µs
Bus Wake-up Deglitcher (Sleep and Stop modes) (See Figure 9 for
Sleep and Figure 11 for Low-power mode.)
42
70
95
µs
(24)
Bus Wake-up Event Reported
• From Sleep Mode
• From Stop Mode
–
9.0
250
27
–
35
µs
(24)
TXD Permanent Dominant State Delay
0.65
1.0
1.35
s
(24)
Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR
Notes
23. See Figure 6 and Figure 7.
24. Guaranteed by characterization.
3.4
Timing Diagrams
Figure 4. LIN Timing Measurements for Normal Slew Rate
MC33909
21
Analog Integrated Circuit Device Data
Freescale Semiconductor
Electrical Characteristics
Figure 5. LIN Timing Measurements for Slow Slew Rate
Figure 6. LIN Receiver Timing
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
22
Electrical Characteristics
Figure 7. LIN Wake-up Timing from Low-power VDD OFF Mode
Figure 8. LIN Wake-up Timing from Low-power VDD ON Mode
MC33909
23
Analog Integrated Circuit Device Data
Freescale Semiconductor
Electrical Characteristics
3
14
CS_B
CSb
1
4
2
SCLK
5
10
8
MISO
MSB IN
LSB OUT
DON'T
CARE
12 13
7
6
MOSI
DATA
MSB OUT
9
11
DATA
LSB IN
Figure 9. SPI Timing Diagram
Figure 10. AMUX Access Time
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
Functional Device Operation
4
Functional Device Operation
4.1
Battery Voltage Ranges
The 33909 device operates from 3.5 V  Battery  36 V (2.5 V  VBATP 35 V) and can survive to 41 V Battery. Overvoltage kicks in at
VBATP > 35 V and shuts down main functions of the IC. Battery voltages in excess of 41 V must be clamped externally in order to protect
the IC from destruction. The VBATP pin must be isolated from the main battery node by a diode.
Battery Voltage
VBATP
41 V
40 V
Survivable
36 V
35 V
Full
Parametrics
28 V
27V
Normal Mode
Full Parametrics
7.0 V
8.0 V
Full Parametrics
3.5 V
POR activated
3.3 V
2.5 V
2.3 V
No operation
0V
0V
Figure 11. 33909 (Buck - Boost Mode) Battery Diagram
MC33909
25
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
Battery Voltage
VBATP
41 V
40 V
Survivable
36 V
35 V
Full
Parametrics
28 V
27 V
Normal Mode
Full Parametrics
7.0 V
8.0 V
Degraded Parametrics
3.5 V
POR activated
3.3 V
2.5 V
2.3 V
No operation
0V
0V
Figure 12. 33909 (Buck Only Mode) Battery Diagram
4.1.1
POR
A Power On Reset occurs between 2.3 V < VBATP < 2.5 V. The 33909 is held in reset when VBATP < PORFALLING. The 33909 reinitializes after the POR is de-asserted (VBATP_MIN_SU).
4.1.2
No Operation
No operation in this range. The device does not send or receive SPI commands, and must reset properly upon leaving this range (when
battery is supplied). No unintended leakage currents flows causing undesired effects.
4.1.3
Start-up Requirements
Upon application of voltage to the VBATP node, the IC does not supply the VDD and VAUX voltage rails until all parameters can be
guaranteed. Internal circuitry can power up and begin to function, but the supply rails remain OFF until a stable output voltage (VDD and
VAUX) can be supplied. A typical voltage of 7.2 V on VBATP is expected to be the value where VDD and VAUX would be able to regulate
within specified range (another voltage may be determined to be the correct value, 7.0 V is a guide). This allows the micro to power up in
a known state with no glitches due to the power supply.
Upon startup of the VDD and VAUX rails, a soft start circuit limits the turn ON time of the rails (15 V/ms typical - dVDD/dt), to reduce the
overshoot of the regulated voltages. Figure 13 shows the desired waveform for the startup of the VDD and VAUX supplies.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
Functional Device Operation
VBATP_st
VBATP
Vint_2.5
Vpre_EN
Vpre_UV
Tdelay_VPREINT
Vpre
Vpre_INT_Buffer
(Low Power)
VDD_UV
Tdelay_VDDINT
VDD
VDD_INT_Buffer
(Low power)
INT_B
INIT
Initial RESET
Softstart Vregs
Softstart Vpre
Startup and
IC states
UV Lock-out
RESET_B
Figure 13. Power Up Sequencing
MC33909
27
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
VBATP_MIN_SU
5.0v
PORFALLING
2.5v
VBATP
Buck / Boost On
VPRE_EN
Figure 14. VBATP Start-up and POR
4.1.4
Power Supply Functional Block
This block has the VBATP supply and VPRE supply as an input. The internal 2.5 V rail is generated in this block. Power On Reset (POR),
Sleep mode power, and the Bandgap reference are controlled here as well.
4.2
Input Functional Block
There are six Switch-to-Ground inputs used to detect switch closures and provide wetting current. The main functions of this block is to
detect a change of state at the input via a 3.5 V (typical) comparator, provide a signal to the main logic to issue an interrupt signal, and
also provide wetting/sustain current for the switch. A SPI read allows the micro to know the status of all the inputs.
4.2.1
SG Inputs
The SG inputs are switch to ground detect inputs with a comparator threshold (VICTHR - 3.5 V typical). A closed switch is a switch shorted
to ground (or otherwise below the VICTHR value) and is reported via the SPI as a logic 1. An open switch is any condition causing the
input voltage to rise above the VICTHR value, and is reported via the SPI as a logic 0. In the case where the user needs a Switch to Battery,
the user must take note that the IC reports a logic 1 when the input voltage is less then VICTHR. The inputs also provide a wetting current
output with selectable values ranging from 6.0 to 20 mA (IWETX) in steps of 2.0 mA. A sustain (ISUSTAIN) current level is used to decrease
power consumption in the IC. The current sources are pull-up sources with a reference of VPRE. A blocking diode is in series with the
current source to block voltages at the input greater than the VPRE from back feeding into the IC. Due to this diode, the maximum voltage
the SGx pins can pull up to is ~ 6.5 V (VPRE) - 1 diode drop (~0.7 V) for a final value of ~5.7 V. This use greatly benefits the power
consumption of the input current sources, but does limit headroom when using the current sources to drive external loads. VPRE voltage
is supplied during Normal (via the SMPS) and Low-power modes (via internal linear). Battery voltages below 7.0 V are not supported in
Low-power mode.
All register settings programmed in Normal mode are remembered in Sleep mode. The current used to detect open switches in Low-power
mode is ~1.0 mA. Upon leaving Low-power mode the programmed settings are used.
In Low-power mode, the inputs do not use the typical 3.5 V switch threshold. Rather a comparison threshold is used to measure the
beginning of the tSCAN time (before the LPM current source is turned on) and after the tSCAN timer (typical 55 s) has completed. If this
voltage has passed the low-power switch detection threshold (typ 210 mV), the IC detects an open switch and compares to the internal
logic to determine if a change of state has occurred.
Figure 16 describes the state diagram for the SGx inputs and how they move from state to state. Of note is the three times retry of the
wetting current (IPRGM in this notation) in case of a tLIM. This allows for one time thermal events to be dealt with and still operate normally
when able. After three times tLIM, the input goes to tri-state and wait for the user to clear the tLIM fault via the SPI word.
In the case where a SAFE mode operation would like to sense the key OFF condition of the module, SG0 is used in conjunction with the
WDI pin to facilitate the SAFE operation and turn OFF the VDD supply.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
28
Functional Device Operation
Go To LPM
CS_B
64ms (config)
Normal
Normal
Mode
LPM
Polling time
Tscan time
55us
X * 1mA SG
Load Current
0uA
Figure 15. Low-power Mode Typical Timing Diagram
MC33909
29
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
Tri-state
I = 0 mA
1
4
3
2
IWETTING
10
6
5
11
LPM (1.0 mA)
7
ISUSTAIN
8
9
1) Change from 0 mA to Wetting current value: Wetting current programmed to all time or Pulsed
Mode and untristate the input.
2) Maintain Wetting current: When switch is closed to ground and 20 ms timer not expired (wetting
current timer enabled).
3) Change from Wetting Current to 0 mA: Go to Low Power mode (LPM) or Tri-state command sent.
4) Change from 0 mA to Sustain current (2.0 mA): Wetting current off command sent and untri-state.
5) Change from Sustain current to 0 mA: Go to LPM or Tri-state command
6) Change from LPM to Wetting current: Wake-up and not in Wetting current off mode.
7) Change from LPM to Sustain current: Wake-up and in Wetting current off mode.
8) Change from Sustain to Wetting current: Switch opens and wetting current timer on or a SPI
message to turn Wetting current on.
9) Change from Wetting current to Sustain: Closed switch and timer expired or a SPI message
turning Wetting current off.
10) Change from 0 mA to LPM current: During active scan timer (100 us long) in LPM (Periodic
sense).
11) Change from LPM current to 0 mA: During inactive scan timer in LPM.
Note 1. Three Tlim instances on the SG sensor puts the device into Sustain only mode for the SGs.
A SPI read clears the function and allows wetting current to be active again.
Note 2. Overvoltage on the VBATP pin causes the SG inputs to switch to Sustain only until the
overvoltage condition is gone.
Note 3. A POR results in the IC resetting and the SG inputs back in the Tri-state condition.
Figure 16. 33909 SG State Diagram
4.2.1.1
Alternative Functions of the SG0 Pin
There are some additional functions for SG0. These functions are described in the block most closely associated with their additional
functions.
1. SG0 can be used in conjunction with the SAFE mode to determine how the IC should operate when a SAFE condition is detected.
See Table 7 for information on SAFE mode operation.
4.2.2
SG Input Pin Functions: SGx
Each input pin is the connection used by the user to determine the state of the switch, and source the wetting and sustain currents. A
capacitor is required on the input with a minimum value of 47 nF (CAPSG) and a maximum capacitance of 100 nF. Characterization of the
input defines the available capacitor range.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
30
Functional Device Operation
4.2.3
Oscillator and Timer Control Functional Block
The oscillator is generated in this block. All timers are generated from the reference oscillator. The oscillator is trimmed to 5.0%. There
is no external pin for the oscillator and timer control block. The 5.0% oscillator is turned OFF in Low-power mode to reduce quiescent
current.
A second oscillator is used in Low-power mode. The oscillator operates at 200 kHz and is accurate to 20%. All of the Low-power mode
timers are based on this Low-power oscillator.
4.2.4
TLIM Functional Block
The device has multiple tlim cells to detect thermal excursions. An independent tLIM cell exists for multiple circuit blocks including:
1. CAN regulator
2. VPRE circuitry
3. SG inputs
4. LIN cells
The corresponding block contains the description of what occurs when tLIM is seen by the related circuitry. Hysteresis for each cell is used
to keep the device from cycling. There is no external pin connection for the tLIM functional block.
4.2.4.1
INT_B Functional Block
This block is used to alert the micro to a change of state on an input. The INT_B pin is an interrupt output from the 33909 device. The
INT_B pin is an open-drain output with an internal pull-up to VDD. In Normal mode, a switch state change triggers the INT_B pin (when
enabled). The INT_B pin and INT_B bit in the SPI register are latched on the falling edge of CS_B. This permits the MCU to determine
the origin of the interrupt. The INT_B pin is cleared on the rising edge of CS_B. The INT_B pin does not clear with rising edge of CS_B if
a switch contact change has occurred while CS_B was LOW.
4.2.5
INT_B Pin Functions: INT_B
The INT_B output is asserted low or drives a pulse when an interrupt condition occurs. The INT condition is enabled in the INT register.
The INT_B operation (assertion of a low level or a pulse) is defined by the SPI.
4.2.6
SAFE_B Functional Block
This mode is entered when specific fail conditions occur. The “Safe state” condition defaults to condition A in Table 7. A SPI word can then
be used to modify the operation as found in Table 7. Safe mode is entered after additional event or conditions are met: timeout for CAN
communication. Exit of the Safe state is always possible by a wake-up event: in the safe state the device is automatically wakeable CAN.
Upon wake-up, the device operation is resumed: enter in Reset mode.
4.2.6.1
Debug Detect
The operation of the SAFE_B block is determined by the state of the WDI pin and the associated resistance to ground is supplied external
to the IC. The IC is put into watchdog inhibit mode when the voltage at the WDI pin is > 10 V. This results in a SAFE mode A, but no
watchdog refresh is needed.
The debug detect circuit measures an external pull-down resistor on the WDI. Three thresholds exist (excluding the Test mode) and
outputs to the logic block, in which mode the SAFE_B block should operate (Mode<B3:A>). The mode is read in by determining the resistor
value on the WDI pin at power ON only (during the INIT RESET node), and remains in this state until a new power ON sequence is
detected.
4.2.6.2
4.2.6.2.1
Fail-safe Operation
Fail-safe Functionality
Upon a dedicated event or issue, detected at a device pin (i.e RESET), the Safe mode can be entered. In this mode, the SAFE_B pin is
active low.
MC33909
31
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
4.2.6.2.2
Description
Upon activation of the SAFE_B pin, and if the failure condition which caused the activation of SAFE_B has not recovered, the device can
help to reduce ECU consumption, assuming the MCU is not able to set the whole ECU in Low-power mode.
Two main cases are available:
• Upon SAFE_B activation, the MCU remains powered (VDD stays ON), until the failure condition recovers (i.e S/W is able to properly
control the device and properly refresh the W/D).
• Upon SAFE_B activation, the system continues to monitor external events, and disable the MCU supply (turn VDD off). The external
events monitored are: SG0 switch to ground and CAN and LIN traffic. For this condition, three sub cases exist: B1,B2, B3.
Note: CAN and LIN traffic bus idle indicates the ECU of the vehicle is no longer active, thus the car is being parked and stopped.
SAFE_B Mode Code
VDD Status
A
Remains ON
B1
Turn OFF 8 sec. after CAN and LIN traffic bus idle detection.
B2
Turn OFF when the SG0 switch is closed to ground.
B3
Turn OFF 8 sec. after CAN and LIN traffic bus idle detection when SG0 low level is detected.
Exit of the safe state with VDD OFF is always possible by a wake-up event: in this Safe state the device is automatically wakeable with
CAN and the SG0 input. Upon wake-up, the device operation is resumed: enter in Reset mode. The SAFE_B pin remains active, until a
proper read and clear of the SPI flags reporting the SAFE_B conditions.
Figure 17 illustrates the SAFE_B mode activation and the power consumption reduction after CAN traffic idle time.
bit 11,12 of INIT command xx(1)
Reset 1.0 ms pulse
nth W/D
failure
SAFE Low
Reset 1.0 ms pulse
SAFE Low
No (SAFE_B remains low)
7 consecutive
W/D Failure
Note (4)
State A: RWDI < 2.5 k
W/D Failure
Yes
B) ECU external
signal monitoring
- bus idle time out
- SG0 monitoring
RESET_B short-circuit to
GND Failure:
RESET_B < RST-TVH; t > 100 ms
SAFE State B
- Reset Low
- SAFE Low
- VDD on
SAFE State A
SAFE_B pin
release
(SAFE_B High)(3)
A) Evaluation of
Resistor detected
at WDI pin during
power up or SPI
register content
VDD Low Failure:
VDD < VDD_UVTH
t > 100ms
State:
INIT, Normal, Normal
Request, Flash
Return to
Normal mode
Yes
bit 11,12 of INIT command 00
W/D
Failure
No
SAFE High
State A: RWDI < 2.5 k
VDD Low or RESETB
s/c to ground Failure
State B1: 7.0 k < RWDI <
14 k
BUS idle time out expired(2)
(CAN and LIN)
- SAFE Low
- VDD On
- Reset 1.0 ms
periodic pulse
- SAFE Low
- VDD On
- Reset Low
- SAFE Low
State B2: 29 k < RWDI < 40 k - VDD Off
& SG0 Low
- Reset Low
State B3: 80 k < RWDI
BUS idle time out expired(2)
(CAN and LIN) & SG0 Low
State:
1.0 ms Reset
pulse
Wake-up event, VDD ON, SAFE_B pin remains Low
Failure recovery, SAFE_B pin remains Low
Notes:
1) Bits 11 and 12 of the INIT command control the number of times a reset / Watchdog failure should occur nth
time: 00 = 1st time, 01
= 2nd time, 10 = 3rd time, 11 = 5th time.
2) 8 second timer for bus idle time out.
3) SPI command to release SAFE_B pin after recovery from failure (5F000000).
4) Dynamic behavior: 1.0 ms reset pulse every 256 ms due to no watchdog refresh SPI command and the
device state transitions between RESET and Normal Request or INIT RESET and INIT modes.
Figure 17. SAFE Operation Flow Chart
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
32
Functional Device Operation
Table 7. Safe Mode Operation
State
VDD
CAN5V
VAUX
LINx
SGx
CAN0
Power down
OFF
OFF
OFF
High-impedance
High-impedance
High-impedance
Init Reset
ON
OFF
OFF
OFF: internal 30 kΩ pull-up
active. Transmitter: receiver/
wake-up OFF.
High-impedance
OFF: CAN termination 25k to
GND Transmitter/receiver /wakeup OFF
INIT
ON
OFF
OFF
OFF
High-impedance
OFF
Reset
ON
Keep SPI
configuration
OFF
OFF
SPI configuration
OFF
Normal
Request
ON
Keep SPI
configuration
OFF
OFF
SPI configuration
OFF
Normal
ON
SPI
configuration
SPI
configuration
SPI configuration
SPI configuration
SPI configuration
Low-power
VDDOFF
OFF
OFF
OFF
OFF + wake-up enable/disable
SPI configuration
OFF + wake-up enable/disable
Low-power
VDDON
ON
OFF
OFF
OFF + wake-up enable/disable
SPI configuration
OFF + wake-up enable/disable
SAFE_B
output low:
SAFE_B case
A
safe
case A:
ON
safe
case B:
OFF
A: Keep SPI
configuration, B:
OFF
OFF
OFF + wake-up enable
SPI configuration
OFF + wake-up en
FLASH
ON
SPI
configuration
SPI
configuration
OFF
SPI configuration
SPI configuration
MC33909
33
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
WDI resistor mode A
VDD (High)
VDD (High)
RESET_B
SAFE_B
RESET_B
OFF State
SAFE_B
ON State
Delay time to enter in SAFE mode
with consumption reduction and
evaluate resistor at WDI pin
WDI resistor mode B(1,2,3)
VDD
RESET_B
SAFE_B (Low)
CANx Bus
(mode 1 and 3
CAN bus idle time(8s)
LINx Bus
(mode 1 and 3)
LIN bus idle time (8s)
SG0
(mode 2 and 3)
Figure 18. SAFE Mode A and B (1, 2, 3)
4.2.6.3
SAFE_B Pin Functions: SAFE_B
This pin is an output which is asserted low in case a fault event occurs. The objective is to drive electrical safe circuitry outside the MCU
and the SBC. This safe circuitry activates the default function of the ECU, independent of the MCU and SBC.
Flexibility is provided to the user to select SAFE output operation via a resistor at the WDI pin. The SAFE output is an open drain structure.
4.2.6.4
SAFE_B Pin Functions: WDI
This pin is an input used to set the device in Debug mode. When the device is powered up with a voltage at the WDI pin > 10 V, the device
enters into Debug mode. In this mode, only a single WD refresh command (SPI 0x47000000) is necessary to put the device in Normal
Mode. This allows for easy debugging of the software routine controlling the device.
In addition, a resistor can be connected from the WDI pin to GND to select Fail-safe mode operation.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
34
Functional Device Operation
4.2.7
4.2.7.1
Watchdog Functional Block
In Normal Request Mode
In Normal Request mode, the device expects to receive a watchdog configuration before the end of the normal request timeout period.
This period is reset to a long (256 ms) after power-on and when BATFAIL is set. In Normal Request mode the watchdog operation is
“timeout” only and can be triggered/served any time within the period.
4.2.7.2
Watchdog Type Selection
Two different watchdog modes are implemented: Window or Advance. The selection of “Window” or “Advance” is done in INIT mode, after
device power up when the Batfail flag is set. Configuration is done via the SPI. Then the watchdog mode selection content is locked and
can be changed only via a secured SPI procedure.
4.2.7.3
Window Watchdog Operation
The window watchdog is available in Normal mode only. The watchdog period selection can be kept (SPI is selectable in INIT Mode), while
the device enters into Low-power Stop mode. The watchdog period is reset to the default long period after BATFAIL.
The period and the refresh of watchdog are done by the SPI. A refresh must be done in the open window of the period, which starts at
50% of the selected period and ends at the end of the period. If the watchdog is triggered before 50%, or not triggered before end of period,
a reset has occurred. The device enters into Reset mode.
4.2.7.4
Watchdog in Debug Mode
When the device is in Debug mode (entered after a POR when the WDI is > 10.0 V), the watchdog continues to operate, but does not
affect the device operation by asserting a reset. A single WD refresh command (SPI 0x47000000) is necessary to put the device in Normal
Mode. For the user, operation appears without the watchdog once Normal Mode is entered. When Debug is left by software (SPI mode
reg.), the watchdog period starts at the end of the SPI command. When Debug mode is left by hardware, when the voltage on the WDI
drops below 8.9 V, the device enters into an INIT Reset mode. The WDI pin is discussed in the SAFE_B functional block section.
4.2.7.5
Watchdog in Flash Mode
During Flash mode operation, the watchdog can be selected to a long timeout period. Watchdog is timeout only and an INT pulse can be
generated at 50% of the time window.
4.2.7.6
Advance Watchdog Operation
When the Advance watchdog is selected (at INIT mode), the refresh of the watchdog must be done using a random number and with 1,
2, or 4 SPI commands. The software must read a random byte from the SBC, then it must return the random byte inverted to clear the
watchdog. The random byte write can be done in 1, 2, or 4 different SPI commands.
If 1 command is selected, all 8 bits are written at once.
If 2 commands are selected, first write command must include 4 of the 8 bits of the inverted random byte. The second command must
include the next 4 bits. This completes the watchdog refresh.
If 4 commands are selected, the first write command must include 2 of the 8 bits of the inverted random byte. The second command must
include the next 2 bits, the 3rd command the next 2, and the last command, the last 2. This completes the watchdog refresh.
When multiple writes are used, the most significant bits are sent first. The latest SPI command needs to be done inside the open window
time frame.
MC33909
35
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
4.2.7.7
Detail SPI Operation and SPI Commands for all Watchdog Types
In INIT mode, the W/D type is selected using register Init W/D, bits 1, 2, and 3. The W/D period is selected via TIM_A register. The W/D
period selection can also be done in Normal mode or in Normal Request mode.
Transition from INIT mode to Normal mode, or from Normal Request mode to Normal mode is done via a single W/D refresh command
(SPI 0x47000000).
While in Normal mode, the W/D refresh command depends upon the W/D type selected in INIT mode. These are detailed in the following
paragraph:
Simple W/D: refresh commands is 0x47000000. It can be sent any time within the W/D period if the timeout W/D operation is selected
(INIT-W/D register, bit 1 WD N/Win = 0). It must be sent in the open window (second half of the period) if the Window Watchdog operation
was selected (INIT-W/D register, bit 1 WD N/Win = 1).
4.2.7.8
Advance Watchdog
The first time device enters into Normal mode (entry on Normal mode using the 0x47000000 command), the RND code must be read using
SPI command 0x0B000000. Device returns on the MISO fourth byte of the RND code. The full 32 bit MISO response is 0xXX0000RD.
Advance Watchdog, refresh by 1 SPI command:
The refresh command is 0x4B0000RD. During each refresh command device returns a new Random Code on MISO. This new random
code must be inverted and sent along with the next refresh command, and so on.
It must be done in the open window if the Window operation was selected.
Advance Watchdog, refresh by 2 SPI commands:
The refresh command is split in 2 SPI commands.
The first partial refresh command is 0x4B0000w1, and the second is 0x4B0000w2. Byte w1 contains the first 4 inverted bits of the RD byte
plus the last 4 bits equal to zero. Byte w2 contains 4 bits equal to zero plus the last 4 inverted bits of the RD byte.
During this second refresh command, the device returns a new Random Code on MISO. This new random code must be inverted and
send along with the next 2 refresh commands and so on.
The second command must be done in the open window if the Window operation was selected.
Advance Watchdog, refresh by 4 SPI commands:
The refresh command is split in 4 SPI commands.
The first partial refresh command is 0x4B0000w1, the second is 0x4B0000w2, the third is 0x4B0000w3 and the last is 0x5Aw4.
Byte w1 contains the first 2 inverted bits of the RD byte plus the last 6 bits equal to zero.
Byte w2 contains 2 bits equal to zero plus the next 2 inverted bits of the RD byte plus 4 bits equal to zero.
Byte w3 contains 4 bits equal to zero plus the next 2 inverted bits of the RD byte plus 2 bits equal to zero.
Byte w4 contains 6 bits equal to zero plus the next 2 inverted bits of the RD byte.
During this fourth refresh command, the device returns on MISO a new Random Code. This new random code must be inverted and sent
along with the next 4 refresh commands. The fourth command must be done in the open window, if the Window operation was selected.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
36
Functional Device Operation
4.3
4.3.1
Operational Modes
Introduction
The device has several operation modes. The transitions and conditions to enter or leave each mode are described in Figure 19.
VBATP rise &
VDD > VDD_UVTH
VBATP fail
Power Down
INIT Reset
start tIR
(tIR = 1.0 ms)
VBATP fail
tINIT expired
Or VDD < VDD_UVTH
W/D refresh
by SPI
tIR expired &
VDD > VDD_UVTH
FLASH
start tWDF
(max 32768 ms)
External
RESETb
Wake-up
SPI secured (1)
or tWDF expired
or VDD < VDD_UVTH
RESET
start tR
(1.0 ms or config)
Debug
mode
detection
INIT
Start tINIT
(tINIT = 256 ms)
SPI secured (1)
SPI write
(0x47000000 )
(W/D refresh)
SPI secured (1)
VDD < VDD_UVTH
or tWD expired
or W/D failure (3)
or SPI secured (1)
tR expired
& VDD > VDD_UVTH
SPI write
(0x47000000 )
(W/D refresh)
tNR expired
Wake-up
W/D refresh
by SPI
SPI
NORMAL
REQUEST
start tNR
(256 ms)
tOC expired
or Wake-up
Normal
Start tWDN
(tWDN = config)
LOW POWER
VDD ON
SG scan
Start tWDL (2)
Wake-up
IDD < IOC
(2.0 mA)
tOC ended
if enable
W/D refresh
by SPI
IDD > IOC
(2.0 mA)
LP VDDON
IDD > 2.0 mA
SG scan
start tOC time
VDD < VDD_UVTHLP
tWDL expired or VDD < VDD_UVTHLP
SPI
LOW POWER
VDD OFF
SG scan
SPI
FAIL SAFE
DETECTED
(1) Refer to “SPI secured” description.
(2) If enabled by SPI prior to entering LP VDD ON mode.
(3) W/D refresh in closed window or enhanced W/D refresh failure.
Figure 19. State Diagram
MC33909
37
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
4.3.1.1
INIT Reset
This mode is automatically entered after device “power ON”. In this mode, the RST_B pin is asserted low, for a duration of typically 1.0 ms.
Control bits and flags are “set” to their default reset condition. The BATFAIL is set to indicate the device is coming from an unpowered
condition, and all previous device configurations are lost and “reset” is the default value. The duration of the INIT reset is typically 1.0 ms.
INIT reset mode is also entered from INIT mode, if the expected SPI command does not occur in due time (ref. INIT mode)
4.3.1.1.1
INIT
This mode is automatically entered from “INIT reset” mode. In this mode, the device must be configured via the SPI within a time of 256 ms
max. One SPI word to configure the INIT registers (three registers called Watchdog, REG, and MISC) must be configured during INIT
mode.
Once the INIT registers configuration is done, a SPI Watchdog Refresh command must be sent in order to set the device into Normal
mode. If the SPI W/D refresh does not occur within the 256 ms period, the device returns into INIT reset mode for a typical 1.0 ms, and
then reenter into INIT mode.
Register read operation is allowed in INIT mode, to collect device status or to read back the INIT register configuration. When INIT mode
is left by a SPI Watchdog refresh command, it is possible to reenter the INIT mode only by a secured SPI command.
4.3.1.1.2
Reset
In this mode, the RST_B pin is asserted low. Some bits and flags are reset. Reset mode is entered from Normal mode, from Normal
Request mode, from LP VDD ON mode and from Flash mode, when the watchdog is not triggered, or a VDD low condition is detected.
The duration of reset is typically 1.0 ms by default. The user can define a longer Reset pulse activation, only when the Reset mode is
entered, following a VDD low condition. Reset pulse is always 1.0 ms, in case the Reset mode is entered due to a wrong watchdog refresh
command.
4.3.1.2
Normal Request
This mode is automatically entered from Reset mode, or after a wake-up from Low-power VDD ON mode. A watchdog refresh SPI
command is necessary to allow a transition to Normal mode. The duration of the Normal request mode is 256 ms maximum duration when
Normal Request mode is entered after Reset or when entered from the LP VDD ON mode. If the watchdog refresh SPI command does not
occur within the 256 ms, the device enters into Reset mode for a duration of typically 1.0 ms.
4.3.1.2.1
Normal
In this mode, all device functions are available. This mode is entered by a SPI watchdog refresh command from Normal Request mode,
or from INIT mode. During Normal mode, the device watchdog function is operating, and a periodic watchdog refresh must occur. In case
of an incorrect or missing watchdog refresh command, the device enters into Reset mode.
From Normal mode, the device can be set by a SPI command into Low-power modes (Low-power VDD ON or Low-power VDD OFF).
Dedicated secured SPI commands can be used to enter from Normal mode in Reset mode, INIT mode, or Flash mode.
4.3.1.2.2
Debug
Debug is a special operation condition of the device which allows the system easy software and hardware debugging. The debug operation
is detected after power up if the WDI pin is set above 10 V.
When debug is detected, all the software watchdog operations are disabled: 256 ms of INIT mode, watchdog refresh of Normal mode and
Flash mode of 256 ms, or a user defined timeout of Normal request mode, are not operating and does not lead to a transition into INIT
reset or Reset mode.
4.3.1.3
Flash
In this mode, the software watchdog period is extended up to typically 32 seconds. This allows the MCU flash memory to be reloaded,
while the software overhead refreshes the watchdog is limited. The Flash mode is left by the SPI command and the device enters into
Reset mode. In case of an incorrect or missing watchdog refresh, the command device enters into Reset mode.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
38
Functional Device Operation
4.3.1.3.1
Low-power Modes
The device has two main Low-power modes: Low-power mode with VDD OFF, and Low-power mode with VDD ON.
4.3.1.3.2
Low-power - VDD OFF
In this mode, VDD is turned OFF and the MCU connected to VDD is unsupplied. This mode is entered by the SPI. In order to prevent
accidental VDD turn off, a VDDoff en control bit is used. This bit must be set to "1" for Low-power - VDD OFF mode to be activated.It can
also be entered by automatic transition due to fail-safe management. The 5 V-CAN and VAUX regulators are also turned off.
When the device is in Low-power VDD OFF mode, it monitors external events to wake-up and leave the LP mode. The wake-up events
can occur from:
• CAN bus
• LIN bus
• Expiration of an internal timer
• SG input
When a wake-up event is detected, the device enters into Reset mode and then into Normal Request mode. The wake-up source is
reported into the device SPI registers. In summary, a wake-up event from LP VDD OFF, leads to a VDD regulator turn ON, and an MCU
operation restart.
4.3.1.3.3
Low-power - VDD ON
In this mode, the voltage at the VDD pin remains at 5.0 V (or 3.3 V, depending upon device part number). The objective is to maintain the
MCU in a reduced power consumption mode. In this mode, the DC output current is expected to be limited to a few 100 A or some mA,
as the ECU is in reduced power operation mode. The 5 V-CAN and VAUX regulators are turned OFF.
However, in Low-power VDD ON mode, the device is able to deliver several micro amps of current on VDD (up to typ. 2.0 mA). The current
delivery can be time limited, by a selectable internal timer. Timer duration is up to 32 ms, and is triggered when the output current exceeds
the output current threshold, typically 2.0 mA. This allows, for instance, a periodic activation of the MCU while the device remains in LP
VDD ON mode. If the duration exceeds the selected time (ex 32 ms), the device detects a wake-up.
The same wake-up event as in LP VDD OFF mode (CAN, SGx, timer, cyclic sense) are available in LP VDD ON mode. In addition, two
additional wake-up conditions are available.
• By a dedicated SPI command (hex 0x49000010).
• Output current from VDD exceeding typically a 2.0 mA threshold, the device wakes up, provided additional conditions are met (timing
detection...).
• If VDD maximum load is exceeded (>80 ma), VDD starts to fall. When VDD falls below approximately 1.0 V, the device then wakes up
and issue a reset.
Wake-up events are reported to the MCU via a low level pulse at the INT pin. The MCU detects the INT pulse and resume operation.
4.3.1.3.4
Watchdog Function in LP VDD ON mode
It is possible to enable the watchdog function in low-power VDD ON mode, for timeout functionality.
Refresh of the watchdog is done either by:
• a dedicated SPI command (different from any other SPI command, or simple CS activation, which would wake-up)
• or by a temporary (less than 32 ms max) VDD overcurrent wake-up (IDD > 2.0 mA typ).
As long as the watchdog refresh occurs, the device remains in LP VDD ON mode.
MC33909
39
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
4.3.1.3.5
Cyclic Sense Operation
This function can be used in both Low-power modes (LP VDD OFF and LP VDD ON). Cyclic sense is a specific detection of an event on
an SGx, during the cyclic activation of the SGx input. Cyclic sense principle (synchronous cyclic sense):
A dedicated timer allows to select a cyclic sense period from 3.0 to 512 ms (selection in timer B). At the end of the period, the SGx is
activated for a duration of tSCAN. During the TSCAN duration, the SGx is monitored. If it is it the expected level, the device detects a wakeup. Cyclic sense can operate for both Low-power modes: Low-power VDD ON and Low-power VDD OFF.
Cyclic sense period is selected by the SPI configuration prior to entering Low-power mode. The expected level on SGx is selected at the
time the device is set into Low-power mode. This means prior to entering Low-power mode, SGx must be activated, so the level of SGx
can be sampled. During device Low-power mode, if the opposite level on SGx is reached during the SGx activation mode, the device
wakes up.
During Cyclic Sense active time (tSCAN), the level of SGx is the same as the one before entering Low-power mode. So full flexibility is
offered, as the SGx high-side or low-side switch can be activated by the SPI in Normal mode. The level of SGx is sensed during the SGx
active time, and is deglitched for a duration of typically 30 s. This means SGx should be in the expected state for a duration longer than
the deglitcher time.
4.3.1.3.6
CAN Functional Block
The 33909 has an enhanced High Speed CAN physical interface. A single CAN5V pin is used for a capacitor for the internal 5.0 V regulator
to power the CAN interface. There is also a single dedicated Ground for the CAN bus (CANGND).
The CAN5V regulator supplies a maximum of 200 mA, while the CAN physical layer is designed to current limit to less than 100 mA in
case of a short on the bus. If the user does not use the physical layer, the user may use the CAN5V supply as another supply rail. The
CAN5V regulator turns OFF in LP modes.
VBATP
SPI & State machine
Pattern
Detection
Wake-up
Receiver
CAN5V
QH
Driver
RIN
2.5V
CANH
Differential
Receiver
RXD
RIN
CANL
5VCAN
Driver
TXD
SPI & State machine
SPI & State machine
QL
Thermal
Failure Detection
& Management
Figure 20. CAN Interface Block Diagram
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
40
Functional Device Operation
4.3.1.3.7
TX/RX Mode
In TX/RX mode, both the CAN driver and the receiver are ON. In this mode, the CAN lines are controlled by the TXD pin level, and the
CAN bus state is reported on the RXD pin.
The CAN5V regulator must be ON. It supplies the CAN driver and receiver.
TLRD
TXD
0. 3 CAN5V
0. 7 CAN5V
T LDR
RXD
0. 7 CAN5V
0. 3 CAN5V
Figure 21. CAN Propagation Delays TXD to CAN and CAN to RXD
TTRD
TXD
0.7 CAN5V
0.3 CAN5V
TTDR
0.9V
VDIFF
TRRD
0.5V
TRDR
RXD
0.7 CAN5V
0.3 CAN5V
Figure 22. CAN Propagation Delays TXD to CAN and CAN to RXD
VBAT
VBATP
VDD
100nF
2.2µF
CANH
Signal
generator
RBUS
60O
TXD
CBUS
100pF
CANL
15pF
RXD
GND
All pins are not
shown
Figure 23. CAN Test Setup
4.3.1.3.8
Sleep Mode
Sleep mode is a reduced current consumption mode. CANH and CANL lines are terminated to GND via the RIN resistor (typ 25 k). In
order to monitor bus activities, the CAN wake-up receiver is ON.
Wake-up events occurring on the CAN bus pin are reporting by dedicated flags in SPI, and results in a device mode transition out of Lowpower mode.
4.3.1.3.9
Listen Only Mode
This mode is used to disable the CAN driver, but leave the CAN receiver active. In this mode, the device is only able to report the CAN
state on the RXD pin. The TXD pin has no effect on CAN bus lines. The CAN5V regulator must be ON.
MC33909
41
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
4.3.1.3.10
CAN Interface Supply
The supply voltage for the CAN driver is the CAN5V pin. The CAN interface also has a supply path from the battery line, through the
VBATP pin. This path is used in CAN sleep mode to allow wake-up detection. During CAN communication (transmission and reception),
the CAN interface current is sourced from the CAN5V pin. During CAN Low-power mode, the current is sourced from the VBATP pin.
4.3.1.3.11
CAN Driver Operation in TX/RX Mode
The CAN drive can be enabled via SPI as soon as the device is in normal mode. When the CAN interface is in Normal mode, the driver
has two states: recessive or dominant. The driver state is controlled by the TXD pin. The bus state is reported through the RXD pin.
When TXD is high, the driver is set in the recessive state, and CANH and CANL lines are biased to the voltage set with CAN5V divided
by 2, or approximately 2.5 V. When TXD is low, the bus is set into the dominant state, and CANL and CANH drivers are active. CANL is
pulled low and CANH is pulled high.
The RXD pin reports the bus state: CANH minus the CANL voltage is compared versus an internal threshold (a few hundred mV).
If “CANH minus CANL” is below the threshold, the bus is recessive and RXD is set high.
If “CANH minus CANL” is above the threshold, the bus is dominant and RXD is set low.
Recessive State
TXD
Dominant State
CANH-DOM
2.5 V
CANH
CANL/CANHREC
CANL
High ohmic termination
(50 k) to GND
CANL-DOM
RXD
Receiver
(bus dominant set by other IC)
BUS Driver
Normal or Listen Only Mode
Go to sleep, Sleep
or Stand-by Mode
Normal or Listen Only Mode
Figure 24. BUS Signal in Tx/Rx and Low-power Mode_48LD
4.3.1.3.12
Minimum Baud Rate
The minimum baud is determined by the shortest TXD permanent dominant timing detection. The maximum number of consecutive
dominant bits in a frame is twelve (six bits of active error flag and its echo error flag). The shortest TXD dominant detection time of 300 s
lead to a single bit time of: 300 s/12 = 25 s, so the minimum Baud rate is 1/25 s = 40 kBaud.
4.3.1.3.13
Termination
The device supports differential termination resistors between CANH and CANL lines. Refer to device typical application.
4.3.1.3.14
Low-power Mode
In Low-power mode, the CAN is internally supplied from the VBATP pin. In Low-power mode, the CANH and CANL drivers are disabled,
and the receiver is also disabled. CANH and CANL have a typical 25 k impedance to GND. The wake-up receiver can be activated if
wake-up is enabled by the SPI command. When the device is set back into Normal mode, CANH and CANL are set back into the recessive
level. This is illustrated in Figure 24.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
42
Functional Device Operation
4.3.1.3.15
Wake-up
When the CAN interface is in Sleep mode with wake-up enabled, the CAN bus traffic is detected. The CAN bus wake-up is a pattern wakeup. The wake-up by the CAN is enabled or disabled via the SPI. There are two methods for wake-up, Three dominant pulses or a single
dominant pulse described in the figures below. The default condition is for the three dominant pulses to cause a wake-up.
CANH
Dominant
Pulse #1
CAN Bus
Dominant
Pulse #2
CANL
Dominant
Pulse #4
Dominant
Pulse #3
Incoming CAN message
Internal differential
wake-up receiver signal
min 650 ns
Internal wake-up signal
min 650 ns
max 1500 ns
min 1.2 us
max 120 µs
Figure 25. Three Dominant Pulses Pattern Wake-up
CANH
Dominant
Pulse #1
CAN Bus
CANL
Incoming CAN message
Internal differential
wake-up receiver signal
Internal wake-up signal
min 1.2 µs
max 2.5 µs
Figure 26. Single Pulse Pattern Wake-up
4.3.1.3.16
CAN Wake-up Report
The CAN wake reporting is done via the device state machine.
4.3.1.3.17
Pattern Wake-up
In order to wake-up the CAN interface, the wake-up receiver must receive a series of three consecutive valid dominant pulses, by default
when the CANWU bit is low. CANWU bit can be set high by SPI and the wake-up occurs after a single pulse duration of 1.0 s (typ).
A valid dominant pulse is longer than 500 ns. The three pulses occur in a time frame of 120 s, to be considered valid. When three pulses
meet these conditions, the wake signal is detected. This is illustrated by Figure 25.
MC33909
43
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
Standard Termination
CANH
C4
CAN Bus
60
CANL
C5
No Termination
CANH
C4
CAN Bus
CANL
C5
Figure 27. Typical Application and Bus Termination Options
4.3.1.3.18
State Transition
CAN5V regulator OFF only in low-power, or disable by a SPI command. CAN5V can be enabled by SPI after power up and in the INIT
state. This gains the reset, time to charge the external capacitor and have the CAN5V active in Debug and Flash modes. Refer to the
Figure 19.
4.3.1.3.19
CAN BUS Diagnostic
The aim is to implement a diagnostic of bus short-circuit to GND, VBATP, and internal ECU 5.0 V. Several comparators are implemented
on CANH and CANL lines. These comparators monitor the bus level in the recessive and dominant states. The information is then
managed by a logic circuitry to properly determine the failure and report it. Table 8 indicates the state of the comparators in case of a bus
failure, and depending upon the driver state.
Table 8. CAN Failure Detection Truth Table
Driver Recessive State
Driver Dominant State
Failure Description
Lg (threshold 1.75 V)
Hg (threshold 1.75 V)
Lg (threshold 1.75 V)
Hg (threshold 1.75 V)
No failure
1
1
0
1
CANL to GND
0
0
0
1
CANH to GND
0
0
0
0
Lb (threshold VBATP-2.0 V)
Hb (threshold VBATP-2.0 V)
Lb (threshold VBATP-2.0 V)
Hb (threshold VBATP-2.0 V)
No failure
0
0
0
0
CANL to VBATP
1
1
1
1
CANH to VBATP
1
1
0
1
4.3.1.3.20
Detection Principle
In the recessive state, if one of the two bus lines are shorted to GND or VBATP, the voltage at the other line follows the shorted line, due
to the bus termination resistance. For example: if CANL is shorted to GND, the CANL voltage is zero, the CANH voltage measured by the
Hg comparator is also close to zero.
In the recessive state, the failure detection to GND or VBATP is possible. However, it is not possible with the above implementation to
distinguish which of the CANL or CANH lines are shorted to GND or VBATP. A complete diagnostic is possible once the driver is turned
on, and in the dominant state.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
44
Functional Device Operation
H5
Hb
Vrvb
VBAT (12-14V)
VDD
VRVB (VBAT-2.0V)
VDD (5.0V)
Vrg
H5
TX
Vr5
CANH
VR5 (VDD-0.43V)
CANL
CANH dominant level (3.6V)
Logic
Diag
H5
Vrg
H5
Recessive level (2.5V)
Vrvb
VRG (1.75V)
CANL dominant level (1.4V)
H5
Vr5
GND (0.0V)
Figure 28. CAN Bus Simplified Structure Truth Table for Failure Detection
4.3.1.3.21
Number of Samples for Proper Failure Detection
The failure detector requires at least one cycle of the recessive and dominant states to properly recognize the bus failure. The error is fully
detected after five cycles of the recessive-dominant states. As long as the failure detection circuitry has not detected the same error for
five recessive-dominant cycles, the error is not reported.
4.3.1.3.22
Bus Clamping Detection
If the bus is detected to be in dominant for a time longer than (TDOM), the bus failure flag is set and the error is reported in the SPI.
Such condition could occur in case the CANH line is shorted to a high voltage. In this case, current flows from the high voltage short-circuit
through the bus termination resistors (60 ), and the device CANH and CANL input resistors, which are terminated to internal 2.5 V
biasing or to GND (sleep mode).
Depending upon the high voltage short-circuit, the number of nodes, RIN actual resistor, and node state (sleep or active), the voltage
across the bus termination can be sufficient to create a positive dominant voltage between CANH and CANL, and RXD pin is low. This
would prevent start of any CAN communication, and thus a proper failure identification (requires five pulses on TXD). The bus dominant
clamp circuit helps to determine such failure situation.
4.3.1.3.23
RX Permanent Recessive Failure
The aim of this detection is to diagnose an external hardware failure at the RX output pin and ensure a permanent failure at RX does not
disturb the network communication. If RX is shorted to a logic high signal, the CAN protocol module within the MCU does not recognize
any incoming message. In addition, it is not be able to easily distinguish the bus idle state and can start communication at any time. In
order to prevent this, an RX failure detection is necessary.
Figure 29. RX Path Simplified Schematic, RX Short to VDD Detection
MC33909
45
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
4.3.1.4
Implementation for Detection
The proposed implementation is to sense the RXD output voltage at each low to high transition of the differential receiver. Excluding the
internal propagation delay, the RXD output is low when the differential receiver is low. In case of an external short to VDD at the RXD
output, RXD is tied to a high level and can be detected at the next low to high transition of the differential receiver.
As soon as the RXD permanent recessive is detected, the RXD driver is deactivated. Once the error is detected, the flag is latched and
the driver is disabled.
4.3.1.4.1
Recovery Condition
The internal recovery is done by sampling a correct low level at TXD, as shown in Figure 30.
CANL & H
Diff output
Sampling
RXD output
RX flag
Sampling
Rx short to VDD
RX flag latched
RX no longer shorted to VDD
The RX flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register.
Figure 30. RX Path Simplified Schematic, RX Short to VDD Detection
4.3.1.4.2
Important Information for Bus Driver Reactivation
The driver stays disabled until the failure is cleared (RX is no longer permanent recessive). One transition on the CAN bus (internal
differential receiver transition) and the bus driver is activated by entering into Normal mode.
4.3.1.4.3
TXD Permanent Dominant
Principle
If the TXD is set to a permanent low level, the CAN bus is set into dominant level and no communication is possible. The device has a
TXD permanent timeout detector. After the timeout, the bus driver is disabled and the bus is released into a recessive state. The TXD
permanent flag is set.
Recovery
The TXD permanent dominant is also used and activated, in case of a TXD short to RXD. The recovery condition for a TXD permanent
dominant (recovery means the re-activation of the CAN drivers) is done by entering into a Normal mode controlled by the MCU, or when
TXD is recessive while RXD changes from recessive to dominant.
4.3.1.5
4.3.1.5.1
TXD to RXD Short-circuit
Principle
In case TXD is shorted to RXD, during incoming dominant information, RXD is set low. Consequently, the TXD pin is low and drives CANH
and CANL into a dominant state. Thus the bus is stuck in dominant. No further communication is possible.
4.3.1.5.2
Detection and Recovery
The TXD permanent dominant timeout activates and releases the CANL and CANH drivers. However, at the next incoming dominant bit,
the bus is stuck in dominant again. The recovery condition is same as the TXD dominant failure.
4.3.1.5.3
CAN Functional Pin: TXD
CAN bus transmit data input. Internal pull-up to VDD
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
46
Functional Device Operation
4.3.1.5.4
CAN Functional Pin: RXD
CAN bus receive data output.
4.3.1.5.5
CAN Functional Pin: CANH
CAN high output.
4.3.1.5.6
CAN Functional Pin: CANL
CAN low output.
4.3.1.6
LIN Interface Functional Block
The 33909 has 4 LIN interfaces which fulfill LIN protocol specification 2.1 and SAEJ2602-2. The LIN pin represents the single-wire bus
transmitter and receiver, and is suited for automotive bus systems. The LIN interface is only active during Normal mode. The CAN5V
regulator serves as the internal supply for the LIN and must be enabled for LIN functionality.
The LIN driver is a low-side MOSFET with internal overcurrent thermal shutdown. An internal pull-up resistor with a serial diode structure
is integrated, so no external pull-up components are required for the application in a slave node. An additional pull-up resistor of 1.0 k
must be added when the device is used in the master node. The LIN pin exhibits no reverse current from the LIN bus line to VBATP, even
in the event of GND shift or VBATP disconnection. The transmitter has a 20 kbps baud rate (normal mode) or 10 kbps baud rate (slow
mode) which is configurable via the SPI.
The receiver thresholds are ratiometric with the device supply pin. If the LIN voltage goes below the LIN undervoltage threshold (VUVL,
VUVH), the bus enters in recessive state, even if communication is sent on TXD. In case of LIN Thermal Shutdown, the transceiver and
receiver are disabled. When the temperature is below the TLINSD, the TSD flag must be cleared and the LIN is able to continue
communication. The LIN driver remains OFF until the TSD flag is cleared.
4.3.1.6.1
Data Input Pin (TXD)
The TXD input pin is the MCU interface to control the state of the LIN output. When TXD is LOW (dominant), LIN output is LOW; when
TXD is HIGH (recessive), the LIN output transistor is turned OFF. The threshold is 3.3 V and 5.0 V compatible. This pin has an internal
pull-up current source to force the recessive state, in case the input pin is left floating.
4.3.1.6.2
Data Output Pin (RXD)
The RXD output pin is the MCU interface, which reports the state of the LIN bus voltage. In Normal or Slow mode, LIN HIGH (recessive)
is reported by a high voltage on RXD; LIN LOW (dominant) is reported by a low voltage on RXD. In Fast mode, the RXD output signal is
inverted compare to the LIN: a high level on the LIN reports a low level on RXD, and a low level on the LIN reports a high level on RXD.
The RXD output structure is a buffer tristate output.
It is the receiver output of the LIN interface. The low level is fixed. The high level is dependant on the VDD voltage. If VDD is set at 3.3 V,
RXD VOH is 3.3 V. If VDD is set at 5.0 V, RXD VOH is 5.0 V. In the sleep mode, RXD is high-impedance. Due to internal biasing, the RXD
pin cannot be pulled up to another supply besides VDD. When a wake-up event is recognized from the LIN bus pin, RXD is pulled LOW
to report the wake-up event. For this, an external pull-up resistor connected on RXD pin is needed.
4.3.1.6.3
Normal Mode
In the Normal mode, the LIN bus can transmit and receive information. The default condition is the 20 kbps mode and has slew rate and
timing compatible with Normal Baud Rate and LIN protocol specification 2.1. The 10 kbps selection is SPI configurable and has slew rate
and timing compatible with Low Baud Rate. From Normal mode the device can enter in Fast Baud Rate (Toggle function).
4.3.1.6.4
Fast Mode
In the Fast mode, the slew rate is around 10 times faster than the Normal mode. This allows very fast data transmission (>100 kbps), for
instance, for electronic control unit (ECU) tests and microcontroller program downloads. The bus pull-up resistor might be reduced to
ensure a correct RC time constant in line with the high baud rate used. Fast mode is entered via the SPI.
MC33909
47
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
4.3.1.6.5
Sleep Mode
In the Sleep mode, the transmission path is disabled and the device is in low-power mode. Supply current from VBATP is very low. Wakeup can occur from LIN bus activity. After a wake-up event, the device enters in Awake Mode. In the Sleep mode, the internal 725 k pullup resistor is connected and the 30 k disconnected.
4.3.1.6.6
Remote Wake from LIN Bus (Awake Transitional Mode)
The LIN bus wake-up is recognized by a recessive-to-dominant transition, followed by a dominant level with a duration greater than 70 s,
followed by a dominant-to-recessive transition. This is illustrated in Figure 7 and Figure 8. Once the wake-up is detected, the device enters
to the Awake transitional mode with RXD pulled LOW.
4.3.2
Fail-safe Features
Table 9 describes the protections.
Table 9. Fail-safe Protections
Block
Fault
Function Mode
undervoltage
LIN
TXD pin
permanent
Dominant
Normal
LIN thermal
shutdown
Normal and
Awake modes
4.3.2.0.1
Condition
Fallout
Recovery
LIN voltage < 5.8 V (Typical)
LIN transmitter in recessive state
Condition gone
TXD pin low for more then 1.0 s (Typ)
LIN transmitter in recessive state
Condition gone
Temperature > 160 °C (Typ)
LIN transmitter in recessive state
High-side turned off.
Condition gone
LIN Functional Pin: LINx
LIN bus.
4.3.2.0.2
LIN Functional Pin: TXD-Lx
LIN bus transmit data input. Includes an internal pull-up resistor to VDD.
4.3.2.0.3
LIN Functional Pin: RXD-Lx
LIN bus receive data output
4.3.2.1
VPRE Regulator Functional Block
The 33909 has a VPRE pre-regulator designed to run as a non-inverting Buck - Boost supply for the VDD and VAUX power supplies. This
regulator provides efficient DC-DC conversion as well as boost operation at low input voltage (low battery). The output voltage level is
6.5 V.
The converter has both a high and low-side FET and requires a single inductor for operation. The high-side FET is integrated into the
33909. The low-side Boost FET is external. The converter uses external diodes instead of synchronous switches to reduce the number of
pins.
The 33909 has a Low-power mode to reduce quiescent current when full power is not needed by the micro. In Low-power mode, the buck
boost converter is placed in a zero quiescent current mode and a small internal regulator is employed to power the VPRE node.
The VPRE supply contains a thermal limit circuit, which is used to supply a thermal warning as well as provide a thermal limit which turns
OFF the IC. A flag exists for both of these functions. When thermal limit is reached the VPRE supply turns off. The thermal shutdown limit
was designed to be above the other IC thermal thresholds. The user should take care when the IC thermal limits are reached in order to
maintain Voltage regulator operation of VPRE and VDD.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
48
Functional Device Operation
BOOTSTRAP
VBATP
VSW
Control
VPREGATE
VBATP
COMP1 COMP2
VPRE
Figure 31. VPRE Block Diagram
4.3.2.1.1
VPRE Pin Functions:
There are four pins associated with the VPRE regulator
•
•
•
•
VPREGATE - Gate drive for low-side (Boost) FET.
VSW - Switching node of high-side (Buck) FET.
BOOT - Supply for high-side (internal) pre-driver.
VPRE - Pre-regulator output (6.5 V).
4.3.2.1.2
VPRE Pin Functions: BOOT
An external bootstrap 0.1 F capacitor connected between VSW and the BOOT pin is used to generate a high voltage supply for the highside driver circuit of the buck controller. The capacitor is pre-charged to approximately 10 V, while the internal FET is off. On switching,
the VSW pin is pulled up to VBATP, causing the BOOT pin to rise to approximately VBATP + 10 V.
4.3.2.1.3
VPRE Pin Functions: VPREGATE
This is an output for driving an external FET for boost mode operation. Due to the fact the gate drive supply voltage is VPRE, the external
power MOSFET should be a logic level device. It also has to have a low RDS(ON) for acceptable efficiency. During Buck mode, this gate
output is held low.
To use the 33909 in Buck Only mode, the VPREGATE pin is held at Ground and an internal comparator alerts the IC it is in Buck Only
mode.
4.3.2.1.4
VPRE Pin Functions: VPRE
The output of the switching regulator is brought into the chip at the VPRE pin. This voltage is required for both the switching regulator
control and as the supply voltage for all the linear regulators. The VPRE pin functions as a supply rail for some IC functions, including the
rail for the SG input current sources. The VPRE supply also supplies the CAN5V internal rail.
4.3.2.1.5
VPRE Pin Functions: VSW
The internal switching transistor is an N-channel power MOSFET. The RDS(ON) of this internal power FET is approximately 0.25  at
+125 ºC. The nominal instantaneous current limits well below the saturation current of the MOSFET and external surface mounted
inductor, to supply the current for the linear regulators connected to the VPRE pin. The input to the drain of the internal n-channel MOSFET
must be protected by an external series blocking diode, for reverse battery protection.
4.3.2.1.6
VPRE External Components
The VPRE power supply requires external components for the Buck and Boost mode architecture. The VPRE supply uses an external
inductor, MOSFET and two diodes. Buck-Boost usage case
MC33909
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Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
Usage of the Buck-Boost feature is the most widely used case. In this case, all of the external components are populated and VPRE
produces approximately 6.5 V through the full battery operation range. This use case allows the 33909 to remain fully functional during
the battery crank profile down to 2.5 V.
The Boost circuitry remains OFF when the VBATP pin is above the VBATPTHD threshold and the Buck circuitry operates as required in
Boost mode when the VBATP pin is below VBATPTHU as seen in Figure 32. In the range between VBATPTHD and VBATPTHU, the IC
operates as needed to supply VPRE at 6.5 V.
VBATP
VBATPTHD
7.5v
VBATPTHU
6.5v
VBATPBOOSTNOT
VBATPBUCKNOT
Figure 32. VPRE Buck-Boost Voltage Levels
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
50
Functional Device Operation
4.3.2.2
Buck Usage Case
A second option for the user is to use only the Buck circuitry and not the Boost circuitry (saving the added cost if Boost is not required).
When using the Buck only mode, the user does not populate the low-side FET (VPREGATE) and the associated diode. In this case, the
user grounds the VPREGATE and the 33909 detects this during startup. The VBATP pin voltage range in this mode is ~7.0 V to 35 V.
As the battery voltage decreases, the high-side switch turns ON to 100% duty cycle and operate in a “pass thru” mode. The following
figures illustrate some of the device mode transitions.
Power up to
Normal Mode
A
B
B
Normal Mode to Sleep
Mode (VDD Off)
C
B
Normal Mode to STOP
Mode (VDD On)
D
Vpre_UV
VBATP
Vpre
VDD_UV
VDD
CAN5V
VAUX
INT_B
RESET_B
6
STOP Mode
4
3
5
Normal
4
3
Sleep Mode
2
Normal
INIT
INIT RESET
Softstart Vregs
Modes
UV Lock-out
1
Normal
SPI
Notes: SPI communications.
1) INIT command
2) Watchdog refresh (INIT to Normal)
3) Normal SPI commands as needed
4) Low power configuration setup
5) Sleep mode command
6) Stop mode command
Figure 33. Power Up to Normal and to Low-power Modes
MC33909
51
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
B
D
VBATP
VBATP
Vpre
Vpre
VDD
VDD
CAN5V
CAN5V
VAUX
VAUX
INT_B
INT_B
RESET_B
RESET_B
SPI
8
7
Sleep
Mode
Normal
Request
Modes
RESET
Sleep
Mode
7
Normal
SPI
Wake up from Low Power
VDD on mode
B
8
Normal
Wake up from Low Power
VDD off mode
Normal
Request
C
CAN BUS
CAN BUS
CAN wake
up pattern
CAN wake
up pattern
LIN BUS
LIN BUS
LIN Wake
up filter
LIN Wake
up filter
SGx
SGx
FWU
Timer
FWU
Timer
Start
Start
Stop
Stop
FWU Timer (SPI selectable)
FWU Timer (SPI selectable)
Wake up detected
IDD
IDD 3mA typ
IDD deglitcher or timer
Notes:
7) SPI communications as needed
8) Watchdog refresh
9) SPI communication (except watchdog if configured)
SPI
9
Wake up detected
Figure 34. Wake-up from Low-power Modes
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
52
Functional Device Operation
4.3.2.3
VDD Supply
The VDD output is an external LDO regulator supplying +5.0 V (3.0 V selectable via a different part number) with 2.0% accuracy. The
VDD supply is capable of sourcing a maximum of 500 mA steady state current from VPRE (6.5 V typical) for VBATP pin voltages from
2.5 V to 35 V (45 V transient) [Buck only to VBATP = 7.0 V]. This regulator incorporates external current limit short-circuit protection and
internal thermal protection. The regulator remains on in current limitation. The voltage output is stable under all load/line conditions. The
VDD rail does not turn on until the specified voltage can be obtained from the VPRE node.
4.3.2.3.1
VDD Pins
There are three pins associated with the VDD regulator
• VDDE - Emitter connection for external LDO device.
• VDDB - Base connection for external LDO device.
• VDD - Feedback voltage and main supply voltage node
4.3.2.3.2
VDD Pin Functions: VDDE
Input pin used to sense the voltage (VDDSNS) across the external sense resistor from VPRE to VDDE. Current limit is derived from this
sense voltage measurement. Kelvin lines is used by the user to ensure proper voltage sensing, therefore careful layout planning is
required.
4.3.2.3.3
VDD Pin Functions: VDDB
Output pin used to for the base drive of the external LDO device.
4.3.2.3.4
VDD Pin Functions: VDD
Input pin used for feedback control loop of the VDD supply. A Kelvin trace is provided to the VDD pin for proper feedback control.
4.3.2.3.5
VDD External Components
The VDD power supply requires an external PNP be connected to the VPRE pin. The VDD supply uses an external resistor to monitor and
limit the VDDSNS voltage and provide load current limit; this is placed between the VPRE and VDDE pins.
4.3.2.4
VAUX Regulator Functional Block
The VAUX regulator uses an external PNP pass device referenced to the pre regulator voltage, VPRE, via an internal short to battery
protection switch. VAUX is capable of driving up to 200mA of load current and can be configured for an output voltage of 5.0 V or 3.3 V
with 3.0% accuracy. Additionally, VAUX can be configured as a tracking regulator. In tracking mode, VAUX tracks the VDD regulator voltage
to within 15 mV, but note that tracking mode is only possible when the VDD regulator is configured as a 5.0 V supply, as shown in the
Table 10.
The VAUX regulator is short to battery protected and current limited (200 mA min.). No external components are required for these two
features. In low-power mode, VAUX is disabled and draws zero quiescent current. Upon power up, VAUX is disabled. VAUX is enabled by
writing to bits 7 and 6 of the REG register as shown by the following:
Table 10. REG Register
Bits
b7 b6
Description
VAUX[1], VAUX[0]- Vauxilary regulator control
00
Regulator OFF
01
Regulator ON. Undervoltage (UV) and overcurrent (OC) and overvoltage (OV) monitoring flags not reported. VAUXdisable in case OC or UV
detected after 1.0 ms blanking time (monitoring of flags not reported).
10
Regulator ON. Undervoltage (UV) and overcurrent (OC) and overvoltage (OV) monitoring flags active. VAUX disable in case OC or UV
detected after 1.0 ms blanking time. (monitoring of flags not reported).
11
Regulator ON. Undervoltage (UV) and overcurrent (OC) and overvoltage (OV) monitoring flags active. VAUX disable in case OC or UV
detected after 25 μs blanking time.
MC33909
53
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
At power up, when the device is in its INIT state, the REG INIT register can be written to set VAUX to 3.3 V or 5.0 V or 5.0 V tracking, as
shown by the following:
Table 11. Setting VAUX to 3.3 or 5.0 V
Bits
b2
Description
[VAUX5/3]- Select Vauxilary output voltage
0
VAUX = 3.3 V
1
VAUX = 5.0 V
b1
Tracking Enable
0
VAUX is independent of VDD
1
VAUX tracks VDD (VAUX does not turn ON if set in 3.3 V part)
Writing to this initialization register is locked out when the device leaves the INIT state. Also, note that the logic does not allow tracking
mode if VDD is set to 3.3 V, as Table 12 illustrates.
Table 12. VAUX Tracking vs. Supply
VDD value
VAUX value
VAUX Tracking
VAUX Supply
5.0 V
5.0 V
SPI Configurable
SPI configurable
5.0 V
3.3 V
Not capable
Default
3.3 V
5.0 V
Not capable
SPI configurable
3.3 V
3.3 V
Not capable
Default
The VAUX regulator also contains a digitally controlled soft start to minimize overshoots upon power up. Also included in VAUX, is a foldback current limit.
4.3.2.4.1
VAUX Pins
There are three pins exclusively associated with the VAUX regulator
• VAUXB - This pin is connected to the base of the external PNP and provides the necessary base current.
• VAUXE - This pin is connected to the emitter of the external PNP transistor. 33909 includes short to battery blocking FET between
VPRE and VAUXE.
• VAUX - This pin is the feedback pin as well as the main supply node for supply the voltage (3.3/5.0 V).
Additionally:
• VPRE - supply to VAUX and also note all VAUX load current flows into 33909 via the VPRE pin before reaching the external PNP.
4.3.2.4.2
VAUX External Components
VAUX requires an external PNP with sufficient beta to provide up to 200 mA load current within the constraints of the max base drive
available from the VAUXB pin. Also, a capacitor is required for loop stability and transient load response.
4.3.2.4.3
VAUX Fault Mode Behavior
Current Limit: VAUX limits the load current to 200 mA minimum, 360 mA maximum. A current limit event can be reported via the SPI and
INT pin if configured as such in the REG register.
Undervoltage: After VAUX has come up, an undervoltage event can be reported via the SPI and INT pin if configured as such in the REG
register. The undervoltage event disables the VAUX regulator if configured as such in the REG register. If configured to disable, the VAUX
can only be turned back ON by re-writing to the REG register.
Overvoltage: Overvoltage, or short to VBAT causes an internal switch between the VPRE and VAUX_E to be turned off. This is done to
protect the VAUX PNP device and other things on the Vpre line. This event is not latched. When the overvoltage event has ended, the
internal switch is re-activated and VAUX returns to normal operation.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
54
Functional Device Operation
4.3.2.5
VBATSNS
The 33909 contains a VBATSNS function to allow the user to see the battery voltage via the AMUX pin. This pin connects directly to the
battery (before the series diode connected to VBATP). The VBATSNS is used for additional functions internal to the die and should have
pcb traces capable of running up to some current. The ratio of the resister divider is 1/5.94 (5.0 V part) or 1/8.9 (3.3 V part).
4.3.2.5.1
VBATSNS Pin Functions: VBATSNS
Direct battery voltage input sense. A series resistor is required to limit the input current during high voltage transients.
4.3.2.5.2
MUX Output (AMUX)
Various signals may be brought out via the analog multiplexer (AMUX) pin. The AMUX pin is referenced to VDD and can be selected via
the SPI. The signals which can be viewed on the AMUX are located in Table 13. The AMUX output pin is clamped to a maximum of VDD
volts regardless of the higher voltages present on the input pin.
For SG inputs, when an input has been selected to output on the AMUX, the corresponding bit in the MISO data stream is logic [0]. When
selecting a channel to be read out the AMUX, the user may also set the desired current (16 mA, 2.0 mA, or high-impedance) in the SPI
word. The MCU may change or update the analog select register via software at any time in Normal Mode when set for SPI selection.
Table 13. AMUX SPI Selection
Bits
Description
b8 b7 b6 b5 b4 b3
MUX_4, MUX_3, MUX_2, MUX_1, MUX_0 - Selection of the device external input signal or internal signal to be measured
at AMUX pin
0 00000
All functions disable. AMUX pin high-impedance
0 00001
Voltage at SG0
0 00101
Voltage at SG1
0 00110
Voltage at SG2
0 00111
Voltage at SG3
0 01000
Voltage at SG4
0 01011
Voltage at SG5
0 10001
Ground
0 10010
Voltage at VBATSNS pin. Refer to electrical table for attenuation ratio (approximately 6 for VDD = 5.0 V, approximately 9
for VDD = 3.3 V) [Default]
0 10011
Device internal temperature sensor voltage
A diode/circuit is brought out the AMUX pin to allow for knowledge of the temperature on the IC. The diode is characterized and a voltage/
temperature curve generated to allow for temperature monitoring of the IC.
4.3.2.5.3
MUX Pin Functions: AMUX
The MUX output delivers an internal analog voltage to the MCU A/D input. Value is selected via the SPI. Output is clamped at VDD.
MC33909
55
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
4.3.2.5.4
Undervoltage Reset And Reset Function (RST_B)
The RST_B pin is an open drain structure with an internal pull-up current source. The low-side driver has limited current capability when
asserted low, in order to tolerate a short to high level (i.e short to 5.0 V).The RST_B pin voltage is monitored in order to detect a failure
(e.g. RST_B pin shorted to 5.0 V or GND).
During sleep mode the under voltage detect circuit polls during normal scan timer periods to determine if VBATP is in an undervoltage
condition. If the IC is in under voltage the IC wakes up and issues a reset to the system.
The RESET pin reports the MCU undervoltage condition at the VDD pin, as well as a failure in the watchdog refresh operation. VDD
undervoltage reset operates also in Low-power VDD ON Mode.
The undervoltage threshold at VDD can lead to a Reset or an Interrupt. This is selected by the SPI. When “RST-TH1-5”is selected in
Normal mode, an INT is asserted when VDD falls below “RST-TH1-5”. This allows the MCU to operate in a degraded mode (e.g. with VDD
= 4.0 V).
4.3.2.5.5
RESET Pin Functions: RST_B
The RESET pin is an open drain structure with an internal pull-up current source.
4.3.2.5.6
Serial Peripheral Interface (SPI)
The 33909 contains a serial peripheral interface consisting of Serial Clock (SCLK), Serial Data Out (MISO), Serial Data In (MOSI), and
Chip Select Bar (CS_B). The SPI interface is used (as applicable) to provide configuration, control, and status functions. This device is
configured as an SPI slave. The 33909 contains a data valid method via SCLK input to keep non-modulo 32-bit transmissions from being
written into the IC.
4.3.2.5.7
Chip Select Low (CS_B)
The CS_B input selects this device for serial transfers. On the falling edge of CS_B, the MISO pin is released from tri-state mode, and all
status information are latched in the SPI shift register. While CS_B is asserted, register data is shifted in the MOSI pin and shifted out the
MISO pin on each subsequent SCLK. On the rising edge of CS_B, the MISO pin is tri-stated and the fault register reloaded (latched) with
the current filtered status data. To allow sufficient time to reload the fault registers, the CS_B pin must remain low for a minimum of tCSN
prior to going high again. The CS_B is immune to spurious pulses of shorter duration than tCSGRT (MISO may come out of tri-state, but
neither status bits nor control bits are altered).
The CS_B input contains a passive pull-up to VDD to command the de-asserted state should an open circuit condition occur. This pin has
threshold compatible voltages allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply.
4.3.2.5.8
Serial Clock (SCLK)
The SCLK input is the clock signal input for synchronization of serial data transfer. This pin has threshold compatible voltages allowing
proper operation with microprocessors using a 3.3 to 5.0 volt supply.
When CS_B is asserted, both the Master Microprocessor and this device latch input data on the rising edge of SCLK. The SPI master
typically shifts data out on the falling edge of SCLK, while this device shifts data out on the rising edge of SCLK, to allow more time to drive
the MISO pin to the proper level.
This input is used as the input for the modulo-32 bit counter validation. Any SPI transmissions which are NOT exact multiples of 32-bits
(i.e. clock edges) is treated as an illegal transmission. The entire frame aborts and no information is changed in the configuration or control
registers. The entire frame aborts and no information is changed in the configuration or control registers.
4.3.2.5.9
Serial Data Output (MISO)
The MISO output pin is in a tri-state condition when CS_B is negated. When CS_B is asserted, MISO is driven to the state of the MSB of
the internal register and is the first bit transmitted on MISO. This pin supplies a “rail to rail” output, depending on the voltage at the VDD pin.
4.3.2.5.10
Serial Data Input (MOSI)
The MOSI input takes data from the master microprocessor while CS_B is asserted. The MSB is the first bit of each word received on
MOSI and the LSB is the last bit of each word received on MOSI. This pin has a threshold level compatible input voltages allowing proper
operation with microprocessors using a 3.3 to 5.0 V (VDD) supply.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
56
Functional Device Operation
4.3.2.5.11
Secured SPI Description
A request is done by sending a specific SPI command the 33909 device provides an unpredictable “random code” on MISO. Software
must perform a logical change on the code and return it to the device with the new SPI command to perform the desired action. The
“random code” is different at every exercise of the secured procedure and can be read back at any time. The SPI secure uses the Special
MODE register for the following transitions:
- from Normal mode to Init mode
- from INIT mode to activate SAFE_B mode
- from Normal mode to Flash mode
- from Normal mode to Reset mode (reset request).
- from Normal mode to Reset SG registers (reset request).
“Random code” is also used when the “advance watchdog” is selected.
Changing of Device Critical Parameter
Some critical parameters are configured one time at device power ON only, while the batfail flag is set in the INIT mode. If a change is
required while device is no longer in INIT mode, device must be set back in INIT mode using the secured SPI procedure.
4.3.2.5.12
SPI Control Register Definition for SBC operations
The device uses a 32 -bit SPI word and does not have the ability to daisy chain to another IC. The IC decodes the first byte of the MOSI
word and supply the requested data on the following 3 bytes. In read register mode, the IC decodes the first byte and provides the full
contents of the registers called out in the address in the next three bytes. This causes the device status (12-bits) to be cut off at 8-bits.
In write register mode, the IC decodes the first byte then writes the contents of the MOSI word to the correct address. The MISO word
sends the full device status and the contents of all the SG registers. In the read flags mode, the IC decodes the first byte and provides the
full contents of the device flag depending on the address. In some cases the first bit of the second byte (bit 23 is used to determine which
registers are provided). The MISO output is the full device status along with the contents of the selected device flags address.
The SPI word structure is as follows:
MOSI, Master Out Slave In bits:
• bits 31 and 30 (called C1 and C0) are control bits to select the SPI operation mode (write control bit to device register, read back of
the control bits, read of device flag).
• bit 29 to 24 (A5 to A0) to select the register address (read and write).
• bits 23 to 0 (D23 to D0): control bits
MISO, Master IN Slave Out bits:
• bits 31 to 20 is the Device status registers (Do31 to Do20)
• bits 19 to 17 (Do19 to Do17) are unused in normal (write) MISO words.
• bits 16 to 0 (Do16 to Do0) the SGn Status register bits.
MC33909
57
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
SPI Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MOSI
C1
C0
A5
A4
A3
A2
A1
A0
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Do
10
Do9
Do8
Do7
Do6
Do5
Do4
Do3
Do2
Do1
Do0
Do6
Do5
Do4
Do3
Do2
Do1
Do0
Control bits
MISO
S31
S30
Register Address
S29
RST
INTb
WU
S28
S27
S26
TRAN-G
S25
S24
VREG-G
VPRE-G
Tlim
Data
S23
S22
LIN23-G
SAFE-G
S21
S20
S19
S18
Do
16
S17
Do
15
Do
14
Do
13
Do
12
Do
11
SG Status registers
CAN-G
LIN01-G
SG-G
Device Status
Reg
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
Do
19
Do
18
Do
17
Do
16
Device Status
Do
15
Do
14
Do
13
Do
12
Do
11
Do
10
Do9
Do8
Do7
Extended Device Status, Register Control bits or Device Flags
Figure 35. SPI Word
Table 14. SPI Control Bits
Control bits MOSI [31-30] C1-C0
Type of Command
Note
00
Read back of register content
Allows user to read back any register.
01
Write to register address, to control device operation and
read back of device status register and SG status register
set.
Write to any register for operational control.
This SPI word results in the “normal” MISO SPI
pattern.
10
Read of device flags form a register address
Read back device flags. There are multiple flag
registers containing various device information
of interest.
11
Reserved
Not used
The device contains several registers. Their address is coded on 6-bits (bits 29 to 24). Each register controls or reports part of the device
function. Data can be written to the register to control the device operation or set the default value or behavior. Every register can also be
read back to ensure its content (default setting or value previously written) is correct.
In addition, some of the registers are used to report device flags. The device returns one of three messages, a read of an existing register,
normal MISO, or a register set of Flags depending on the previous command. After a POR the default word is for the normal MISO registers
to be read out with the next word determined by the previous SPI command control bits.
MISO: When a write operation is performed to store data or control bit into the device, MISO pin report a 32-bits fixed device status
composed of 4 bytes: In a read operation, MISO reports the fixed device status (bits 31 to 24) and the next 24-bits are the content of the
selected register is the list of device registers and their associated address, coded with bits 29 to 24.
Table 15. SPI Command Overview
Address MOSI
[31-30]A29...A24
Description
Quick Reference
Name
00_0000
Unused
00_0001
Memory Word A
RAM_A
00_0010
Memory Word B
RAM_B
Initialization Regulators
Init REG
Initialization Watchdog
Init W/D
Initialization Miscellaneous functions
Init MISC
Specific Modes
SPE_MODE
00_0011
00_0100
Functionality
1) Write “data word” to register address. 2) Read back “data word”
from register address
1) Write “device initialization control bits” to register address. 2)
Read back “initialization control bits” from register address
1) Write to register to select device Specific Mode, using “Inverted
Random Code”. 2) Read “Random Code”.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
58
Functional Device Operation
Table 15. SPI Command Overview (continued)
Address MOSI
[31-30]A29...A24
Description
Quick Reference
Name
Functionality
Timer_A: W/D & Low-power MCU
consumption
TIM_A
Timer_B: Periodic scan & Cyclic Interrupt
TIM_B
Timer_C: W/D Low-power & Forced Wakeup
TIM_C
00_0110
Analog Multiplexer
MUX
1) Write “device control bits” to register address. 2) Read back
register “control bits”
00_0111
Watchdog Refresh
W/D
Watchdog Refresh Commands
00_1000
Interrupt Control
Interrupt
1) Write “device control bits” to register address, to select device
operation. 2) Read back register “control bits”
1) Write to register to select Low-power mode, with optional
“Inverted Random code” and select wake-up functionality. 2)
Read operations: Read back device “Current Mode” Read
“Random Code”, Leave “Debug Mode”
00_0101
1) Write “timing values” to register address. 2) Read back register
“timing values”
00_1001
Mode register
MODE
00_1010
Regulator Control
REG
00_1011
CAN interface control
CAN
00_1100
LIN 0-1
LIN01
00_1101
LIN 2-3
LIN23
00_1110
SG wake-up enable
SGWU
Enable for wake-up from sleep after a change of state for SG
inputs: Wake-up enable = 1, Non-wake-up = 0 (Default = 1)
00_1111
Fast scan for SG5-0
SGFS
Enable polling at 1.0 ms for fast wake-up independent of nominal
sleep polling timer: Override polling settings for SG5-0 to 
1.0 ms = 1, use polling setting as defined in sleep state command
= 0 (Default = 0)
01_0000
SG wake-up delay enable
SGWUD
Enable for wake-up from sleep after a change of state for SG
inputs after three consecutive polling results confirming change of
state: Wake-up enable = 1, Non-wake-up = 0 (Default = 0)
01_0001
Wetting Command Register 0
SGM0
Configure Wetting current sources to desired current level for
SG4-0 (Default = 101 = 16 mA)
01_0010
Wetting Command Register 1
SGM1
Configure Wetting current sources to desired current level for
SG5 (Default = 101 = 16 mA)
01_0011
Wetting current timer
SGMT
Enable Wetting current source timer: Enable Wetting current
source timer = 1, disable – Wetting current ON full time = 0
(Default = 1)
01_0100
Tri-state command
SGT
Enable tristate at input: Enable tristate = 1, Input active = 0
(Default = 1)
1) Write “device control bits” to register address, to select device
operation. 2) Read back register “control bits”. 3) Read device
flags from each of the register addresses.
Additionally, there are three specific SPI words to carry out certain functions on the IC.
Table 16. SPI Specific Instructions
SPI MOSI Word
Function
Resulting Behavior
0x5E000000
Command Part of Watchdog Inhibit mode
Even with WDI pin > 10 V, IC leaves WD Inhibit mode (requires WD refreshed)
0x5F000000
Acknowledge Safe condition
Clears SAFE registers and unasserts SAFE_B pin (after SAFE condition is gone)
0x49000010
Wake-up via the SPI
Wakes the IC from low-power mode (VDD ON) with specific SPI word
MC33909
59
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
Table 17. Overview Individual Bits
Type of Command
Read back of “device control bits”
MOSI/
MISO
Control
bits [31-30]
MOSI
00
MISO
Write device control bit to address selected by bits
(29-24). MISO return 32-bits status
Read device flags and wake-up flags, from register
address (bit29-24). MISO return fixed device status
(bit 31-20) + flags from the selected address
(requires a double write)
MOSI
MISO
MOSI
MISO
Address [29-24]
Bits [23-0]
address
All 0’s (except when noted)
Device Fixed Status (8 bits)
01
Register control bits content
address
Control Bits
Device Fixed Status (12 bits)
10
Normal MISO status registers
Read of device flags from a register
address, and sub address LOW (bit 23)
address
Device Fixed Status (12 bits)
Flag Registers
Table 18. MISO Device Status Bits Description
Flag
Description
INT
Indicates an INT has occurred and INT flags are pending to be read.
WU
Indicates a Wake-up has occurred and Wake-up flags are pending to be read.
RST
Indicates an Reset has occurred and the flags reporting the Reset source are pending to be read.
TLIM
Indicates a TLIM has occurred and TLIM flags are pending to be read.
TRAN-G
The INT, or WU or RST source is a transceiver interface (CAN or LIN).
VPRE-G
The INT, or WU or RST source is the VPRE switch mode power supply.
VREG-G
The INT, or WU or RST source is a regulator supply (VDD or VAUX).
SAFE_B-G
The INT, or WU or RST source is from a SAFE condition.
LIN23-G
The INT, or WU or RST source is a LIN bus (LIN2 or LIN3).
LIN01-G
The INT, or WU or RST source is a LIN bus (LIN0 or LIN1).
CAN-G
The INT, or WU or RST source is CAN interface. CAN local or CAN bus source.
SG-G
The INT, or WU or RST source is SG interface, flag from SG inputs.
Table 19. Internal Memory Registers A and B, RAM_A and RAM_B
MOSI First Byte [31-24] [b_31
b_30] 00_0xxx
MOSI, bits 23-0
a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10
Default state
a7
a6
a5
a4
a3
a2
a1
a0
POR
Rb2 Rb2 Rb2 Rb2 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1
Rb9 Rb8 Rb7 Rb6 Rb5 Rb4 Rb3 Rb2 Rb1 Rb0
3
2
1
0
9
8
7
6
5
4
3
2
1
0
Default state
0
Condition for default
RAM_B
00_0010
a8
0
Condition for default
RAM_A
00_0001
a9
POR
Rb2 Rb2 Rb2 Rb2 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1 Rb1
Rb9 Rb8 Rb7 Rb6 Rb5 Rb4 Rb3 Rb2 Rb1 Rb0
3
2
1
0
9
8
7
6
5
4
3
2
1
0
Default state
Condition for default
0
POR
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
60
Functional Device Operation
Table 20. Initialization Registers - Regulator, INIT REG
MOSI bits
[31-24]
[b_31 b_30] 00_0011
MOSI bits 7-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00_0011
VPRE_Disable
VDDLrst[1]
VDDLrst[0]
VDDrstD[1]
VDDrstD[0]
VAUX5/3
VAUXtracker
Unused
Default state
0
0
0
1
0
0
0
0
Condition for default
POR/Reset
Table 21. Individual Bits (Watchdog)
Bit
Description
b7
VPRE_Disable
0
VPRE is enabled and used by the IC
1
Disable VPRE internal circuitry (use external source to power VPRE node)
b6, b5
VDDLRST[1] VDDL RST[0] - Select the VDD undervoltage threshold, to activate Reset pin and/or INT
00
Reset at approximately 0.9 VDD.
01
INT at approximately 0.9 VDD, Reset at approximately 0.7 VDD
10
Reset at approximately 0.7 VDD
11
Reset at approximately 0.9 VDD
b4, b3
VDDRSTD[1] VDDRSTD[0] - Select the Reset pin low lev duration, after VDD rises above the VDD undervoltage threshold
00
1.0 ms
01
5.0 ms
10
10 ms [Default]
11
20 ms
b2
[VAUX5/3]- Select Vauxilary output voltage
0
VAUX = 3.3 V
1
VAUX = 5.0 V
b1
Tracking Enable
0
VAUX is independent of VDD
1
VAUX tracks VDD (ignored if VDD and VAUX not set to 5.0 V)
b0
Unused
Table 22. Initialization Registers - Watchdog
MOSI bits 15-8
MOSI bits [31-24] [b_31
b_30] 00_0011
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
00_0011
WD2INT
MCU_OC
OC-TIM
WD SAFE_B[1]
WD
SAFE_B[0]
WD_spi[1]
WD_spi[0]
WD N/Win
Default state
0
0
0
0
0
0
0
0
Condition for default
POR
MC33909
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Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
Table 23. Individual Bits (Watchdog)
Bit
b15
Description
WD2INT - Select the maximum time delay between INT occurrence and INT source read SPI command
0
Function disabled. No constraint between INT occurrence and INT source read.
1
INT source read must occur before the remaining of the current W/D period plus 2 complete W/D periods.
b14, b13
MCU_OC, OC-TIM - In Low-power VDDON, select watchdog refresh and VDD current monitoring functionality.VDD_OC_LP threshold
is defined in device electrical parameters (approximately 2.0 mA)
In low-power mode, W/D is not selected
no W/D + 00
In Low-power VDD ON mode, VDD overcurrent has no effect.
no W/D + 01
In Low-power VDD ON mode, VDD overcurrent has no effect.
no W/D + 10
In Low-power VDD ON mode, VDD current > VDD_OC_LP threshold for a time > I_mcu_OC is a wake-up event. I_mcu_OC time is
selected in Timer register (selection range from 0.1 to 32 ms – 8 total options).
no W/D + 11
Unused
In low-power mode W/D is selected
W/D + 00
In Low-power VDD ON mode, VDD current > VDD_OC_LP threshold has no effect. W/D refresh must occur by SPI command.
W/D + 01
In Low-power VDD ON mode, VDD current > VDD_OC_LP threshold has no effect. W/D refresh must occur by SPI command.
W/D + 10
In Low-power VDD ON mode, VDD current > VDD_OC_LP threshold for a time < I_mcu_OC is a W/D refresh condition. VDD current >
VDD_OC_LP threshold for a time > I_mcu_OC is wake-up event. I_mcu_OC time is selected in Timer register (selection range from 0.1
to 32 ms – 8 total options)
W/D + 11
Unused
b12, b11
WD SAFE_B - Select the activation of the SAFE_B pin low, at first or second consecutive RESET pulse.
00
SAFE_B pin is set low at the time of the RESET pin low activation
01
SAFE_B pin is set low at the second consecutive time RESET pulse
10
SAFE_B pin is set low at the third consecutive time RESET pulse
11
SAFE_B pin is set low at the fifth consecutive time RESET pulse
b10, b9
WD_spi[1] WD_spi[0] - Select the Watchdog (W/D) Operation
00
Simple Watchdog selection: W/D refresh done by a 8 bits or 32 bits SPI
01
Enhanced 1: Refresh is done using the Random Code, and by a single 32 bits.
10
Enhanced 2: Refresh is done using the Random Code, and by two 32 bit commands.
11
Enhanced 4: Refresh is done using the Random Code, and by four 32 bit commands.
b8
WD N/Win - Select the Watchdog (W/D) Window or Timeout operation
0
Watchdog operation is TIMEOUT, W/D refresh can occur anytime in the period
1
Watchdog operation is WINDOW, W/D refresh must occur in the open window (second half of period)
Table 24. Initialization Registers - Miscellaneous, INIT MISC
MOSI, bits 23-16
MOSI bits [31-24]
[b_31 b_30] 00_0011
bit 23
00_0011
LPM w RND
Default state
0
Condition for default
bit 22
bit 21
bit 20
bit 19
AMUX config INT_B pulse INT_B width INT_B flash
0
0
0
0
bit 18
bit 17
bit 16
SAFE_B[2]
SAFE_B[1]
SAFE_B[0]
0
0
0
POR
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
62
Functional Device Operation
Table 25. Individual Bits (INIT MISC)
Bit
b23
Description
LPM w RND - Select the functionality to change mode (enter in Low-power) using the device Random Code
0
Function disable: the Low-power mode can be entered without usage of Random Code
1
Function enabled: the Low-power mode is entered using the Random Code
b22
AMUX SPI configured
0
AMUX is determined by the SPI
1
N/A
b21
INT_B pulse - Select INT pin operation: low level pulse or low level
0
INT_B pin asserts a low level pulse, duration selected by bit [b4]
1
INT_B pin assert a permanent low level (no pulse)
b20
INT_B width - Select the INT pulse duration
0
INT_B pulse duration is typ. 100 μs. Refer to dynamic parameter table for exact value.
1
INT_B pulse duration is typ. 25 μs. Refer to dynamic parameter table for exact value.
b19
INT_B flash - Select INT pulse generation at 50% of the Watchdog Period in Flash mode
0
Function disable
1
Function enable: an INT pulse occurs at 50% of the Watchdog Period when device in Flash mode.
b18, b17, b16
SAFE_B[2], SAFE_B[1], SAFE_B[0] - Set state of Safe operation
0xx
Function disable (W/D inhibit mode)
100
RB3
101
RB2
110
RB1
111
RA
Table 26. Specific Mode Register SPE-MODE
MOSI, bits 7-0
MOSI bits [31-24]
[b_31 b_30] 00_0100
MOSI bits
23-11
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00_0100
Unused
Rnd_C7b
Rnd_C6b
Rnd_C5b
Rnd_C4b
Rnd_C3b
Rnd_C2b
Rnd_C1b
Rnd_C0b
Default state
0
0
0
0
0
0
0
0
Condition for default
POR
Table 27. Specific Mode Register SPE-MODE
MOSI bits [31-24]
MOSI bits 2311
[b_31 b_30] 00_0100
MOSI, bits 10-8
bit 10
bit 9
bit 8
00_0100
Unused
Sel_Mod[2]
Sel_Mod[1]
Sel_Mod[0]
Default state
0
0
0
0
Condition for default
POR
MC33909
63
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
Table 28. Individual Bit Description (SPE-MODE)
Bit
b10, b9, b8
Description
Sel_Mod[2] Sel_Mod[1], Sel_Mod[0]- Mode selection: these 3 bits are used to select which mode the device enters upon a SPI
command.
000
RESET mode
001
INIT mode
010
FLASH mode
011
RESET SG inputs
100 - 111
b7....b0
N/A
[Rnd_C7b... Rnd_C0b]- Random Code inverted, these 8 bits are the inverted bits obtained from the SPE-MODE Register read
command.
The SPE MODE register is used for the following operation:
- Set the device in Reset mode, to exercise or test the Reset functions.
- Go to Init mode, using the Secure SPI command.
- Go to Flash mode (in this mode the watchdog timer can be extended up to 32 sec).
- Reset the registers for SG (switch to ground) inputs only.
- Activate the SAFE_B pin by S/W.
These mode (called Special Mode) are accessible via secured SPI command, which consist in two commands:
1. Reading a random code and
2. Write the inverted random code plus mode selection or SAFE_B pin activation:
Return to INIT mode is done as follow (this is done from Normal mode only):
1. Read random code:
MOSI: 0000 0100 0000 0000 0000 0000 0000 0000 [Hex:0x 04 00 00 00]
MISO report 32 bits, random code are bits (7-0)
MISO = xxxx xxxx xxxx xxxx xxxx xxxx R7 R6 R5 R4 R3 R2 R1 R0 (Rx = 8 bits random code)
2. Write INIT mode + random code inverted
MOSI: 0100 0100 0000 0000 0000 0001 Ri7 Ri6 Ri5 Ri4 Ri3 Ri2 Ri1 Ri0 [Hex:0x 44 00 01 HH] (Rix = random code inverted)
MISO: xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx (don't care)
SAFE_B pin activation: SAFE_B pin can be set low, in INIT and Normal mode, with following commands:
1. Read random code:
MOSI: 0000 0100 0000 0000 0000 0000 0000 0000 [Hex:0x 04 00 00 00]
MISO report 32 bits, random code are bits (7-0)
MISO = xxxx xxxx xxxx xxxx xxxx xxxx R7 R6 R5 R4 R3 R2 R1 R0 (Rx = 8 bits random code)
2. Write INIT mode + random code bits 7:6 not inverted and random code bits 5:0 inverted
MOSI: 0100 0100 0000 0000 0000 0001 R7 R6 Ri5 Ri4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 44 00 01 HH] (Ri7-6 = random code, Ri5-0 = random
code inverted)
MISO: xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx (don't care)
Go to Reset mode is done as follow (this is done from Normal mode only):
1. Read random code:
MOSI: 0000 0100 0000 0000 0000 0000 0000 0000 [Hex:0x 04 00 00 00]
MISO report 32 bits, random code are bits (7-0)
MISO = xxxx xxxx xxxx xxxx xxxx xxxx R7 R6 R5 R4 R3 R2 R1 R0 (Rx = 8 bits random code)
2. Write Reset mode + random code bits inverted
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
64
Functional Device Operation
MOSI: 0100 0100 0000 0000 0000 0000 Ri7 Ri6 Ri5 Ri4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 44 00 00 HH] (RiX = random code inverted)
MISO: xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx (don't care)
Go to Flash mode is done as follow (this is done from Normal mode only):
1. Read random code:
MOSI: 0000 0100 0000 0000 0000 0000 0000 0000 [Hex:0x 04 00 00 00]
MISO report 32 bits, random code are bits (7-0)
MISO = xxxx xxxx xxxx xxxx xxxx xxxx R7 R6 R5 R4 R3 R2 R1 R0 (Rx = 8 bits random code)
2. Write INIT mode + random code bits 7:6 not inverted and random code bits 5:0 inverted
MOSI: 0100 0100 0000 0000 0000 0010 Ri7 Ri6 Ri5 Ri4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 44 00 02 HH] (RiX = random code inverted)
MISO: xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx (don't care)
Reset SG registers is done as follow (this is done from Normal mode only):
1. Read random code:
MOSI: 0000 0100 0000 0000 0000 0000 0000 0000 [Hex:0x 04 00 03 00]
MISO report 32 bits, random code are bits (7-0)
MISO = xxxx xxxx xxxx xxxx xxxx xxxx R7 R6 R5 R4 R3 R2 R1 R0 (Rx = 8 bits random code)
2. Write SG reset mode + random code bits inverted
MOSI: 0100 0100 0000 0000 0000 0011 Ri7 Ri6 Ri5 Ri4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 44 00 03 HH] (RiX = random code inverted)
MISO: xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx (don't care).
Table 29. Watchdog and Low-power MCU Consumption, TIM_A
MOSI, bits 7-0
MOSI bits [31-24]
[b_31 b_30] 00_0101
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00_0101
I_mcu[2]
I_mcu[1]
I_mcu[0]
W/D Nor[4]
W/D_N[3]
W/D_Nor[2]
W/D_N[1]
W/D_Nor[0]
Default state
0
0
0
1
1
1
1
0
Condition for default
POR
Table 30. Individual Bit Description for I_mcu Timer
Typical Timing Value (in ms)
b7
b6, b5
00
01
10
11
0
3 (def)
6
12
24
1
4
8
16
32
Table 31. Individual Bit Description for Watchdog Period in Device Normal Mode
Typical Timing Value (in ms)
b2, b1, b0
b4, b3
000
001
010
011
100
101
110
111
00
2.5
5
10
20
40
80
160
320
01
3
6
12
24
48
96
192
384
10
3.5
7
14
28
56
112
224
448
11
4
8
16
32
64
128
256 (def)
512
MC33909
65
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
Table 32. Timer Register B, Periodic Scan and Cyclic INT, in Device Low-power Mode, TIM_B
MOSI, bits 15-8
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Cyc-sen[3]
Cyc-sen[2]
Cyc-sen[1]
Cyc-sen[0]
Cyc-int[3]
Cyc-int[2]
Cyc-int[1]
Cyc-int[0]
1
1
0
0
0
0
0
0
Default state
Condition for default
POR
Table 33. Individual Bit Description for Periodic Scan
Typical Timing Value (in ms)
b14, b13, b12
b15
000
001
010
011
100
101
110
111
0
3
6
12
24
48
96
192
384
1
4
8
16
32
64 (def)
128
256
512
Table 34. Individual Bit Description for Periodic Interrupt
Typical Timing Value (in ms)
b10, b9, b8
b11
000
001
010
011
100
101
110
111
0
6 (def)
12
24
48
96
192
384
768
1
8
16
32
64
128
258
512
1024
Table 35. Timer Register C, Watchdog LP Mode and Forced Wake-up Timer, TIM_C
MOSI bits 23-16
Default state
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
WD-LP-F[3]
WD-LP-F[2]
WD-LP-F[1]
WD-LP-F[0]
FWU[3]
FWU[2]
FWU[1]
FWU[0]
0
0
0
0
0
0
0
0
Condition for default
POR
Table 36. Individual Bit Description for Watchdog in Low-power VDD ON Mode
Typical Timing Value (in ms)
b22, b21, b20
b23
000
001
010
011
100
101
110
111
0
12 (def)
24
48
96
192
384
768
1536
1
16
32
64
128
256
512
1024
2048
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
66
Functional Device Operation
Table 37. Individual Bit Description for Watchdog in Flash Mode
Typical Timing Value (in ms)
b22, b21, b20
b23
000
001
010
011
100
101
110
111
0
48 (def)
96
192
384
768
1536
3072
6144
1
256
512
1024
2048
4096
8192
16384
32768
Table 38. Individual Bit Description for Forced Wake-up
Typical Timing Value (in ms)
b18, b17, b16
b19
000
001
010
011
100
101
110
111
0
48 (def)
96
192
384
768
1536
3072
6144
1
64
128
258
512
1024
2048
4096
8192
Table 39. AMUX
MOSI, bits 7-0
MOSI First Byte [31-24]
[b_31 b_30] 00_0110
MOSI, bits
23-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00_0110
Unused
MUX_4
MUX_3
MUX_2
MUX_1
MUX_0
Unused
Unused
Unused
Default state
0
0
0
0
0
0
0
0
0
Condition for default
POR
Table 40. Individual Bits AMUX
Bits
Description
MUX_4, MUX_3, MUX_2, MUX_1, MUX_0 - Selection of the device external input signal or internal signal to be measured at AMUX
b8 b7 b6 b5 b4 b3 pin
0 00000
All functions disable. AMUX pin high-impedance.
0 00001
Voltage at SG0
0 00101
Voltage at SG1
0 00110
Voltage at SG2
0 00111
Voltage at SG3
0 01000
Voltage at SG4
0 01011
Voltage at SG5
0 10010
Voltage at VBATSNS pin. Refer to electrical table for attenuation ratio (approximately 6 for VDD = 5.0 V, approximately 9 for 
VDD = 3.3 V) [Default].
0 10011
Device internal temperature sensor voltage
MC33909
67
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
Table 41. Watchdog Refresh Register, W/D
MOSI bits [31-24]
[b_31 b_30] 00_0111
MOSI bits
23-8
00_0111
Default state
MOSI bits 7-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Condition for default
POR
Table 42. INT_B Register(25)
MOSI bits 7-0
MOSI bits [31-24]
[b_31 b_30] 00_1000
MOSI bits
23-9
bit8
bit 7
bit 6
bit 5
bit 4
bit 3
00_1000
Unused
MCU req
LIN3 fail
LIN2fail
LIN1 fail
LIN0 fail
SAFE_B
0
0
0
0
0
0
Default state
Condition for default
bit 2
0
bit 1
bit 0
CAN
failure
Vmon
0
0
POR
Notes
25. The first time the device is set in Normal mode, the CAN is in Sleep wake-up enable (10). The next time device is set in Normal mode, the CAN
state is controlled by the bit7 and bit6 states.
Table 43. Individual Bit Description (INT_B Register)
Bits
Description
b8
MCU req- Control bit to request an INT. INT occurs once when the bit is enabled.
0
INT disable
1
INT enable
b7
LIN3 Fail
0
INT disable
1
INT enable
b6
LIN2 Fail
0
INT disable
1
INT enable
b5
LIN1 Fail
0
INT disable
1
INT enable
b4
LIN0 Fail
0
NT disable
1
INT enable
b3
SAFE_B- description to be done
0
INT disable
1
INT enable
b2
0
INT disable
1
INT enable
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
68
Functional Device Operation
Table 43. Individual Bit Description (INT_B Register) (continued)
Bits
Description
b1
CAN failure- control bit for CAN failure INT (CANH/L to GND, VDD or VBATP, CAN overcurrent, Driver Over Temp, TX-PD, RX-PR,
RX2HIGH, and CANBUS Dominate clamp)
0
INT disable
1
INT enable
b0
Vmon- enable interruption by voltage monitoring of one of the voltage regulator: VAUX, CAN5V, VDD(IDD overcurrent, overvoltage,
undervoltage), VSUV, VSOV, VBATP_BATFAIL, CAN5V low or thermal shutdown, VAUXlow or VAUXovercurrent
0
INT disable
1
INT enable
Table 44. MODE Register, MODE
MOSI bits [31-24]
[b_31 b_30] 00_1001
MOSI bits
23-8
00_1001
Default state
MOSI bits 7-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unused
Mode[4]
Mode[3]
Mode[2]
Mode[1]
Mode[0]
Rnd_b[2]
Rnd_b[1]
Rnd_b[0]
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Table 45. Individual Bit Description for Low-power VDD OFF Selection and Operation Mode
Low-power VDD OFF Selection and Function
b7, b6, b5, b4, b3
FWU
Periodic Sense
0 1100
OFF
OFF
0 1101
OFF
ON
0 1110
ON
OFF
0 1111
ON
ON
Table 46. Individual Bit Description for Low-power VDD ON Selection and Operation Mode
Low-power VDDON Selection and Function
b7, b6, b5, b4, b3
FWU
Periodic Sense
Periodic INT
Watchdog
1 0000
OFF
OFF
OFF
OFF
1 0001
OFF
OFF
OFF
ON
1 0010
OFF
OFF
ON
OFF
1 0011
OFF
OFF
ON
ON
1 0100
OFF
ON
OFF
OFF
1 0101
OFF
ON
OFF
ON
1 0110
OFF
ON
ON
OFF
1 0111
OFF
ON
ON
ON
1 1000
ON
OFF
OFF
OFF
1 1001
ON
OFF
OFF
ON
1 1010
ON
OFF
ON
OFF
1 1011
ON
OFF
ON
ON
1 1100
ON
ON
OFF
OFF
MC33909
69
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
Table 46. Individual Bit Description for Low-power VDD ON Selection and Operation Mode (continued)
Low-power VDDON Selection and Function
b7, b6, b5, b4, b3
FWU
Periodic Sense
Periodic INT
Watchdog
1 1101
ON
ON
OFF
ON
1 1110
ON
ON
ON
OFF
1 1111
ON
ON
ON
ON
Table 47. REGULATOR Register, REG
MOSI bits [31-24]
[b_31 b_30] 00_1010
MOSI bits
23-8
00_1010
Default state
MOSI bits 7-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unused
VAUX[1]
VAUX[0]
Unused
CAN5V[1]
CAN5V[0]
Unused
Unused
VDDoff en
0
0
0
N/A
0
0
N/A
N/A
N/A
Condition for default
POR
POR
Table 48. Individual Bit Description (REG)
Bits
b7 b6
Description
VAUX[1], VAUX[0]- Vauxilary regulator control
00
Regulator OFF
01
Regulator ON. Undervoltage (UV) and overcurrent (OC) and overvoltage (OV) monitoring flags not reported. VAUX disable in case
OC or UV detected after 1.0 ms blanking time (monitoring of flags not reported).
10
Regulator ON. Undervoltage (UV) and overcurrent (OC) and overvoltage (OV) monitoring flags active. VAUX disable in case OC or
UV detected after 1.0 ms blanking time. (monitoring of flags not reported).
11
Regulator ON. Undervoltage (UV) and overcurrent (OC) and overvoltage (OV) monitoring flags active. VAUX disable in case OC or
UV detected after 25 μs blanking time.
b4 b3
CAN5V[1], CAN5V[0]- CAN5V regulator control
00
Regulator OFF
01
Regulator ON. Thermal protection active. Undervoltage (UV) and overcurrent (OC) monitoring flags not reported.
10
Regulator ON. Thermal protection active. Undervoltage (UV) and overcurrent (OC) monitoring flags active.
11
Regulator ON. Thermal protection active. Undervoltage (UV) and overcurrent (OC) monitoring flags active. CAN5V disable in case
OC or UV detected after 25 μs blanking time.
b0
VDDoff en - Control bit to allow transition into Low-power VDDOFF mode (to prevent VDD turn OFF)
0
Disable Usage of Low-power VDD OFF mode
1
Enable Usage of Low-power VDD OFF mode
Table 49. CAN Registers, CAN(26)
MOSI bits 7-0
MOSI bits [31-24]
[b_31 b_30] 00_1011
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00_1011
Unused
Unused
Unused
CMFB Enable
Wake-up 1/3
CAN
mod[1]
CAN
mod[0]
CAN int
Default state
0
0
0
0
0
1
0
0
Condition for default
POR
note
POR
Note:
26. The first time the device is set in Normal mode, the CAN is in Sleep wake-up enable (10). The next time the device is set in Normal mode, the
CAN state is controlled by the bit 2 and bit 1 states.
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
70
Functional Device Operation
Table 50. Individual Bit Description (CAN)
Bits
Description
b4
CMFB enable for CAN
0
Common Mode Feed Back circuit is turned off
1
Common Mode Feed Back circuit is turned on
b3
Wake-up 1/3- Selection of CAN wake-up mechanism
0
Three dominant pulses wake-up mechanism
1
Single dominant pulse wake-up mechanism
CAN mod[1], CAN mod[0]- CAN interface mode control, wake-up enable/disable
b2 b1
00
CAN interface in sleep mode, CAN wake-up disable.
01
CAN interface in receive only mode, CAN driver disable.
10
CAN interface is in sleep mode, CAN wake-up enabled. In device low-power mode, CAN wake-up is reported by device wake-up. In
device normal mode, CAN wake-up reported by INT and Flags generated.
11
CAN interface in transmit and receive mode
b0
CAN INT - Select the CAN failure detection reporting
0
Select INT generation when a bus failure is fully identified and decoded (i.e. after five dominant pulses on TxCAN)
1
Select INT generation as soon as a bus failure is detected, event if not fully identified.
Table 51. LIN 0-1 Register
MOSI bits [31-24]
[b_31 b_30] 00_1100
MOSI bits
23-10
00_1100
Unused
Default state
0
MOSI bits 9-0
bit 9
bit 8
LIN1
LIN1mode
mode[1]
[0]
1
bit 7
bit 6
LIN1 Slew
rate[1]
LIN1 Slew
rate[0]
0
0
0
Condition for default
bit 5
bit 4
bit 3
LIN1
LIN0
LIN0
J260
mode[1] mode[0]
2
0
1
bit 2
bit 1
bit 0
LIN0 Slew
rate[1]
LIN0 Slew
rate[0]
LIN0
J2602
0
0
0
0
POR
Table 52. Individual Bit Description (LIN0-1)
Bits
b9 b8
Description
LIN1 mode [1], LIN1 mode [0]- LIN 1 interface mode control, wake-up enable/disable
00
LIN1 disable, wake-up capability disable
01
not used
10
LIN1 disable, wake-up capability enable
11
LIN1 Transmit Receive mode
b7 b6
Slew rate[1], Slew rate[0] LIN 1 slew rate selection
00
Slew rate for 20 kbit/s baud rate
01
Slew rate for 10 kbit/s baud rate
10
Slew rate for fast baud rate
11
Slew rate for fast baud rate
b5
LIN1 J2602
0
LIN1 remain recessive
1
LIN1 operates below 6 V
MC33909
71
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
Table 52. Individual Bit Description (LIN0-1) (continued)
Bits
Description
LIN0 mode [1], LIN0 mode [0]- LIN 0 interface mode control, wake-up enable/disable
b4 b3
00
LIN0 disable, wake-up capability disable
01
not used
10
LIN0 disable, wake-up capability enable
11
LIN0 Transmit Receive mode
Slew rate[1], Slew rate[0] LIN0 slew rate selection
b2 b1
00
Slew rate for 20 kbit/s baud rate
01
Slew rate for 10 kbit/s baud rate
10
Slew rate for fast baud rate
11
Slew rate for fast baud rate
b0
LIN0 J2602
0
LIN0 remain recessive
1
LIN0 operate below 6.0 V
Table 53. LIN 2-3 Register
MOSI bits [31-24]
[b_31 b_30] 00_1101
MOSI
bits 2310
00_1101
Unused
Default state
0
MOSI bits 9-0
bit 9
bit 8
LIN3
LIN3
mode[1] mode[0]
1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LIN3
Slew
rate[1]
LIN3 Slew
rate[0]
LIN3 J2602
LIN2
mode[1]
LIN2
mode[0]
LIN2 Slew
rate[1]
LIN2
Slew
rate[0]
LIN2
J2602
0
0
0
1
0
0
0
0
0
Condition for default
POR
Table 54. Individual Bit Description (LIN2-3)
Bits
b9 b8
Description
LIN3 mode [1], LIN3 mode [0]- LIN 3 interface mode control, wake-up enable/disable
00
LIN3 disable, wake-up capability disable
01
Not used
10
LIN3 disable, wake-up capability enable
11
LIN3 Transmit Receive mode
b7 b6
Slew rate[1], Slew rate[0] LIN 3 slew rate selection
00
Slew rate for 20 kbit/s baud rate
01
Slew rate for 10 kbit/s baud rate
10
Slew rate for fast baud rate
11
Slew rate for fast baud rate
b5
LIN3 J2602
0
LIN3 remain recessive
1
LIN3 operate below 6.0 V
b4 b3
00
LIN2 mode [1], LIN2 mode [0]- LIN2 interface mode control, wake-up enable/disable
LIN2 disable, wake-up capability disable
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
72
Functional Device Operation
Table 54. Individual Bit Description (LIN2-3) (continued)
Bits
Description
01
Not used
10
LIN2 disable, wake-up capability enable
11
LIN2 Transmit Receive mode
Slew rate[1], Slew rate[0] LIN 2 slew rate selection
b2 b1
00
Slew rate for 20 kbit/s baud rate
01
Slew rate for 10 kbit/s baud rate
10
Slew rate for fast baud rate
11
Slew rate for fast baud rate
b5
LIN2 J2602
0
LIN2 remain recessive
1
LIN2 operate below 6.0 V
Table 55. SG Wake-up Enable
MOSI bits 23-0
MOSI bits [31-24]
[b_31 b_30] 00_1110
bit 23-17
bit 15-11
bit 10
00_ 1110
Unused
Unused
SG5
Default state
0
1
bit 9
bit 8
Unused Unused
bit 7
bit 6
bit 5
bit 4
SG4
SG3
SG2
SG1
bit 3
bit 2
bit 1
Unused Unused Unused
bit 0
SG0
1
Condition for default
POR/Reset command
Table 56. SG5-0 Fast Scan Enable
MOSI bits 23-0
MOSI bits [31-24]
[b_31 b_30] 00_1111
bit 23-17
bit 15-0
bit 10
00_ 1111
Unused
Unused
SG5
Default state
0
0
bit 9
bit 8
Unused Unused
bit 7
bit 6
bit 5
bit 4
SG4
SG3
SG2
SG1
bit 3
bit 2
bit 1
Unused Unused Unused
bit 0
SG0
0
Condition for default
POR/Reset command
Table 57. Individual Bit Description (SG5-0 Fast Scan Enable)
Bits
Description
SG5-0 (Default = 0)
b10,b7-4,b0
0
Use normal wake-up timing as defined in sleep state command.
1
Enables fast wake-up at 1.0 ms polling independent of normal wake-up selected in sleep state command.
Table 58. SG Wake-up Delay Enable
MOSI bits 23-0
MOSI bits [31-24]
[b_31 b_30] 01_0000
bit 23-17
bit 15-11
bit 10
01_ 0000
Unused
Unused
SG5
Default state
0
0
Condition for default
bit 9
bit 8
Unused Unused
bit 7
bit 6
bit 5
bit 4
SG4
SG3
SG2
SG1
bit 3
bit 2
bit 1
Unused Unused Unused
bit 0
SG0
0
POR/Reset command
MC33909
73
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
Table 59. Individual Bit Description (Wake-up Delay Enable)
Bits
b10,b7-4,b0
Description
Controls SG5 – SG0 to Enable/Disable Wake-up delay during sleep mode. (Default = 0)
0
Disables wake-up delay for SGn from sleep mode (Device does not wake up with change of state on SGn).
1
Enable wake-up delay for SGn from sleep mode (Device wakes up with change of state on SGn)
Table 60. Wetting Current Register 0
MOSI bits 23-0
MOSI bits [31-24]
[b_31 b_30] 01_0001
bits 23-21
bit 20-18
bits 17-15
bits 14-12
bits 11-9
bits 8-6
bit 5-3
bit 2-0
01_ 0001
SG4
SG3
SG2
SG1
Unused
Unused
Unused
SG0
Default state
110
110
110
110
Unused
Unused
Unused
110
Condition for default
POR/Reset command
Table 61. Individual Bit Description (Wetting Current Register 0)
Bits
b[cba]
Description
Bit pattern for Wetting current level for input pins (Default = 110)
000
Sets the Wetting current Off
001
Sets the Wetting current level to 6.0 mA
010
Sets the Wetting current level to 8.0 mA
011
Sets the Wetting current level to 10 mA
100
Sets the Wetting current level to 12 mA
101
Sets the Wetting current level to 14 mA
110
Sets the Wetting current level to 16 mA
111
Sets the Wetting current level to 20 mA
b23-21
Controls SG4 Wetting current setting. (Default = 110)
b20-18
Controls SG3 Wetting current setting. (Default = 110)
b17-15
Controls SG2 Wetting current setting. (Default = 110)
b14-12
Controls SG1 Wetting current setting. (Default = 110)
b2-0
Controls SG0 Wetting current setting. (Default = 110)
Table 62. Wetting Current Register 1
MOSI bits 23-0
MOSI bits [31-24]
[b_31 b_30] 01_0010
bits 23-21
bit 20-18
bits 17-15
bits 14-12
bits 11-9
bits 8-6
bit 5-3
bit 2-0
01_ 0010
Unused
Unused
Unused
Unused
Unused
SG5
Unused
Unused
Default state
Unused
Unused
Unused
Unused
Unused
110
Unused
Unused
Condition for default
POR/Reset command
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
74
Functional Device Operation
Table 63. Individual Bit Description (Wetting Current Register 1)
Bits
Description
Bit pattern for Wetting current level for input pins (Default = 110)
b[cba]
000
Sets the Wetting current to Off
001
Sets the Wetting current level to 6.0 mA
010
Sets the Wetting current level to 8.0 mA
011
Sets the Wetting current level to 10 mA
100
Sets the Wetting current level to 12 mA
101
Sets the Wetting current level to 14 mA
110
Sets the Wetting current level to 16 mA
111
Sets the Wetting current level to 20 mA
b8-6
Controls SG5 Wetting current setting. (Default = 110)
Table 64. SG Wetting Current Timer Enable
MOSI bits 23-0
MOSI bits [31-24]
[b_31 b_30] 01_0011
bit 23-17
bit 15-11
bit 10
01_ 0011
Unused
Unused
SG5
Default state
0
0
bit 9
bit 8
Unused Unused
bit 7
bit 6
bit 5
bit 4
SG4
SG3
SG2
SG1
bit 3
bit 2
bit 1
Unused Unused Unused
bit 0
SG0
1
Condition for default
POR/Reset command
Table 65. Individual Bit Description (Wetting Current Timer Enable)
Bits
Description
b10,b7-b4,b0
Controls SG5-0 Wetting current timer enable. (Default = 1). This enables a 20 ms (nominal) timer turns off the Wetting
current
0
Disables timer and results in the Wetting current to run continuously
1
Enables timer to turn off Wetting current after 20 ms (nominal)
Table 66. SG Tristate
MOSI bits 23-0
MOSI bits [31-24]
[b_31 b_30] 01_0100
bit 23-17
bit 15-11
bit 10
01_ 0100
Unused
Unused
SG5
Default state
0
0
bit 9
bit 8
Unused Unused
Condition for default
bit 7
bit 6
bit 5
bit 4
SG4
SG3
SG2
SG1
bit 3
bit 2
bit 1
Unused Unused Unused
bit 0
SG0
1
POR/Reset command
Table 67. Individual Bit Description (Tristate)
Bits
b10,b7-b4,b0
Description
Set SG5-0 to tri-state (Default = 1)
0
Sets input to active mode.
1
Sets input to tristate (Hi Z) mode.
MC33909
75
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
4.3.3
DEVICE FLAGS REGISTERS
Table 68. Device Flags - MISC
MOSI bits [31-24]
10 00_1001
MOSI
bits 2310
10 00_1001
Default state
MISO bits 8-0
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Unused
WD INT at
50% Flash
mode
SAFE_B
Activated
FSM
State
(bit4)
FSM
State
(bit3)
FSM State
(bit2)
FSM
State
(bit1)
FSM
State
(bit0)
WDI
mode
0
0
0
0
0
0
1
0
0
Condition for default
bit 1
bit 0
WDI pin
WDI pin
status (bit 1) status (bit 0)
0
0
POR
Table 69. Individual Bit Description - MISC
Bits
Description
Unused
b23-10
WD INT at 50% Flash mode
b9
Description
Watchdog interrupt pulse generation at 50% of the watchdog period in Flash mode
Set/Reset condition
Set: Time elapsed to 50% of watchdog timer in Flash mode. Reset: Flag read (SPI) 
Note: Flag resets only after exiting Flash mode and then SPI flag read.
SAFE_B activated
b8
Description
SAFE_B pin activated for any reason
Set/Reset condition
Set: Safe mode activated. Reset: POR or SPI read
FSM State (Bit 4,3,2,1,0)
b7, b6, b5,
b4, b3
Description
Determine what state the device is in (see Table 70 for description)
Set/Reset condition
Set: Determined by state of IC. Reset: POR
WDI Mode
b2
Description
In watchdog inhibit mode
Set/Reset condition
Set: Voltage at WDI greater then threshold. Reset: Voltage lowered below threshold or POR
WDI pin status (BIT1,0)
b1, b0
Description
WDI pin in Safe mode A [00], B1 [01], B2 [10], B3 [11]
Set/Reset condition
Set: WDI set during INIT Reset. Reset: POR.
Table 70. FSM State
Bits
Description
b7, b6, b5, b4, b3
State
00000
INIT
00010
Normal Request
00011
Normal
00001
Flash
10000
Low-power VDD ON – xxx = SPI Mode command bits 6:3 (forced wake-up, periodic interrupt, watchdog)
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
76
Functional Device Operation
Table 71. Device Flags - Regulators
MOSI bits [31-24]
10 00_1010
MOSI
bits 2320
10 00_1010
Default state
MISO bits 7-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unused
VAUX
Undervoltage
VAUX
overcurrent
CAN5V
Thermal
shutdown
CAN5V
UV
CAN5Voverc
urrent
VBATP
batfail
VBATP
Undervoltage
VBATP
Overvoltage
0
0
0
0
0
0
0
0
0
bit 10
bit 9
Condition for default
POR
Table 72. Device Flags - Regulators
MOSI bits [31-24]
10 00_1010
MOSI
bits 2320
MISO bits 15-8
bit 15
bit 14
bit 13
bit 12
bit 11
VPRE
Boosted
IDD
Overcurrent
Low-power
VDD On mode
IDD
Overcurrent
NORMAL
mode
VDD
Overvoltage
0
0
0
0
10 00_1010
Unused
VPRE
Thermal
Shutdown
Default state
0
0
Condition for default
bit 8
VDD
VDD
Undervolta Undervoltage >
ge
100 ms
0
VAUX
Overvoltage
0
0
POR
Table 73. Device Flags - Regulators
MISO bits 19-16
MOSI bits [31-24]
10 00_1010
MOSI bits
23-20
bit 19
bit 18
bit 17
bit 16
10 00_1010
Unused
VPRE IPFF
VPRE Overcurrent
VPRE Overvoltage
VPRE Undervoltage
Default state
0
0
0
0
0
Condition for default
POR
Table 74. Individual Bit Description - Regulators
Bits
Description
Unused
b23-8
VPRE IPFF
b19
Description
Report VPRE IPFF
Set/Reset condition
Set: VPRE IPFF. Reset: VPRE out of IPFF and flag read (SPI)
VPRE Overcurrent
b18
Description
Reports current out of VPRE is higher than the IPRE-OC threshold.
Set/Reset condition
Set: current above threshold for t > 100 s typ. Reset; current below threshold and flag read (SPI)
VPRE Overvoltage
b17
Description
Reports when VPRE was above overvoltage threshold
Set/Reset condition
Set: VPRE was above OV threshold. Reset: VPRE below OV and flag read (SPI)
VPRE Undervoltage
b16
Description
Reports when VPRE is below undervoltage threshold
Set/Reset condition
Set: VPRE below threshold for t > 100 s typ. Reset: VPRE above threshold and flag read (SPI)
MC33909
77
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
Table 74. Individual Bit Description - Regulators (continued)
Bits
Description
VPRE Thermal Shutdown
b15
Description
Reports the VPRE has reached overtemperature threshold, and was turned off.
Set/Reset condition
Set: VPRE OFF due to thermal condition. Reset: VPRE recover and flag read (SPI)
VPRE_Boosted
b14
Description
Reports VPRE boost circuit activated
Set/Reset condition
Set: VPRE boost activated. Reset: VPRE out of boost mode and flag read (SPI)
IDD Overcurrent Low-power VDD
On mode
b13
Description
Reports current out of VDD pin is higher than the IDD-OC threshold LP, while device is in Low-power VDD
ON mode.
Set/Reset condition
Set: current above threshold for t > 100 s typ. Reset; current below threshold and flag read (SPI)
IDD Overcurrent NORMAL mode
b12
Description
Reports current out of VDD pin is higher than IDD-OC threshold, while device is in Normal mode.
Set/Reset condition
Set: current above threshold for t > 100 s typ. Reset; current below threshold and flag read (SPI)
VDD Overvoltage
b11
Description
Reports VDD pin is higher than the typ VDD + 0.6 V threshold (27)
Set/Reset condition
Set: VDD above threshold for t >100 s typ. Reset: VDD below threshold and flag read (SPI)
VDD low interrupt
b10
Description
Reports VDD output voltage is lower than the VDD_UV threshold and causing an Interrupt, based on the
VDDLRST[1:0] bits set in the INIT register. This flag only sets if the setup in INIT is set to cause an Interrupt
on an undervoltage.
Set/Reset condition
Set: VDD below threshold for t > 100 s typ. Reset: VDD above threshold and flag read (SPI)
VDD low >100 ms
b9
Description
Reports VDD pin is lower than the VDDUV threshold for a time longer than 100 ms (27)
Set/Reset condition
Set: VDD below threshold for t > 100 ms typ. Reset: VDD above threshold and flag read (SPI)
VAUX Overvoltage
b8
Description
Reports VAUX pin is higher than the typ VAUX + 0.6 V threshold.
Set/Reset condition
Set: VAUX above threshold for t > 100 s typ. Reset: VAUX below threshold and flag read (SPI)
VAUX Under voltage
b7
Description
Reports VAUX regulator output voltage is lower than the VAUX_UV threshold. The VAUX undervoltage flag
typically occurs in conjunction with the VAUX overcurrent flag, due to the functional cause.
Set/Reset condition
Set: VAUX below threshold for t > 100 s typ. Reset: VAUX above threshold and flag read (SPI)
VAUX_OVERCURRENT
b6
Description
Report current out of VAUX regulator is above VAUX_OC threshold.
Set/Reset condition
Set: Current above threshold for t > 100 s. Reset: Current below threshold and flag read by SPI.
CAN5V Thermal shutdown
b5
Description
Report the CAN5V regulator has reached overtemperature threshold.
Set/Reset condition
Set: CAN5V thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI)
CAN5V UV
b4
Description
Reports CAN5V regulator output voltage is lower than the CAN5V UV threshold.
Set/Reset condition
Set: CAN5V below CAN5V UV for t > 100 s typ. Reset: CAN5V > threshold and flag read (SPI)
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
78
Functional Device Operation
Table 74. Individual Bit Description - Regulators (continued)
Bits
Description
CAN5V overcurrent
b3
Description
Report the CAN driver output current is above threshold.
Set/Reset condition
Set: CAN5V current above threshold for t > 100 s. Reset: CAN5V current below threshold and flag read
(SPI)
VBATP batfail
b2
Description
Report the device voltage at VBATP pin was below BATFAIL threshold.
Set/Reset condition
Set: VBATP below BATFAIL. Reset: VBATP above threshold, and flag read (SPI)
VBATP_underVOLTAGE
b1
Description
Reports VBATP pin is lower than the VBATP low resoled.
Set/Reset condition
Set: VBATP below threshold for t > 100 s typ. Reset: VBATP above threshold and flag read (SPI)
VBATP Overvoltage
b0
Description
Report VBATP was above overvoltage threshold
Set/Reset condition
Set: VBATP was above OV threshold. Reset: VBATP below OV and flag read (SPI)
Notes
27. When a VDD overvoltage condition occurs, the flag register for VDD undervoltage > 100 ms is also set. This was done to logically enable a SAFE
condition when the over voltage occurs.
Table 75. Device Flags – CAN
MOSI bits [31-24]
10 00_1011
MOSI
MOSI bit 23
bits 22Select bit
17
10 00_1011
0
Default state
MISO bits 7-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unused
CAN
wake-up
-
CAN
Overtemp
RxD low
RxD high
TxD dom
Bus Dom
clamp
CAN
Overcurrent
0
0
0
0
0
0
0
0
0
Condition for default
POR
Table 76. Device Flags – CAN
MOSI bits [31-24]
10 00_1011
10 00_1011
MISO bits 7-0
MOSI bit 23 MOSI bits
22-16
Select bit
0
Default state
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Unused
CAN_UF
CAN_F
CANL to
VBAT
Unused
CANL to
GND
CANH to
VBAT
Unused
CANH to
GND
0
0
0
0
0
0
0
0
0
Condition for default
POR
Table 77. Individual Bit Description – CAN
Bits
Description
CAN_UF
b15
Description
Report the CAN failure detection has not yet identified the bus failure
Set/Reset condition
Set: bus failure pre detection. Reset: CAN bus failure recovered and flag read
CAN_F
b14
Description
Report the CAN failure detection has identified the bus failure
Set/Reset condition
Set: bus failure complete detetction.Reset: CAN bus failure recovered and flag read
MC33909
79
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
Table 77. Individual Bit Description – CAN (continued)
Bits
Description
CANL to VBAT
b13
Description
Report CAN L short to VBAT failure
Set/Reset condition
Set: failure detected. Reset failure recovered and flag read (SPI)
CANL to GND
b11
Description
Report CAN L short to GND failure
Set/Reset condition
Set: failure detected. Reset failure recovered and flag read (SPI)
CANH to VBAT
b10
Description
Report CAN H short to VBAT failure
Set/Reset condition
Set: failure detected. Reset failure recovered and flag read (SPI)
CANH to GND
b8
Description
Reports CAN H short to VBATP failure
Set/Reset condition
Set: failure detected. Reset failure recovered and flag read (SPI)
CAN wake-up
b7
Description
Reports the wake-up source is CAN
Set/Reset condition
Set: after CAN wake detected. Reset: Flag read (SPI)
CAN Overtemp
b5
Description
Reports the CAN interface has reach overtemperature threshold.
Set/Reset condition
Set: CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI)
RxD low
b4
Description
Reports the Rx pin is shorted to GND.
Set/Reset condition
Set: Rx low failure detected. Reset: failure recovered and flag read (SPI)
RxD high
b3
Description
Reports the Rx pin is shorted to recessive voltage.
Set/Reset condition
Set: Rx high failure detected. Reset: failure recovered and flag read (SPI)
TxD dom
b2
Description
Reports the Tx pin is shorted to GND
Set/Reset condition
Set: Tx low failure detected. Reset: failure recovered and flag read (SPI)
Bus Dom clamp
b1
Description
Reports the CAN bus is dominant for a time longer than tDOM
Set/Reset condition
Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI)
CAN Overcurrent
b0
Description
Reports the CAN current is above CAN overcurrent threshold.
Set/Reset condition
Set: CAN current above threshold. Reset: current below threshold and flag read (SPI)
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
80
Functional Device Operation
Table 78. Device Flags – Interrupt
MISO bits 7-0
MOSI bits [31-24]
10 00_1000
MOSI bits
23-16
bit 7
bit 6
bit 5
10 00_1000
Unused
INT request
RST high
Reset
request
Default state
0
0
0
0
bit 4
bit 3
Unused Unused
0
bit 2
bit 1
bit 0
RESET Low <
100 ms
SAFE SPI
resistor
mismatch
VPRE thermal
warning
0
0
0
0
Condition for default
POR
Table 79. Device Flags – Interrupt
MOSI bits [31-24]
10 00_1000
MOSI bits
23-16
10 00_1000
Default state
MISO bits 15-8
bit 15
bit 14
Unused
INT service
Timeout
FWU
0
0
0
bit 13
bit 12
SPI Wake-up Unused
0
Condition for default
0
bit 11
bit 10
bit 9
bit 8
VDD low
RST
RST low >
100 ms
multiple
Resets
W/D refresh
failure
0
0
0
0
POR
Table 80. Individual Bit Description – Interrupt
Bits
Description
INT service Timeout
b15
Description
Reports the INT timeout error detected. An interrupt occurrence stays asserted for more than three watchdog
periods without ever being cleared.
Set/Reset condition
Set: INT service timeout expired and WD2INT set. Reset: flag read and original INT cleared.
FWU
b14
Description
Reports the wake-up source is Forced Wake-up
Set/Reset condition
Set: after Forced Wake-up detected. Reset: Flag read (SPI)
SPI Wake-up
b13
Description
Reports the wake-up source is SPI command, in Low-power VDD on.
Set/Reset condition
Set: after SPI Wake-up detected. Reset: Flag read (SPI)
VDD low RST
b11
Description
Reports VDD is below the VDD undervoltage threshold and causes a RESET, based on the VDDLRST [1:0] bits
set in the INIT register.
Set/Reset condition
Set: VDD below threshold. Reset: flag read (SPI)
RST low > 100ms
b10
Description
Reports the Reset pin has detected a low level, longer than 100 ms (Reset permanent low)
Set/Reset condition
Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI)
Multiple Resets
b9
Description
Reports the more than 8 consecutive reset pulses occurred, due to missing or wrong W/D refresh.
Set/Reset condition
Set: after detection of multiple reset pulses. Reset: flag read (SPI)
W/D refresh failure
b8
Description
Reports a wrong or missing W/D failure occurred
Set/Reset condition
Set: Failure detected. Reset: flag read (SPI)
MC33909
81
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
Table 80. Individual Bit Description – Interrupt (continued)
Bits
Description
INT request
b7
Description
Reports the INT source is an INT request from a SPI command.
Set/Reset condition
Set: INT occurred. Reset: flag read (SPI)
RST high
b6
Description
Reports the RST_B pin is shorted to high voltage.
Set/Reset condition
Set: RST failure detection. Reset: flag read.
Reset Request
b5
Description
Reports the RST source is an request from a SPI command (go to RST mode).
Set/Reset condition
Set: After reset occurred due to SPI request. Reset: flag read (SPI)
RESET Low < 100 ms
b2
Description
Reports the Reset pin has detected a low level, shorter than 100 ms
Set/Reset condition
Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI)
SAFE SPI resistor
mismatch
b1
Description
Reports the SPI word setting the state of SAFE (A, B1, B2, B3) does not match the resistor value set at startup
Set/Reset condition
Set: after SPI command to set SAFE mode and if it does not match. Reset: POR or matching SPI word sent.
VPRE thermal warning
b0
Description
Reports the VPRE thermal warning temperature has been reached
Set/Reset condition
Set: after VPRE thermal warning: Reset Temperature falls below thermal warning limit and SPI read.
Table 81. Device Flags – LIN01
MISO bits 7-0
MOSI bits [31-24]
10 00_1100
MOSI bits
23-16
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
10 00_1100
Unused
Unused
LIN0 wakeup
Unused
LIN 0
Overtemp
RxD0 low
RxD0 high
TxD0 dom
LIN0 bus dom
clamp
Default state
0
0
0
0
0
0
0
0
0
Condition for default
POR
Table 82. Device Flags – LIN01
MISO bits 7-0
MOSI bits [31-24]
10 00_1100
MOSI bits
23-16
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
10 00_1100
Unused
Unused
LIN1wake-up
Unused
LIN
1Overtemp
RxD1 low
RxD1 high
TxD1 dom
LIN1 bus dom
clamp
Default state
0
0
0
0
0
0
0
0
0
Condition for default
POR
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
82
Functional Device Operation
Table 83. Individual Bit Description – LIN01
Bits
Description
LIN1 wake-up
b14
Description
Reports the wake-up source is LIN1
Set/Reset condition
Set: after CAN wake detected. Reset: Flag read (SPI)
LIN 1 Overtemp
b12
Description
Reports the LIN1 interface has reach overtemperature threshold.
Set/Reset condition
Set: CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI)
RxD1 low
b11
Description
Reports the RxDL pin is shorted to GND.
Set/Reset condition
Set: Rx low failure detected. Reset: failure recovered and flag read (SPI)
RxD1 high
b10
Description
Reports the RxDL pin is shorted to recessive voltage.
Set/Reset condition
Set: Rx high failure detected. Reset: failure recovered and flag read (SPI)
TxD1 dom
b9
Description
Reports the TxDL pin is shorted to GND.
Set/Reset condition
Set: Tx low failure detected. Reset: failure recovered and flag read (SPI)
LIN1 busdom clamp
b8
Description
Reports the LIN1 bus is dominant for a time longer than tDOM
Set/Reset condition
Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI)
LIN0 wake-up
b6
Description
Reports the wake-up source is LIN0
Set/Reset condition
Set: after CAN wake detected. Reset: Flag read (SPI)
LIN 0 Overtemp
b4
Description
Reports the LIN0 interface has reach overtemperature threshold.
Set/Reset condition
Set: CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI)
RxD0 low
b3
Description
Reports the RxDL pin is shorted to GND.
Set/Reset condition
Set: Rx low failure detected. Reset: failure recovered and flag read (SPI)
RxD0 high
b2
Description
Reports the RxDL pin is shorted to recessive voltage.
Set/Reset condition
Set: Rx high failure detected. Reset: failure recovered and flag read (SPI)
TxD0 dom
b1
Description
Reports the TxDL pin is shorted to GND.
Set/Reset condition
Set: Tx low failure detected. Reset: failure recovered and flag read (SPI)
LIN0 busdom clamp
b0
Description
Reports the LIN0 bus is dominant for a time longer than tDOM
Set/Reset condition
Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI)
MC33909
83
Analog Integrated Circuit Device Data
Freescale Semiconductor
Functional Device Operation
Table 84. Device Flags – LIN23
MISO bits 7-0
MOSI bits [31-24]
10 00_1101
MOSI bits
23-16
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
10 00_1101
Unused
Unused
LIN2 wakeup
Unused
LIN 2
Overtemp
RxD2 low
RxD2 high
TxD2 dom
LIN2 busdom
clamp
Default state
0
0
0
0
0
0
0
0
0
Condition for default
POR
Table 85. Device Flags – LIN23
MISO bits 7-0
MOSI bits [31-24]
10 00_1101
MOSI bits
23-16
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
10 00_1101
Unused
Unused
LIN3 wakeup
Unused
LIN 3
Overtemp
RxD3 low
RxD3 high
TxD3 dom
LIN3 busdom
clamp
Default state
0
0
0
0
0
0
0
0
0
Condition for default
POR
Table 86. Individual Bit Description – LIN23
Bits
Description
LIN3 wake-up
b14
Description
Reports the wake-up source is LIN3
Set/Reset condition
Set: after CAN wake detected. Reset: Flag read (SPI)
LIN 3 Overtemp
b12
Description
Reports the LIN3 interface has reach overtemperature threshold.
Set/Reset condition
Set: CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI)
RxD3 low
b11
Description
Reports the RxDL pin is shorted to GND.
Set/Reset condition
Set: Rx low failure detected. Reset: failure recovered and flag read (SPI)
RxD3 high
b10
Description
Reports the RxDL pin is shorted to recessive voltage.
Set/Reset condition
Set: Rx high failure detected. Reset: failure recovered and flag read (SPI)
TxD3 dom
b9
Description
Reports the TxDL pin is shorted to GND.
Set/Reset condition
Set: Tx low failure detected. Reset: failure recovered and flag read (SPI)
LIN3 busdom clamp
b8
Description
Reports the LINx bus is dominant for a time longer than tDOM
Set/Reset condition
Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI)
LIN2 wake-up
b6
Description
Reports the wake-up source is LIN2
Set/Reset condition
Set: after CAN wake detected. Reset: Flag read (SPI)
LIN 2 Overtemp
b4
Description
Reports the LIN2 interface has reach overtemperature threshold.
Set/Reset condition
Set: CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI)
MC33909
Analog Integrated Circuit Device Data
Freescale Semiconductor
84
Functional Device Operation
Table 86. Individual Bit Description – LIN23 (continued)
Bits
Description
RxD2 low
b3
Description
Reports the RxDL pin is shorted to GND.
Set/Reset condition
Set: Rx low failure detected. Reset: failure recovered and flag read (SPI)
RxD2 high
b2
Description
Reports the RxDL pin is shorted to recessive voltage.
Set/Reset condition
Set: Rx high failure detected. Reset: failure recovered and flag read (SPI)
TxD2 dom
b1
Description
Reports the TxDL pin is shorted to GND.
Set/Reset condition
Set: Tx low failure detected. Reset: failure recovered and flag read (SPI)
LIN2 busdom clamp
b0
4.3.3.1
Description
Reports the LINx bus is dominant for a time longer than tDOM
Set/Reset condition
Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI)
Abnormal Operation (As Applicable to Each Specific ASIC)
The 33909 is subject to various conditions considered abnormal as defined within this section.
4.3.3.1.1
Jump Start
Complete functionality is guaranteed for a battery voltage of 26.5 V (or other application specific value) up to TA 50 °C for at least two
minutes. A complete characterization is completed at this voltage and temperature. Performance at two minutes is guaranteed by bench
characterization. No internal faults is set or abnormal operation noted as a result of operating in this range.
4.3.3.1.2
Load Dump
The device must be capable of withstanding a typical load dump transient voltage of 40 V (or other application specific value) over the
entire specified operating temperature range. Full parametric conformance is not required, Functionality up to overvoltage shutdown is
guaranteed as well as up to the thermal capability of the package and external components with the exception of internal diagnostics,
which are not required. No internal faults are set as a result of operating in this range.
4.3.3.1.3
Low Voltage Operation
The low voltage operating range is the application specific voltage range where full parametric conformance is not required of the device.
However, all functions remain in stable operation and return to their proper behavior upon return to the normal operation voltage range.
4.3.3.1.4
Undervoltage Lockout
This undervoltage lockout voltage range is dependent upon the silicon technology and the design, but is defined as the voltage range
where all applicable output drivers are maintained in their OFF state. This range is intended to define the voltages at which the device is
not capable of meeting internal threshold requirements to guarantee functionality. While in undervoltage lockout, the driver outputs are
not be allowed to 'float' and inadvertently turn an output ON.
4.3.3.1.5
Reverse Battery
This device with applicable external components is not damaged by exposure to reverse battery conditions of -14 V (or other application
specific values). This test is performed for a period of one minute at 25 °C. In addition, this negative voltage condition does not force any
of the logic level I/O pins to a negative voltage less than -0.6 V at 10 mA, or to a positive voltage greater the 5.0 V DC. This insures
protection of the digital device interfacing with this device.
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Functional Device Operation
4.3.3.1.6
Ground Offset
The applicable driver outputs and/or current sense inputs are capable of operation with a ground offset of 2.0 V DC. The device is not
damaged by exposure to this condition and maintains specified functionality.
4.3.3.1.7
Shorts to Ground
All I/O's of the device are available at the module connector and are protected against shorts to ground with maximum ground offset
considered (i.e. -2.0 V referenced to device ground or other application specific value). The device is not be damaged by this condition.
4.3.3.1.8
Shorts to Battery
All I/O's of the device are available at the module connector and are protected against a short to battery (voltage value is application
dependent, there may be cases where short to jump start or load dump voltage values are required). The device is not damaged by this
condition.
4.3.3.1.9
Unpowered Shorts to Battery
All I/O's of the device are available at the module connector and are protected against unpowered (battery to the module is open) shorts
to battery per application specifics. The device is not damaged by this condition, does not enable any outputs, and does not back feed
onto the power rails (i.e, VBATP, VDD) or the digital I/O pins.
4.3.3.1.10
Loss of Module Ground
The definition of a loss of ground condition at the device level is, all pins of the IC see very low-impedance to battery. The nomenclature
is suited to a test environment. In the application, a loss of ground condition results in all I/O pins floating to battery voltage, while all
externally referenced I/O pins are at worst case pulled to ground. All applicable driver outputs and current sense inputs are protected
against excessive leakage current due to loads are referenced to an external ground (i.e, high-side drivers).
4.3.3.1.11
Loss of Module Battery
The loss of battery condition at the parts level is, the power input pins of the IC see infinite impedance to the battery supply voltage
(depending upon the application), but there is some undefined impedance looking from these pins to ground. All applicable driver outputs
and current sense inputs are protected against excessive leakage current due to loads are referenced to an external battery connection
(i.e., low-side drivers).
4.3.3.1.12
Stress Tests (As Applicable to Each Specific ASIC)
Each of the outputs must have a series of stress tests performed on 100% of the parts shipped. Experience has shown failure to
incorporate these tests results in field and plant failures. The following is a list of the tests required and a brief description of each test. In
general, for all of the following tests a significant number of parts must be tested to failure for the parameter in question so a statistically
valid destruction level can be found. After this level is determined for each of the following parameters, a level for a production test is
determined. This level must not be so high as to damage a normal part, but it must fail parts which do not fit in the normal process window.
Note: In all cases, the stress test must be performed to the level found during the previous part characterization and is not be tested to the
specification level. Even if the part meets this specification, but the parameter in question does not fall within the proper statistical window,
the part must be rejected. The only way a part can be considered good if it does not fall within the normal statistical window is if an exact
root cause analysis is performed and a detailed explanation is given, along with an assessment of risk. Any stress test limits arrived at
must at least meet the minimum requirements listed in this specification or the test has no validity.
4.3.3.1.13
Gate Stress Tests (As Applicable to Large Power MOSFET Drivers)
The gate stress test helps to test out random manufacturing defects within the gate oxide of the MOSFET. An initial gate-to-source leakage
test is performed with as high a voltage as possible without causing significant leakage of the Gate-to-source zener clamp. The leakage
is measured and recorded. Now a higher voltage (18 Volts, process and design related.) is applied to the gate of the MOSFET for a short
period of time. The leakage is again tested at the lower voltage and recorded. If the leakage is above an absolute value, or if possible
above a delta increase, the part is bad and must be rejected.
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Functional Device Operation
4.3.3.1.14
BVDSS Test (As Applicable to Power Output Drivers)
The purpose of this test is to ensure there is adequate headroom between the breakdown of the MOSFET output and the maximum clamp
voltage. Provisions need to be made to be able to defeat the drain-to-gate clamp diode so that the BVDSS value can be measured. It is
also acceptable if the exact value is not found, but that a minimum guard band is tested to. A guard band of 5.0 to 10 V would be typical.
4.3.3.1.15
Elevated Supply Voltage Stress
The purpose of this test is to find weak devices might fail if an unusual transient was seen. An elevated voltage of 40 Volts (Process
dependent) is applied to the VBATP pin.
4.3.3.1.16
IDDQ Stress Test
The purpose of this test is to identify defects (shorted or leaky devices) which cannot be detected by conventional functional testing. IDDQ
testing is required to be done separately for digital and analog circuit blocks. Test definition is per AEC Q100-007.
4.3.3.1.17
SCAN testing
The purpose of this test is to identify defects (shorted or leaky devices) which cannot be detected by conventional functional testing. IDDQ
testing is required to be done separately for digital and analog circuit blocks. Test definition is per AEC Q100-007.
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Typical Applications
5
Typical Applications
The 33909 System basis chip is a highly integrated system basis chip with switch to ground input detection inputs. The 33909 was
designed to supply microprocessors and module power along with many of the most commonly needed functions in body modules.
C26
L2
R25
D3
D2
U1
VAUX
U2
C19
C20
CBOOT
VPRE VAUXE VAUXB VAUX
VSW VPREGATE
VBAT
L1
C27
CPI1 CPI2
D1
BOOT
VDDE
VBAT_SMPS
VDDB
VDD
PI Filter
C17
RVBATSNS
C1
R1
C2
R2
C3
R3
C4
R4
C5
C25
RST_B
WDI
RWDI
R0
SG0
33909
RXD_L0
SG4
D4
R17
D5
R18
MCU
TXD_L0
SG5
RXD_L1
TXD_L1
CANH
RXD_L2
TXD_L2
CANL
RXD_L3
TXD_L3
RXD_C
TXD_C
VBATP
D6
R19
SPI
CS_B
SG3
R21
MOSI
SCLK
SG2
R5
INT_B
MISO
SG1
R22
CAN Bus
VDD
C21
AMUX
VBATSNS
C0
U3
SAFE_B
VBATP
C18
R16
D7
R20
LIN Bus
LIN_0
LIN Bus
LIN_1
CAN5V
C22
LIN Bus
LIN Bus
LIN_2
LIN_3
GND
GND
CANGND
Figure 36. 33909AD Typical Application Diagram
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Packaging
6
Packaging
6.1
Package Dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and
perform a keyword search for the drawing’s document number.
Table 87.
Package
Suffix
48-Pin LQFP
AD
Package Outline Drawing Number
98ASA00737D
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Packaging
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Packaging
.
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Revision History
7
Revision History
Revision
Date
Description of Changes
1.0
10/2013
2.0
1/2015
3.0
4.0
3/2015
• Initial Release
•
•
•
•
•
•
Removed 64-pin version
Major update
Added DC/DC to device description.
Updated Electrical Characteristics tables for ILOAD_BUCK, VDD Undervoltage, SPI VIH/VIL specs.
Updated text to match current device.
Updated SPI tables to remove unused bits.
4/2015
• Changed device status in Orderable Parts from PC to MC.
7/2015
• Added SG Low-power Mode Timing Diagram
• Corrected TXD pin timing in Table 9
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Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by
customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others.
Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address:
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Freescale and the Freescale logo, are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.
SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their
respective owners.
© 2015 Freescale Semiconductor, Inc.
Document Number: MC33909
Rev. 4.0
7/2015
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