TLE 5250 2.5-A High Performance Smart Power Stepper-Motor Driver with Diagnostic Interface SPT-IC Overview Features • • • • • • • • • • • • Single phase driver for stepper motor 2.5 A Low ON-resistance (typical 0.3 Ω) Wide supply range 6 V to 45 V Wide current range 10 mA to 3 A Fast nominal/actual comparator for micro stepper mode Wide temperature range Short circuit protection Under voltage shutdown Overtemperature shutdown Serial diagnostic interface Fast freewheeling diodes TTL-compatible inputs P-SIP-15-1 Type Ordering Code Package TLE 5250 Q67000-A9103 P-SIP-15-1 Description TLE 5250 is a monolithic IC in Smart Power technology for controlling and regulating the motor current in one phase of a bipolar stepping motor. There are other applications in driving DC motors and inductive loads that are operated on constant current. The device has TTL-compatible logic inputs, includes a H-bridge with integrated, fast free-wheeling diodes plus dynamic limiting of the motor current by a chopper mode. The nominal current can be set continuously by a control voltage. Microstep mode can be produced by applying a sinusoidal control voltage. Two TLE 5250s, with a minimum of external circuitry and a single supply voltage, form a complete system - that can be driven direct by an MC- for two-phase, bipolar stepping motors with output current of up to 2.5 A per phase. The outputs of the IC are internally protected against shorted to ground, supply voltage and shorted load. The output stages are also disabled by undervoltage and overtemperature. All fault functions can be detected by the internal diagnostics, which can be read out serially. Semiconductor Group 1 1998-02-01 TLE 5250 15 DIAG PH EN VS Q1 Q1 Sense GND Sense Q2 Q2 VS RS NOM ACT 1 AEP01471 Figure 1 Pin Configuration (top view) Semiconductor Group 2 1998-02-01 TLE 5250 Pin Definitions and Functions Pin No. Symbol Function 1 DIAG Open-drain diagnostics output 2 PH Input for determining source/sink on outputs Q1 and Q2; when Enable = Low, this pin serves as clock input for reading out diagnostics 3 EN Input for activating or turning off device (all output transistors turned off); Enable High = output active, Enable Low = diagnostics 4, 12 VS Supply voltage of IC 5, 6 Q1 Power output with integrated free-wheeling diodes 7, 9 Sense Actual-current output: shared, open-source output of sink transistors 8 GND Ground 10, 11 Q2 Power output with integrated free-wheeling diodes 13 RS Determines turning back on of sink transistor by internally driven, external RC element or external TTL trigger signal 14 NOM Input for reference potential (nominal current) for nominal/ actual comparator 15 ACT Input for actual current for nominal/actual comparator Semiconductor Group 3 1998-02-01 Figure 2 Semiconductor Group 4 Nominal Diagn Phase Enable 14 1 2 3 RC/Sync + - Actual 1 mA V ref 13 Off/ Ι Charge VS VCC1 VCC2 Bias Chop Logic Overload Functional Logic 15 + - Nom/Act Comp PWM Logic Diagnostics Logic Overtemperature Undervoltage 16 Cooling Pin T1 T2 T3 T4 GND 8 Driver 3 G on T4 Q1 Low Q1 High Driver 1 3V 5V T3 G on T5 + - Q2 Low + - 9 Sense Sense 5V 3V VS -1.5 V 12 VS 7 + - + - + - VS -1.5 V Q2 High + - T1 Bandgap/Bias 4 VS Driver 2 T4 Driver 4 H-Bridge Output Stage T2 VS -6 V Charge Pump AEB01468 11 10 6 5 Q2 Q1 TLE 5250 Block Diagram 1998-02-01 TLE 5250 Application Two TLE 5250 drivers are required to operate a bipolar stepping motor. To implement full-step operation, a squarewave voltage with the required stepping frequency is applied to the phase input of the upper driver, and the same squarewave voltage, but offset in phase by 90°el, to the phase input of the lower driver. Motor-current limiting is produced by a DC signal that is applied to both nominal-current inputs. In microstep operation the nominal current tracks sinusoidally and synchronously with the required stepping frequency. This produces a sinusoidal current in the motor windings to ensure very smooth running and a high stepping frequency. If an instantaneous nominal value (sine or cosine) is held on the second driver, it is possible to set a certain angle of rotation while the motor is stationary. The motor current produced by this depends on nominal voltage and sense resistance (normally 0.5 Ω), i.e. V nom [ V ] I M [ V ] = ----------------------RS [ Ω ] The actual voltage should be thoroughly filtered for precise current regulation, especially in microstep operation. So the actual input is accessible, and an RC element is necessary between the Sense output and Actual input. The resistance RR should correspond to the internal resistance of the nominal-current input-voltage source to prevent additional voltage offset on the nominal/actual comparator. Circuit Description Outputs Outputs Q1 and Q2 are fed by push-pull output stages. Four integrated free-wheeling diodes referred to ground or the supply voltage protect the integrated circuit against reverse voltages from an inductive load. Enable and Phase Outputs Q1 and Q2 can be disabled by a voltage VInh of ≤ 0.8 V on the Enable pin. The sink transistors are enabled by VInh ≥ 2 V. The voltage on the Phase input determines the phase of the output current. Output Q1 acts as a sink for VPh ≤ 0.8 V and as a source for VPh ≥ 2 V. For output Q2 this is reversed: sink for VPh ≥ 2 V and source for VPh ≤ 0.8 V. The sink transistors are chopped. Low signal on the Enable pin plus a clock signal on the Phase pin enable readout of the multiplexer. Semiconductor Group 5 1998-02-01 TLE 5250 Nominal-Current Input The peak current in the motor winding is defined by the voltage on the Nominal input. This is compared by a fast comparator to the voltage drop on the actual-current sensor. If the nominal current is exceeded, the sink transistors of the outputs are turned off by the logic. RC/Sync Input The outputs are turned on by the signal applied to the RC input. Synchronization is possible by TTL signal or chopper mode with an external RC combination. Chopper Mode After the supply voltage is applied, capacitor CT is charged with constant current of 1 mA. A regulator limits the maximum voltage on the capacitor to 2.3 V. As a result of the rising current in the motor winding, the voltage on the actual sensor increases. Once the value defined by the nominal-current input is exceeded, the fast comparator resets an RS flipflop. Thus sink transistors T3 and T4 are turned off by the logic. The charge current is turned off and the parallel RT discharges CT. The internal logic is designed so that capacitor CT is always charged before the discharge operation is triggered. This guarantees a constant charge time, even for very small coil currents (see Figure 7). Sync Operation If a sync signal with TTL level is applied to the RC input, the negative edge will set the RS flipflop - by way of the combined Schmitt trigger and monoflop - if the voltage on the current sensor is smaller than the nominal value on the nominal-current input. As in chopper mode, the appropriate output transistors conduct. They are again turned off by resetting the RS flipflop when the voltage on the current sensor becomes greater than the nominal value (see Figure 8). Output-Stage Control This part of the circuit handles turn-off of the output stages when the output is shorted to ground. There is separate current monitoring for this purpose in the source transistors. The temperature of the output stages is also monitored. If this exceeds 175 °C, all output stages are turned off, and then turned on again when the temperature drops. Undervoltage also causes turn-off of the transistors in the output stages. These possible fault states are stored in the diagnostics register. Semiconductor Group 6 1998-02-01 TLE 5250 Diagnostics The information from the different parts of the circuit is collected in the diagnostics and stored in the fault logic. The information is read out on the Diagnostics output (open collector). The fault logic consists of a 16-bit multiplexer that switches information in three categories through to the Diagnostics output. Bit 0 always appears inverted on DIAG when EN is High. This means that, if there is overcurrent on the upper transistor, undervoltage or overtemperature, it will be signaled immediately on the Diagnostics output. DIAG changes from High to Low. Bit 1: check bit. Bits 2, 3, 4 and 5 indicate the momentary status of the comparators on the two outputs (see Figure 2). Changes in the status of the comparators for output monitoring can be observed on DIAG when EN is Low and the counter of the multiplexer is on 2, 3, 4 or 5. This is necessary for detecting underload. Bits 6, 7, 8, 9 The monoflop generates a short strobe signal when the EN edge changes from High to Low. The status of the comparators for output monitoring is stored with this signal and can be read out in bits 6, 7, 8 and 9. When Enable is Low, the Phase input is used as a clock input. As the edge rises, an internal counter is incremented and the corresponding channel of the multiplexer is switched through. As the edge falls, the signal is output inverted. When Enable is High, the counter is reset to zero. EN Strobe Reset AED01467 Figure 3 Semiconductor Group 7 1998-02-01 TLE 5250 Bits 10, 11 With these bits it is possible to detect the status of the gate voltages of the lower outputstage transistors T3 and T4. Bit 10: status for EN edge transition. Bit 11: whether the lower transistor has at all been turned on. Bit 12 indicates whether the nominal/actual comparator has switched. The comparator switches when the output current is regulated. Bits 13, 14, 15 These bits indicate the presence of overcurrent, undervoltage or overtemperature. A fault is ORed and output direct by bit 0 on DI. When the multiplexer is read out, bits 0 through 15 are output once non-inverted (Phase = Low) and once inverted (Phase = High). Bit Assignment in Error Register Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bits 2-5 Bit 6 Bit 7 Bit 8 Bit 9 = = = = = = = = = = = High for overtemperature/undervoltage/overcurrent always High High when sink transistor Q1 turned on High when sink transistor Q2 turned on High when source transistor Q1 turned on High when source transistor Q2 turned on momentary states for readout bit 2 state for falling edge of Enable signal bit 3 state for falling edge of Enable signal bit 4 state for falling edge of Enable signal bit 5 state for falling edge of Enable signal Bits 6-10 represent status of outputs for negative change in edge of Enable signal Bit 11 High if gate-source voltage of sink transistors is > 5 V at moment of readout = Bits 11-15 are set if event occurs during switching (Enable = High) Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 High if sink transistor VGS > 5 V High if actual current lower than nominal current High if overcurrent detected on source transistors High if undervoltage detected High if thermal link tripped = = = = = The memories are erased by a rising edge on the Enable input. Semiconductor Group 8 1998-02-01 TLE 5250 Logic Assignment: Control Inputs, Output Transistors Enable L L H H Phase L H L H Output Q1 / / L H Output Q2 / / H L Transistor T1 Transistor T2 Transistor T3 Transistor T4 X X X X X X X X X – – X – X X – L H X – – / = = = = = = Low voltage level, input open High voltage level transistor turned off transistor conducting transistor conducting, switched in current limiting output high-impedance Semiconductor Group 9 1998-02-01 TLE 5250 RC/Sync 5V 5V 1 mA + 1.8 V 0.8 V Input T3 Deadtime Comparator Gate T3 & Gate T4 RS FF DFF D + - & Q T R S Q R DT Output Input T4 Nom/Act QRS FF Comparator 2.3 V Charge-Current and SwitchingThreshold Control, Reset-Pulse Generation N/A Output Nominal Actual + - AES01469 Figure 4 PWM Logic Semiconductor Group 10 1998-02-01 TLE 5250 Error Status Continuous Q1 Low Status Q1 Low Status Continuous Q2 Low Status Q2 Low Status Continuous Q1 High Status Q1 High Status Continuous Q2 High Status Q2 High Status Continuous Diagn. Pin C h a n n e l 2 3 1 4 1 1 Overcurrent Flag 5 6 S Q Q1 High Status Strobed R Q 8 S Q 9 S Q Gon Status Strobed R Q & GOn T3 10 S Q <_1 GOn Status Gon Status Latched R Q & GOn T4 11 S Q Actual Current up to Nominal Latched R Q Nom/Act Stat. Act>Nom->High & 12 S Q Overcurrent T1/T2 Latched R Q Overcurrent T1/T2 Status & <_1 Undervoltage Status & 13 S Q Undervoltage Latched R Q 14 S Q Overtemperature Latched R Q Overtemperature Status & 15 S Q Reset Clock R Q Monoflop Strobe <_1 Latch Monoflop Sequential Multiplexer Q2 High Status Strobed R Q & MUX 16-to-1 7 S Q & Q Q2 Low Status Strobed R Q & & Q1 Low Status Strobed & Enable Phase M U X Check Bit Low 1 <_ 1 0 Reset AES01470 Figure 5 Diagnostics Logic Semiconductor Group 11 1998-02-01 TLE 5250 Absolute Maximum Ratings TJ = – 40 to 150 °C Parameter Symbol Limit Values min. max. Unit Supply voltage VS – 0.3 45 V Supply current IS 0 3 A Peak currents on outputs IQ –3 3 A Diode to + VS IFH – 3 A Diode to sense IFL – 3 A Output current on actual-current pin IAct – 3 A Voltage on actual-current pin VAct – 0.3 5 V Ground current, pin 6 IGND – 3 A Chip temperature TC – 40 150 °C Storage temperature Tstg – 125 °C Junction to ambient RthjA – 70 K/W Junction case RthjC – 3 K/W Supply voltage VS 6 40 V Input voltage Enable, Phase, RC/Sync VI – 0.3 5.5 V Voltage on nominal pin VNOM – 0.3 2 V Voltage on actual pin VACT – 2 V Output current Q1, Q2 IQ – 2.5 2.5 A Junction temperature TJ – 40 150 °C H input voltage VIH 2 – V L input voltage VIL – 0.8 V Diode Forward Currents Thermal Resistances Operating Range Enable and Phase Inputs Semiconductor Group 12 1998-02-01 TLE 5250 Characteristics VS = 6 to 25 V; TJ ≤ 150 °C Parameter Supply current Symbol IS Limit Values Unit Test Condition min. typ. max. – – 11 mA Enable = High 0.3 – 0.5 Ω I = 2.5 A, 150 °C Output Q1, Q2 Turn-on resistance of output RDS ON transistors Phase deadtime tD – 10 – µs – Diode forward voltage output to + VS VFQ – – 1.5 V IFH = 2.5 V Diode forward voltage actual-current pin to output – – – 1.5 V IFH = 2.5 V 0 1 2 µA – –4 – 8 mV – Nominal Current II8 Offset voltage measured for VI(8 – 4) Input current 0 V actual/nominal pin Actual Current Turn-off delay of nom/act comparator td – – 0.5 µs – Common-mode error VComm –5 – 10 mV – f – 20 100 kHz – VtL VtH VChm 0.8 1.7 – – 1 2 V V – – 2.2 2.3 2.4 V R = 39 kΩ C = 820 pF RC/Sync Sync frequency Trigger threshold lower upper Maximum charge voltage Semiconductor Group 13 1998-02-01 TLE 5250 Characteristics (cont’d) Parameter Symbol Limit Values Unit Test Condition min. typ. max. VUDIAG VUEN VUH 4 – – V – – – 5.3 V – – – 400 mV – Activating delay (Enable High → Low) tdef – – 400 ns – Delay phase low to high tddr – – 500 ns Enable = Low VS > 5.5 V Delay phase high to low tddf – – 450 ns Enable = Low VS > 5.5 V Output voltage low VDiag IDiag – – 0.4 V – – 10 µA IQL = 5 mA VQH = 5 V Undervoltage Cutout Disable Enable Hysteresis Diagnostics Output Leakage current high Semiconductor Group 14 1998-02-01 TLE 5250 5V R 2 kΩ 100 nF Cooling Pin GND 22 µF (Tantalum) V Batt VS 1 nF Diagnostics Q1 Phase TLE 5250 µC M Enable Q2 RN 1 kΩ CN Nominal 1 nF Actual 68 pF RC/Sync. RT 39.2 k Ω Sense CT RR 820 pF RK 1kΩ CF RS 680 pF 0.5 Ω AES01472 Figure 6 Application Circuit 1 Semiconductor Group 15 1998-02-01 TLE 5250 Phase = High or Low Enable 2.3 V 1.8 V VRC/Sync 0.8 V QRSFF SI OUT Coil Current Actual Voltage Discharge operation is started when nominal current is reached. C T is discharged by R T . Voltage on RC/Sync was limited internally to 2.3 V in charge operation. When coil current reaches nominal value, sink transistor is turned off. Independently of this, RC element is charged up to 1.8 V and then discharged. Charge operation is controlled by deadtime comparator. RC element is charged with 1mA. Figure 7 AED01475 Chopper Mode with External Capacitor CT and Resistor RT Semiconductor Group 16 1998-02-01 TLE 5250 RC/Sync QRSFF Coil Current Nominal Voltage Actual Voltage N/A Output Falling edge turns on sink transistor. Figure 8 Sink transistor is turned off again when nominal voltage is reached. AED01476 Synchron Mode Semiconductor Group 17 1998-02-01 TLE 5250 EN PH Q1 Q2 ΙL Strobe Reset Bit 2 Bit 3 Q1 Low Q2 Low Q1 High Bit 4 Bit 5 Q2 High Bit 6 Q1 Low Strobed Bit 7 Q2 Low Strobed Bit 8 Q1 High Strobed Bit 9 Q2 High Strobed Bit 0 AED01477 For inductive load and faultfree operation, diagnostics when read out must show bit 2 inverted to bit 6 bit 3 inverted to bit 7 bit 4 inverted to bit 8 bit 5 inverted to bit 9 Figure 9 Response to Inductive Loads a) Normal Operation (no current regulation) Semiconductor Group 18 1998-02-01 TLE 5250 EN PH Q1 Q2 ΙL Strobe Reset Bit 2 Bit 3 Q1 Low Q2 Low Q1 High Bit 4 Bit 5 Q2 High Bit 6 Q1 Low Strobed Bit 7 Q2 Low Strobed Bit 8 Q1 High Strobed Bit 9 Q2 High Strobed Bit 0 AED01478 Bit 2 identical to bit 6 Bit 4 identical to bit 8 = fault Figure 10 Response to Inductive Loads b) Q1 Shorted to + VS (Phase = High) Semiconductor Group 19 1998-02-01 TLE 5250 EN PH Q1 Q2 ΙL RC/Sync Strobe Reset Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 AED01479 Figure 11 Response to Inductive Loads c) Q2 Shorted to + VS (Phase = High) Semiconductor Group 20 1998-02-01 TLE 5250 EN PH Q1 Q2 ΙL ΙL = 0 RC/Sync Strobe Reset Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 AED01480 Indication of low load: bit 2 = bit 3 bit 4 = bit 5 while Enable = Low And conditions bit 2 = /bit 6 bit 3 = /bit 7 bit 4 = /bit 8 bit 5 = /bit 9 are not all satisfied Figure 12 Response to Inductive Loads d) Low Load Semiconductor Group 21 1998-02-01 TLE 5250 Package Outlines P-SIP-15-1 (Plastic Single In-Line) 4.62 max 20 ±0.3 3.8 ±0.06 1 15 1.27 0.69 ±0.1 17.78 0.25 M 15x 17.5 ±0.15 10.7 +0.15 17.78 ±0.25 4.14 ±0.33 21 max 1.52 ±0.08 0.5 ±0.13 4.29 0.61 M 15x GPI09015 9.37 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Semiconductor Group 22 Dimensions in mm 1998-02-01