CE95314 - PSoC® 3, PSoC 4, and PSoC 5LP
EZI2C
Objective
2
These code examples demonstrate the usage of the EZI2C slave and I C master Components in PSoC 3, PSoC 4, and PSoC
5LP.
Overview
2
2
These code examples show how two I C Components – EZI2C slave and I C master – communicate with each other.
Normally, these Components would be on separate devices, but for this example project, they are on the same PSoC chip. An
off-chip connection is made between them.
There are two examples:
For PSoC 3 and PSoC 5LP, running on a kit with two buttons and a character LCD, such as the Cypress CY8CKIT-030
and CY8CKIT-050 kits.
For PSoC 4200, running on the Cypress CY8CKIT-042 kit, which has one button and an RGB LED.
Each I2C Component maintains its own data buffer. Note that an EZI2C buffer can be defined such that only the first N bytes
are writeable by the master and the remaining bytes are read-only. This functionality is demonstrated in this example.
Requirements
Tool: PSoC Creator 3.3 CP1.
Programming Language: C (DP8051 Keil 9.51, ARM GCC 4.7.3, and ARM MDK compilers)
Associated Parts: All PSoC 3, PSoC 4200, and PSoC 5LP parts
Related Hardware: CY8CKIT-030, CY8CKIT-050, CY8CKIT-042, CY8CKIT-001
www.cypress.com
Document No. 001-95314 Rev.*A
1
PSoC® 3, PSoC 4, and PSoC 5LP EZI2C
Design
Figure 1 shows the code example design for PSoC 3 and PSoC 5LP, and Figure 2 shows the example design for PSoC 4200.
Figure 1. EZI2C Code Example for PSoC 3 and PSoC 5LP
Figure 2. EZI2C Code Example for PSoC 4200 on the CY8CKIT-042
www.cypress.com
Document No. 001-95314 Rev.*A
2
PSoC® 3, PSoC 4, and PSoC 5LP EZI2C
Both code examples feature the following:
2
2
An I C master communicating with an EZI2C slave over an off-chip I C bus connection
For the PSoC 3 and PSoC 5LP design, the EZI2C uses one of the fixed I C blocks, and the master is configured in the
universal digital blocks (UDBs)
For PSoC 4200, both Components use a PSoC 4 serial communication block (SCB), in I C or EZI2C mode
2
2
Button press detect subsystem
The input Pin Component (labeled ‘SW’) is configured for Resistive Pull Up. The button shorts the pin to ground,
resulting in a logic ‘0’ when the button is pressed and a logic ‘1’ when it is released.
The CPU reads the button through a Status Register Component, which is connected to a Debouncer output
The Debouncer has a negative edge detect function, and the Status Register is configured for Sticky mode. This
causes the CPU to read a ‘1’ when a button is pressed, and a ‘0’ at all other times.
2
A display Component (Character LCD or Pins driving LEDs) to show that the I C Components are communicating.
Code Design
2
In both code examples, the main loop first executes the EZI2C slave side code, followed by the I C master code:
for(;;)
{
/* Do slave side tasks, with the EZI2C Component */
. . .
/* Do master side tasks, with the I2C Master Component */
. . .
}
The master and slave side each maintain their own data buffers. With EZI2C, the first N bytes of the buffer can be written by
the master; the remaining bytes are read-only. The master side buffer includes an additional byte ‘writeOffset’ to indicate the
location in the write area to start writing. All buffers are packed to ensure reading and writing the correct bytes.
PSoC 3 and PSoC 5LP Design
The PSoC 3 and PSoC 5LP example uses two buttons, which are available on the CY8CKIT-030, CY8CKIT-050, and
CY8CKIT-001. Button presses do the following:
If the button SW2 (on kit CY8CKIT-030 and CY8CKIT-050) is pressed, the EZI2C side updates its data buffer.
2
If the button SW3 is pressed, the I C master side does the following:
Reads the EZI2C buffer to its data buffer
Updates the write portion of its data buffer
Writes the write portion of its data buffer to the EZI2C
The Character LCD Component displays the contents of both data buffers.
PSoC 4200 Design
The PSoC 4200 example uses the single button, SW2, on the CY8CKIT-042 kit. The master and slave sides do the following:
The EZI2C side runs a code-based counter; the reload value is in its data buffer. Each time the counter rolls over, a
control byte for the LEDs is updated.
The I C master side does the following:
2
Reads the EZI2C buffer to its data buffer
Updates the LEDs based on the control byte in its buffer
If SW2 is pressed:
- Updates the counter reload value in the write portion of its data buffer
- Writes the write portion of its data buffer to the EZI2C
The LEDs change color continually; pressing the button changes the update rate.
www.cypress.com
Document No. 001-95314 Rev.*A
3
PSoC® 3, PSoC 4, and PSoC 5LP EZI2C
Design Considerations
Off-chip connections between the I C master and slave pins form an I C bus. External I C bus pull-up resistors may need
to be installed, depending on the kit that is used as well as the Pin Component configuration.
These code examples can be modified to:
2
2
2
Run on other kits, such as the CY8CKIT-049 or the CY8CKIT-001.
Communicate between two or more kits.
The PSoC Creator installation includes a program called Bridge Control Panel (BCP). BCP enables communications
between your PC and PSoC target devices, over I2C. You can use this link to control the PSoC and read and display data
from the PSoC. For more information, click the Help menu item in the BCP window.
Hardware Setup
For basic kit board setup, see the corresponding Kit Guide.
2
To form the off-chip I C bus, connect the master and slave SCL and SDA pins on the kit board:
For the PSoC 3 and PSoC 5LP example, connect P12[0] to P12[2], and P12[1] to P12[3]. This applies to all supported
kits.
2
To avoid having to add external I C bus pull-up resistors, configure the Pin Components as Resistive Pull Up instead
2
of the default Open Drain, Drives Low. This technique does not meet formal I C specifications but does work in most
cases. PSoC Creator emits warnings at project build time; the warnings can be ignored.
For the PSoC 4200 example, using the CY8CKIT-042:
Connect P0[4] to P4[0], by wiring kit connector J4 pin 1 to J3 pin 10.
Connect P0[5] to P4[1], by wiring kit connector J4 pin 2 to J3 pin 9.
2
Note that on the CY8CKIT-042 board, P4[0] and P4[1] have I C bus pull-up resistors installed.
Software Setup
No special software setup is required. All supported compilers can be used with any optimization.
At the PSoC Creator project’s default CPU clock speed (48 MHz for PSoC 3 and PSoC 5LP, 24 MHz for PSoC 4200), the CPU
has enough cycles to support the examples.
Components
Table 1 and Table 2 list the PSoC Creator Components used in each of the examples, as well as the hardware resources used
by each Component.
Table 1. List of PSoC Creator Components for PSoC 3 and PSoC 5LP Example
Component
www.cypress.com
Placement
EZI2C Slave
PSoC 3 or PSoC 5LP fixed I2C block, 1 interrupt
I2C Master (UDB)
~2 UDBs, 1 interrupt, 1 clock divider
Debouncer, 2 inputs
UDB (10 macrocells)
Clock
1 clock divider
Status Register, 2 input
UDB (1 status register)
Character LCD
7 pins
Pin
4 pins for the two I2C Components,
2 pins for the buttons, 7 pins for the Character LCD
Document No. 001-95314 Rev.*A
4
PSoC® 3, PSoC 4, and PSoC 5LP EZI2C
Table 2. List of PSoC Creator Components for PSoC 4200 Example
Component
Placement
EZI2C Slave (SCB mode)
PSoC 4200 SCB, 2 pins, 1 interrupt, 1 clock divider
I2C (SCB mode)
PSoC 4200 SCB, 2 pins, 1 interrupt, 1 clock divider
Debouncer, 1 input
UDB (5 macrocells)
Clock
1 clock divider
Status Register, 1 input
UDB (1 status register)
Control Register, 3 outputs
UDB (1 control register)
Pin
4 pins for the two I2C Components,
1 pin for the button, 3 pins for the RGB LED
Parameter Settings
Table 3 and Table 4 list the parameter settings for each of the PSoC Creator Components used in each of the examples. Only
the parameters that vary from the default values are listed.
Table 3. List of PSoC Creator Component Parameter Settings for PSoC 3 and PSoC 5LP Example
Component
Non-default Parameter Settings
EZI2C Slave
None
I2C Master (UDB)
UDB Clock Source = Internal Clock
Debouncer, 2 inputs
Signal width (bits) = 2, only Negative edge is checked
Clock
Frequency = 50 Hz
Status Register, 2 input
Inputs = 2, Display as bus is checked, Mode = Sticky for all bits
Character LCD
None
Pin
I2C Component pins: Drive mode = Resistive Pull Up
Button pins: Number of Pins = 2, Drive mode = Resistive Pull Up
Table 4. List of PSoC Creator Component Parameter Settings for PSoC 4200 Example
Component
www.cypress.com
Non-default Parameter Settings
EZI2C Slave (SCB mode)
None
I2C (SCB mode)
Mode = Master
Debouncer, 1 input
Only Negative edge is checked
Clock
Frequency = 50 Hz
Status Register, 1 input
Inputs = 1, Mode = Sticky for all bits
Control Register, 3 outputs
Outputs = 3
Pin
Button pin: Drive mode = Resistive Pull Up
Document No. 001-95314 Rev.*A
5
PSoC® 3, PSoC 4, and PSoC 5LP EZI2C
Design-Wide Resources
Figure 3 and Figure 4 show the pin assignments for each of the examples. No other design-wide resources need to be
changed from their default setting.
Figure 3. Pin Assignments for PSoC 3 and PSoC 5LP Example
Figure 4. Pin Assignments for PSoC 4200 Example
Operation
After building and installing the code example in the appropriate kit, test the code example by doing the following:
For the PSoC 3 and PSoC 5LP example:
Reset the PSoC. For example, press SW1 on the CY8CKIT-030 or CY8CKIT-050. Observe the character LCD.
2
Confirm that the bottom row is blank, indicating that the I C master has not yet read the EZI2C buffer.
Press the button SW2 (on the CY8CKIT-030 or CY8CKIT-050).
Confirm that the top row displays “EZ: 00 00 00 00”. That is, the EZI2C buffer is all zeros.
Confirm that the bytes in the EZI2C buffer are incremented, by different values, on each button press.
Press the button SW3 (on the CY8CKIT-030 or CY8CKIT-050).
Confirm that the bottom row displays “MST: ” followed by the contents of the EZI2C buffer. Confirm also that the first
2
two bytes are decremented by different values. That is, the I C master has read the EZI2C buffer and decremented the
read/write bytes of its buffer.
www.cypress.com
Document No. 001-95314 Rev.*A
6
PSoC® 3, PSoC 4, and PSoC 5LP EZI2C
Confirm that the top row displays the first two bytes in the EZI2C buffer as the same as those in the master buffer. This
indicates a successful write of the EZI2C data by the master.
For the PSoC 4200 example:
Reset the PSoC by pressing the button SW1 on the CY8CKIT-042.
Press the button SW2 on the CY8CKIT-042. Confirm that the RGB LEDs change color at a different rate. This indicates a
successful write of the EZI2C data by the master. The EZI2C data has a counter reload value that controls the rate of
change of the LED color.
Confirm that the RGB LED changes color at a high rate. This indicates a successful read of the EZI2C data by the master.
The EZI2C data has LED control bits that are continually changed by the EZI2C side code.
Upgrade Information
N/A
Related Documents
Table 5 lists all relevant application notes, code examples, knowledge base articles, device datasheets, and Component
datasheets.
Table 5. Related Documents
Application Notes
AN60317
PSoC 3 and PSoC 5LP I2C Bootloader
Shows how to build an I2C-based bootloader for PSoC 3 and PSoC 5LP
AN86526
PSoC 4 I2C Bootloader
Shows how to build an I2C-based bootloader for PSoC 4 family devices
AN50987
Getting Started with I2C in PSoC 1
Discusses the I2C protocol, and how PSoC 1 devices handle I2C
communications
AN74875
Designing with Cypress Serial I2C nvSRAM
Provides design guidelines and example circuits for the Cypress I2C
nvSRAM device
Code Examples
DelSig_I2CM
Provides an 8-channel multiplexed Delta Sigma ADC with sequencing logic. The analog inputs to the ADC
are converted to digital sequentially and then made available through an I 2C Master interface.
DelSig_I2CS
Provides an 8-channel multiplexed Delta Sigma ADC with sequencing logic. The analog inputs to the ADC
are converted to digital sequentially and then made available through an I2C Slave interface.
I2C_LCD_Example
Demonstrates the functionality of the I2C LCD Component
SCB_EzI2cCommSlave
Demonstrates the basic operation of the EZI2C Slave (SCB mode) Component
SCB_I2cCommMaster
Demonstrates the basic operation of the I2C Master (SCB mode) Component
SCB_I2cCommSlave
Demonstrates the basic operation of the I2C Slave (SCB mode) Component
Knowledge Base Articles
I2C pins in PSoC 3 and PSoC 5
Per PSoC 3 and PSoC 5 pinouts in the datasheet, there are only two sets of I2C
pins. Are these the only pins which can be used for I2C or is there a way to use
some other pins for I2C?
Assigning I2C SDA and SCL pins to any GPIO in
PSoC 3 and PSoC 5LP
When I try to route the I2C SCL and SDA pins to any GPIO, I get the following
error: IO "I2C_SCL(0)" cannot be placed into "PX[x]" because the pin does not
support the features required by the IO. (App=cydsfit) What is the reason for this
error and how can this be fixed?
Wiring a bus to I2C in PSoC Creator
How can I connect my I2C Component to a digital pin through a bus?
Multiple Slave Addresses with EZI2C
Can I have three slave address using an EZI2C Slave Component?
EZI2C does not work with address greater than
63
Why does the EZI2C User Module not work when the I2C address is greater than
63?
MiniProg3 connections for bootloading over I2C
How should I connect the MiniProg3 to a DVK board, to bootload over I2C?
www.cypress.com
Document No. 001-95314 Rev.*A
7
PSoC® 3, PSoC 4, and PSoC 5LP EZI2C
BootLdrI2C - In Master mode
Is it possible to configure the I2C bootloader in Master mode and read the firmware
from an external source?
Choosing an I2C slave in PSoC1
Under what application needs should we use I2CHW slave and under what needs
should we use EzI2Cs slave?
Dynamic I2C Pin Selection in PSoC 1
Can you dynamically change the I2C pin (from P1[7/5] to P1[1/0] or vice versa)?
Glitch on the PSoC 1 I2C Lines During Power Up
Why is there a glich on the I2C lines during Power On or Reset? How can this be
removed?
Operating EZI2C in PSoC at lower than 50KHz
frequency
I want to operate PSoC EZI2C as a slave in I2C communication. The I2C Master
clock frequency is 40KHz, but in PSoC Designer the options available for CLK are
50KHz, 100KHz and 400KHz. Can PSoC respond to 40KHz ?
Drive Mode Registers modification by I2Cm User
Module
Why does the I2Cm User Module modify the drive mode registers of the I2C pins,
rather than changing the data register?
Clock Stretching and I2C speed
How does the I2C clock speed affect the duration of clock stretching introduced by
the I2C slave?
Series resistors on I2C lines
Why are resistors of 330 ohm required on I2C lines?
PSoC Creator Component Datasheets
EZI2C Slave
Implements an I2C register-based slave device
I2C Master/Multi-Master/Slave
Supports I2C Slave, Master, and Multi-Master configurations
PSoC 4 Serial Communication Block (SCB)
Supports a PSoC 4 multifunction hardware block that implements I2C, SPI, UART, and
EZI2C communications
Debouncer
Takes an input signal from a bouncing switch contact and generates a clean output for
digital circuits
Control Register
Allows firmware to generate output digital signals
Status Register
Allows firmware to read digital signals
Character LCD (CharLCD)
Contains a set of library routines that enable simple use of one, two, or four-line LCD
modules that follow the Hitachi 44780 standard 4-bit interface
Clock
Creates local clocks, and allows connection to system and design-wide clocks
Pins
Controls interface with physical I/O port pins
External Library
Provides a way to include components external to the PSoC device – resistors,
capacitors, transistors, inductors, switches, etc. – on a PSoC Creator schematic.
Device Documentation
PSoC 3 Datasheets
PSoC 3 Technical Reference Manuals
PSoC 4 Datasheets
PSoC 4 Technical Reference Manuals
PSoC 5LP Datasheets
PSoC 5LP Technical Reference Manuals
Development Kit (DVK) Documentation
PSoC 3 and PSoC 5LP Kits
PSoC 4 Kits
www.cypress.com
Document No. 001-95314 Rev.*A
8
PSoC® 3, PSoC 4, and PSoC 5LP EZI2C
Document History
®
Document Title: CE95314 - PSoC 3, PSoC 4, and PSoC 5LP EZI2C
Document Number: 001-95314
Orig. of
Change
Submission
Date
Revision
ECN
**
4622360
MKEA
01/15/2015
New code example
*A
5081848
TDU
01/13/2016
Minor Grammatical Fixes
www.cypress.com
Description of Change
Document No. 001-95314 Rev.*A
9
PSoC® 3, PSoC 4, and PSoC 5LP EZI2C
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find
the office closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
cypress.com/go/automotive
psoc.cypress.com/solutions
Clocks & Buffers
cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Interface
cypress.com/go/interface
Lighting & Power Control
cypress.com/go/powerpsoc
Memory
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
cypress.com/go/usb
Wireless/RF
cypress.com/go/wireless
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
PSoC is a registered trademark and PSoC Creator is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks
referenced herein are the property of their respective owners.
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone
Fax
Website
: 408-943-2600
: 408-943-4730
: www.cypress.com
© Cypress Semiconductor Corporation, 2015-2016. The information contained herein is subject to change without notice. Cypress Semiconductor
Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any
license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or
safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The
inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies
Cypress against all charges.
This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide
patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a
personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative
works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source
Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the
right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or
use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a
malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
www.cypress.com
Document No. 001-95314 Rev.*A
10