AN96578 Designing with I2C F-RAM™ Author: Harsha Medu Associated Part Family: FM24xxx, CY15BxxxJ Associated Code Examples: For details, click here. Related Application Notes: For a complete list, click here. 2 AN96578 provides design guidelines and example circuits to help you design with the I C F-RAM™ device, a highperformance nonvolatile serial interface memory. Contents 1 2 Introduction ...............................................................1 2 I C F-RAM Configurations ........................................1 2 2.1 Applicability of I C-Bus Protocol Features .......2 2 2.2 I C F-RAM Device Options ..............................2 2 3 I C F-RAM System – Typical Configuration ..............3 2 4 Design Criteria for I C F-RAM ..................................4 4.1 Supply Voltage (VDD) .......................................4 4.2 Total Bus Capacitance (CB) .............................5 2 5 I C F-RAM Operation................................................7 5.1 WP Pin .............................................................7 5.2 A0, A1, A2 Pins................................................7 5.3 Slave Address..................................................7 1 5.4 Address Bytes ................................................. 7 5.5 Write Operation ............................................... 8 5.6 Read Operation ............................................... 8 5.7 Sleep Mode Entry ............................................ 9 5.8 Device ID ......................................................... 9 5.9 Serial Number ................................................ 10 2 6 I C F-RAM Code Example...................................... 10 7 Summary ................................................................ 10 8 Related Application Notes ...................................... 10 Document History............................................................ 11 Worldwide Sales and Design Support ............................. 12 Introduction Ferroelectric Random Access Memory (F-RAM) is a nonvolatile memory that uses ferroelectric technology to store data. The serial F-RAM device offers advantages over other nonvolatile serial memories due to its no-delay (or zerodelay) write. F-RAM can write hundreds of bytes in tens of microseconds. In comparison, EEPROM and flash memories take tens of milliseconds to write the same amount of data. The ability of F-RAM to write data quickly before losing power is particularly useful in systems that require preserving machine state information, parameter settings, or other vital data in a power-down event. F-RAM also has very high endurance over other nonvolatile solutions, allowing a large number of writes/reads to F-RAM without damaging its nonvolatile cells. F-RAM is a true nonvolatile RAM since it combines the advantages of both RAM and nonvolatile memory. It is 2 2 available in different interface options such as SPI, I C, and parallel. This application note discusses the I C interface 2 2 in F-RAM. It describes the different I C F-RAM configurations, shows I C F-RAM interface in a typical system, and gives design guidelines for using it in a system and the data format for accessing it. For other details such as AC, DC, 2 and timing parameters, refer to the specific I C F-RAM datasheet. 2 I2C F-RAM Configurations 2 The I C F-RAM supports a data transfer rate up to 3.4 Mbps as well as all other lower frequency accesses as defined 2 in the I C-bus specification. Standard mode (Sm): Bit rate up to100 Kbps Fast mode (Fm): Bit rate up to 400 Kbps Fast mode plus (Fm+): Bit rate up to 1 Mbps www.cypress.com Document No. 001-96578 Rev. ** 1 Designing with I2C F-RAM™ High-speed mode (Hs-mode): Bit rate up to 3.4 Mbps The Sm, Fm, and Fm+ bus modes are offered in all device configurations. The Hs-mode is offered only FM24Vxx and CY15BxxxJ series devices. 2.1 Applicability of I2C-Bus Protocol Features 2 2 Table 1 summarizes the mandatory and optional features of the standard I C-slave bus specifications. The I C 2 F-RAM supports all the mandatory features of a standard I C slave device. 2 Table 1. Applicability of I C Protocol I2C Spec Standards Feature I2C F-RAM START condition Mandatory Offered STOP condition Mandatory Offered Acknowledge Mandatory Offered 7-bit slave address Mandatory Offered 10-bit slave address Optional Not offered Clock stretching Optional Not offered General call address Optional Not offered Device ID Optional Offered1 Software reset Optional Not offered 1. Device ID feature is offered in FM24VXX and CY15BxxxJ devices only 2.2 I2C F-RAM Device Options 2 Cypress supports I C F-RAM in different configurations and packages, as listed in Table 2. 2 Table 2. I C F-RAM Configurations Part Number Status Density Operating Package Voltage (Typical) WP Pin A0 Pin A1/ No. of Device Serial Sleep Hs-Mode A2 Devices ID Number Mode (3.4 MHz) Pin per I2C Bus FM24C04B In Production 4 Kb 5.0 V 8 SOIC Yes No Yes 4 No No No No FM24CL04B In Production 4 Kb 3.3 V 8 SOIC Yes No Yes 4 No No No No FM24C16B In Production 16 Kb 5.0 V 8 SOIC Yes No No 1 No No No No FM24CL16B In Production 16 Kb 3.3 V 8 SOIC Yes No No 1 No No No No 8 DFN FM24C64B In Production 64 Kb 5.0 V 8 SOIC Yes Yes Yes 8 No No No No FM24CL64B In Production 64 Kb 3.3 V 8 SOIC Yes Yes Yes 8 No No No No Yes Yes Yes 8 Yes No Yes Yes 8 DFN FM24V01 NRND1 www.cypress.com 128 Kb 3.3 V 8 SOIC Document No. 001-96578 Rev. ** 2 Designing with I2C F-RAM™ Part Number Status Density Operating Package Voltage (Typical) WP Pin A0 Pin A1/ No. of Device Serial Sleep Hs-Mode A2 Devices ID Number Mode (3.4 MHz) 2 Pin per I C Bus FM24V01A In Production 128 Kb 3.3 V 8 SOIC Yes Yes Yes 8 Yes No Yes Yes CY15B128J In Production 128 Kb 3.3 V 8 SOIC Yes Yes Yes 8 Yes No Yes Yes FM24V02 NRND1 256 Kb 3.3 V 8 SOIC Yes Yes Yes 8 Yes No Yes Yes FM24V02A In Production 256 Kb 3.3 V 8 SOIC Yes Yes Yes 8 Yes No Yes Yes CY15B256J In Production 256 Kb 3.3 V 8 SOIC Yes Yes Yes 8 Yes No Yes Yes FM24W256 In Production 256 Kb 3.3 V 8 SOIC Yes Yes Yes 8 No No No No FM24V05 In Production 512 Kb 3.3 V 8 SOIC Yes Yes Yes 8 Yes No Yes Yes FM24V10 In Production 1 Mb 3.3 V 8 SOIC Yes No Yes 4 Yes No Yes Yes FM24VN10 In Production 1 Mb 3.3 V 8 SOIC Yes No Yes 4 Yes Yes Yes Yes 1. 3 Not Recommended for New Design I2C F-RAM System – Typical Configuration 2 2 Figure 1 shows a typical I C single-master multi-slave configuration. The I C master device can be any 2 microcontroller or a programmable device that is capable of generating the I C master protocols. The slave devices 2 2 can be any standard I C slave devices. In Figure 1, the slave devices are I C F-RAM devices. Since the 512-Kb and 2 lower density I C F-RAM devices support three slave addressing bits (A0, A1, and A2), it is possible to connect up to 2 2 eight devices on the same I C bus. A typical I C F-RAM slave device is shown in Figure 2. A unique slave ID is assigned to each slave device by configuring the slave select address lines (A2, A1, and A0). In packages where the 2 slave select address, A0, is not available, such as the 4-Kb and 1-Mb I C F-RAM, it is possible to connect only up to four slave devices sharing the same bus by configuring the slave select address pins A2 and A1. For 16-Kb F-RAM devices, the device select address pins (A0, A1, and A2) are not available; hence, only one device can be connected on the bus. 2 Figure 1. Single-Master Multi-Slave I C Configuration Slave Devices # www.cypress.com Document No. 001-96578 Rev. ** 3 Designing with I2C F-RAM™ 2 Figure 2. I C F-RAM Slave Device 4 Design Criteria for I2C F-RAM 2 I C is a two-wire synchronous bus with an SCL line used for transmitting clock and an SDA line used for transmitting 2 data. On the I C F-RAM device, the SCL line is an input, while the SDA line is an open-drain output. The open drain allows easy arbitration over control of the bus to implement bidirectional communication on a single data line and multi-master support. The SCL line, though input at F-RAM, is an open-drain output at the master. Hence, both the SCL and SDA lines require an external resistor to VDD to pull up the lines when they are released. There are two considerations when determining the pull-up resistor values (RP): Supply voltage (VDD) Total bus capacitance (CB) 2 Note: The pull-up resistor value calculations in the following sections are for the I C F-RAM SDA line. Based on the 2 master I C device, the calculation shown below should be repeated to determine the pull-up resistor value for the SCL line. 4.1 Supply Voltage (VDD) 2 2 Figure 3 shows the I C logic levels. The I C specification defines logic level low as the voltage below V IL, which is typically 30 percent of the supply voltage. Logic level high is defined as the voltage level above VIH, which is typically 70 percent of the supply voltage. A voltage between these two levels is undefined. 2 Figure 3. I C Bus Logic Levels The supply voltage will limit the minimum value of the pull-up resistor (RP). The pull-up resistor along with the ON resistance of the device transistor will form a potential divider network, as shown in Figure 4. A strong pull-up resistor will prevent the line from being sufficiently pulled low (below VIL) to allow it to be detected as a logical low. www.cypress.com Document No. 001-96578 Rev. ** 4 Designing with I2C F-RAM™ 2 Figure 4. I C Bus Line The ON resistance of the transistor is typically not specified. Instead, a maximum sink current (IOL) is specified, for which the voltage drop across the transistor should be below the output logical low-voltage level (VOL). – R R 2 For a typical 3.0-V I C F-RAM part operating at the maximum VDD voltage of 3.6 V, the VOL specification is a maximum of 0.4 V at an IOL of 2 mA. Hence – R 4.2 R Total Bus Capacitance (CB) Bus capacitance is the total capacitance contributed by all pins, connections, and PCB traces and wire. It can be significant for long traces and cabling of the SDA and SCL lines. When the SDA and SCL lines are released, it is pulled up by the external resistor (RP). The pull-up resistor (RP), along with the bus capacitance (CB), forms an RC circuit and thus limits the rise time of the SDA and SCL lines. The rise time is critical in high-speed operations, and if the resistor value is too high, the line may not rise to a logical high in time. Therefore, the total bus capacitance limits the rise time and in turn the maximum value of the pull-up resistor. For an RC circuit, R –R – 2 For I C, the rise time (tr) is defined as the time taken for the SDA or SCL line to rise from VIL (0.3 × VDD) to VIH (0.7 × VDD), as shown in Figure 5. The time taken to charge to the VIL level is –R – R – R The time taken to charge to the VIH level is –R Hence, the rise time R – R R 2 For the I C F-RAM in Fm-mode, the rise time tr = 120 ns. Hence, R www.cypress.com Document No. 001-96578 Rev. ** 5 Designing with I2C F-RAM™ 2 Figure 5. I C Line Rise Time Low-power designs should prefer using a pull-up resistor (RP) value towards the higher limit of the range to limit current consumption. Table 3 provides a list of the values of RP (Min, Max) for a given bus load condition and operating voltage. Shaded regions indicate that RP (Min) exceeds the RP (Max) value for a few bus loads (CB) under a given operating voltage condition. Since the RP (Min) can never exceed the RP (Max) value, this will put a limit on the 2 maximum capacitive load (CB) to be used on the I C bus. For example, if a 3-V part is configured to operate at a minimum VDD supply (VDD = 2.7 V), then the system must not exceed the load (in picofarads) given in Table 3 for the 2 SDA line. A similar calculation can be done on the SCL line for the I C master. Table 3. RP (Min, Max) Values for Different Bus Loads and Operating Voltages VDD = 3.6 V, R P(min) = 1.6 kΩ VDD = 3.0 V, R P(min) = 1.3 kΩ VDD = 2.7 V, R P(min) = 1.15 kΩ RP(Max) k Ω 1 MHz 3.4 MHz 120000 80000 RP(Max) k Ω 1 MHz 3.4 MHz 120000 80000 RP(Max) k Ω 1 MHz 3.4 MHz 120000 80000 Freq tR (ps) CB (pF) 10 20 30 40 50 60 70 80 90 100 125 150 175 200 250 300 350 400 450 500 550 Freq tR (ps) CB (pF) 14.16 7.08 4.72 3.54 2.83 2.36 2.02 1.77 1.57 1.42 1.13 0.94 0.81 0.71 0.57 0.47 0.40 0.35 0.31 0.28 0.26 www.cypress.com 9.44 4.72 3.15 2.36 1.89 1.57 1.35 1.18 1.05 0.94 0.76 0.63 0.54 0.47 0.38 0.31 0.27 0.24 0.21 0.19 0.17 10 20 30 40 50 60 70 80 90 100 125 150 175 200 250 300 350 400 450 500 550 Freq tR (ps) CB (pF) 14.16 7.08 4.72 3.54 2.83 2.36 2.02 1.77 1.57 1.42 1.13 0.94 0.81 0.71 0.57 0.47 0.40 0.35 0.31 0.28 0.26 9.44 4.72 3.15 2.36 1.89 1.57 1.35 1.18 1.05 0.94 0.76 0.63 0.54 0.47 0.38 0.31 0.27 0.24 0.21 0.19 0.17 10 20 30 40 50 60 70 80 90 100 125 150 175 200 250 300 350 400 450 500 550 Document No. 001-96578 Rev. ** VDD = 2.0 V, R P(min) = 0.8 kΩ Freq tR (ps) RP(Max) k Ω 1 MHz 3.4 MHz 120000 80000 CB (pF) 14.16 7.08 4.72 3.54 2.83 2.36 2.02 1.77 1.57 1.42 1.13 0.94 0.81 0.71 0.57 0.47 0.40 0.35 0.31 0.28 0.26 9.44 4.72 3.15 2.36 1.89 1.57 1.35 1.18 1.05 0.94 0.76 0.63 0.54 0.47 0.38 0.31 0.27 0.24 0.21 0.19 0.17 10 20 30 40 50 60 70 80 90 100 125 150 175 200 250 300 350 400 450 500 550 14.16 7.08 4.72 3.54 2.83 2.36 2.02 1.77 1.57 1.42 1.13 0.94 0.81 0.71 0.57 0.47 0.40 0.35 0.31 0.28 0.26 9.44 4.72 3.15 2.36 1.89 1.57 1.35 1.18 1.05 0.94 0.76 0.63 0.54 0.47 0.38 0.31 0.27 0.24 0.21 0.19 0.17 6 Designing with I2C F-RAM™ 5 I2C F-RAM Operation 2 The following sections briefly explain the I C F-RAM operation. For a detailed explanation, refer to the respective datasheets. 5.1 WP Pin The WP (Write Protect) pin protects the entire memory when pulled to V DD. It can be controlled by the microcontroller through a GPIO. For an application that does not use the write protect feature, this pin can be left floating. An internal pull-down will make the pin LOW. 5.2 A0, A1, A2 Pins 2 The A0, A1, A2 pins control the device address selection for the I C F-RAM device. They are internally pulled to LOW, so the default device address is 000 when these pins are left unconnected (floating). With different 2 combinations of A0, A1, A2 settings, a maximum of eight F-RAM devices can be connected to the same I C bus. 2 Most I C F-RAM devices have all three device address select pins. The exceptions are the 4-Kb and 1-Mb devices, which do not have the A0 pin, and the 16-Kb devices, which have none of the address select pins. 5.3 Slave Address 2 The I C F-RAM slave address is a 7-bit ID that includes fixed 4-bit slave id 1010b and user-configurable 3-bit device select bits (determined by the A0, A1, and A2 pins). 5.4 Address Bytes 2 Based on the memory density, the I C F-RAM read/write has 1- or 2-byte addresses, as shown in Table 4. 2 Table 4. Address Bits for Different Densities of I C F-RAM Slave Address Byte Density Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Address Byte 2 (MSB) Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Address Byte 1 (LSB) Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 4 Kb Slave Device Address A2 A1 A81 R/ N/A2 A7 A6 A5 A4 A3 A2 A1 A0 16 Kb Slave Device Address A101 A91 A81 R/ N/A2 A7 A6 A5 A4 A3 A2 A1 A0 64 Kb Slave Device Address A2 A1 A0 R/ X3 X3 X3 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 128 Kb Slave Device Address A2 A1 A0 R/ X3 X3 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 256 Kb Slave Device Address A2 A1 A0 R/ X3 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Slave Device Address A2 A1 A0 R/ A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Slave Device Address A2 A1 A161 R/ A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 512 Kb 1 Mb 1. This is the page select address bit. 2. 4-Kb and 16-Kb density F-RAMs have a 1-byte address. 3. U u d b of mo g fc dd by u u d dd b oc o o‘ ’ to a higher density option in the future. www.cypress.com do ’ c f mw T b , and F-RAM ignores them. However, the best practice is to pp o c m y to upgrade the firmware when moving Document No. 001-96578 Rev. ** 7 Designing with I2C F-RAM™ 5.5 Write Operation 2 All writes start with the master sending a slave address that identifies the device for communication on the I C bus. The write operation is indicated by setting the least significant bit of the slave address (R/ bit) to a '0'. The slave address is then followed by a 2-byte or 1-byte address based on the density of the F-RAM device, as listed in 2 Table 4. For 4-Kb, 16-Kb, and 1-Mb I C F-RAM devices, the slave address contains a few of the most significant bits of the memory address. The address is followed by the data to be written. For each byte, the F-RAM slave generates an Acknowledge. The write operation is terminated with a STOP condition. Figure 6 shows single-byte write, Figure 7 shows multi-byte write, and Figure 8 shows high-speed write. Hs-mode requires the Hs-mode command (0x08) before the write operation starts. Figure 6. Single-Byte Write Operation (256-Kb F-RAM) Figure 7. Multi-Byte Write Operation (256-Kb F-RAM) Figure 8. HS-Mode Single-Byte Write Operation (256-Kb F-RAM) 5.6 Read Operation The read operation involves either current address or selective (random) address reads. In current address reads, 2 shown in Figure 9, Figure 10, and Figure 11, the I C F-RAM uses the address latched internally in the last read/write operation. In selective (random) address read, shown in Figure 12, the address from which the data is being read is specified. Figure 9. Single-Byte Current Address Read Operation (256-Kb F-RAM) www.cypress.com Document No. 001-96578 Rev. ** 8 Designing with I2C F-RAM™ Figure 10. Multi-Byte (Sequential) Current Address Read Operation (256-Kb F-RAM) Figure 11. HS-Mode Single-Byte Current Address Read Operation (256-Kb F-RAM) Figure 12. Single-Byte Selective (Random) Address Read Operation (256-Kb F-RAM) 5.7 Sleep Mode Entry 2 A low-power mode called “sleep mode” is implemented in some I C F-RAM devices, as listed in Table 2. The F-RAM device enters sleep mode through the command 0x86, as shown in Figure 13. Figure 13. Sleep Mode Entry 5.8 Device ID Most F-RAM products define a three byte Device ID, which consists of a Manufacturing ID and a Product ID. It can be read through the command 0xF9, as shown in Figure 14. Figure 14. Read Device ID www.cypress.com Document No. 001-96578 Rev. ** 9 Designing with I2C F-RAM™ 5.9 Serial Number FM24VN10 defines a serial number that is unique to each device and read only. It is an 8-byte number that can be read through the command 0xCD, as shown in Figure 15. Figure 15. Read Serial Number 6 I2C F-RAM Code Example 2 2 I C F-RAM code example can be found in the pp c o o “AN74875 - Designing with Serial I C nvSRAM” AN74875 provides an associated project, which has a PSoC Creator Compo vRAM fo yp ’ o vo tile RAM products (nvSRAM and F-RAM). The PSoC Creator Component provides APIs to read and write from the memory. They also have APIs to execute device ID, serial number, and sleep mode entry. 7 Summary 2 2 This application note provides guidelines for designing applications with Cypress I C F-RAM. The I C F-RAM 2 2 supports the standard I C access protocols, similar to any other nonvolatile I C memory products. This makes the 2 F-RAM compatible with all I C master controllers and reduces system development cycle time. 8 Related Application Notes 2 AN407 - A Design Guide to I C F-RAM Processor Companions AN94901 - Migrating from FM24V02/FM24V01 to FM24V02A/FM24V01A www.cypress.com Document No. 001-96578 Rev. ** 10 Designing with I2C F-RAM™ Document History 2 Document Title: AN96578 – Designing with I C F-RAM™ Document Number: 001-96578 Revision ** ECN 4815420 www.cypress.com Orig. of Change MEDU Submission Date 06/29/2015 Description of Change New application note Document No. 001-96578 Rev. ** 11 Designing with I2C F-RAM™ Worldwide Sales and Design Support yp m wo dw d wo of off c ou o c the office closest to you, visit us at Cypress Locations. m uf c u ’ p v dd bu o To f d PSoC® Solutions Products Automotive cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Interface cypress.com/go/interface Cypress Developer Community Lighting & Power Control cypress.com/go/powerpsoc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/usb Wireless/RF cypress.com/go/wireless Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support PSoC is a registered trademark and F-RAM is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone Fax Website : 408-943-2600 : 408-943-4730 : www.cypress.com © Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a m fu c o o f u m y o b y b xp c d o u g fc ju y o u T c u o of yp ’ p oduct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. www.cypress.com Document No. 001-96578 Rev. ** 12