ISDN Remote Power Controller (IRPC) PSB 2120 CMOS IC Features ● Switched mode DC/DC-converter ● Switched mode DC/DC-converter ● CCITT (I.430) ISDN compatible ● Integrated 200 V power FET (only PSB 2120-P in P-DIP-22) ● Low power dissipation ● Supply voltage range 10 V to 60 V P-DSO-24-1 ● Input undervoltage detection ● Programmable overcurrent protection ● Soft start ● Control circuit to achieve minimum start-up current ● Power housekeeping input ● Oscillator synchronization input/output ● Polarity reversal detection ● High voltage CMOS-technology 60 V P-DIP-22 Type Version Ordering Code Package PSB 2120-P V B5 Q67100-H8645 P-DIP-22 PSB 2120-T V B5 Q67100-H6278 P-DSO-24-1 (SMD) The PSB 2120 is a Pulse Width Modulator (PWM) circuit designed for fixed-frequency switching regulators especially for telephony and ISDN-environments. The PSB 2120 is fully compatible with the CCITT-power recommendations on the “S”-interface. Coupled with a few external components it can provide a stable 5 V DC-supply for subscriber terminals (TE’s) or network terminators (NT’s). It can also be programmed for higher output voltages, e.g. to supply the S-lines with 40 V. In telephony and ISDN-systems a high conversion yield is crucial to maintain functionality in all supply conditions via “S”- or “U”-interfaces. The PSB 2120 design and technology realizes high conversion efficiency and low power dissipation. It should be recognized that the PSB 2120 can also be used in numerous DC/DC-conversion systems other than ISDN-power supplies. Semiconductor Group 3 12.92 PSB 2120 Pin Configurations (top view) P-DSO-24 Semiconductor Group P-DIP-22 2 PSB 2120 Pin Definitions and Functions Pin Pin No. No. P-DSO P-DIP Symbol Input (I) Output (O) Definition Function 1 1 SYNC I/O Synchronization Input for synchronization of the oscillator to an external frequency, or output to synchronize multiple devices. 2 2 RC I RC-Oscillator The external timing components of the ramp generator are attached to this pin. 3 3 COMP O Compensation Error amplifier output and Pulse Width Modulator (PWM) input for loop stabilization network. 4 4 VP I Positive Voltage Sense Non-inverting input of the error amplifier. 5 5 VN I Negative Voltage Inverting input of the error amplifier. Sense 6 6 CSS I Soft Start Capacitor The capacitor at this pin determines the soft-start characteristic. 7 7 EME O Emergency A low input voltage at POL will activate the output EME. 8 8 POL I Polarity Detection POL is the input to a non inverting Schmitt-trigger. 11 9 GA O Gate Output of the FET-driver. N.C. 10 DR O Drain Drain connection of the power FET. N.C. 11 SO O Source Source connection of the power FET. 14 12 CIN I Input Capacitor CIN has to be connected to the input buffer-capacitor and a current limiting charging-resistor. Semiconductor Group 3 PSB 2120 Pin Definitions and Functions (cont’d) Pin Pin No. No. P-DSO P-DIP Symbol Input (I) Output (O) Definition Function 15 13 ENA I Enable A high input voltage at this pin will stop the IRPC-function. 16 14 CO O Comparator output 17 15 CN I Comparator neg. input 18 16 CP I Comparator pos. input 19 17 GND I Ground All analog and digital signals are referred to this pin. 20 18 VEXT I/O External supply Output of the internal CMOS-supply. Via VEXT the internal CMOS-circuits can be supplied from an external DC-supply in order to reduce chip power dissipation. 21 19 IN I Negative current sense 22 20 IP I Positive current sense When the voltage difference between these two pins exceeds 100 mV, the digital current limiting becomes active. 23 21 VREF O Reference voltage Output of the 4.0 V reference voltage. 24 22 VS I Supply voltage VBAT is the positive input voltage. Semiconductor Group 4 Connections of the universal usable comparator. PSB 2120 Figure 1 IRPC Functional Diagram Semiconductor Group 5 PSB 2120 Functional Description The reference provides a 4.0 V voltage for the regulation loop. A high gain error amplifier compares the reference voltage with the switch mode supply output voltage. The output of the error amplifier is compared with a periodic linear ramp, which is generated by the sawtooth-oscillator circuit. The comparator output is a fixed-frequency, variable pulse width logic signal, which passes through logic circuits to the high voltage power-switching-FET. A digital current limiting device suppresses the PWM logic signal when the voltage difference at the current limit sense input reaches 100 mV. In this case the control logic inhibits double pulses during one oscillator period. Start-Up Procedure Before the switched-mode DC/DC-converter starts, a sequence of several conditions has to be passed in order to avoid any system malfunction. The primary undervoltage detection inhibits the converter function. This insures that all control functions have stabilized in the proper state when the turn on voltage (ca. 10 V) is reached, and it prevents start-up glitches. In case of connecting the TE to powered lines or if a line is powered up, the charge current of the primary buffer capacitor is limited by an external resistor (figure 2). This resistor is short-circuited by the PSB 2120 when the voltage drop across it falls below approximately 2.0 V. The residual resistance of this short-circuit is about 3 Ω. In case of a primary undervoltage detection the short-circuit will be always deactivated. So, the DC/DC-converter does not start until the charging of the primary buffer capacitor is completed, and the maximum line input voltage is reached. If this feature is not desired, CIN has to be connected to GND. In this case the primary current measuring circuit turns off, to reduce chip-power dissipation from 9 mW to 6 mW. In order to avoid high current peaks during the charging of the secondary capacitors or line capacitors in case of supplying an S-interface, a soft start circuit is implemented in the PSB 2120. This circuit requires an external capacitor, connected between CSS and GND. In addition, the enable input (ENA) allows an external switch-on/switch-off control. If the DC/DCconverter is disabled via ENA, the soft-start-capacitor at pin CSS is discharged. This input can also be used for several other functions, e.g. secondary overvoltage protection. Semiconductor Group 6 PSB 2120 Figure 2 DC/DC-Conversion The PSB 2120 contains a SIPMOS-transistor for power handling. Non-isolated and isolated SMPSconfigurations are possible. Logic and analog circuits are implemented in CMOS in order to achieve low power dissipation. The error amplifier compares the sensed voltage with a reference attached to VP and thus controls the Pulse Width Modulator (PWM). The conversion frequency is generated by a sawtooth oscillator which can be controlled by external RC-components (figure 4) or by an external synchronization signal. The PSB 2120 is synchronized by the rising edge of the sync signal, whose frequency must be 10 % higher than the free run frequency, determined by the RC-components. The SYNC-pin can also be used as a trigger-output. As long as the capacitor of the sawtooth oscillator is discharged, SYNC is high. The output of the PWM is processed by the control logic and fed to the SIPMOS-transistor. The control logic suppresses higher oscillations of the regulation loop caused e.g. in case of current limit detection. Semiconductor Group 7 PSB 2120 Polarity Detection Emergency conditions are signaled to the TE by the reversed polarity of the line feeding voltage. When polarity reversal is detected via pin POL of the PSB 2120, emergency conditions are signaled to the microprocessor via pin EME, which should shut down all activity except simple telephony functions to minimize power dissipation. The polarity detection circuit can also be used for other detection or protection-functions, e.g. programmable primary undervoltage detection. Power Housekeeping An integrated 6 V linear voltage regulator supplies the internal circuits during the start-up phase. Power dissipation of this regulator can be reduced, if an auxiliary winding of the transformer or an external supply is used for that purpose by connecting it to VEXT. If the input voltage at VEXT reaches 6.2 V the internal linear voltage regulator turns off and the internal circuits are fed from this external voltage. In this case the input current at VEXT is approx. 0.5 mA. Note: An internal 7.5 V Zener-diode protects the VEXT input against overvoltages. The maximum Zener-current is 2 mA! If the external supply isn’t stabilized, the input current must be limited (e.g. by a resistor)! Interface to Microprocessor The PSB 2120 offers two TTL-compatible signals: EME and CO. The EME (Emergency-output) becomes active, if polarity reversal is detected. CO is the output of a universal usable comparator; e.g.: to generate a microprocessor-reset signal. Semiconductor Group 8 PSB 2120 PSB 2120 Applications in ISDN-Environments Figure 3 shows an example out of the wide application field of the PSB 2120. In the network termination one PSB 2120 supplies the internal IC’s directly from the U–interface. A second IRPC, also powered from the U-line, supplies the S–interface if the main supply of the NT is out of order. A third IRPC is used in the main supply to regulate the S-line feeding voltage. In the subscriber terminal the PSB 2120 is used for feeding the internal circuits. The PSB 2120 accommodates both galvanically isolated and non-isolated configuration. Considering the diversity of DC/DC-converter applications, this part of the specification only shows how to use the special ISDN-features of the PSB 2120. The switching frequency of the SMPS is programmable by two external components. Figure 4 shows the switching frequency as a function of RT and CT. The minimum configuration so as to be able to use the PSB 2120 in ISDN-applications is by using a flyback converter (figure 5). The time constant of the soft start circuit is programmed by a capacitor at Pin CSS. Figure 6 shows the primary start-up current limitation by connecting Pin CIN. To reduce chip-powerdissipation, an auxiliary winding of the transformer is used to switch off the internal linear CMOSsupply (pin VEXT). Polarity reversal is detected by pin POL. Figure 7 shows the realization of a microprocessor-reset-signal with the universal usable comparator of the IRPC. Figure 8 shows the PSB 2120 in flyback configuration with transformer isolation. Figure 9 shows the PSB 2120 in flyback configuration with opto isolation, which is useful for a high reliability galvanically isolated application. Semiconductor Group 9 PSB 2120 Figure 3 IRPC in ISDN-Concept Semiconductor Group 10 PSB 2120 Switching Frequency Figure 4 Switching Frequency as a Function of RT and CT Semiconductor Group 11 PSB 2120 Figure 5 PSB 2120 Minimum Configuration Semiconductor Group 12 PSB 2120 Figure 6 Advanced IRPC-Application with Power Housekeeping and Polarity Reversal Detection Semiconductor Group 13 PSB 2120 According to the application in figure 5 and an output power of 500 mW, t1 will be 400 ms and t2 50 ms. Figure 7 Generation of a µP-Reset Signal with the PSB 2120 Semiconductor Group 14 PSB 2120 Figure 8 PSB 2120 in Flyback Configuration with Transformer Isolation Semiconductor Group 15 PSB 2120 Figure 9 PSB 2120 in Flyback Configuration with Opto Isolation Semiconductor Group 16 PSB 2120 Absolute Maximum Ratings (All pin references made for P-DIP-22) Parameter Symbol Limit Values Unit Supply voltage DR (pin 10) referred to S0 (pin 11) VS 200 V Continuous drain current (pin 10) IDR 350 mA Supply voltage VBAT (pin 22) referred to GND VBAT 60 V Analog/digital input voltage referred to GND (pins 2, 3, 4, 5, 7, 8, 13, 15, 16, 19, 20) VI A/D 6 V Reference output current (pin 21) IO REF –5 mA VEXT input Z-current II Z 2 mA VEXT output current IO –5 mA SYNC-output current (pin 1) IO SYNC –5 mA Driver output current (pin 9) IO DR –5 mA Ambient temperature under bias TA – 25 to 85 ˚C Storage temperature Tstg – 40 to 125 ˚C Thermal resistance junction – ambient Tj 50 K/W MOS-Handling: The integrated SIPMOS-transistor (pin 9, 10 and 11) has to be protected against electrostatic charges. The input gate-source (pin 9 and pin 11) must be protected against ± 10 V. DC Characteristics TA = 0 to 70 ˚C, VS = 11 to 60 V Parameter Symbol Limit Values Unit Test Condition min. typ. max. 3.92 4.0 4.08 V IL = 0 mA, VS = 40 V 60 mV VS = 20 to 60 V, IL = 0 mA, 40 mV IL = 0.1 to 0.3 mA, VS = 40 V Reference VREF TA = 25 ˚C Output voltage VREF O Line regulation VREF Line Load regulation VREF Load 20 Temperature stability VREF TS 25 Load current IREF Load Semiconductor Group mV 0.5 17 mA PSB 2120 DC Characteristics (cont’d) Parameter Symbol Limit Values min. typ. Unit Test Condition max. Oscillator SYNC (pin1), RC (pin 2) fOSC = 20 kHz, RT 39 kΩ ± 1 %, CT= 1 nF ± 1 %, TA = 25 ˚C Initial accuracy ± 10 Voltage stability of fOSC 1 Temperature stability of fOSC 5 % kHz % 3 % Max. frequency fmax 180 250 RT = 27 kΩ CT = 39 pF H-sawtooth voltage VH 3.0 3.2 3.4 V L-sawtooth voltage VL 1.6 1.8 2.0 V H-sync output level VOH 2.4 3.5 5.25 V IL = 0.5 mA VS EXT ≤ 6.3 V L-sync output level VOL 0.2 0.8 V IL = 20 µA VCM = 3.0 V Error Amplifier COMP (pin 3), VP (pin 4), VN (pin 5) Input offset voltage VIO 3 10 mV Input current II 0 25 nA Common mode range VC 1.8 4.0 V DC open loop gain GVO 60 70 dB Common mode rejection kCMR 60 70 dB Unit gain bandwidth f 0.5 1 MHz 60 70 dB 4 5.5 V IL = 100 µA 0.02 V IL = 10 µA VS = 40 V Supply voltage rejection H-output voltage VOH L-output voltage VOL VOFFSET = ± 15 mV CL (pin) 10 pF Current Limit Comparator IP (pin 20), IN (pin 19) TA = 25 ˚C Sense voltage VSense Input current II Input voltage range VI Response time to signal at GA (pin 9) tRes Semiconductor Group 85 100 115 mV 0 100 nA 1 V 2 µs 0 1 18 IN = 0 V IP = 0 → 200 mV PSB 2120 DC Characteristics (cont’d) Parameter Symbol Limit Values min. typ. Unit Test Condition max. Pulse Width Modulator td 0 Start-up threshold VUV St 8.1 Threshold hysteresis VUV Hy Duty cycle 50 % 11 V Undervoltage Detection 10 0.3 V Soft Start CSS (pin 6) Charging current IC 2 4 8 µA Output Driver GA (pin 9) TA = 25 ˚C, CL = CGS – Power FET H-output voltage VOH V ISource = 5 mA H-output voltage VOH V EXT V ISource = 0 mA L-output voltage VOL 0.3 0.4 V ISink = 5 mA Rise time tr 130 200 ns V EXT = 6.3 V Fall time tf 70 200 ns V EXT = 6.3 V Output current IO 5 mA 4.5 External Supply VEXT (pin 18) Output voltage VO Output current IO Input voltage VI Z-current IZ 5.8 V 2 mA 7.5 V 2 mA 5.25 V 0.8 V 0.5 1 µs 2.5 20 µA 6.0 Enable Input ENA (pin 13) H-input voltage VIH L-input voltage VIL Response time to signal at GA (pin 9) tRes H-input current IIH Semiconductor Group 2.0 0.2 19 TA = 25 ˚C PSB 2120 DC Characteristics (cont’d) Parameter Symbol Limit Values min. typ. max. Unit Test Condition VCM = 3 V Comparator CN (pin 15), CP (pin 16), TA = 25 ˚C Input offset voltage VIO 3 10 mV Input bias current II 0 25 nA Input voltage range VI 4.5 V Response time to signal at CO (pin 14) tRes 0.2 1 µs 2 3 V 3 4 Ω 5.25 V 0.8 V 1 10 µA 0.2 1 µs 3.5 5.25 V 0.2 0.4 V RDS (on) 4 6 Ω ton td (on) 55 150 ns toff td (off) 110 200 ns Leakage current ILeak 200 nA VDS = 110 V Power consumption Ptot 9 10 mA VS = 40 V fOSC = 20 kHz V EXT = 6.3 – 6.7 V CGS 200 1.8 Short Circuit GI (pin 12), TA = 25 ˚C Sense voltage VSense 1 RDS (on) (VS – VCIN) Polarity Detection POL (pin 8), EME (pin 7) H-input voltage VIH L-input voltage VIL H-input current IIH Response time to signal at EME (pin 7) tRes 2.0 0.1 Digital Outputs EME (pin 7), CO (pin 14) IOUT = 0.5 mA H-output voltage VOH L-input voltage VIL 2.4 V EXT ≤ 6.3 V Power FET GA (pin 9), DR (pin 10), SO (pin 11) Semiconductor Group 20 pF ID = 300 mA