DC947A - Demo Manual

DEMO CIRCUIT 947
LT3740EDHC
QUICK START
GUIDE
LT3740EDHC
Wide Operating Range, Valley Mode,
No RSENSE™ Synchronous Step-Down Controller
DESCRIPTION
Demonstration circuit 947 is a Wide Operating
Range, Valley Mode, No RSENSE™ Synchronous
Step-Down Controller featuring the LT3740EDHC.
It produces 1.8VDC for loads up to 10A from an
input range of 3-15VDC, switching at a fixed frequency of 300KHz.
control of the output voltage during operation, output voltage tracking or soft-start.
In order to operate from an input voltage as low as
3V, the circuit must provide adequate voltage to
drive the external power MOSFETs. To this end,
the LT3740 includes an on-chip step-up converter
to provide a bias about 7V above the input voltage
to power the top MOSFET gate driver. The stock
configuration of DC947 also uses this bias to
power the bottom gate drive circuit, but pads have
been added to the circuit board to power the bottom gate drive from another source.
DC947 is equipped with jumpers that allow the
user to select among soft-start options and reference voltage sources. Unpopulated pads have
been added to DC947 in order to facilitate input
voltages higher than 15V and No RSENSE™ operation.
The LT3740 is equipped with an external reference
input that allows the user to override the 0.8V internal reference with any lower value, allowing full
PERFORMANCE SUMMARY
SYMBOL
VIN
VOUT
IOUT
VRIPPLE
PARAMETER
Input Supply Range
Output Voltage Range
Output current
Output Ripple
In addition, the LT3740 has three current limit levels that can be chosen by connecting the RANGE
pin to ground, leaving it open circuit, or tying to the
input.
Design files for this circuit board are available.
Call the LTC factory.
and LT are registered trademarks of Linear Technology Corporation. No RSENSE
is a trademark of Linear Technology Corporation. Other product names may be
trademarks of the companies that manufacture the products.
Specifications are at TA = 25°C
CONDITIONS
VIN = 3.0 – 15.0V, ILOAD = 0-10A
VIN = 3.0 – 15.0V, VOUT = 1.8V
VIN = 3.0 – 15.0V, ILOAD = 0-10A
MIN
3.0
1.76
0
TYP
MAX
15.0
1.84
10.0
20
UNITS
V
V
A
mV
QUICK START PROCEDURE
Demonstration circuit 947 is easy to set up to
evaluate the performance of the LT3740EDHC.
Refer to Figure 1 for proper measurement equipment setup and follow the procedure below:
1
LT3740EDHC
NOTE. When measuring the output voltage ripple, care must be
taken to avoid a long ground lead on the oscilloscope probe.
Measure the input or output voltage ripple by touching the probe tip
directly across the Vin or Vout and GND terminals. See Figure 2 for
proper scope probe technique.
1. Place jumpers in the following positions:
JP1 Up (Internal Reference)
JP2 Up (Voltage_SS ON)
JP3 Down (Current_SS ON)
2. With power off, connect the input power supply
to Vin and GND.
4. Turn on the power at the input. Make sure that
the input voltage is between 3 and 15V.
NOTE. Make sure that the input voltage does not exceed 15V.
5. Check for the proper output voltages. Vout
should be 1.8V, nominal. If there is no output,
temporarily disconnect the load to make sure
that the load is not set too high.
6. Once the proper output voltages are established, adjust the loads within the operating
range and observe the output voltage regulation, ripple voltage, efficiency and other parameters.
3. Connect the 0-10A load.
Figure 1. Proper Measurement Equipment Setup
2
LT3740EDHC
GND
VIN
Figure 2. Measuring Input/Output Ripple
OPERATION
The LT3740 is a current-mode synchronous buck
controller that can accept input voltages as low as
2.2V, and as high as 22V, but still provides at least
7V for the MOSFET gate drives through an internal
boost regulator. It is equipped for No RsenseTM
operation to maximize efficiency and features
three user selectable current limit ranges and a
flexible soft-start system capable of output tracking.
To close the current loop, the LT3740 reads the
switching current through the bottom MOSFET
“on” resistance. The chip features three user selectable current limit thresholds to optimize efficiency: 45mV, 75mV and 105mV. DC947 uses the
middle setting, but unpopulated pads are available
for selecting the other two settings.
In the interest of making the board able to handle a
wide variety of input and output voltage combinations, DC947 does not use the No RsenseTM feature, but has been configured so that it is easy to
do so. This is accomplished by shorting out the
R1 sense resistor and moving the zero ohm resistor at location R14 to location R13. Change R28
to 1 ohm. Other component changes unique to
the desired output voltage, input voltage range and
frequency compensation may be necessary.
DC947 is configured such that the bottom gate
drive power (BGDP) pin is connected directly to
the output of the on-chip boost regulator (BIAS)
through R32. This is what allows the circuit to provide sufficient power MOSFET gate drive when the
input is as low as 3V.
If the design is not required to operate at input
voltages below 7V, the BGDP pin can be tied to
Vin to reduce the loading on the boost converter
and thus save power. To do this, move the zero
ohm resistor at location R32 to R31 and add a 1uF
ceramic capacitor at location C25. Also, implement the UVLO circuit by removing R30 and populating the circuitry made up of D3, Q3, and R29.
The LT3740 has an active high, open collector
power good signal. On the demo board, it is pulled
up to the 1.8V output through a 100K resistor, and
can be conveniently read at TP6. Note that this
pull-up voltage may not be compatible with all voltage systems. Please refer to the data sheet for a
detailed description of the PGOOD signal.
A 0-0.8V external reference may be applied to the
LT3740 at TP5. This is used to over-ride the internal 0.8V reference, giving control of the DC947
output voltage to an external signal source. Use of
this function must first be enabled by setting JP1
(REFERENCE) to the EXTERNAL position. For
further details about the external reference function, please refer to the XREF function described
in the LT3740 data sheet.
JP2 (VOLTAGE_SS) and JP3 (CURRENT_SS)
must both be set to their respective ON positions
in order for the DC947 output to power up. If either of these jumpers is set to the OFF position,
the output will not turn on. JP2 (VOLTAGE_SS) is
associated with the XREF input, while JP3
(CURRENT_SS) ties into the SHDN input. For
further details about the LT3740 soft-start operation, please refer to the data sheet.
On the DC947 demo board, the signals applied to
both of the soft-start inputs are generated by simple RC circuits. The RC time constant of the
CURRENT_SS soft-start is much longer than that
of the VOLTAGE_SS, so the CURRENT_SS will
3
LT3740EDHC
dominate the behavior of the demo board output.
To observe the behavior of the output when under
VOLTAGE_SS control, simply change the RC time
constant of R18 and C15 to make it longer than
that of R22 and C20. Make sure that JP1 is set to
INTERNAL.
DC947A is equipped with many optional components to facilitate the implementation of many optional functions. A simplified schematic of essential components is shown in figure 3, while a full
schematic of the board is given in at the end of this
document.
VIN
3-15V
R22
15K
9
10
C22
10uF
R18
100K
13
12
14
16
11
R20
12K
C14
100pF
C13
2200pF
SWB
BGDP
VIN
BIAS
SHDN
TGATE
PGOOD
SW
XREF
SN+
VC
BGATE
RANGE
C20
1uF
SNGND
R33
100K
C21
1uF
U1
LT3740EDHC
C23
0.01uF
PGND
FB
4
8
C10
C16
10uF each
7
L1
6
R19
10
3
2
VOUT
1.8V @ 10A
0.9uH
5
1
+ C1
150uF
Q1
PH8230E
Q2
PH3830L
D1
B320A
C12
22pF
R16
100K
1%
15
17
L2
22uH
R1
0.007
R17
80.6K
1%
Figure 3. Simplified Schematic showing only essential components.
4
C17
C18
C19
100uF each
LT3740EDHC
5
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