Three-Phase Buck Controller with 5-Bit DAC

CS5323
Three−Phase Buck
Controller with 5−Bit DAC
The CS5323 is a three−phase step down controller that incorporates
all control functions required to power next generation processors.
Proprietary multi−phase architecture guarantees balanced load current
distribution and reduces overall solution cost in high current
applications. Enhanced V2™ control architecture provides the fastest
possible transient response, excellent overall regulation, and ease of
use.
The multi−phase architecture reduces input and output filter ripple,
allowing for a reduction in filter size and inductor values with a
corresponding increase in the output inductor current slew rate.
20
1
SO−20L
DW SUFFIX
CASE 751D
PIN CONNECTIONS AND
MARKING DIAGRAM
ROSC
COMP
VFB
VDRP
CS1
CS2
CS3
CSREF
ILIM
REF
1
A
WL, L
YY, Y
WW, W
CS5323
AWLYWW
Features
• Enhanced V2 Control Method
• 5−Bit DAC with 1.0% Tolerance
• Adjustable Output Voltage Positioning
• Programmable Frequency Set by Single Resistor
• 200 kHz to 800 kHz Operation (Per Phase)
• Current Sensed through Sense Resistors, or Buck Inductors
• Adjustable Current Sense Threshold
• Hiccup Mode Current Limit
• Over−Voltage Protection through Synchronous MOSFET’s
• Individual Current Limits for Each Phase
• On−Board Current Sense Amplifiers
• 3.3 V, 1.0 mA Reference Output
• 5.0 V and/or 12 V Operation
• On/Off Control (through COMP Pin)
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VCC
GATE1
GATE2
GATE3
GND
VID4
VID3
VID2
VID1
VID0
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 7
1
Package
Shipping
CS5323GDW20
SO−20L
37 Units/Rail
CS5323GDWR20
SO−20L
1000 Tape & Reel
Publication Order Number:
CS5323/D
CS5323
L1
12 VIN
300 nH
D1
+
C4
C13
3 × 16S0180M
5 VIN
C5
1.0 μF
C24
.01 μF .01 μF
10 k
U3
VID4
VID3
CSREF
VID2
ILIM
REF
VID1
VID0
D5
VID0
C21
.01 μF
R15
30.1 k
R16
30.1 k
R17
30.1 k
R14
2.7 k
C25
0.1 μF
BAS40LT1
C27
1.0 μF
VID1
Q2
BAS40LT1
L3
850 nH
Q4
C20
3×
10 μF
C26
1.0 μF
Q5
MTD3302
VID2
L4
VID3
U4
VID4
R18
1.0 k
R19
10 k
Figure 1. Application Diagram, 12 V to 1.7 V Converter
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2
VOUT
+ C16
8×
4SP560M
Q3
1.0 μF
MTD3302
MTP75N06HD
C23
CS3
C19
1.0 μF
CO
CST
TG
DRN
R13
GATE3
Gnd
L2
850 nH
C18
D3
NCP5351
CS2
VCC
GATE1
GATE2
EN
VS
BG
Gnd
ROSC
COMP
VFB
VDRP
CS1
R6
7.5 k
C22
.01 μF
MTP75N06HD
U2
MTP75N06HD
C11
2.0 nF
CO
CST
TG
DRN
.01 μF
75 k
U1
NCP5351
R12
CS5323
C28
1.0 nF
C17
EN
VS
BG
Gnd
C4
0.1 μF
R9
1.0 k
Q1
MTD3302
R1
10 Ω
C12
1.0 nF
R10
8.0 k
1.0 μF
NCP5351
EN
CO
VS CST
TG
BG
Gnd DRN
ENABLE
BAS40LT1
850 nH
Q6
CS5323
MAXIMUM RATINGS*
Rating
Operating Junction Temperature
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1)
Storage Temperature Range
ESD Susceptibility (Human Body Model)
Value
Unit
150
°C
230 peak
°C
−65 to +150
°C
2.0
kV
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
MAXIMUM RATINGS
Pin Number
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
1
ROSC
6.0 V
−0.3 V
1.0 mA
1.0 mA
2
COMP
6.0 V
−0.3 V
1.0 mA
1.0 mA
3
VFB
6.0 V
−0.3 V
1.0 mA
1.0 mA
4
VDRP
6.0 V
−0.3 V
1.0 mA
1.0 mA
5−7
CS1−CS3
6.0 V
−0.3 V
1.0 mA
1.0 mA
8
CSREF
6.0 V
−0.3 V
1.0 mA
1.0 mA
9
ILIM
6.0 V
−0.3 V
1.0 mA
1.0 mA
10
REF
6.0 V
−0.3 V
1.0 mA
50 mA
11−15
VID0−4
6.0 V
−0.3 V
1.0 mA
1.0 mA
16
Gnd
0V
0V
0.4 A, 1.0 μs, 100 mA
DC
N/A
17−19
GATE 1−3
16 V
−0.3 V
0.1 A, 1.0 μs, 25 mA DC
0.1 A, 1.0 μs, 25 mA DC
20
VCC
16 V
−0.3 V
N/A
0.4 A, 1.0 μs, 100 mA
DC
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3
CS5323
ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 0°C < TJ < 85°C; 4.7 V < VCC < 14 V; CGATE = 100 pF,
RR(OSC) = 53.6 k, CCOMP = 0.1 μF, CREF = 0.1μF, DAC Code 10000, CVCC = 0.1 μF, ILIM ≥ 1.0 V; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
± 1.0
%
Voltage Identification DAC (0 = Connected to VSS; 1 = Open or Pull−up to 3.3 V)
Measure VFB = COMP
Accuracy (all codes)
VID4
VID3
VID2
VID1
VID0
1
1
1
1
1
−
1.064
1.075
1.086
V
1
1
1
1
0
−
1.089
1.100
1.111
V
1
1
1
0
1
−
1.114
1.125
1.136
V
1
1
1
0
0
−
1.139
1.150
1.162
V
1
1
0
1
1
−
1.163
1.175
1.187
V
1
1
0
1
0
−
1.188
1.200
1.212
V
1
1
0
0
1
−
1.213
1.225
1.237
V
1
1
0
0
0
−
1.238
1.250
1.263
V
1
0
1
1
1
−
1.262
1.275
1.288
V
1
0
1
1
0
−
1.287
1.300
1.313
V
1
0
1
0
1
−
1.312
1.325
1.338
V
1
0
1
0
0
−
1.337
1.350
1.364
V
1
0
0
1
1
−
1.361
1.375
1.389
V
1
0
0
1
0
−
1.386
1.400
1.414
V
1
0
0
0
1
−
1.411
1.425
1.439
V
1
0
0
0
0
−
1.436
1.450
1.465
V
0
1
1
1
1
−
1.460
1.475
1.490
V
0
1
1
1
0
−
1.485
1.500
1.515
V
0
1
1
0
1
−
1.510
1.525
1.540
V
0
1
1
0
0
−
1.535
1.550
1.566
V
0
1
0
1
1
−
1.559
1.575
1.591
V
0
1
0
1
0
−
1.584
1.600
1.616
V
0
1
0
0
1
−
1.609
1.625
1.641
V
0
1
0
0
0
−
1.634
1.650
1.667
V
0
0
1
1
1
−
1.658
1.675
1.692
V
0
0
1
1
0
−
1.683
1.700
1.717
V
0
0
1
0
1
−
1.708
1.725
1.742
V
0
0
1
0
0
−
1.733
1.750
1.768
V
0
0
0
1
1
−
1.757
1.775
1.793
V
0
0
0
1
0
−
1.782
1.800
1.818
V
0
0
0
0
1
−
1.807
1.825
1.843
V
0
0
0
0
0
−
1.832
1.850
1.869
V
Input Threshold
VID4, VID3, VID2, VID1, VID0
1.00
1.25
1.50
V
Input Pull−up Resistance
VID4, VID3, VID2, VID1, VID0
25
50
100
kΩ
3.15
3.30
3.45
V
Pull−up Voltage
−
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CS5323
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 85°C; 4.7 V < VCC < 14 V; CGATE = 100 pF,
RR(OSC) = 53.6 k, CCOMP = 0.1 μF, CREF = 0.1μF, DAC Code 10000, CVCC = 0.1 μF, ILIM ≥ 1.0 V; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
17.6
19.0
20.6
μA
Voltage Feedback Error Amplifier
VFB Bias Current (Note 2)
0.9 V < VFB < 1.9 V
COMP Source Current
COMP = 0.5 V to 2.0 V; VFB = 1.8 V; DAC = 00000
15
30
60
μA
COMP Sink Current
COMP = 0.5 V to 2.0 V; VFB = 1.9 V; DAC = 00000
15
30
60
μA
−
0.20
0.27
0.34
V
−
32
−
mmho
−
2.5
−
MΩ
COMP Discharge Threshold Voltage
Transconductance
−10 μA < ICOMP < +10 μA
Output Impedance
−
Open Loop DC Gain
Note 3
60
90
−
dB
Unity Gain Bandwidth
0.01 μF
−
400
−
kHz
−
70
−
dB
PSRR @ 1 kHz
−
COMP Max Voltage
VFB = 1.8 V; COMP Open; DAC = 00000
2.4
2.7
−
V
COMP Min Voltage
VFB = 1.9 V; COMP Open; DAC = 00000
−
0.1
0.2
V
Hiccup Latch Discharge Current
−
2.0
5.0
10
μA
COMP Discharge Ratio
−
4.0
6.0
10
−
Minimum Pulse Width
Measured from CSx to GATE(H) with 60 mV step
between CSx and CSREF
−
350
500
ns
Channel Start Up Offset
V(CS1) = V(CS2) = V(CS3) = V(VFB)
V(CSREF) = 0 V; Measure V(COMP) when
GATE (H) 1, 2 switch high
0.3
0.4
0.5
V
PWM Comparators
GATEs
High Voltage
Measure VCC − GATEx, IGATEx = 1.0 mA
−
1.2
2.1
V
Low Voltage
Measure GATEx, IGATEx = 1.0 mA
−
0.25
0.50
V
Rise Time GATE
1.0 V < GATE < 8.0 V; VCC = 10 V
−
30
60
ns
Fall Time GATE
8.0 V > GATE > 1.0 V; VCC = 10 V
−
30
60
ns
Oscillator
Switching Frequency
ROSC = 53.6 k
220
250
280
kHz
Switching Frequency
Note 3 ROSC = 32.4 k
300
400
500
kHz
Switching Frequency
Note 3 ROSC = 16.2 k
600
800
1000
kHz
−
1.00
−
V
Rising edge only
105
120
135
deg
VDRP Offset
CS1 = CS2 = CS3 = CSREF, VFB = COMP
Measure VDRP − COMP
−20
−
20
mV
Maximum VDRP Voltage
|(CS1 = CS2 = CS3) − CREF| = 50 mV,
VFB = COMP, Measure VDRP − COMP
360
465
570
mV
2.7
3.0
3.5
V/V
ROSC Voltage
Phase Delay
−
Adaptive Voltage Positioning
Current Share Amp to VDRP Gain
−
2. The VFB Bias Current changes with the value of ROSC per Figure 4.
3. Guaranteed by design. Not tested in production.
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5
CS5323
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 85°C; 4.7 V < VCC < 14 V; CGATE = 100 pF,
RR(OSC) = 53.6 k, CCOMP = 0.1 μF, CREF = 0.1μF, DAC Code 10000, CVCC = 0.1 μF, ILIM ≥ 1.0 V; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
−
0.2
2.0
μA
Current Sensing and Sharing
CS1−CS3 Input Bias Current
V(CSx) = V(CSREF) = 0 V
CSREF Input Bias Current
−
−
0.6
2.0
μA
Current Sense Amplifier Gain
−
3.7
4.2
4.7
V/V
−5.0
−
5.0
mV
0
−
VCC − 2
V
Current Sense Amp Mismatch
(The sum of gain and offset errors)
0 < (CSx − CSREF) < 50 mV
Current Sense Amplifiers Input
Common Mode Range Limit
Note 4
Current Sense Input to ILIM Gain
0.25 V < 1.20 V
5.0
6.5
8.0
V/V
Current Limit Filter Slew Rate
Note 4
7.5
15
40
mV/μs
ILIM Bias Current
0 < ILIM < 1.0 V
−
0.1
1.0
μA
75
105
115
mV
Note 4
1.0
−
−
mHz
0 mA < I(VREF) < 1.0 mA
3.2
3.3
3.4
V
−
23
28
mA
Single Phase Pulse by Pulse
Current Limit: V(CSx) −
V(CSREF)
Current Share Amplifier Bandwidth
−
Reference Output
VREF Output Voltage
General Electrical Specifications
VCC Operating Current
VFB = COMP(no switching)
VCC Start Threshold
GATEs switching, COMP charging
4.05
4.60
4.70
V
VCC Stop Threshold
GATEs stop switching, COMP discharging
3.75
4.4
4.65
V
VCC Hysteresis
GATEs not switching, COMP not charging
100
200
300
mV
4. Guaranteed by design. Not tested in production.
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6
CS5323
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
20 Lead SO Wide
PIN SYMBOL
FUNCTION
1
ROSC
A resistor from this pin to ground sets operating frequency
and VFB bias current.
2
COMP
Output of the error amplifier and input for the PWM
comparators.
3
VFB
Voltage Feedback Pin. To use Adaptive Positioning, set the
light load offset voltage by connecting a resistor between VFB
and CSREF. The resistor and the VFB bias current determine
the offset. For no adaptive positioning connect VFB directly to
CSREF.
4
VDRP
Current sense output for adaptive voltage positioning (AVP).
The level of this pin above the DAC voltage is proportional to
the output current. Connect a resistor from this pin to VFB to
set AVP or leave this pin open for no AVP.
5−7
CS1−CS3
Current sense inputs. Connect current sense network for the
corresponding phase to each CSx pin.
Reference for Current Sense Amplifiers. To balance input
offset voltages between the inverting and noninverting inputs
of the Current Sense Amplifiers, connect a resistor between
CSREF and the output voltage. The value should be 1/3 of
the value of the resistors connected to the CSx pins.
8
CSREF
9
ILIM
Sets the threshold for hiccup mode current limit. Connect to
reference through a resistive divider.
10
REF
Reference output. Decouple with 0.1 μF.
11−15
VID0−VID4
16
Gnd
17−19
GATE1−3
20
VCC
Voltage ID DAC inputs. These pins are internally pulled up to
3.3 V if left open.
IC Gnd.
GATE drive signal.
Power for IC.
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7
CS5323
VCC
VCC
3.3 V
REF
ILIM
−
Start
+Stop
DACOUT
DAC
VID3
S
4.6 V
4.4 V
−
+
VID1
−
+
PWMC1
+
MAXC1
−
CO1
OVIC
+
−
−
+
CO2
−
+
−
+
×1.5
2
1
DACOUT
5 μA
CSREF
OFFSET
1
2
+
−
+
−
+
AVPA
CO3
−
FAULT
CO3
GATE
R
+
MAXC3
−
+
VITotal
S
PH 3
−
PWMC3
+
CO3
CO2
GATE
R
+
MAXC2
−
FAULT
0.44 V
0.44 V
−
−
+
CSA3
CO2
−
CS3
+
+
−
CSA2
0.27 V
S
PWMC2
RESC
−
CO1
CSA1
+
FAULT PH 2
Reset
Dominant
R
0.44 V
−
S
Set
Dominant
+
FAULT
CS2
R
CO1
VID4
CS1
GATE
Reset
Dominant
VID0
VID2
PH 1
Reset
Dominant
REF
VCC
FAULT
Current
Source
Gen
EA
FAULT
BIAS
PH 1
DACOUT
OSC
PH 2
PH 3
Gnd
VDRP
VFB ROSC
COMP
Figure 2. Block Diagram
TYPICAL PERFORMANCE CHARACTERISTICS
900
80
VFB Bias Current, μA
800
Frequency, kHz
700
600
500
400
300
60
40
20
200
100
10
20
30
40
50
60
0
10
70
ROSC Value, kΩ
20
30
40
50
60
70
ROSC Value, kΩ
Figure 3. Oscillator Frequency
Figure 4. VFB Bias Current vs. ROSC Value
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80
CS5323
APPLICATIONS INFORMATION
FIXED FREQUENCY MULTI−PHASE CONTROL
comparator rises and terminates the pwm cycle. If the
inductor starts the cycle with a higher current the PWM
cycle will terminate earlier providing negative feedback.
The CS5323 provides a CX input for each phase, but the
CSREF, VFB and COMP inputs are common to all phases.
Current sharing is accomplished by referencing all phases to
the same VFB and COMP pins, so that a phase with a larger
current signal will turn off earlier than phases with a smaller
current signal.
Including both current and voltage information in the
feedback signal allows the open loop output impedance of
the power stage to be controlled. If the COMP pin is held
steady and the inductor current changes there must also be
a change in the output voltage. Or, in a closed loop
configuration when the output current changes, the COMP
pin must move to keep the same output voltage. The required
change in the output voltage or COMP pin depends on the
scaling of the current feedback signal and is calculated as
In a multi−phase converter, multiple converters are
connected in parallel and are switched on at different times.
This reduces output current from the individual converters
and increases the apparent ripple frequency. Because several
converters are connected in parallel, output current can ramp
up or down faster than a single converter (with the same
value output inductor) and heat is spread among multiple
components.
The CS5323 uses a three−phase, fixed frequency,
enhanced V2 architecture. Each phase is delayed 120° from
the previous phase. Normally the GATE transitions high at
the beginning of each oscillator cycle. Inductor current
ramps up until the combination of the current sense signal
and the output ripple trip the PWM comparator and bring the
GATE low. Once the GATE goes low, it will remain low until
the beginning of the next oscillator cycle. While the GATE
is high, the enhanced V2 loop will respond to line and load
transients. Once the GATE is low, the loop will not respond
again until the beginning of the next cycle. Therefore,
constant frequency, enhanced V2 will typically respond
within the off−time of the converter.
The enhanced V2 architecture measures and adjusts
current in each phase. An additional input (CX) for inductor
current information has been added to the V2 loop for each
phase as shown in Figure 5.
SWNODE
L
RL
CSX
+
CSA
RS
OFFSET
CSREF
VOUT
DACOUT
+
CSA Gain
DI
Single Stage Impedance + DVńDI + RS
CSA Gain.
The multi−phase power stage output impedance is the
single−phase output impedance divided by the number of
phases. The output impedance of the power stage determines
how the converter will respond during the first few μs of a
transient before the feedback loop has repositioned the
COMP pin.
The peak output current of each phase can also be
calculated from;
+
V
* VFB * VOFFSET
Ipkout (per phase) + COMP
RS CSA Gain
+
+
PWMCOMP
Figure 6 shows the step response of a single phase with the
COMP pin at a fixed level. Before T1 the converter is in
normal steady state operation. The inductor current provides
the pwm ramp through the Current Share Amplifier. The
pwm cycle ends when the sum of the current signal, voltage
signal and OFFSET exceed the level of the COMP pin. At
T1 the output current increases and the output voltage sags.
The next pwm cycle begins and the cycle continues longer
than previously while the current signal increases enough to
make up for the lower voltage at the VFB pin and the cycle
ends at T2. After T2 the output voltage remains lower than
at light load and the current signal level is raised so that the
sum of the current and voltage signal is the same as with the
original load. In a closed loop system the COMP pin would
move higher to restore the output voltage to the original
level.
+
VFB
+
DV + RS
The single−phase power stage output impedance is;
E.A.
+
COMP
Figure 5. Enhanced V2 Feedback and Current
Sense Scheme
The inductor current is measured across RS, amplified by
CSA and summed with the OFFSET and Output Voltage at
the non−inverting input of the PWM comparator. The
inductor current provides the PWM ramp and as inductor
current increases the voltage on the positive pin of the pwm
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CS5323
considered when setting the ILIM threshold. If a more
accurate current sense is required than inductive sensing can
provide, current can be sensed through a resistor as shown
in Figure 5.
SWNODE
Current Sharing Accuracy
PCB traces that carry inductor current can be used as part
of the current sense resistance depending on where the
current sense signal is picked off. For accurate current
sharing, the current sense inputs should sense the current at
the same point for each phase and the connection to the
CSREF should be made so that no phase is favored. (In some
cases, especially with inductive sensing, resistance of the
pcb can be useful for increasing the current sense
resistance.) The total current sense resistance used for
calculations must include any pcb trace between the CS
inputs and the CSREF input that carries inductor current.
Current Sense Amplifier Input Mismatch and the value of
the current sense element will determine the accuracy of
current sharing between phases. The worst case Current
Sense Amplifier Input Mismatch is 5 mV and will typically
be within 3 mV. The difference in peak currents between
phases will be the CSA Input Mismatch divided by the
current sense resistance. If all current sense elements are of
equal resistance a 3 mV mismatch with a 2 mΩ sense
resistance will produce a 1.5 A difference in current between
phases.
VFB (VOUT)
CSA Out
COMP − Offset
CSA Out + VFB
T1
T2
Figure 6. Open Loop Operation
Inductive Current Sensing
For lossless sensing current can be sensed across the
inductor as shown below in Figure 7. In the diagram, L is the
output inductance and RL is the inherent inductor resistance.
To compensate the current sense signal the values of R1 and
C1 are chosen so that L/RL = R1 × C1. If this criteria is met
the current sense signal will be the same shape as the
inductor current, the voltage signal at Cx will represent the
instantaneous value of inductor current and the circuit can be
analyzed as if a sense resistor of value RL was used as a sense
resistor (RS).
For operation at duty cycles above 50% Enhanced V2
will exhibit subharmonic oscillation unless a compensation
ramp is added to each phase. A circuit like the one on the left
side of Figure 8 can be added to each current sense network
to implement slope compensation. The value of R1 can be
varied to adjust the ramp size.
R1
SWNODE
CSX
L
C1
RL
VOUT
Operation at > 50% Duty Cycle
CSREF
+
CSA
OFFSET
+
+
+
+
PWMCOMP
Switch Node
GATE(L)X
VFB
DACOUT
E.A.
+
COMP
R1
3k
25 k
CSX
Figure 7. Lossless Inductive Current Sensing with
Enhanced V2
1.0 nF
0.1 μF
When choosing or designing inductors for use with
inductive sensing, tolerances and temperature effects should
be considered. Cores with a low permeability material or a
large gap will usually have minimal inductance change with
temperature and load. Copper magnet wire has a
temperature coefficient of 0.39% per °C. The increase in
winding resistance at higher temperatures should be
.01 μF
CSREF
MMBT2222LT1
Slope Comp
Circuit
Existing Current
Sense Circuit
Figure 8. External Slope Compensation Circuit
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CS5323
Ramp Size and Current Sensing
Because the current ramp is used for both the PWM ramp
and to sense current, the inductor and sense resistor values
will be constrained. A small ramp will provide a quick
transient response by minimizing the difference over which
the COMP pin must travel between light and heavy loads,
but a steady state ramp of 25 mVP−P or greater is typically
required to prevent pulse skipping and minimize pulse width
jitter. For resistive current sensing the combination of the
inductor and sense resistor values must be chosen to provide
a large enough steady state ramp. For large inductor values
the sense resistor value must also be increased.
For inductive current sensing the RC network must meet
the requirement of L/RL = R × C to accurately sense the AC
and DC components of the current the signal. Again the
values for L and RL will be constrained in order to provide
a large enough steady state ramp with a compensated current
sense signal. A smaller L, or a larger RL than optimum might
be required. But unlike resistive sensing, with inductive
sensing small adjustments can be made easily with the
values of R and C to increase the ramp size if needed.
If RC is chosen to be smaller (faster) than L/RL, the AC
portion of the current sensing signal will be scaled larger
than the DC portion. This will provide a larger steady state
ramp, but circuit performance will be affected and must be
evaluated carefully. The current signal will overshoot during
transients and settle at the rate determined by R × C. It will
eventually settle to the correct DC level, but the error will
decay with the time constant of R × C. If this error is
excessive it will effect transient response, adaptive
positioning and current limit. During transients the COMP
pin will be required to overshoot along with the current
signal in order to maintain the output voltage. The VDRP pin
will also overshoot during transients and possibly slow the
response. Single phase overcurrent will trip earlier than it
would if compensated correctly and hiccup mode current
limit will have a lower threshold for fast rise step loads than
for slowly rising output currents.
The waveforms in Figure 9 show a simulation of the
current sense signal and the actual inductor current during
a positive step in load current with values of L = 500 nH,
RL = 1.6 mΩ, R1 = 20 k and C1 = .01 μF. For ideal current
signal compensation the value of R1 should be 31 kΩ. Due
to the faster than ideal RC time constant there is an
overshoot of 50% and the overshoot decays with a 200 μs
time constant. With this compensation the ILIM pin
threshold must be set more than 50% above the full load
current to avoid triggering hiccup mode during a large
output load step.
Figure 9. Inductive Sensing waveform during a Step
with Fast RC Time Constant (50 ms/div)
Current Limit
Two levels of overcurrent protection are provided. Any
time the voltage on a Current Sense pin exceeds CSREF by
more than the Single Phase Pulse by Pulse Current Limit, the
pwm comparator for that phase is turned off. This provides
fast peak current protection for individual phases. The
outputs of all the currents are also summed and filtered to
compare an averaged current signal to the voltage on the
ILIM pin. If this voltage is exceeded, the fault latch trips and
the SS capacitor is discharged by a 5 μA source until the
COMP pin reaches 0.2 V. Then soft−start begins. The
converter will continue to operate in this mode until the fault
condition is corrected.
Overvoltage Protection
Overvoltage protection (OVP) is provided as a result of
the normal operation of the enhanced V2 control topology
with synchronous rectifiers. The control loop responds to an
overvoltage condition within 400 ns, causing the top
MOSFET’s to shut off, and the synchronous MOSFET’s to
turn on. This results in a “crowbar” action to clamp the
output voltage and prevents damage to the load. The
regulator will remain in this state until the overvoltage
condition ceases or the input voltage is pulled low.
Transient Response and Adaptive Positioning
For applications with fast transient currents the output
filter is frequently sized larger than ripple currents require in
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CS5323
increases the VDRP pin increases proportionally and the
VDRP pin current offsets the VFB bias current and causes the
output voltage to further decrease.
The VFB and VDRP pins take care of the slower and DC
voltage positioning. The first few μs are controlled primarily
by the ESR and ESL of the output filter. The transition
between fast and slow positioning is controlled by the ramp
size and the error amp compensation. If the ramp size is too
large or the error amp too slow there will be a long transition
to the final voltage after a transient. This will be most
apparent with lower capacitance output filters.
Note: Large levels of adaptive positioning can cause pulse
width jitter.
order to reduce voltage excursions during transients.
Adaptive voltage positioning can reduce peak−peak output
voltage deviations during load transients and allow for a
smaller output filter. The output voltage can be set higher at
light loads to reduce output voltage sag when the load
current is stepped up and set lower during heavy loads to
reduce overshoot when the load current is stepped up. For
low current applications a droop resistor can provide fast
accurate adaptive positioning. However at high currents, the
loss in a droop resistor becomes excessive. For example; in
a 50 A converter a 1 mΩ resistor to provide a 50 mV change
in output voltage between no load and full load would
dissipate 2.5 Watts.
Lossless adaptive positioning is an alternative to using a
droop resistor, but must respond quickly to changes in load
current. Figure 10 shows how adaptive positioning works.
The waveform labeled normal shows a converter without
adaptive positioning. On the left, the output voltage sags
when the output current is stepped up and later overshoots
when current is stepped back down. With fast (ideal)
adaptive positioning the peak to peak excursions are cut in
half. In the slow adaptive positioning waveform the output
voltage is not repositioned quickly enough after current is
stepped up and the upper limit is exceeded.
Error Amp Compensation
The transconductance error amplifier can be configured to
provide both a slow soft−start and a fast transient response.
C4 in the main applications diagram controls soft−start. A
0.1 μF capacitor with the 30 μA error amplifier output
capability will allow the output to ramp up at 0.3 V/ms or
1.5 V in 5 ms.
R10 is connected in series with C4 to allow the error
amplifier to slew quickly over a narrow range during load
transients. Here the 30 μA error amplifier output capability
works against 8 kΩ (R10) to limit the window of fast slewing
too 240 mV − enough to allow for fast transients, but not
enough to interfere with soft−start. This window will be
noticeable as a step in the COMP pin voltage at start−up. The
size of this step must be kept smaller than the Channel
Start−Up Offset (nominally 0.4 V) for proper soft−start
operation. If adaptive positioning is used the R9 and R8 form
a divider with the VDRP end held at the DAC voltage during
start−up, which effectively makes the Channel Start−Up
Offset larger.
C12 is included for error amp stability. A capacitive load
is required on the error amp output. Use of values less than
1 nF may result in error amp oscillation of several MHz.
C11 and the parallel resistance of the VFB resistor (R9)
and the VDRP resistor (R6) are used to roll off the error amp
gain. C28 adds a zero to the error amp response to boost the
phase near the crossover frequency.
Normal
Fast Adaptive Positioning
Slow Adaptive Positioning
Limits
Figure 10. Adaptive Positioning
The CS5323 uses two methods to provide fast and
accurate adaptive positioning. For low frequency
positioning the VFB and VDRP pins are used to adjust the
output voltage with varying load currents. For high
frequency positioning, the current sense input pins can be
used to control the power stage output impedance. The
transition between fast and slow positioning is adjusted by
the error amp compensation.
The CS5323 can be configured to adjust the output
voltage based on the output current of the converter. The
adaptive positioning circuit is designed to select the DAC
setting as the maximum output voltage. (Refer to Figure 1 on
page 2.)
To set the no−load positioning a resistor (R9) is placed
between the output voltage and VFB pin. The VFB bias
current will develop a voltage across the resistor to decrease
the output voltage. The VFB bias current is dependent on the
value of ROSC. See Figure 4 on the datasheet.
During no load conditions the VDRP pin is at the same
voltage as the VFB pin, so none of the VFB bias current flows
through the VDRP resistor (R6). When output current
UVLO
The CS5323 has one undervoltage lockout function
connected to the VCC pin. In applications where the
converter is powered from multiple voltages, additional
UVLO protection might be required if the voltage powering
the controller can turn on before other voltages.
For the 12 VIN converter in Figure 1, the CS5323 UVLO
function monitors the 5.0 V supply. If the 5.0 V supply
comes up before the 12 V supply, the COMP pin will rise
until it reaches the upper rail or until the 12 V supply comes
up and the converter comes into regulation. If the delay
between the 5.0 V and 12 V supplies is too long, soft−start
will be compromised. A diode connected from the 12 V
supply to the COMP pin can hold the COMP pin down until
the 12 V supply starts to come up. Or, if a higher UVLO
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CS5323
the controller and the output voltage or in the return path of
the gate drive. Additional power and ground planes or
islands can be added as required for a particular layout.
Output filter components should be placed on wide planes
connected directly to the load to minimize resistive drops
during heavy loads and inductive drops and ringing during
transients. If required, the planes for the output voltage and
return can be interleaved to minimize inductance between
the filter and load.
Voltage feedback should be taken from a point of the
output or the output filter that doesn’t favor any one phase.
If the feedback connection is closer to one inductor than the
others the ripple associated with that phase may appear
larger than the ripple associated with the other phases and
poor current sharing can result.
The current sense signal is typically tens of milli−volts.
Noise pick−up should be avoided wherever possible.
Current feedback traces should be routed away from noisy
areas such as switch nodes and gate drive signals. The paths
should be matched as well as possible. It is especially
important that all current sense signals be picked off at
similar points for accurate current sharing. If the current
signal is taken from a place other than directly at the inductor
any additional resistance between the pick−off point and the
inductor appears as part of the inherent inductor resistance
and should be considered in design calculations. Capacitors
for the current feedback networks should be placed as close
to the current sense pins as practical.
threshold is needed, a circuit like the one in Figure 11 will
lock out the converter until the 12 V supply reaches about
7.0 V.
+12 V
+5 V
50 k
COMP
100 k
100 k
Figure 11. External UVLO Circuit
Remote Sense
In some applications that require remote output voltage
sensing, there are conditions when the path of the feedback
signal can be broken. In a voltage regulator module (VRM)
the remote voltage feedback sense point is typically off the
module. If the module is powered apart from the intended
application, the feedback will be left open. On a
motherboard, the feedback path might be broken when the
processor socket is left open. Without the feedback
connection the output voltage is likely to exceed the
intended voltage. To protect the circuit from overvoltage
conditions, a resistor can be connected between the local
output voltage and the remote sense line as shown in Figure
12.
Local VOUT
DESIGN PROCEDURE
Current Sensing, Power Stage and
Output Filter Components
1. Choose the output filter components to meet peak
transient requirements. The formula below can be
used to provide an approximate starting point for
capacitor choice, but will be inadequate to calculate
actual values.
Remote VOUT
CSREF Network
Remote Sense Line
100 Ω
DVPEAK + (DIńDT)
ESL ) DI
ESR
Ideally the output filter should be simulated with
models including ESR, ESL, circuit board parasitics
and delays due to switching frequency and converter
response. Typically both bulk capacitance
(electrolytic, Oscon, etc,) and low impedance
capacitance (ceramic chip) will be required. The bulk
capacitance provides “hold up” during the converter
response. The low impedance capacitance reduces
steady state ripple and bypasses the bulk capacitance
during slewing of output current.
2. For inductive current sensing (only) choose the
current sense network RC to provide a 25 mV
minimum ramp during steady state operation.
VFB Network
Figure 12. Remote Sense Connection
Layout Guidelines
With the fast rise, high output currents of microprocessor
applications parasitic inductance and resistance should be
considered when laying out the power, filter and feedback
signal sections of the board. Typically a multi−layer board
with at least one ground plane is recommended. If the layout
is such that high currents can exist in the ground plane
underneath the controller or control circuitry, the ground
plane can be slotted to reroute the currents away from the
controller. The slots should typically not be placed between
R + (VIN * VOUT)
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13
F
VOUTńVIN
C 25 mV
CS5323
Then choose the inductor value and inherent resistance
to satisfy L/RL = R × C.
For ideal current sense compensation the ratio of L and
RL is fixed, so the values of L and RL will be a
compromise typically with the maximum value RL
limited by conduction losses or inductor temperature
rise and the minimum value of L limited by ripple
current.
3. For resistive current sensing choose L and RS to
provide a steady state ramp greater than 25 mV.
LńRS + (VIN * VOUT)
R is RL or RS;
IOUT(LIM) is the current limit threshold.
For the overcurrent to work properly the inductor time
constant (L/R) should be ≤ the Current sense RC. If the
RC is too fast, during step loads the current waveform
will appear larger than it is (typically for a few hundred
μs) and may trip the current limit at a level lower than
the DC limit.
Adaptive Positioning
7. To set the amount of voltage positioning below the
DAC setting at no load connect a resistor (RV(FB))
between the output voltage and the VFB pin. Choose
RV(FB) as;
TONń25 mV
Again the ratio of L and RL is fixed and the values of
L and RS will be a compromise.
4. Calculate the high frequency output impedance
(ConverterZ) of the converter during transients. This
is the impedance of the Output filter ESR in parallel
with the power stage output impedance (PwrstgZ)
and will indicate how far from the original level
(ΔVR) the output voltage will typically recover to
within one switching cycle. For a good transient
response ΔVR should be less than the peak output
voltage overshoot or undershoot.
DVR + ConverterZ
ConverterZ +
RV(FB) + NL PositionńVFB Bias Current
See Figure 4 for VFB Bias Current.
8. To set the difference in output voltage between no load
and full load, connect a resistor (RV(DRP)) between the
VDRP and VFB pins. RV(DRP) can be calculated in two
steps. First calculate the difference between the VDRP
and VFB pin at full load. (The VFB voltage should be
the same as the DAC voltage during closed loop
operation.) Then choose the RV(DRP) to source enough
current across RV(FB) for the desired change in output
voltage.
ESR
PwrstgZ ESR
PwrstgZ ) ESR
DVV(DRP) + IOUTFL
where:
PwrstgZ + RS
CS to VDRP Gain
where:
R = RL or RS for one phase;
IOUTFL is the full load output current.
CSA Gainń3
Multiply the converterZ by the output current step size
to calculate where the output voltage should recover to
within the first switching cycle after a transient. If the
ConverterZ is higher than the value required to recover
to where the adaptive positioning is set the remainder
of the recovery will be controlled by the error amp
compensation and will typically recover in 10 − 20 μs.
DVR + DIOUT
R
RV(DRP) + DVDRP
RV(FB)ńDVOUT
Calculate Input Filter Capacitor Current Ripple
The procedure below assumes that phases do not overlap
and output inductor ripple current (P−P) is less than the
average output current of one phase.
9. Calculate Input Current
ConverterZ
IIN +
Make sure that ΔVR is less than the expected peak
transient for a good transient response.
5. Adjust L and RL or RS as required to meet the best
combination of transient response, steady state output
voltage ripple and pulse width jitter.
VOUT IOUT
(Efficiency VIN)
10. Calculate Duty Cycle (per phase).
Duty Cycle +
VOUT
(Efficiency VIN)
11. Calculate Apparent Duty Cycle.
Current Limit
When the sum of the Current Sense amplifiers (VITOTAL)
exceeds the voltage on the ILIM pin the part will enter hiccup
mode. For inductive sensing the ILIM pin voltage should be
set based on the inductor resistance (or current sense
resistor) at max temperature and max current. To set the level
of the ILIM pin:
6. VI(LIM) + R IOUT(LIM) CS to ILIM Gain
Apparent Duty Cycle + Duty Cycle
# of Phases
12. Calculate Input Filter Capacitor Ripple Current. Use
the chart in Figure 13 to calculate the normalized
ripple current (KRMS) based on the reciprocal of
Apparent Duty Cycle. Then multiply the input current
by KRMS to obtain the Input Filter Capacitor Ripple
Current.
where:
Ripple (RMS) + IIN
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KRMS
CS5323
4.00
3. n/a
4. PwrstgZ + RL
CSA Gainń3
+ 1.5 mW 4.2ń3 + 2.1 mW
Frequency, kHz
3.50
3.00
2.50
ConverterZ +
PwrstgZ
ESR
PwrstgZ ) ESR
+ 2.8 mW 1.5 mW ^ 1.0 mW
2.8 mW ) 1.5 mW
DVR + 1.0 mW 60 A + 60 mV
2.00
1.50
1.00
0.50
0.00
0
5. n/a
15
10
5
1/ Apparent Duty Cycle
Current Limit
6.VI(LIM) + RL
IOUT(LIM) CS to ILIM Gain
+ 1.5 mW 75 A 6.5 + 731 mV
Figure 13. Normalized Input Filter Capacitor
Ripple Current
Adaptive Positioning
DESIGN EXAMPLE
Choose the component values for lossless current sensing,
adaptive positioning and current limit for a 12 V to 1.5 V 60
A converter. The adaptive positioning is chosen 20 mV
below the maximum VOUT at no load and 70 mV below the
no−load position with 60 A out. The peak output voltage
transient is 100 mV max during a 60 A step current. The
overcurrent limit is nominally 75 A.
7. RV(FB) + NL PositionńVFB Bias Current
+ 20 mVń19 mA ^ 1.00 kW
8. DVDRP + RL
+ 2 mW
RV(DRP) + DVDRP
+ 360 mV
+ (12 * 1.5) (1.5ń12)ń(250 k
+ 21 kW å Choose 20 kW
RV(FB)ńDVOUT
1.00 kWń50 mV + 7.2 kW
9. IIN + 1.6 V 60 A + 9.4 A
(0.85 12VIN)
Current Sensing, Power Stage
and Output Filter Components
1. Assume 1.5 mΩ of output filter ESR.
2. R + (VIN * VOUT) (VOUTńVIN)ń(F
IOUT Current Sense to VDRP Gain
60 A 3 + 360 mV
1.6 V
+ 0.16
12 VIN)
C
25 mV)
10. Duty Cycle + (
.01 mF
25 mV)
11. Apparent Duty Cycle + 0.16
0.85
12. RMS ripple is 9.4 A
LńRL + .01 mF 20 kW + 200 ms
Choose RL + 2.0 mW
L + 2 mW 200 ms + 400 nH
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15
3.0 + 0.48
1.0 + 9.4 A
CS5323
PACKAGE DIMENSIONS
SO−20L
DW SUFFIX
CASE 751D−05
ISSUE F
A
20
q
X 45 E
h
H
M
10X
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
B
M
D
1
10
20X
0.25
DIM
A
A1
B
C
D
E
e
H
h
L
q
B
B
M
T A
S
B
S
L
A
18X
e
A1
SEATING
PLANE
T
C
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0
7
PACKAGE THERMAL DATA
Parameter
SO−20L
Unit
RΘJC
Typical
17
°C/W
RΘJA
Typical
90
°C/W
V2 is a trademark of Switch Power, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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CS5323/D