INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT11 Triple 3-input AND gate Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Triple 3-input AND gate 74HC/HCT11 FEATURES • Output capability: standard • ICC category: SSI GENERAL DESCRIPTION The 74HC/HCT11 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT11 provide the 3-input AND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay nA, nB, nC to nY CI CPD CL = 15 pF; VCC = 5 V HCT 10 11 ns input capacitance 3.5 3.5 pF power dissipation capacitance per gate notes 1 and 2 18 20 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V ∑ (CL × VCC2 × fo) = sum of outputs 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 Philips Semiconductors Product specification Triple 3-input AND gate 74HC/HCT11 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 3, 9 1A to 3A data inputs 2, 4, 10 1B to 3B data inputs 7 GND ground (0 V) 12, 6, 8 1Y to 3Y data outputs 13, 5, 11 1C to 3C data inputs 14 VCC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. FUNCTION TABLE INPUTS Fig.4 Functional diagram. Fig.5 Logic diagram (one gate). OUTPUT nA nB nC nY L L L L L L H L L H L L L H H L H L L L H L H L H H L L H H H H Notes 1. H = HIGH voltage level L = LOW voltage level December 1990 3 Philips Semiconductors Product specification Triple 3-input AND gate 74HC/HCT11 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER −40 to +85 +25 min. tPHL/ tPLH tTHL/ tTLH propagation delay nA, nB, nC to nY output transition times December 1990 typ. max. min. max. −40 to +125 min. UNIT VCC WAVEFORMS (V) max. 32 100 125 150 12 20 25 30 10 17 21 26 19 75 95 110 7 15 19 22 4.5 6 13 16 19 6.0 4 ns 2.0 Fig.6 4.5 6.0 ns 2.0 Fig.6 Philips Semiconductors Product specification Triple 3-input AND gate 74HC/HCT11 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. ‘To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT nA, nB, nC 1.00 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER −40 to +85 +25 min. typ. max. min. max. −40 to +125 min. UNIT VCC (V) WAVEFORMS max. tPHL/ tPLH propagation delay nA, nB, nC to nY 16 24 30 36 ns 4.5 Fig.6 tTHL/ tTLH output transition times 7 15 19 22 ns 4.5 Fig.6 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the input (nA, nB, nC) to output (nY) propagation delays and the output transition times. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 5