PHILIPS 74LVC244ADB

74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
Rev. 06 — 13 August 2009
Product data sheet
1. General description
The 74LVC244A; 74LVCH244A is an octal non-inverting buffer/line driver with 3-state
outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE.
A HIGH on nOE causes the outputs to assume a high-impedance OFF-state.
Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise
and fall times.
Inputs can be driven from either 3.3 V or 5.0 V devices. In 3-state operation, outputs can
handle 5 V. These features allow the use of these devices as translators in a mixed
3.3 V and 5 V environment.
The 74LVCH244A bus hold on data inputs eliminates the need for external pull-up
resistors to hold unused inputs.
2. Features
n
n
n
n
n
n
n
n
n
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
High-impedance when VCC = 0 V
Bus hold on all data inputs (74LVCH244A only)
Complies with JEDEC standard no. 8-1A
ESD protection:
u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
n Specified from −40 °C to +85 °C and −40 °C to +125 °C
74LVC244A; 74LVCH244A
NXP Semiconductors
Octal buffer/line driver; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
74LVC244AD
Package
Temperature range
Name
Description
Version
−40 °C to +125 °C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
−40 °C to +125 °C
SSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
−40 °C to +125 °C
TSSOP20
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
−40 °C to +125 °C
DHVQFN20
SOT764-1
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
−40 °C to +125 °C
DHXQFN20U plastic dual in-line compatible thermal enhanced
extremely thin quad flat package; no leads; 20
terminals; UTLP based; body 2.5 × 4.5 × 0.5 mm
74LVCH244AD
74LVC244ADB
74LVCH244ADB
74LVC244APW
74LVCH244APW
74LVC244ABQ
74LVCH244ABQ
74LVC244ABX
74LVCH244ABX
SOT1045-1
4. Functional diagram
1A0
1A1
1A2
1A3
1OE
2
18
4
16
6
14
8
12
1
1Y0
2A0
1Y1
2A1
1Y2
2A2
1Y3
2A3
2OE
17
3
15
5
13
7
11
9
2Y0
2Y1
2Y2
2Y3
19
mna874
Fig 1.
Logic symbol
74LVC_LVCH244A_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 13 August 2009
2 of 18
74LVC244A; 74LVCH244A
NXP Semiconductors
Octal buffer/line driver; 3-state
2
4
6
1
8
EN
2
18
4
16
6
14
8
12
1
17
15
19
EN
13
11
9
13
7
15
5
17
3
11
19
1A0
1Y0
1A1
1Y1
1A2
1Y2
1A3
1Y3
IEC logic diagram
14
12
2A0
2Y0
2A1
2Y1
2A2
2Y2
2A3
2Y3
3
5
7
9
2OE
mna875
Fig 3.
Functional diagram
74LVC_LVCH244A_6
Product data sheet
16
1OE
mna873
Fig 2.
18
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 13 August 2009
3 of 18
74LVC244A; 74LVCH244A
NXP Semiconductors
Octal buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
terminal 1
index area
1
74LVC244A
74LVCH244A
1OE
1
20 VCC
1A0
2
19 2OE
20 VCC
1OE
74LVC244A
74LVCH244A
1A0
2
19 2OE
2Y0
3
18 1Y0
1A1
4
17 2A0
5
16 1Y1
2Y0
3
18 1Y0
2Y1
1A1
4
17 2A0
1A2
6
15 2A1
2Y1
5
16 1Y1
2Y2
7
14 1Y2
1A2
6
15 2A1
8
7
14 1Y2
1A3
2Y2
1A3
8
13 2A2
2Y3
9
2Y3
9
12 1Y3
GND 10
11 2A3
GND (1)
13 2A2
2A3 11
GND 10
12 1Y3
001aad114
Transparent top view
001aad113
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 4.
Pin configuration for SO20 and (T)SSOP20
Fig 5.
Pin configuration for DHVQFN20 and
DHXQFN20U
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1OE, 2OE
1, 19
output enable input (active low)
1A0, 1A1, 1A2, 1A3
2, 4, 6, 8
data input
2Y0, 2Y1, 2Y2, 2Y3
3, 5, 7, 9
data output
GND
10
ground (0 V)
2A0, 2A1, 2A2, 2A3
17, 15, 13, 11 data input
1Y0, 1Y1, 1Y2, 1Y3,
18, 16, 14, 12 data output
VCC
20
supply voltage
74LVC_LVCH244A_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 13 August 2009
4 of 18
74LVC244A; 74LVCH244A
NXP Semiconductors
Octal buffer/line driver; 3-state
6. Functional description
Table 3.
Function table [1]
Control
Input
Output
nOE
nAn
nYn
L
L
L
L
H
H
H
X
Z
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
output voltage
VO
Conditions
VI < 0 V
[1]
Min
Max
Unit
−0.5
+6.5
V
−50
-
mA
−0.5
+6.5
V
-
±50
mA
output HIGH or LOW
[2]
−0.5
VCC + 0.5
V
output 3-state
[2]
−0.5
+6.5
V
-
±50
mA
VO > VCC or VO < 0 V
IO
output current
VO = 0 V to VCC
ICC
supply current
-
100
mA
IGND
ground current
−100
-
mA
Tstg
storage temperature
−65
+150
°C
Ptot
total power dissipation
-
500
mW
Tamb = −40 °C to +125 °C
[3]
[1]
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2]
The output voltage ratings may be exceeded if the output current ratings are observed.
[3]
For SO20 packages: above 70 °C derate linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN20 and DHXQFN20U packages: above 60 °C derate linearly with 4.5 mW/K.
74LVC_LVCH244A_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 13 August 2009
5 of 18
74LVC244A; 74LVCH244A
NXP Semiconductors
Octal buffer/line driver; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC
supply voltage
maximum speed
performance
2.7
-
3.6
V
functional
1.2
-
3.6
V
VI
input voltage
0
-
5.5
V
VO
output voltage
output HIGH or LOW
0
-
VCC
V
output 3-state
0
-
5.5
V
Tamb
ambient temperature
in free air
−40
-
+125
°C
∆t/∆V
input transition rise and fall rate
VCC = 1.2 V to 2.7 V
0
-
20
ns/V
VCC = 2.7 V to 3.6 V
0
-
10
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
−40 °C to +85 °C
Conditions
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
HIGH-level input
voltage
VCC = 1.2 V
VCC
-
-
VCC
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
VIL
LOW-level input
voltage
VCC = 1.2 V
-
-
0
-
0
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
VOH
HIGH-level output VI = VIH or VIL
voltage
IO = −100 µA;
VCC = 2.7 V to 3.6 V
VCC − 0.2
VCC
-
VCC − 0.3
-
V
VIH
VOL
LOW-level output
voltage
IO = −12 mA; VCC = 2.7 V
2.2
-
-
2.05
-
V
IO = −18 mA; VCC = 3.0 V
2.4
-
-
2.25
-
V
IO = −24 mA; VCC = 3.0 V
2.2
-
-
2.0
-
V
IO = 100 µA;
VCC = 2.7 V to 3.6 V
-
0
0.20
-
0.3
V
IO = 12 mA; VCC = 2.7 V
-
-
0.40
-
0.6
V
VI = VIH or VIL
IO = 24 mA; VCC = 3.0 V
-
-
0.55
-
0.8
V
[2]
-
±0.1
±5
-
±20
µA
[2][3]
-
±0.1
±5
-
±20
µA
II
input leakage
current
VI = 5.5 V or GND; VCC = 3.6 V
IOZ
OFF-state output
current
VI = VIH or VIL;
VO = 5.5 V or GND;
VCC = 3.6 V
IOFF
power-off leakage VI or VO = 5.5 V; VCC = 0.0 V
current
-
±0.1
±10
-
±20
µA
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 3.6 V
-
0.1
10
-
40
µA
∆ICC
additional supply
current
per input pin; VI = VCC − 0.6 V;
IO = 0 A; VCC = 2.7 V to 3.6 V
-
5
500
-
5000
µA
74LVC_LVCH244A_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 13 August 2009
6 of 18
74LVC244A; 74LVCH244A
NXP Semiconductors
Octal buffer/line driver; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol
CI
Parameter
−40 °C to +85 °C
Conditions
input capacitance
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
-
4.0
-
-
-
pF
75
-
-
60
-
µA
IBHL
bus hold LOW
current
VCC = 3.0 V; VI = 0.8 V
[4][5]
IBHH
bus hold HIGH
current
VCC = 3.0 V; VI = 2.0 V
[4][5]
−75
-
-
−60
-
µA
IBHLO
bus hold LOW
overdrive current
VCC = 3.6 V
[4][6]
500
-
-
500
-
µA
IBHHO
bus hold HIGH
overdrive current
VCC = 3.6 V
[4][6]
−500
-
-
−500
-
µA
[1]
All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
[2]
The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input terminal.
[3]
For I/O ports the parameter IOZ includes the input leakage current.
[4]
Valid for data inputs of bus hold parts only (74LVCH244A). Note that control inputs do not have a bus hold circuit.
[5]
The specified sustaining current at the data input holds the input below the specified VI level.
[6]
The specified overdrive current at the data input forces the data input to the opposite input state.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter
tpd
propagation
delay
−40 °C to +85 °C
Conditions
nAn to nYn; see Figure 6
enable time
Min
Max
Min
Max
-
17.0
-
-
-
ns
1.5
3.3
6.9
1.5
9.0
ns
1.5
2.8
5.9
1.5
7.5
ns
-
24.0
-
-
-
ns
1.5
3.3
8.6
1.5
11
ns
1.0
3.4
7.6
1.0
9.5
ns
-
9.0
-
-
-
ns
[1]
VCC = 1.2 V
VCC = 2.7 V
ten
VCC = 3.0 V to 3.6 V
[3]
nOE to nYn; see Figure 7
[1]
VCC = 1.2 V
VCC = 2.7 V
tdis
disable time
VCC = 3.0 V to 3.6 V
[3]
nOE to nYn; see Figure 7
[1]
VCC = 1.2 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
tsk(o)
output skew
time
1.5
3.2
6.8
1.5
8.5
ns
[3]
1.5
2.9
5.8
1.5
7.5
ns
[4]
-
-
1.0
-
1.5
ns
74LVC_LVCH244A_6
Product data sheet
−40 °C to +125 °C Unit
Typ[2]
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 13 August 2009
7 of 18
74LVC244A; 74LVCH244A
NXP Semiconductors
Octal buffer/line driver; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter
CPD
[1]
power
dissipation
capacitance
−40 °C to +85 °C
Conditions
per buffer; VI = GND to VCC; VCC = 3.3 V
−40 °C to +125 °C Unit
Min
Typ[2]
Max
Min
Max
-
10
-
-
-
[5]
pF
tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[2]
Typical values are measured at Tamb = 25 °C.
[3]
Typical values are measured at Tamb = 25 °C and VCC = 3.3 V.
[4]
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[5]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs.
11. AC waveforms
VI
nAn input
VM
VM
GND
tPLH
tPHL
VOH
nYn output
VM
VOL
VM
mna171
Measurement points are given in Table 8.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6.
The input (nAn) to output (nYn) propagation delays
74LVC_LVCH244A_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 13 August 2009
8 of 18
74LVC244A; 74LVCH244A
NXP Semiconductors
Octal buffer/line driver; 3-state
VI
nOE input
VM
GND
tPLZ
tPZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
tPHZ
VOH
tPZH
VY
output
HIGH-to-OFF
OFF-to-HIGH
GND
VM
outputs
enabled
outputs
enabled
outputs
disabled
mna362
Measurement points are given in Table 8.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7.
3-state enable and disable times.
Table 8.
Measurement points
Supply voltage
Input
Output
VCC
VI
VM
VM
VX
VY
1.2 V
VCC
0.5 × VCC
0.5 × VCC
VOL + 0.1 V
VOH − 0.1 V
2.7 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
3.0 V to 3.6 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
74LVC_LVCH244A_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 13 August 2009
9 of 18
74LVC244A; 74LVCH244A
NXP Semiconductors
Octal buffer/line driver; 3-state
tW
VI
90 %
negative
pulse
VM
VM
10 %
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
VM
VM
10 %
0V
tW
VEXT
VCC
VI
RL
VO
G
DUT
RT
CL
RL
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8.
Test circuit for measuring switching times
Table 9.
Test data
Supply voltage
Input
Load
VEXT
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
1.2 V
VCC
≤ 2.5 ns
50 pF
500 Ω[1]
open
2 × VCC
GND
2.7 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
2 × VCC
GND
3.0 V to 3.6 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
2 × VCC
GND
[1]
The circuit performs better when RL = 1 kΩ.
74LVC_LVCH244A_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 13 August 2009
10 of 18
74LVC244A; 74LVCH244A
NXP Semiconductors
Octal buffer/line driver; 3-state
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
HE
y
v M A
Z
20
11
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
10
1
e
bp
detail X
w M
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.51
0.49
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
Fig 9.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT163-1
075E04
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Package outline SOT163-1 (SO20)
74LVC_LVCH244A_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 13 August 2009
11 of 18
74LVC244A; 74LVCH244A
NXP Semiconductors
Octal buffer/line driver; 3-state
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
D
SOT339-1
E
A
X
c
HE
y
v M A
Z
20
11
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
10
w M
bp
e
detail X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
0.9
0.5
8
o
0
o
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
OUTLINE
VERSION
SOT339-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-150
Fig 10. Package outline SOT339-1 (SSOP20)
74LVC_LVCH244A_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 13 August 2009
12 of 18
74LVC244A; 74LVCH244A
NXP Semiconductors
Octal buffer/line driver; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
E
D
A
X
c
HE
y
v M A
Z
11
20
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
10
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT360-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 11. Package outline SOT360-1 (TSSOP20)
74LVC_LVCH244A_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 13 August 2009
13 of 18
74LVC244A; 74LVCH244A
NXP Semiconductors
Octal buffer/line driver; 3-state
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT764-1
20 terminals; body 2.5 x 4.5 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
9
y
y1 C
v M C A B
w M C
b
L
1
10
Eh
e
20
11
19
12
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
1
0.05
0.00
0.30
0.18
mm
c
D (1)
Dh
E (1)
Eh
0.2
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
e
0.5
e1
L
v
w
y
y1
3.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT764-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 12. Package outline SOT764-1 (DHVQFN20)
74LVC_LVCH244A_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 13 August 2009
14 of 18
74LVC244A; 74LVCH244A
NXP Semiconductors
Octal buffer/line driver; 3-state
DHXQFN20U: plastic dual in-line compatible thermal enhanced extremely thin quad flat package;
no leads; 20 terminals; UTLP based; body 2.5 x 4.5 x 0.5 mm
B
D
SOT1045-1
A
A
E
A1
detail X
terminal 1
index area
terminal 1
index area
e1
v
w
b
e
L1
2
M
M
C
C A B
C
y
y1 C
9
L
10
1
Eh
e
20
11
19
12
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
b
D
Dh
E
Eh
e
e1
L
L1
v
w
y
y1
mm
0.5
0.05
0.00
0.30
0.18
4.6
4.4
3.35
3.05
2.6
2.4
1.35
1.05
0.5
3.5
0.45
0.25
0.13
0.05
0.1
0.05
0.05
0.1
REFERENCES
OUTLINE
VERSION
IEC
SOT1045-1
---
JEDEC
JEITA
---
EUROPEAN
PROJECTION
ISSUE DATE
07-12-01
09-08-04
Fig 13. Package outline SOT1045-1 (DHXQFN20U)
74LVC_LVCH244A_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 13 August 2009
15 of 18
74LVC244A; 74LVCH244A
NXP Semiconductors
Octal buffer/line driver; 3-state
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date Data sheet status
Change notice
Supersedes
74LVC_LVCH244A_6
20090813
-
74LVC_LVCH244A_5
Modifications:
74LVC_LVCH244A_5
Modifications:
•
Product data sheet
New SOT1045-1 package outline drawing (DHXQFN20U package).
20090709
Product data sheet
-
74LVC_LVCH244A_4
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Added type numbers 74LVC244ABX and 74LVCH244ABX (DHXQFN20U package).
74LVC_LVCH244A_4
20031030
Product specification
-
74LVC_LVCH244A_3
74LVC_LVCH244A_3
20030520
Product specification
-
74LVC_H244A_2
74LVC_H244A_2
19980520
Product specification
-
74LVC244A_74LVCH244A_1
74LVC244A_74LVCH244A_1 19960906
Product specification
-
-
74LVC_LVCH244A_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 13 August 2009
16 of 18
74LVC244A; 74LVCH244A
NXP Semiconductors
Octal buffer/line driver; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74LVC_LVCH244A_6
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 06 — 13 August 2009
17 of 18
NXP Semiconductors
74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 13 August 2009
Document identifier: 74LVC_LVCH244A_6