PPG33F data 3 delay devices, inc. 3-BIT PROGRAMMABLE PULSE GENERATOR (SERIES PPG33F) FEATURES • • • • • • • • • PACKAGES Digitally programmable in 7 steps Monotonic pulse-width-vs-address variation Rising edge triggered Two separate outputs: inverting & non-inverting Precise and stable pulse width Input & outputs fully TTL interfaced & buffered 10 T2L fan-out capability Fits standard 14-pin DIP socket Auto-insertable TRIG 1 16 VCC TRIG 1 14 VCC N/C 2 15 OUT/ OUT 2 13 OUT/ OUT 3 14 N/C N/C 3 12 N/C N/C 4 13 N/C N/C 4 11 N/C N/C 5 12 A0 A1 N/C 5 10 A0 N/C 6 11 RES 6 9 A1 RES 7 10 A2 GND 7 8 A2 GND 8 9 N/C DIP PPG33F-xx Commercial PPG33F-xxM Military Gull-Wing PPG33F-xxC3 Commercial PPG33F-xxMC3 Military FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS The PPG33F-series device is a 3-bit digitally programmable pulse generator. The width, PWA, depends on the address code (A2-A0) according to the following formula: TRIG OUT OUT/ A0-A2 RES VCC GND PWA = PW0 + TINC * A Trigger Input Non-inverted Output Inverted Output Address Bits Reset +5 Volts Ground where A is the address code, TINC is the incremental pulse width of the device, and PW0 is the inherent pulse width of the device. The incremental width is specified by the dash number of the device and can range from 0.5ns through 50ns, inclusively. RESET is held LOW during normal operation. When it is brought HIGH, OUT and OUT/ are forced into LOW and HIGH states, respectively, and the unit is ready for the next trigger input. The address is not latched and must remain asserted while the output pulse is active. SERIES SPECIFICATIONS • • • • • • DASH NUMBER SPECIFICATIONS Programmed pulse width tolerance: 5% or 1ns, whichever is greater Inherent width (PW0): 9ns typical Inherent delay (TTO): 3.5ns ± 2ns Operating temperature: 0° to 70° C Supply voltage VCC: 5VDC ± 5% Supply current: ICC = 41ma typical 1997 Data Delay Devices Doc #97010 1/15/97 Part Number PPG33F-.5 PPG33F-1 PPG33F-2 PPG33F-3 PPG33F-4 PPG33F-5 PPG33F-6 PPG33F-8 PPG33F-10 PPG33F-20 PPG33F-30 PPG33F-40 PPG33F-50 Incremental Width Per Step (ns) 0.5 ± 0.3 1 ± 0.4 2 ± 0.4 3 ± 0.5 4 ± 0.5 5 ± 0.6 6 ± 0.7 8 ± 0.8 10 ± 1.0 20 ± 1.5 30 ± 1.8 40 ± 2.0 50 ± 2.5 Total Width Change (ns) 3.50 ± 1.00 7.00 ± 1.00 14.0 ± 1.00 21.0 ± 1.05 28.0 ± 1.40 35.0 ± 1.75 42.0 ± 2.10 56.0 ± 2.80 70.0 ± 3.50 140 ± 7.00 210 ± 10.5 280 ± 14.0 350 ± 17.5 NOTE: Any dash number between .5 and 50 not shown is also available. DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 1 PPG33F APPLICATION NOTES DEVICE TIMING POWER SUPPLY BYPASSING The timing definitions and restrictions for the PPG33F are shown in Figure 1. The unit is activated by a rising edge on the TRIG input. After a time, TTO (called the inherent delay), the rising edge of the pulse appears at OUT. The duration of the pulse is given by the above equation. For the duration of the pulse, the device ignores subsequent triggers. Once the falling edge of the pulse has appeared at OUT, an additional time, TOTR, is required before the device can respond to the next trigger. The PPG33F relies on a stable power supply to produce repeatable pulses within the stated tolerances. A 0.1uf capacitor from VCC to GND, located as close as possible to each VCC pin, is recommended. A wide VCC trace should connect all VCC pins externally, and a clean ground plane should be used. At power-up, the state of the PPG33F is unknown. Consequently, after power is applied, the unit may not respond to input triggers for a time equal to the maximum pulse width, PWT. After this time, the unit will function properly. If your application requires that the device function immediately, issue a quick reset at power-up. `A2-A0 INCREMENT TOLERANCES Please note that the increment tolerances listed represent a design goal. Although most increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. Monotonicity is, however, guaranteed over all addresses. Ai Ai+1 TRW TOAX TATS RES TRTS TTW TRIG TTO TRO OUT TOTR TSKEW PW A OUT/ Figure 1: Timing Diagram Doc #97010 1/15/97 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2 PPG33F DEVICE SPECIFICATIONS TABLE 1: AC CHARACTERISTICS PARAMETER Total Programmable Pulse Width Inherent Pulse Width Trigger to Output Delay Reset to Output Delay Output Skew Trigger Pulse Width Reset Pulse Width Reset to Trigger Setup Time Address to Trigger Setup Time Output Low to Address Change Output to Trigger Recovery Time SYMBOL PWT PW0 TTO TRO TSKEW TTW TRW TRTS TATS TOAX TOTR MIN TYP 7 9.0 3.5 6.0 1.5 MAX 12.0 5.5 17.0 1.5 5.0 10.0 9.0 6.0 0.0 15 UNITS TINC ns ns ns ns ns ns ns ns ns % of PWT* *or 10ns, whichever is greater TABLE 2: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Storage Temperature Lead Temperature SYMBOL VCC VIN TSTRG TLEAD MIN -0.3 -0.3 -55 MAX 7.0 VDD+0.3 150 300 UNITS V V C C NOTES 10 sec TABLE 3: DC ELECTRICAL CHARACTERISTICS (0C to 70C, 4.75V to 5.25V) PARAMETER High Level Output Voltage SYMBOL VOH Low Level Output Voltage VOL High Level Output Current Low Level Output Current High Level Input Voltage Low Level Input Voltage Input Clamp Voltage Input Current at Maximum Input Voltage High Level Input Current Low Level Input Current Short-circuit Output Current Output High Fan-out Output Low Fan-out IOH IOL VIH VIL VIK IIHH Doc #97010 1/15/97 IIH IIL IOS MIN 2.5 TYP 3.4 MAX UNITS V 0.35 0.5 V -1.0 20.0 0.8 -1.2 0.1 mA mA V V V mA 20 -0.6 -150 25 12.5 µA mA mA Unit Load 2.0 -60 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 NOTES VCC = MIN, IOH = MAX VIH = MIN, VIL = MAX VCC = MIN, IOL = MAX VIH = MIN, VIL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX 3 PPG33F PACKAGE DIMENSIONS 14 13 12 11 10 8 9 .440 MAX. 1 2 3 4 5 6 7 .830 MAX. .030 .290 MAX. ±.005 .195 ±.010 .010 TYP. .020 TYP. .600 TYP. .300 TYP. DIP (PPG33F-xx, PPG33F-xxM) .020 TYP. .040 TYP. 16 15 14 13 12 11 10 .010±.002 9 .882 ±.005 .710 .590 ±.005 MAX. 1 2 3 4 5 6 .090 7 .007 ±.005 8 .100 .280 MAX. .700 .880±.020 .050 ±.010 Gull-Wing (PPG33F-xxC3, PPG33F-xxMC3) Doc #97010 1/15/97 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 4 PPG33F DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: Ambient Temperature: 25oC ± 3oC Supply Voltage (Vcc): 5.0V ± 0.1V Input Pulse: High = 3.0V ± 0.1V Low = 0.0V ± 0.1V Source Impedance: 50Ω Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) Pulse Width: PWIN = 10ns Period: PERIN = 2 x Max. Pulse Width OUTPUT: Load: Cload: Threshold: 1 FAST-TTL Gate 5pf ± 10% 1.5V (Rising & Falling) NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. PRINTER COMPUTER SYSTEM REF PULSE GENERATOR OUT IN TRIG DEVICE UNDER TEST (DUT) OUT IN TRIG TIME INTERVAL COUNTER Test Setup PERIN PW IN TRISE INPUT SIGNAL TFALL VIH 2.4V 1.5V 0.6V 2.4V 1.5V 0.6V TTO OUTPUT SIGNAL VIL PW A 1.5V VOH 1.5V VOL Timing Diagram For Testing Doc #97010 1/15/97 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 5