INFINEON Q67006

5-V Low-Drop Voltage Regulator
TLE 4263
Features
●
●
●
●
●
●
●
●
●
●
Output voltage tolerance ≤ ± 2 %
Low-drop voltage
Very low standby current consumption
Overtemperature protection
Reverse polarity protection
Short-circuit proof
Settable reset threshold
Watchdog
Wide temperature range
Suitable for use in automotive electronics
Type
Ordering Code Package
TLE 4263 G
Q67006-A9095
P-DSO-20-6 (SMD)
▼ TLE 4263 GM Q67006-A9357
P-DSO-14-4 (SMD)
P-DSO-20-6
P-DSO-14-4
▼ New type
Functional Description
TLE 4263 G is a 5-V low-drop voltage regulator in a P-DSO-20-6 SMD package. The
maximum input voltage is 45 V. The maximum output current is more than 200 mA. The
IC is short-circuit proof and incorporates temperature protection that disables the IC at
overtemperature.
The IC regulates an input voltage VI in the range of 6 V < VI < 45 V to VQrated = 5.0 V. A
reset signal is generated for an output voltage of VQ < 4.5 V. This voltage threshold can
be decreased to 3.5 V by external connection. The reset delay can be set externally by
a capacitor. The integrated watchdog logic controls the connected microcontroller. The
IC can be switched off via the inhibit input, which causes the current consumption to drop
from 800 µA to < 50 µA.
Semiconductor Group
1
1998-11-01
TLE 4263
Dimensioning Information on External Components
The input capacitor CI is necessary for compensating line influences. Using a resistor of
approx. 1 Ω in series with CI, the oscillating circuit consisting of input inductivity and input
capacitance can be damped. The output capacitor is necessary for the stability of the
regulating circuit. Stability is guaranteed at values ≥ 22 µF and an ESR of ≤ 3 Ω within
the operating temperature range. For small tolerances of the reset delay the spread of
the capacitance of the delay capacitor and its temperature coefficient should be noted.
Pin Configuration
(top view)
TLE 4263 G
TLE 4263 GM
N.C.
QRES
GND
GND
GND
DRES
SRES
1
2
3
4
5
6
7
14
13
12
11
10
9
8
INH
VΙ
GND
GND
GND
VQ
W
AEP02587
Semiconductor Group
2
1998-11-01
TLE 4263
Pin Definitions and Functions
Pin
Symbol
Function
1, 2, 19, 13
N.C.
Not connected
3
QRES
Reset output; open-collector output connected to the
output via a resistor of 30 kΩ.
4-7,
14-17
GND
Ground
9
DRES
Reset delay; connected to ground with a capacitor.
10
SRES
Reset threshold; for setting the switching threshold
connect with a voltage divider from output to ground. If this
input is connected to GND, reset is triggered at an output
voltage of 4.5 V.
11
W
Watchdog; positive edge triggered input for monitoring a
microcontroller.
12
VQ
5-V output voltage; block to ground with a 22−µF
capacitor.
18
VI
Input voltage; block to ground directly at the IC with a
ceramic capacitor.
20
INH
Inhibit; TTL-compatible, low-active input.
Semiconductor Group
3
1998-11-01
TLE 4263
Circuit Description
The control amplifier compares a reference voltage, which is kept highly accurate by
resistance adjustment, to a voltage that is proportional to the output voltage and drives
the base of the series transistor via a buffer. Saturation control as a function of the load
current prevents any over-saturation of the power element. If the externally scaled down
output voltage at the reset threshold input drops below 1.35 V, the external reset delay
capacitor is discharged by the reset generator. If the voltage on the capacitor reaches
the lower threshold VST, a reset signal is issued on the reset output and not cancelled
again until the upper threshold VdT is exceeded. If the reset threshold input is connected
to GND, reset is triggered at an output voltage of 4.5 V. A connected microcontroller is
controlled by the watchdog logic. If pulses are missing, the reset output is set to low. The
pulse sequence time can be set within a wide range with the reset delay capacitor. The
IC can be switched at the TTL-compatible, low-active inhibit input. The IC also
incorporates a number of internal circuits for protection against:
●
●
●
Overload
Overtemperature
Reverse polarity
11
Saturation
Control and
Protection
Circuit
Temperature
Sensor
Input
Watchdog
12
18
Control
Amplifier
Buffer
Bandgap
Reference
Reset
Generator
Output
9 Reset
Delay
3 Reset
Output
10 Reset
Threshold
Adjustment
20
Inhibit
4-7, 14-17
GND
AEB01100
Block Diagram
Semiconductor Group
4
1998-11-01
TLE 4263
Absolute Maximum Ratings
Tj = – 40 to 150 °C
Parameter
Symbol
Limit Values
Unit Remarks
min.
max.
VI
II
– 42
–
45
–
V
–
–
internally limited
VR
IR
– 0.3
–
42
–
V
–
–
internally limited
VRE
– 0.3
6
V
–
Vd
Id
– 0.3
–
42
–
V
–
–
internally limited
VQ
IQ
– 0.3
–
7
–
V
–
–
internally limited
Ve
– 42
45
V
–
VW
– 0.3
6
V
–
IGND
– 0.5
–
A
–
Input
Input voltage
Input current
Reset Output
Voltage
Current
Reset Input
Reset threshold
Reset Delay
Voltage
Current
Output
Voltage
Current
Inhibit
Voltage
Watchdog
Voltage
Ground
Current
Semiconductor Group
5
1998-11-01
TLE 4263
Absolute Maximum Ratings (cont’d)
Tj = – 40 to 150 °C
Parameter
Symbol
Limit Values
Unit Remarks
min.
max.
Tj
Tstg
–
– 50
150
150
°C
°C
–
–
Input voltage
VI
–
45
V
–
Junction temperature
Tj
– 40
150
°C
–
Thermal resistance
junction-ambient
junction-case
Rth JA
Rth JC
–
–
70
25
K/W soldered
K/W –
Temperature
Junction temperature
Storage temperature
Operating Range
Semiconductor Group
6
1998-11-01
TLE 4263
Characteristics
VI = 13.5 V; Tj = 25 °C; Ve > 3.5 V; (unless specified otherwise)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit Test Condition
Normal Operation
Output voltage
VQ
4.90
5.00
5.10
V
5 mA ≤ IQ ≤ 150 mA;
6 V ≤ VI ≤ 28 V;
– 40 °C ≤ Tj ≤ 125 °C
Output voltage
VQ
4.95
5.00
5.05
V
6 V ≤ VI ≤ 32 V;
IQ = 100 mA;
Tj = 100 °C
Output current
IQ
200
250
–
mA
–
Current consumption;
Iq = Ii – IQ
Iq
–
–
50
µA
Ve = 0
Iq
Iq
Iq
–
–
–
800
10
15
1100 µA
15
mA
20
mA
IQ = 0 mA
IQ = 150 mA
IQ = 150 mA; Vi = 4.5 V
Drop voltage
VDr
–
0.35
0.6
V
IQ = 150 mA *)
Load regulation
∆VQ
–
–
25
mV
IQ = 5 mA to 150 mA
Supply-voltage
regulation
∆VQ
–
15
25
mV
VI = 6 V to 28 V;
IQ = 150 mA
Ripple rejection
SVR
–
54
–
dB
fr = 100 Hz; Vr = 0.5 Vpp
Switching threshold
VRT
4.2
4.5
4.8
V
VRE = 0 V
Switching voltage
VRE
1.28
1.35
1.42
V
VQ > 3.5 V
Reset low voltage
VR
–
0.10
0.40
V
IR = 1 mA
Reset Generator
Note: The reset output is low within the range VQ = 1 V to VRT
*)
Drop voltage = Vi – VQ (measured when the output voltage has dropped 100 mV
from the nominal value obtained at 13.5 V input)
Semiconductor Group
7
1998-11-01
TLE 4263
Characteristics (cont’d)
VI = 13.5 V; Tj = 25 °C; Ve > 3.5 V; (unless specified otherwise)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit Test Condition
Saturation voltage
VC
–
50
100
mV
VQ < VRT
Delay switching
threshold
VdT
1.5
1.7
2.1
V
–
Switching threshold
VST
0.2
0.35
0.55
V
–
Charge current
Id
40
60
80
µA
–
Delay time
td
–
2.8
–
ms
Cd = 100 nF
Delay time
tt
–
2
–
µs
Cd = 100 nF
Discharge current
ICd
4.4
6.25
8.2
µA
VC = 1.5 V
Switching voltage
VCd
1.5
1.7
2.1
V
–
Pulse time
TW
–
22.5
–
ms
Cd = 100 nF
Switching voltage
Ve ON
3.5
–
–
V
IC turned on
Turn-OFF voltage
Ve OFF
–
–
0.8
V
IC turned off
Input current
Ie
5
10
15
µA
Ve = 5 V
Watchdog
Inhibit
Note: The reset output is low within the range VQ = 1 V to VRT
Semiconductor Group
8
1998-11-01
TLE 4263
12
18
Input
6 V ... 45 V
470 nF
20
KL 15
9
TLE 4263G
100 k Ω
100 nF
10
3
Reset
to MC
Output
22 µF
4
56 k Ω
11
Watchdog
from MC
AES01102
Application Circuit
ΙΙ
Ι
12 Q
18
1000 µF
22 µF
470 nF
TLE 4263G
Ι e 20
VΙ + Vr
9
Ιd
Ve VC
5.6 k Ω
Ι
9 R
4
Ι GND
Cd
100 nF
11
10
VW
V RE
VQ
VR
V Dr = V Ι - V Q *)
Vr
SVR = 20 log
∆V Q
*) Outside Control Range
AES01101
Test Circuit
Semiconductor Group
9
1998-11-01
TLE 4263
VΙ
<tt
V Q V RT
Vcd
dV Ι d
=
dt C d
V dT
V ST
tt
td
VR
Power-on-Reset
Overtemperature
Voltage Drop Undervoltage
at Input
Secondary
Spike
Load
Bounce
AET01085
Time Response, Watchdog with High-Frequency Clock
Semiconductor Group
10
1998-11-01
TLE 4263
Switching Voltage VCd, VdT and
VST versus Temperature
Reset Threshold versus
Output Voltage
AED01098
1.6
V
V RE 1.4
AED01087
3.2
V
V 2.8
V Ι = 13.5 V
1.2
2.4
1.0
2.0
V Ι = 13.5 V
0.8
1.6
0.6
1.2
V dT , V cd
0.8
0.4
V ST
0.4
0.2
0
0
1
4 V 5
VQ
3
2
0
-40
0
40
80
120 C 160
Tj
Current Consumption of Inhibit
versus Temperature
Reset Switching Threshold
versus Temperature
AED01088
1.6
V
V RE 1.4
AED01089
12
Ιe
µA
10
1.2
1.0
8
0.8
6
Ve = 5 V
0.6
4
0.4
2
0.2
0
-40
0
40
Semiconductor Group
80
0
-40
120 C 160
Tj
11
0
40
80
120 C 160
Tj
1998-11-01
TLE 4263
Drop Voltage versus
OutputCurrent
Current Consumption versus
Output Current
AED01094
800
mV
V Dr 700
600
24
500
20
T j = 125 C
25 C
400
12
200
8
100
4
0
50
100
150
200
mA
ΙQ
0
300
Current Consumption versus
Input Voltage
50
100
200
150
mA
ΙQ
300
AED01097
12
mA
VQ
25
V
10
20
8
R L = 25 Ω
15
6
10
R L = 25 Ω
4
5
0
0
Output Voltage versus
Input Voltage
AED01096
30
Ιq
V Ι = 13.5 V
16
300
0
AED01095
32
mA
Ι q 28
2
0
10
20
Semiconductor Group
30
0
40 V 50
VΙ
12
0
2
4
6
8 V 10
VΙ
1998-11-01
TLE 4263
Charge Current and Discharge
Current versus Temperature
Ι
Output Voltage versus
Temperature
AED01104
80
µA
70
AED01090
5.2
VQ
Ιd
V
5.1
60
5.0
V Ι = 13.5 V
V C = 1.5 V
50
Ve = 13.5 V
4.9
40
30
4.8
20
10
0
-40
4.7
Ι Cd
0
80
40
4.6
-40
120 C 160
Tj
Pulse Time versus
Temperature
80
40
120 C 160
Tj
Input Response
AED01106
40
ms
T W 35
∆V Ι
30
AED01092
2
V
1
t r = t f ~_ 1 µ s
0
V Ι = 13.5 V
C d = 100 nF
25
20
40
mV
∆V Q 20
15
10
0
5
-20
0
-40
0
0
Semiconductor Group
40
80
-40
-10
120 C 160
Tj
C Q = 22 µ F
0
10
20
40 µ s 50
30
t
13
1998-11-01
TLE 4263
Output Current versus
Input Voltage
AED01091
300
ΙQ
Load Response
mA
AED01093
295
mA
∆ Ι Q 150
T j = 25 C
250
5
200
200
mV
∆V Q 100
150
C Q = 22 µ F
100
0
50
0
-100
0
10
20
Semiconductor Group
30
-200
-10
40 V 50
VΙ
0
10
20
40 µ s 50
30
t
14
1998-11-01
TLE 4263
Package Outlines
1.27
0.35 x 45˚
7.6 -0.2 1)
0.23 +0.0
9
8˚ ma
x
2.65 max
2.45 -0.2
0.2 -0.1
P-DSO-20-6
(Plastic Dual Small Outline)
0.4 +0.8
0.35 +0.15 2)
0.2 24x
20
0.1
10.3 ±0.3
11
GPS05094
1 12.8 1) 10
-0.2
Index Marking
1) Does not include plastic or metal protrusions of 0.15 max per side
2) Does not include dambar protrusion of 0.05 max per side
Weight approx. 0.6 g
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
15
Dimensions in mm
1998-11-01
TLE 4263
P-DSO-14-1
(Plastic Dual Small Outline)
1.27
0.1
0.35 +0.15 2)
8˚ max.
4 -0.2 1)
0.19 +0.06
1.75 max
1.45 -0.2
0.2 -0.1
0.35 x 45˚
0.4 +0.8
0.2 14x
6 ±0.2
14
8
1
7
8.75 -0.21)
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.05 max. per side
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
16
GPS05093
Dimensions in mm
1998-11-01