INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF40195B MSI 4-bit universal shift register Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF40195B MSI 4-bit universal shift register input. When PE is LOW, data are loaded into the register from P0 to P3 on the LOW to HIGH transition of CP. When PE is HIGH, data are shifted into the first register position from J and K and all the data in the register are shifted one position to the right on the LOW to HIGH transition of CP. D-type entry is obtained by interconnecting J and K. When J is HIGH and K is LOW, the first stage is in the toggle mode. When J is LOW and K is HIGH, the first stage is in the hold mode. A LOW on MR resets all four bit positions (O0 to O3 = LOW, O3 = HIGH) independent of all other input conditions. DESCRIPTION The HEF40195B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions (O0 to O3), a buffered inverted output from the last bit position (O3) and an overriding asynchronous master reset input (MR). Each register stage is of a D-type master-slave flip-flop. Operation is synchronous (except for MR) and is edge-triggered on the LOW to HIGH transition of the CP Fig.1 Functional diagram. HEF40195BP(N): 16-lead DIL; plastic HEF40195BD(F): 16-lead DIL; ceramic (cerdip) (SOT38-1) (SOT74) HEF40195BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America Fig.2 Pinning diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors 4-bit universal shift register January 1995 3 Product specification HEF40195B MSI Fig.3 Logic diagram. Philips Semiconductors Product specification HEF40195B MSI 4-bit universal shift register PINNING PE parallel enable input (active LOW) P0 to P3 parallel data inputs J first stage J-input (active HIGH) K first stage K-input (active LOW) CP clock input (LOW to HIGH edge triggered) MR master reset input (active LOW) O0 to O3 buffered parallel outputs O3 buffered inverted output from last stage FUNCTION TABLE INPUTS (MR = HIGH) OUTPUTS AT tn + 1 OPERATING MODE shift mode parallel entry mode PE J K P0 P1 P2 P3 O0 O1 O2 O3 O3 H L L X X X X L O0 O1 O2 O2 H L H X X X X O0 O0 O1 O2 O2 H H L X X X X O0 O0 O1 O2 O2 H H H X X X X H O0 O1 O2 O2 L X X L L L L L L L L H L X X H H H H H H H H L Notes 1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) 3. X = state is immaterial 4. tn + 1 = state after next LOW to HIGH transition of CP January 1995 4 Philips Semiconductors Product specification HEF40195B MSI 4-bit universal shift register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYP. TYPICAL EXTRAPOLATION FORMULA MAX. Propagation delays CP → On HIGH to LOW 105 215 ns 78 ns + (0,55 ns/pF) CL 50 95 ns 39 ns + (0,23 ns/pF) CL 35 65 ns 27 ns + (0,16 ns/pF) CL 90 180 ns 63 ns + (0,55 ns/pF) CL 45 85 ns 34 ns + (0,23 ns/pF) CL 30 60 ns 22 ns + (0,16 ns/pF) CL 125 255 ns 98 ns + (0,55 ns/pF) CL 50 100 ns 39 ns + (0,23 ns/pF) CL 35 70 ns 27 ns + (0,16 ns/pF) CL 120 240 ns 93 ns + (0,55 ns/pF) CL 50 105 ns 39 ns + (0,23 ns/pF) CL 35 75 ns 27 ns + (0,16 ns/pF) CL 100 205 ns 73 ns + (0,55 ns/pF) CL 45 90 ns 34 ns + (0,23 ns/pF) CL 15 30 65 ns 22 ns + (0,16 ns/pF) CL 5 125 235 ns 98 ns + (0,55 ns/pF) CL 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 CP → O3 HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 MR → On HIGH to LOW LOW to HIGH 5 10 10 tPHL tPLH 15 55 115 ns 44 ns + (0,23 ns/pF) CL 40 85 ns 32 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL Output transition times HIGH to LOW 5 10 tTHL 15 5 LOW to HIGH 10 tTLH 15 January 1995 5 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL Philips Semiconductors Product specification HEF40195B MSI 4-bit universal shift register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Set-up times J, K → CP Pn → CP PE → CP Hold times J, K → CP Pn → CP PE → CP Minimum clock pulse width; LOW Minimum MR pulse width; HIGH Recovery time for MR Maximum clock pulse frequency 5 10 TYP. MAX. 70 35 ns 20 10 ns 10 5 ns 5 85 40 ns 10 tsu MIN. 15 25 10 ns 15 10 5 ns 5 115 55 ns 10 tsu 45 20 ns 15 30 15 ns 5 15 −20 ns tsu 5 −5 ns 15 0 −5 ns 5 20 −25 ns 10 thold 10 −5 ns 15 0 −5 ns 5 10 −50 ns 5 −20 ns 15 5 −10 ns 5 60 30 ns 25 10 ns 15 20 10 ns 5 100 50 ns 40 20 ns 10 10 10 10 thold thold tWCPL tWMRL 15 30 15 ns 5 30 10 ns 15 5 ns 10 tRMR 15 15 5 5 5 10 MHz 14 28 MHz 19 39 MHz 10 15 January 1995 SYMBOL fmax 6 ns see also waveforms Figs 4 and 5 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... dissipation per package (P) 5 1900 fi + ∑ (foCL) × VDD2 where 10 8300 fi + ∑ (foCL) × VDD 2 fi = input freq. (MHz) 15 22 800 fi + ∑ (foCL) × VDD 2 fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) Philips Semiconductors Dynamic power TYPICAL FORMULA FOR P (µW) 4-bit universal shift register January 1995 VDD V 7 Product specification Waveforms showing set-up times, hold times for J, K and Pn inputs; minimum MR pulse width, MR to output delays and MR to CP recovery time; minimum CP pulse width and CP to output delays. Set-up and hold times are shown as positive values but may be specified as negative values. HEF40195B MSI Fig.4 Philips Semiconductors Product specification HEF40195B MSI 4-bit universal shift register Fig.5 Waveforms showing set-up and hold times for PE input. Set-up and hold times are shown as positive values but may be specified as negative values. APPLICATION INFORMATION Some examples of applications for the HEF40195B are: • Serial data transfer • Parallel data transfer • Serial to parallel data transfer • Parallel to serial data transfer January 1995 8 WWW.ALLDATASHEET.COM Copyright © Each Manufacturing Company. All Datasheets cannot be modified without permission. This datasheet has been download from : www.AllDataSheet.com 100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www.AllDataSheet.com