PHILIPS PHB44N06LT

Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. Using ’trench’ technology
the device features very low on-state
resistance and has integral zener
diodes giving ESD protection up to
2kV. It is intended for use in DC-DC
converters and general purpose
switching applications.
PINNING - SOT404
PIN
PHB44N06LT
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 5 V
PIN CONFIGURATION
MAX.
UNIT
55
44
114
175
28
V
A
W
˚C
mΩ
SYMBOL
DESCRIPTION
d
mb
1
gate
2
drain
3
source
mb
drain
g
2
1
s
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
ID
ID
IDM
Ptot
Tstg, Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
RGS = 20 kΩ
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
- 55
55
55
10
44
31
176
114
175
V
V
V
A
A
A
W
˚C
MIN.
MAX.
UNIT
-
2
kV
TYP.
MAX.
UNIT
-
1.31
K/W
50
-
K/W
ESD LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
VC
Electrostatic discharge capacitor
voltage, all pins
Human body model
(100 pF, 1.5 kΩ)
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
Rth j-mb
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
-
Rth j-a
December 1997
Minimum footprint, FR4
board
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHB44N06LT
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
V(BR)DSS
Drain-source breakdown
voltage
Gate threshold voltage
VGS = 0 V; ID = 0.25 mA;
VGS(TO)
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 175˚C
Tj = -55˚C
IDSS
Zero gate voltage drain current
VDS = 55 V; VGS = 0 V;
IGSS
Gate source leakage current
VGS = ±5 V; VDS = 0 V
±V(BR)GSS
Gate-source breakdown
voltage
Drain-source on-state
resistance
IG = ±1 mA;
RDS(ON)
Tj = 175˚C
Tj = 175˚C
VGS = 5 V; ID = 20 A
Tj = 175˚C
MIN.
TYP.
MAX.
UNIT
55
50
1
0.5
10
1.5
0.05
0.02
V
V
V
V
-
2
2.3
10
500
1
10
-
µA
µA
µA
µA
V
-
22
-
28
59
mΩ
mΩ
MIN.
TYP.
MAX.
UNIT
13
-
-
S
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
gfs
Forward transconductance
VDS = 25 V; ID = 25 A
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 40 A; VDD = 44 V; VGS = 5 V
-
27.5
7
13
-
nC
nC
nC
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
1300
250
130
1700
300
180
pF
pF
pF
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 25 A;
VGS = 5 V; RG = 10 Ω
Resistive load
-
22
85
70
64
32
125
95
85
ns
ns
ns
ns
Ld
Internal drain inductance
-
2.5
-
nH
Ls
Internal source inductance
Measured from upper edge of drain
tab to centre of die
Measured from source lead
soldering point to source bond pad
-
7.5
-
nH
MIN.
TYP.
MAX.
UNIT
-
-
44
A
IF = 25 A; VGS = 0 V
IF = 40 A; VGS = 0 V
-
0.95
1.0
176
1.2
-
A
V
IF = 40 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 30 V
-
41
0.16
-
ns
µC
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL
PARAMETER
IDR
IDRM
VSD
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
trr
Qrr
Reverse recovery time
Reverse recovery charge
December 1997
CONDITIONS
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHB44N06LT
AVALANCHE LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 35 A; VDD ≤ 25 V;
VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
December 1997
3
MIN.
TYP.
MAX.
UNIT
-
-
70
mJ
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
120
PHB44N06LT
Normalised Power Derating
PD%
10
Zth/ (K/W)
110
100
90
80
1
70
60
0.5
0.2
50
0.1
40
0.1
30
PD
0.02
20
tp
D=
0.05
tp
T
t
T
10
0
0
0
20
40
60
80 100
Tmb / C
120
140
160
0.01
180
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
120
0.0001
0.01
t/s
1
100
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
1.0E-06
100
110
ID/A
100
80
5
10
VGS/V =
4.8
4.6
4.4
8
6
90
4.2
4.0
80
60
70
3.8
60
3.6
50
3.4
40
40
3.2
30
3.0
20
20
2.8
2.6
2.4
2.2
10 2.0
10
0
0
20
40
60
80 100
Tmb / C
120
140
160
180
0
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
0
2
4
VDS/V
6
8
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
1000
36
RDS(ON)/mOhm
34
ID/A
4
VGS/V =
tp =
1 us
RDS(ON) = VDS/ID
100
4.2
32
4.4 4.6
30
4.8
5
10us
28
100 us
DC
26
10
1 ms
24
10ms
100ms
1
22
20
1
10
VDS/V
100
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
December 1997
0
10
20
30
ID/A
40
50
60
70
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
4
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHB44N06LT
80
ID/A
70
2.5
60
2
max.
typ.
50
1.5
40
min.
1
30
20
0.5
10
0
BUK959-60
VGS(TO) / V
Tj/C =
0
25
175
1
2
3
VGS/V
4
5
0
-100
6
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
-50
0
50
Tj / C
100
150
200
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
40
Sub-Threshold Conduction
1E-01
gfs/S
35
1E-02
30
25
2%
1E-03
typ
98%
20
1E-04
15
1E-05
10
5
0
10
20
30
40
ID/A
50
60
70
1E-05
80
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
2.5
BUK959-60
a
0
0.5
1
1.5
2
2.5
3
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
3
Rds(on) normlised to 25degC
2.5
Thousands pF
2
1.5
2
1.5
Ciss
1
1
.5
0.5
-100
-50
0
50
Tmb / degC
100
150
0
0.01
200
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 20 A; VGS = 5 V
December 1997
0.1
1
VDS/V
10
Coss
Crss
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
5
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHB44N06LT
6
120
VGS/V
WDSS%
110
5
100
90
VDS = 14V
4
80
VDS = 44V
70
3
60
50
40
2
30
20
1
10
0
0
0
5
10
15
QG/nC
20
25
20
30
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 40 A; parameter VDS
40
60
80
100
120
Tmb / C
140
160
180
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 40 A
100
IF/A
VDD
+
80
L
VDS
60
Tj/C =
175
25
-
VGS
-ID/100
40
0
20
0
T.U.T.
R 01
shunt
RGS
0
0.5
VSDS/V
1
1.5
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD )
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
+
VDD
RD
VDS
-
VGS
0
RG
T.U.T.
Fig.17. Switching test circuit.
December 1997
6
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHB44N06LT
MECHANICAL DATA
Dimensions in mm
4.5 max
1.4 max
10.3 max
Net Mass: 1.4 g
11 max
15.4
2.5
0.85 max
(x2)
0.5
2.54 (x2)
Fig.18. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.19. SOT404 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
December 1997
7
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHB44N06LT
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1997
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
December 1997
8
Rev 1.100