PHILIPS 74ALVC374PW

74ALVC374
Octal D-type flip-flop; positive-edge trigger; 3-state
Rev. 02 — 17 October 2007
Product data sheet
1. General description
The 74ALVC374 is an octal D-type flip-flop featuring separate D-type inputs for each
flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an
outputs enable input (OE) are common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that meet the set-up and
hold times requirements on the LOW to HIGH CP transition.
When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the flip-flops.
The 74ALVC374 is functionally identical to the 74ALVC574, but has a different pin
arrangement.
2. Features
■
■
■
■
■
■
■
Wide supply voltage range from 1.65 V to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standards:
◆ JESD8-7 (1.65 V to 1.95 V)
◆ JESD8-5 (2.3 V to 2.7 V)
◆ JESD8B/JESD36 (2.7 V to 3.6 V)
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A 115-A exceeds 200 V
74ALVC374
NXP Semiconductors
Octal D-type flip-flop; positive-edge trigger; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
74ALVC374D
Package
Temperature range Name
Description
Version
−40 °C to +85 °C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
TSSOP20
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74ALVC374PW −40 °C to +85 °C
74ALVC374BQ
−40 °C to +85 °C
DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
SOT764-1
4. Functional diagram
1
11
EN
C1
11
3
4
7
8
13
14
17
18
3
CP
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
2
4
5
7
6
9
8
9
12
13
12
14
15
17
16
18
19
5
6
15
16
19
OE
1
Fig 1. Logic symbol
mna196
mna891
Fig 2. IEC logic symbol
74ALVC374_2
Product data sheet
2
1D
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 17 October 2007
2 of 17
74ALVC374
NXP Semiconductors
Octal D-type flip-flop; positive-edge trigger; 3-state
3
D0
Q0
2
4
D1
Q1
5
7
D2
Q2
6
8
D3
Q3
9
13
D4
14
D5
Q5 15
17
D6
Q6 16
18
D7
Q7 19
FF1
to
FF8
3-STATE
OUTPUTS
Q4 12
11 CP
1 OE
mna892
Fig 3. Functional diagram
D0
D1
D
Q
D2
D
CP
Q
D
CP
FF1
D3
Q
D
CP
FF2
D4
Q
D
CP
FF3
D5
Q
D
CP
FF4
D6
Q
D
CP
FF5
D7
Q
D
CP
FF6
Q
CP
FF7
FF8
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna893
Fig 4. Logic diagram
74ALVC374_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 17 October 2007
3 of 17
74ALVC374
NXP Semiconductors
Octal D-type flip-flop; positive-edge trigger; 3-state
5. Pinning information
1
OE
terminal 1
index area
OE
1
20 VCC
20 VCC
5.1 Pinning
Q0
2
19 Q7
D0
3
18 D7
D1
4
17 D6
Q0
2
19 Q7
D0
3
18 D7
Q1
5
17 D6
Q2
6
15 Q5
16 Q6
D2
7
14 D5
D3
8
Q3
9
Q1
5
Q2
6
D2
7
374
15 Q5
14 D5
D3
8
13 D4
Q3
9
12 Q4
GND 10
11 CP
GND(1)
13 D4
12 Q4
CP 11
4
GND 10
D1
16 Q6
374
001aad088
Transparent top view
001aad040
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration SO20 and TSSOP20
Fig 6. Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
D[0:7]
3, 4, 7, 8, 13, 14, 17, 18
data input
CP
11
clock input (LOW to HIGH, edge-triggered)
OE
1
output enable input (active LOW)
Q[0:7]
2, 5, 6, 9, 12, 15, 16, 19
3-state flip-flop output
VCC
20
supply voltage
GND
10
ground (0 V)
74ALVC374_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 17 October 2007
4 of 17
74ALVC374
NXP Semiconductors
Octal D-type flip-flop; positive-edge trigger; 3-state
6. Functional description
Table 3.
Function table[1]
Operating mode
Input
Internal flip-flop Output
OE
CP
Dn
Load and read register
L
↑
l
L
↑
h
H
H
Load register and disable
outputs
H
↑
l
L
Z
H
↑
h
H
Z
[1]
Qn
L
L
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition
Z = high-impedance OFF-state
↑ = LOW to HIGH clock transition
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
output voltage
VO
Conditions
Min
−0.5
+4.6
V
VI < 0 V
−50
-
mA
−0.5
+4.6
V
-
±50
mA
VO > VCC or VO < 0 V
output HIGH or LOW state
[1] [2]
output 3-state
power-down mode, VCC = 0 V
[2]
Unit
−0.5
VCC + 0.5
V
−0.5
+4.6
V
−0.5
+4.6
V
-
±50
mA
IO
output current
ICC
supply current
-
100
mA
IGND
ground current
−100
-
mA
Tstg
storage temperature
−65
+150
°C
-
500
mW
total power dissipation
Ptot
VO = 0 V to VCC
Max
Tamb = −40 °C to +85 °C
[3]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
When VCC = 0 V (power-down mode), the output voltage can be 3.6 V in normal operation.
[3]
For SO20 packages: above 70 °C derate linearly with 8 mW/K.
For TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K.
74ALVC374_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 17 October 2007
5 of 17
74ALVC374
NXP Semiconductors
Octal D-type flip-flop; positive-edge trigger; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VCC
Conditions
Min
Max
Unit
supply voltage
1.65
3.6
V
VI
input voltage
0
3.6
V
VO
output voltage
Tamb
ambient temperature
∆t/∆V
input transition rise and fall rate
output HIGH or LOW state
0
VCC
V
output 3-state
0
3.6
V
power-down mode; VCC = 0 V
0
3.6
V
in free air
−40
+85
°C
VCC = 1.65 V to 2.7 V
-
20
ns/V
VCC = 2.7 V to 3.6 V
-
10
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
−40 °C to +85 °C
Conditions
Min
VIH
VIL
VOH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
input leakage current
-
-
V
1.7
-
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
V
VCC = 1.65 V to 1.95 V
-
-
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
V
VCC − 0.2
-
-
V
0.35 × VCC V
VI = VIH or VIL
IO = −6 mA; VCC = 1.65 V
1.25
1.51
-
V
IO = −12 mA; VCC = 2.3 V
1.8
2.10
-
V
IO = −18 mA; VCC = 2.3 V
1.7
2.01
-
V
IO = −12 mA; VCC = 2.7 V
2.2
2.53
-
V
IO = −18 mA; VCC = 3.0 V
2.4
2.76
-
V
IO = −24 mA; VCC = 3.0 V
2.2
2.68
-
V
-
-
0.2
V
VI = VIH or VIL
IO = 6 mA; VCC = 1.65 V
-
0.11
0.3
V
IO = 12 mA; VCC = 2.3 V
-
0.17
0.4
V
IO = 18 mA; VCC = 2.3 V
-
0.25
0.6
V
IO = 12 mA; VCC = 2.7 V
-
0.16
0.4
V
IO = 18 mA; VCC = 3.0 V
-
0.23
0.4
V
IO = 24 mA; VCC = 3.0 V
-
0.30
0.55
V
-
±0.1
±5
µA
VCC = 3.6 V; VI = 3.6 V or GND
74ALVC374_2
Product data sheet
Max
0.65 × VCC
IO = 100 µA; VCC = 1.65 V to 3.6 V
II
Unit
VCC = 2.3 V to 2.7 V
VCC = 1.65 V to 1.95 V
IO = −100 µA; VCC = 1.65 V to 3.6 V
VOL
Typ[1]
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 17 October 2007
6 of 17
74ALVC374
NXP Semiconductors
Octal D-type flip-flop; positive-edge trigger; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
−40 °C to +85 °C
Conditions
Unit
Min
Typ[1]
Max
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 1.65 V to 3.6 V;
VO = 3.6 V or GND;
-
±0.1
±10
µA
IOFF
power-off leakage supply
VCC = 0 V; VI or VO = 0 V to 3.6 V
-
±0.1
±10
µA
ICC
supply current
VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
-
0.2
10
µA
∆ICC
additional supply current
per input pin; VCC = 3.0 V to 3.6 V;
VI = VCC − 0.6 V; IO = 0 A
-
5
750
µA
CI
input capacitance
-
3.5
-
pF
[1]
All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol
tpd
ten
Parameter
propagation delay
enable time
−40 °C to +85 °C
Conditions
Min
Max
VCC = 1.65 V to 1.95 V
1.0
3.1
6.4
ns
VCC = 2.3 V to 2.7 V
1.0
2.3
3.9
ns
VCC = 2.7 V
1.0
2.5
3.6
ns
VCC = 3.0 V to 3.6 V
1.0
2.5
3.6
ns
1.0
3.2
6.4
ns
CP to Qn; see Figure 7
OE to Qn; see Figure 8
[2]
[2]
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
1.0
2.6
4.5
ns
VCC = 2.7 V
1.0
3.2
4.6
ns
1.0
2.4
4.0
ns
VCC = 3.0 V to 3.6 V
tdis
tW
disable time
pulse width
OE to Qn; see Figure 8
[2]
VCC = 1.65 V to 1.95 V
1.5
3.6
7.0
ns
VCC = 2.3 V to 2.7 V
1.0
2.3
4.4
ns
VCC = 2.7 V
1.5
2.9
4.4
ns
VCC = 3.0 V to 3.6 V
1.0
2.8
4.4
ns
VCC = 1.65 V to 1.95 V
3.8
1.1
-
ns
VCC = 2.3 V to 2.7 V
3.3
0.9
-
ns
VCC = 2.7 V
3.3
0.8
-
ns
VCC = 3.0 V to 3.6 V
3.3
1.2
-
ns
clock HIGH or LOW; see Figure 7
74ALVC374_2
Product data sheet
Unit
Typ[1]
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 17 October 2007
7 of 17
74ALVC374
NXP Semiconductors
Octal D-type flip-flop; positive-edge trigger; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol
tsu
Parameter
set-up time
hold time
th
maximum frequency
fmax
−40 °C to +85 °C
Conditions
Min
VCC = 1.65 V to 1.95 V
0.8
−0.1
-
ns
VCC = 2.3 V to 2.7 V
0.8
0.1
-
ns
VCC = 2.7 V
0.8
0.3
-
ns
VCC = 3.0 V to 3.6 V
0.8
0.0
-
ns
VCC = 1.65 V to 1.95 V
0.8
−0.1
-
ns
VCC = 2.3 V to 2.7 V
0.8
0.1
-
ns
VCC = 2.7 V
0.8
0.4
-
ns
VCC = 3.0 V to 3.6 V
0.7
−0.1
-
ns
VCC = 2.3 V to 2.7 V
100
200
-
MHz
VCC = 2.7 V
100
200
-
MHz
150
300
-
MHz
outputs HIGH or LOW state
-
21
-
pF
outputs 3-state
-
13
-
pF
Dn to CP; see Figure 9
see Figure 7
per flip-flop; VI = GND to VCC; VCC = 3.3 V
[1]
Typical values are measured at Tamb = 25 °C
[2]
tpd is the same as tPHL and tPLH.
ten is the same as tPZH and tPZL.
tdis is the same as tPHZ and tPLZ.
[3]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs
74ALVC374_2
Product data sheet
Max
Dn to CP; see Figure 9
VCC = 3.0 V to 3.6 V
power dissipation
capacitance
CPD
Unit
Typ[1]
[3]
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 17 October 2007
8 of 17
74ALVC374
NXP Semiconductors
Octal D-type flip-flop; positive-edge trigger; 3-state
11. Waveforms
1/f max
VI
CP input
VM
GND
tW
t PHL
t PLH
VOH
VM
Qn output
VOL
mna894
Measurement points are given in Table 8.
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 7. Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum frequency
Table 8.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
Vx
Vy
1.65 V to 1.95 V
0.5VCC
0.5VCC
VOL + 0.15 V
VOH − 0.15 V
2.3 V to 2.7 V
0.5VCC
0.5VCC
VOL + 0.15 V
VOH − 0.15 V
2.7 V
2.7 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
3.0 V to 3.6 V
2.7 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
VI
OE input
VM
GND
tPLZ
tPZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
tPHZ
VOH
tPZH
VY
output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
disabled
outputs
enabled
mna644
Measurement points are given in Table 8.
VOL and VOH are the typical output voltage drops that occur with the output load.
Fig 8. Enable and disable times
74ALVC374_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 17 October 2007
9 of 17
74ALVC374
NXP Semiconductors
Octal D-type flip-flop; positive-edge trigger; 3-state
VI
VM
CP input
GND
tsu
tsu
th
th
VI
VM
Dn input
GND
VOH
VM
Qn output
VOL
mna202
Measurement points are given in Table 8.
VOL and VOH are the typical output voltage drops that occur with the output load.
The shaded areas indicate when the input is permitted to change for predicable output performance.
Fig 9. Data set-up and hold times for the Dn input to the CP input
74ALVC374_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 17 October 2007
10 of 17
74ALVC374
NXP Semiconductors
Octal D-type flip-flop; positive-edge trigger; 3-state
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VEXT
VCC
VI
RL
VO
G
DUT
RT
CL
RL
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Test circuitry for switching times
Table 9.
Test data
Supply voltage
Input
Load
VEXT
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
1.65 V to 1.95 V
VCC
≤ 2.0 ns
30 pF
1 kΩ
open
2VCC
GND
2.3 V to 2.7 V
VCC
≤ 2.0 ns
30 pF
500 Ω
open
2VCC
GND
2.7 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
6V
GND
3.0 V to 3.6 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
6V
GND
74ALVC374_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 17 October 2007
11 of 17
74ALVC374
NXP Semiconductors
Octal D-type flip-flop; positive-edge trigger; 3-state
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
HE
y
v M A
Z
20
11
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
10
1
e
bp
detail X
w M
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.51
0.49
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT163-1
075E04
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 11. Package outline SOT163-1 (SO20)
74ALVC374_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 17 October 2007
12 of 17
74ALVC374
NXP Semiconductors
Octal D-type flip-flop; positive-edge trigger; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
E
D
A
X
c
HE
y
v M A
Z
11
20
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
10
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT360-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 12. Package outline SOT360-1 (TSSOP20)
74ALVC374_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 17 October 2007
13 of 17
74ALVC374
NXP Semiconductors
Octal D-type flip-flop; positive-edge trigger; 3-state
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT764-1
20 terminals; body 2.5 x 4.5 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
9
y
y1 C
v M C A B
w M C
b
L
1
10
Eh
e
20
11
19
12
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
max.
A1
b
1
0.05
0.00
0.30
0.18
c
D (1)
Dh
E (1)
Eh
0.2
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
e
0.5
e1
L
v
w
y
y1
3.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT764-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 13. Package outline SOT764-1 (DHVQFN20)
74ALVC374_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 17 October 2007
14 of 17
74ALVC374
NXP Semiconductors
Octal D-type flip-flop; positive-edge trigger; 3-state
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74ALVC374_2
20071017
Product data sheet
-
74ALVC374_1
Modifications:
74ALVC374_1
•
The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Section 3: DHVQFN20 package added.
Section 7: derating values added for DHVQFN20 package.
Section 12: outline drawing added for DHVQFN20 package.
20020227
Product specification
74ALVC374_2
Product data sheet
-
-
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 17 October 2007
15 of 17
74ALVC374
NXP Semiconductors
Octal D-type flip-flop; positive-edge trigger; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
74ALVC374_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 17 October 2007
16 of 17
74ALVC374
NXP Semiconductors
Octal D-type flip-flop; positive-edge trigger; 3-state
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 17 October 2007
Document identifier: 74ALVC374_2