74LVT574; 74LVTH574 3.3 V octal D-type flip-flop; 3-state Rev. 04 — 11 September 2008 Product data sheet 1. General description The 74LVT574; 74LVTH574 is a high-performance product designed for VCC operation at 3.3 V. This device is an 8-bit, edge triggered register coupled to eight 3-state output buffers. The two sections of the device are controlled independently by the clock (pin CP) and output enable (pin OE) control gates. The state of each D input (one setup time before the LOW-to-HIGH clock transition) is transferred to the corresponding flip-flops Q output. The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories, or MOS microprocessors. The active LOW output enable (pin OE) controls all eight 3-state buffers independent of the clock operation. When pin OE is LOW, the stored data appears at the outputs. When pin OE is HIGH, the outputs are in the high-impedance OFF-state, which means they will neither drive nor load the bus. 2. Features n n n n n n n n n n n Inputs and outputs arranged for easy interfacing to microprocessors 3-state outputs for bus interfacing Common output enable control TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted No bus current loading when output is tied to 5 V bus Power-up reset Power-up 3-state Latch-up protection u JESD78 class II exceeds 500mA n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Specified from −40 °C to +85 °C 74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 3. Ordering information Table 1. Ordering information Type number Package 74LVT574D Temperature range Name Description Version −40 °C to +85 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 −40 °C to +85 °C SSOP20 plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 −40 °C to +85 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 −40 °C to +85 °C DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm 74LVTH574D 74LVT574DB 74LVTH574DB 74LVT574PW 74LVTH574PW 74LVT574BQ 4. Functional diagram 1 11 11 CP 2 3 4 5 D0 Q0 D1 Q1 D2 Q2 D3 6 Q3 D4 7 8 9 Q4 D5 Q5 D6 Q6 D7 Q7 C1 19 2 18 1D 19 2 17 3 18 16 4 17 5 16 6 15 7 14 8 13 9 12 15 14 13 12 OE 1 EN2 mna798 001aae466 Fig 1. Logic symbol D0 Fig 2. D1 D CP D2 D Q CP D3 D Q CP D4 D Q IEC logic symbol CP D5 D Q CP D6 D Q CP D7 D Q CP D Q CP Q CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aae467 Fig 3. Logic diagram 74LVT_LVTH574_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 11 September 2008 2 of 16 74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 5. Pinning information 5.1 Pinning OE 1 1 74LVT574 74LVTH574 OE terminal 1 index area 20 VCC 20 VCC 74LVT574 74LVTH574 D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D0 2 19 Q0 D1 3 18 Q1 D3 5 16 Q3 D2 4 17 Q2 D4 6 15 Q4 D3 5 16 Q3 D5 7 14 Q5 D4 6 15 Q4 D6 8 D5 7 14 Q5 D7 9 13 Q6 D7 9 12 Q7 GND 10 11 CP 13 Q6 12 Q7 CP 11 8 GND 10 D6 GND(1) 001aah711 Transparent top view 001aae758 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input Fig 4. Pin configuration for SO20, and (T)SSOP20 Fig 5. Pin configuration for DHVQFN20 5.2 Pin description Table 2. Pin description Symbol Pin Description OE 1 output enable input (active LOW) D0 to D7 2, 3, 4, 5, 6, 7, 8, 9 data input GND 10 ground (0 V) CP 11 clock pulse input (active rising edge) Q0 to Q7 19, 18, 17, 16, 15, 14, 13, 12 data output VCC 20 supply voltage 74LVT_LVTH574_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 11 September 2008 3 of 16 74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 6. Functional description 6.1 Function table Table 3. Function table [1] Operating mode Load and read register Control Input Internal register Output OE CP Dn Qn L ↑ l L L h H H Hold L NC X NC NC Disable outputs H X X NC Z [1] H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH clock transition; h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition; l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition; Z = high-impedance OFF-state; NC = no change; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage VO output voltage output in OFF-state or HIGH-state IIK input clamping current IOK output clamping current IO output current Tstg storage temperature Tj junction temperature Ptot total power dissipation Conditions Min Max Unit −0.5 +4.6 V [1] −0.5 +7.0 V [1] −0.5 +7.0 V VI < 0 V - −50 mA VO < 0 V - −50 mA output in LOW-state - 128 mA output in HIGH-state - −64 mA −65 +150 °C - 150 °C - 500 mW [2] Tamb = -40 ˚C to +85 ˚C [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. [3] For SO20 packages: above 70 ˚C derate linearly with 8 mW/K. For SSOP20 and TSSOP20 packages: above 60 ˚C derate linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 ˚C derate linearly with 4.5 mW/K. 74LVT_LVTH574_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 11 September 2008 4 of 16 74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC Conditions Min Max Unit supply voltage 2.7 3.6 V VI input voltage 0 5.5 V VIH HIGH-level input voltage 2.0 - V VIL LOW-level input voltage - 0.8 V IOH HIGH-level output current - −32 mA IOL LOW-level output current - 32 mA current duty cycle ≤ 50 %; fi ≥ 1 kHz - 64 mA Tamb ambient temperature in free air −40 +85 °C ∆t/∆V input transition rise and fall rate outputs enabled - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC = 2.7 V; IIK = −18 mA VIK input clamping voltage VOH HIGH-level output voltage VCC = 2.7 V to 3.6 V; IOH = −100 µA VOL LOW-level output voltage Tamb = −40 °C to +85 °C Conditions Unit Min Typ[1] Max −1.2 −0.9 - V - V VCC − 0.2 VCC − 0.1 VCC = 2.7 V; IOH = −8 mA 2.4 2.5 - V VCC = 3.0 V; IOH = −32 mA 2.0 2.2 - V IOL = 100 µA - 0.1 0.2 V IOL = 24 mA - 0.3 0.5 V IOL = 16 mA - 0.25 0.4 V IOL = 32 mA - 0.3 0.5 V - 0.4 0.55 V - 0.13 0.55 V - 1 10 µA - ±0.1 ±1 µA VI = VCC - 0.1 1 µA VI = 0 V −5 −1 - µA - 1 ±100 µA VCC = 2.7 V VCC = 3.0 V IOL = 64 mA VOL(pu) power-up LOW-level output voltage VCC = 3.6 V; IO = 1 mA; VI = GND or VCC II input leakage current all input pins; VCC = 0 V or 3.6 V; VI = 5.5 V [2] control pins; VCC = 3.6 V; VI = VCC or GND data pins; VCC = 3.6 V IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V - 60 125 µA 75 150 - µA VCC = 3.0 V; VI = 2.0 V [4] - −150 −75 µA VCC = 3.6 V; VI = 0V to 3.0 V [4] - - 500 µA ILO output leakage current VO = 5.5 V and VCC = 3.0 V; output HIGH IBHL bus hold LOW current VCC = 3.0 V; VI = 0.8 V IBHH IBHHO [3] bus hold HIGH current bus hold HIGH overdrive current 74LVT_LVTH574_4 Product data sheet [4] © NXP B.V. 2008. All rights reserved. Rev. 04 — 11 September 2008 5 of 16 74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 °C Conditions IBHLO bus hold LOW overdrive current VCC = 0 V; VI = 0V to 3.0 V IO(pu/pd) power-up/power-down output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; OE = don’t care IOZ OFF-state output current VCC = 3.6 V; VI = VIH or VIL supply current ICC Unit Min Typ[1] Max −500 - - µA - 1 ±100 µA [5] output HIGH: VO = 3.0 V - 1 5 µA output LOW: VO = 0.5 V −5 1 - µA - 0.13 0.19 mA VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs HIGH outputs LOW outputs disabled - 3 12 mA [6] - 0.13 0.19 mA [7] - 0.1 0.2 mA ∆ICC additional supply current per input pin; VCC = 3 V to 3.6 V; one input at VCC − 0.6 V and other inputs at VCC or GND CI input capacitance VI = 0 V or 3.0 V - 4 - pF CO output capacitance outputs disabled; VO = 0 V or 3.0 V - 8 - pF [1] Typical values are measured at VCC = 3.3 V and Tamb = 25 °C. [2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. [3] Unused pins at VCC or GND. [4] This is the bus hold overdrive current required to force the input to the opposite logic state. [5] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only. [6] ICC is measured with outputs pulled to VCC or GND. [7] This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to ground (GND = 0 V); for test circuit see Figure 10. Symbol Parameter tPLH LOW to HIGH propagation delay Conditions VCC = 2.7 V HIGH to LOW propagation delay Typ[1] 1.7 3.6 5.4 ns - - 6.2 ns 2.4 4.3 5.9 ns - - 6.6 ns 1.0 2.9 4.8 ns - - 5.9 ns Max CP to Qn; see Table 6 VCC = 3.0 V to 3.6 V VCC = 2.7 V tPZH Min CP to Qn; see Table 6 VCC = 3.0 V to 3.6 V tPHL Tamb = −40 °C to +85 °C Unit OFF-state to HIGH propagation delay OE to Qn; see Figure 7 VCC = 3.0 V to 3.6 V VCC = 2.7 V 74LVT_LVTH574_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 11 September 2008 6 of 16 74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to ground (GND = 0 V); for test circuit see Figure 10. Symbol Parameter tPZL Tamb = −40 °C to +85 °C Unit Conditions VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 2.7 V VCC = 2.7 V set-up time Dn to CP; see Figure 9 VCC = 2.7 V ns 6.2 ns 1.9 4.0 5.5 ns - - 5.9 ns 1.7 3.2 4.5 ns - - 4.5 ns 2.0 - - ns 2.4 - - ns hold time Dn to CP; see Figure 9 [3] VCC = 3.0 V to 3.6 V VCC = 2.7 V pulse width CP input; see Figure 6 VCC = 3.0 V to 3.6 V VCC = 2.7 V fmax 5.1 - [2] VCC = 3.0 V to 3.6 V tW 3.4 - LOW to OFF-state propagation delay OE to Qn; see Figure 8 VCC = 3.0 V to 3.6 V th 1.3 Max HIGH to OFF-state propagation delay OE to Qn; see Figure 7 tPHZ tsu Typ[1] OFF-state to LOW propagation delay OE to Qn; see Figure 8 VCC = 3.0 V to 3.6 V tPLZ Min maximum frequency CP input; VCC = 3.0 V to 3.6 V; see Figure 6 [1] Typical values are at VCC = 3.3 V and Tamb = 25 °C. [2] tsu is the same as tsu(H) and tsu(L) [3] th is the same as th(H) and th(L) [4] tW is the same as tWH and tWL 74LVT_LVTH574_4 Product data sheet 0.3 - - ns 0 - - ns 3.3 - - ns 3.3 - - ns 150 - - MHz [4] © NXP B.V. 2008. All rights reserved. Rev. 04 — 11 September 2008 7 of 16 74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 11. Waveforms 1/f max VI CP input VM GND t WH t WL t PHL t PLH VOH VM Qn output VOL 001aac445 Measurement points are given in Table 8 VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Propagation delay clock input (CP) to output (Qn), pulse width clock (CP) and maximum clock frequency VI OE input VI VM VM GND t PZH t PHZ tPZL VOH Qn output VM VM OE input GND tPLZ 3.0 V VY VM Qn output VM VX VOL GND 001aae468 Fig 7. 001aae469 Measurement points are given in Table 8 Measurement points are given in Table 8 VOL and VOH are typical voltage output levels that occur with the output load. VOL and VOH are typical voltage output levels that occur with the output load. Output enable time to HIGH-state and output disable time from HIGH-state Fig 8. Output enable time to LOW-state and output disable time from LOW-state Vl VM Dn input VM VM VM GND t su(H) t h(H) t su(L) t h(L) Vl VM CP input GND VM 001aac738 Measurement points are given in Table 8 Remark: The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Data setup and hold times 74LVT_LVTH574_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 11 September 2008 8 of 16 74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state Table 8. Measurement points Input Output VM VM VX VY 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V VI tW 90 % negative pulse VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae235 Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 10. Load circuitry for switching times Table 9. Test data Input Load VEXT VI fi tW tr, tf CL RL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω GND 6V open 74LVT_LVTH574_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 11 September 2008 9 of 16 74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT163-1 (SO20) 74LVT_LVTH574_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 11 September 2008 10 of 16 74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm D SOT339-1 E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.9 0.5 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT339-1 (SSOP20) 74LVT_LVTH574_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 11 September 2008 11 of 16 74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 13. Package outline SOT360-1 (TSSOP20) 74LVT_LVTH574_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 11 September 2008 12 of 16 74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 14. Package outline SOT764-1 (DHVQFN20) 74LVT_LVTH574_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 11 September 2008 13 of 16 74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVT_LVTH574_4 20080911 Product data sheet - 74LVT_LVTH574_3 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. • Section 3 “Ordering information” and Section 12 “Package outline”: DHVQFN20 package added. Table 4 “Limiting values” Ptot added. 74LVT_LVTH574_3 20060323 Product data sheet - 74LVT574_2 74LVT574_2 19980219 product specification - 74LVT574_1 74LVT574_1 19951114 product specification - - 74LVT_LVTH574_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 11 September 2008 14 of 16 74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVT_LVTH574_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 11 September 2008 15 of 16 NXP Semiconductors 74LVT574; 74LVTH574 3.3 V octal D-type flip-flop; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 11 September 2008 Document identifier: 74LVT_LVTH574_4