Wireless Components RF/IF Double PLL Frequency Synthesizer PMB 2347 Version 1.1 Specification August 1999 preliminary Revision History: Current Version: 08.99 Previous Version:Data Sheet Page (in previous Version) Page (in current Version) Subjects (major changes since last revision) ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S, ELIC®, FALC®54, FALC®56, FALC®-E1, FALC®-LH, IDEC®, IOM®, IOM®-1, IOM®-2, IPAT®-2, ISAC®-P, ISAC®-S, ISAC®-S TE, ISAC®-P TE, ITAC®, IWE®, MUSAC®-A, OCTAT®-P, QUAT®-S, SICAT®, SICOFI®, SICOFI®2, SICOFI®-4, SICOFI®-4µC, SLICOFI® are registered trademarks of Infineon Technologies AG. ACE™, ASM™, ASP™, POTSWIRE™, QuadFALC™, SCOUT™ are trademarks of Infineon Technologies AG. Edition 03.99 Published by Infineon Technologies AG i. Gr., SC, Balanstraße 73, 81541 München © Infineon Technologies AG i. Gr. 25.10.99. All Rights Reserved. Attention please! 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Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the Infineon Technologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. PMB 2347 preliminary Productinfo Productinfo General Description Features The PMB 2347 is a RF/IF double PLL Package frequency synthesizer implemented in Infineon’ high speed BiCMOS technology B6HFC. The device contains two PLLs with integrated prescalers especially designed for use in battery powered radio equipment and mobile telephones. Primary applications are single- and dual-band digital cellular systems e.g. GSM, PCN (DCS 1800) and PCS systems. ■ Operation range 2.7 to 5.0 V ■ Low operating current consumption ■ Programmable power down modes ■ High input sensitivity and high input frequencies: PLL1 (RF): 2.8 GHz PLL2 (IF): 500 MHz ■ ■ Programmable dual modulus prescaler divide ratio: PLL1: 1:64/65 or 1:32/33 PLL2: 16/17 or 1:8/9 Dividing ratios: A counters: PLL1: 0 to 63 PLL2: 0 to 15 N counters: PLL1: 3 to 16,383 PLL2: 3 to 16,383 R counters 3 to 16,383 for PLL1 and PLL2 ■ High phase noise performance ■ Switchable polarity and programmable phase detector currents ■ External reference current setting for PD outputs ■ Fast serial 3-wire bus interface with low threshold voltage Schmitt-Trigger inputs for interfacing with low voltage baseband circuits ■ Two data registers in PLL2 for fast IF band switching ■ A programmable multi-functional output port for lock detect (quasidigital lock detect) and test mode Fast phase detectors and charge pump outputs without dead zone Ordering Information Type Ordering Code P-TSSOP-20 PMB 2347 Wireless Components Package Product Info Specification, August 1999 1 Table of Contents 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2 2.1 2.2 2.3 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 3 3.1 3.2 3.3 3.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 4 4.1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 5 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.2 5.3 5.4 5.5 5.6 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Typical Supply Current ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Serial Control Data Format Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Serial Control Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Input Sensitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Charge Pump Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Threshold Voltages of Schmitt-Trigger Input . . . . . . . . . . . . . . . . . . 5-16 2 Product Description Contents of this Chapter 2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 PMB 2347 preliminary Product Description 2.1 Overview The PMB 2347 is a RF/IF double PLL frequency synthesizer implemented in Infineon’ high speed BiCMOS technology B6HFC. The device contains two PLLs with integrated prescalers especially designed for use in battery powered radio equipment and mobile telephones. Primary applications are single- and dual-band digital cellular systems e.g. GSM, PCN (DCS 1800) and PCS systems. 2.2 Features Wireless Components ■ Operation range 2.7 to 5.0 V ■ Low operating current consumption ■ Programmable power down modes ■ High input sensitivity and high input frequencies: PLL1 (RF): 2.8 GHz PLL2 (IF): 500 MHz ■ Programmable dual modulus prescaler divide ratio: PLL1: 1:64/65 or 1:32/33 PLL2: 16/17 or 1:8/9 Dividing ratios: A counters: PLL1: 0 to 63 PLL2: 0 to 15 N counters: PLL1: 3 to 16,383 PLL2: 3 to 16,383 R counters 3 to 16,383 for PLL1 and PLL2 ■ Fast phase detectors and charge pump outputs without dead zone ■ High phase noise performance ■ Switchable polarity and programmable phase detector currents ■ External reference current setting for PD outputs ■ Fast serial 3-wire bus interface with low threshold voltage Schmitt-Trigger inputs for interfacing with low voltage baseband circuits ■ Two data registers in PLL2 for fast IF band switching ■ A programmable multi-functional output port for lock detect (quasidigital lock detect) and test mode 2-2 Specification, August 1999 PMB 2347 preliminary Product Description 2.3 Package Outlines P-TSSOP-20 Wireless Components 2-3 Specification, August 1999 3 Functional Description Contents of this Chapter 3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4 1 2 3 4 5 6 7 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Standby Condition (power down) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Divide ratio programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Prescaler Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Fast wake-up programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Phase Detector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 PMB 2347 preliminary Functional Description 3.1 Pin Configuration VCC1 1 20 VCC2 VPD1 2 19 VPD2 CP1 3 18 CP2 GND1 4 17 GND1 RF 5 16 IF PMB 2347 RFX 6 15 IFX GND2 7 14 GND2 EN 8 13 RI DA 9 12 Rext CLK 10 11 LD/fo Pin_config.wmf Figure 3-1 Pin Configuration 3.2 Pin Definition and Function Table 3-1 Pin Definition and Function Pin No. Symbol Equivalent I/O-Schematic Function 1 VCC1 Positive supply voltage for CMOS circuitry 2 VPD1 Positive supply voltage for charge pump of PLL1 3 CP1 PLL1 charge pump output Phase detector tristate charge pump output PD Output Equivalent 3 *2pF CP1 ESD Wireless Components 3-2 Specification, August 1999 PMB 2347 preliminary Functional Description 4 GND1 Ground for CMOS circuitry 5 RF1 RF frequency input 1 RF input with highly sensitive preamplifier for PLL1. AC coupling must be set up. RF and IF Input Equivalent 5/16 6 6/15 RFX RF/IF RFx/IFx RF frequency input (inverted) RF input with highly sensitive preampifier for PLL1. AC coupling must be set up 7 GND1 Ground for bipolar circuitry 8 EN 3-Wire bus input: Enable Enable input of the serial control interface with Schmitt-Trigger input stage. When EN=H the input signals CLK and DA are disabled. When EN=L the serial control interface is enabled. The received data are transferred to the registers with the positive edge of the EN-signal. Serial Control Input Equivalent 75kΩ 8 CLK 560Ω *2pF ESD 9 DA Serial Control Input Equivalent 75kΩ 9 DA 560Ω *2pF 3-Wire bus input: Data Data input of the serial control interface with Schmitt-Trigger input stage.The serial data are read into the internal shift register with the positive edge of CLK. ESD Wireless Components 3-3 Specification, August 1999 PMB 2347 preliminary Functional Description 10 CLK Serial Control Input Equivalent 75kΩ 10 3-Wire bus input: Clock Clock input of the serial control interface with Schmitt-Trigger input stage 560Ω *2pF EN ESD 11 LD/fo Lock detector output Unipolar output of the phase detector in the form of a pulse-width modulated signal. In the locked state the output signal is at H-level. In standby mode the output is resistive. For test purpose the push pull output fo is enabled. LD as Lock Detector 11 *2pF LD/fo ESD 12 Rext CP& Prescaler reference current setting External resistor for CP & Prescaler reference current setting. OSW Output Equivalent 12 2pF Rext ESD 13 RI RI Input Equivalent STDBY 500KΩ 13 560Ω RI Reference frequency input Input with highly sensitive preamplifier. With small input signals AC coupling must be set up, where DC coupling can be used for large input signals. 2pF ESD /STDBY 14 GND2 Wireless Components Ground for bipolar circuitry 3-4 Specification, August 1999 PMB 2347 preliminary Functional Description 15 IFX IF frequency input (inverted) IF input with highly sensitive preampifier for PLL2. AC coupling must be set up. RF and IF Input Equivalent 16 IF 17 GND1 18 CP2 5/16 6/15 RF/IF RFx/IFx IF frequency input IF input with highly sensitive preampifier for PLL2. AC coupling must be set up. Ground for CMOS circuitry Phase detector tristate charge pump output for PLL2 PD Output Equivalent 18 *2pF CP2 ESD 19 VPD2 Positive supply voltage for charge pump 2. 20 VCC2 Positive supply voltage for bipolar circuitry Wireless Components 3-5 Specification, August 1999 PMB 2347 preliminary Functional Description 3.3 Functional Block Diagram 1 PLL1 (RF) 20 Mod1 VCC1 2 VPD1 3 PD1 Phase Detector Mod1 64/65 32/33 4 GND1 5 RF Modulus Control VCC2 14 Bit N-Counter 6 Bit A-Counter Data Reg. Shadow Reg. Data Reg. Shadow Reg. Shift Register Shift Register 19 VPD2 Phase Detector 17 GND1 14 Bit R1-Counter 14 Bit R1-Counter Data Reg. Shadow Reg. Data Reg. Shift Register Shift Register 16 IF 6 RFX Mod2 16/17 8/9 15 IFX 7 GND2 14 GND2 Modulus Control 14 Bit N-Counter 8 4 Bit A-Counter 13 RI EN Serial Control Logic Dec 9 DA 18 PD2 Multiplexer Multiplexer Data Reg. 1 Data Reg. 2 Data Reg. 1 Data Reg. 2 Shift Register 10 CLK Bias Iref Shift Register LD fo 12 REXT 11 LD/fo PLL2 (IF) 376623 Funct_block.wmf Figure 3-2 Wireless Components Functional Block Diagram 3-6 Specification, August 1999 PMB 2347 preliminary Functional Description 3.4 Circuit Description 1. General Description The PMB 2347 consists of two fully programmable PLLs, one for the RF and one for the IF frequency range. Each PLL contains a high frequency dual modulus prescaler, an A- and a N-counter with dual modulus control logic, a reference- (R-) counter, and a phase detector with charge pump output. The two synthesizers are controlled via the common serial 3-wire interface. The reference frequency is applied at the common RI-input and divided by the R-counter of each PLL. Its maximum value is 45 MHz. The RF and IF input frequencies will be divided by the corresponding prescalers with a programmable 32/32 or 64/65 (RF) and 8/9 or 16/17 (IF) divide ratio and the following programmable A/N-counters. The maximum RF frequency value is 2.8 GHz and 500 MHz for the IF frequency. The phase and frequency detectors with the charge pumps have a linear operating range without a dead zone for very small phase deviations. The multifunctional output port LD/fo can be programmed as lock detector and test output. 2. Programming Programming of the IC is done via the serial data interface. The content of the bus telegram (serial data format) is assigned to the functional units according to the address. The most significant bit (MSB) of the serial data formats is shifted first. The short control data format allows a fast PD-current change. The long control data format allows the programming of asynchronous or synchronous data acquisition of PLL1 (RF), 4 different PD-output current modes for the PLL1 and 1 PD-output current modes for PLL2, polarity setting of the PDoutput signals, 2 standby modes, charge pump pulse width and the prescaler divide ratio. The A/N-counter data format of PLL1 contains the A/N-counter value.. The data format of PLL2 comprise the counter values as well. The R-counter data format contains the R-counter values. The PLL1 (RF) of PMB 2347 offers the possibility of synchronous counter and charge pump current programming to avoid phase errors at the phase detector when R- and A-/N-counter are programmed one after another or the charge pump current is altered. Asynchronous Mode: The serial data is written directly to the data registers of the addressed counter with the Enable pulse. As each counter is loading the new starting value after it is decremented to „zero“, the counters changes therefore their counter values asynchronously to the others. Wireless Components 3-7 Specification, August 1999 PMB 2347 preliminary Functional Description Synchronous Mode (only for RF): In this mode counter programming is controlled by the R- and N-counters. The serial data (exception: higher part of long control data format) is first written with the Enable pulse to the corresponding shadow registers. From there the values for R-counter, A-/N-counter and charge pump current values of short/long control data format are loaded into the corresponding data register when the Ncounter reaches „zero+1“. Therefore the change of all counter states is synchronised to the reloading of the N-counter to avoid additional phase error caused by the programming. The transfer of the charge pump current values into the corresponding data register is tied to the N-counter loading, but follows the loading of the N-data register in the distance of one N-counter dividing ratio. This guarantees that a new PD-current value becomes valid at the same time when the counters are loaded with the new data. Synchronous programming sequence: 1.Setting of synchronous counter programming by bit c13 of long control data format. 2.Programming of the R-counter, and optional short control data format. With the Enable signal data is loaded into the shadow registers. 3.Programming of the A/N-counter. Data is loaded into shadow registers, the EN-signal starts the synchronous transfer to the data registers. Synchronous data programming is of especial advantage, when large frequency steps are to be made in a short time. For this purpose a high reference frequency can be programmed in order to achieve rapid – “rough” – transient response. This method increases the fundamental frequency by nearly the square root of the reference frequency ratio and therefore the settling time is reduced. When rough lock is achieved, another synchronous data transfer is needed to switch back to the original channel spacing. A “fine” lock in will finish the total step response. It may not be necessary to change reference frequency, but it make sense to perform synchronous data acquisition in any case. Especially for GSM, PCN (DCS 1800) and PCS systems the synchronous mode should be used to achieve best performance of the PMB 2347. 3. Standby Condition (power down) Each PLL of the PMB 2347 has two programmable standby modes to reduce the current consumption (standby 1, standby 2). Standby 1: The corresponding PLL is switched off, the current consumption is reduced below 1 µA. Standby 2: Wireless Components The corresponding counters, the charge pump and the outputs are switched off. Only the preamplifier of RI-input stays active. (See standby table) 3-8 Specification, August 1999 PMB 2347 preliminary Functional Description 4. Divide ratio programming The frequency of an external VCO controlled by the PMB 2347 is given below: f RI M f VCO = [ ( P ⋅ N ) + A ] ⋅ ------- = ----- ⋅ f RI R R with A ≤ N . fVCO: fRI: N: A: P: R: M=P*N+A: frequency of the external VCO reference frequency divide ratio of the N-counter divide ratio of the A-swallow counter divide ratio of the prescaler divide ratio of the R-counter total divide ratio Note: for continous frequency steps following condition is necessary [P ⋅ N + A] ≥ P ⋅ (P – 1) 5. Prescaler Divide Ratio For the highest input frequencies of the prescalers the larger divide ratio is necessary: RF-PLL: 64/65 for frequencies greater 1500 MHz IF-PLL: 16/17 for frequencies greater 375 MHz 6. Fast wake-up programming When the circuit is connected to the supply voltage all registers are undefined. Due to the fact that each counter is loading its new start value after it is decremented to „zero“, the start-up time of the counters with the programmed values is too long for some applications. If the counters are programmed in standby mode 2 and the PLLs are switched afterwards in operating mode, the counters are starting immediatly with the programmed values. Therefore following data transfer sequence is recommended: Table 3-2 Fast Wake Up Data Transfer Sequence Wireless Components Step Serial Data Transfer Sequence 1 Long Control Word: Asynchronous Mode, Standby2 2 R-Counter 3 A-/N-Counter 4 Long Control Word: Synchronous Mode, Operating Mode 3-9 Specification, August 1999 PMB 2347 preliminary Functional Description 7. Phase Detector Outputs RI IR (RI:R) RF1/2 IV CP (RF1:M) (RF2:M) P-Channel Tri-State N-Channel positive Polarity CP P-Channel Tri-State N-Channel negative Polarity LD FrequencyIV <IR IV lagging FrequencyIV >IR IV leading FrequencyIV = IR lock state The timing diagram is valid for PLL1 and PLL2. Wireless Components 3 - 10 Specification, August 1999 4 Applications Contents of this Chapter 4.1 Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 PMB 2347 preliminary Applications 4.1 Hint More Information about “Application” see in separate Document APPLICATION NOTE PMB 2347. Wireless Components 4-2 Specification, August 1999 5 Reference Contents of this Chapter 5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 Serial Control Data Format Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.3 Serial Control Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.4 Input Sensitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.5 Charge Pump Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.6 Threshold Voltages of Schmitt-Trigger Input . . . . . . . . . . . . . . . . . . 5-16 PMB 2347 preliminary Reference 5.1 Electrical Data 5.1.1 Absolute Maximum Ratings WARNING The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. Table 5-1 Absolute Maximum Ratings Parameter Symbol Limit Values min max Unit Supply Voltage VCC1/2 -0.3 5.5 V Input Voltage 9I -0.3 9&& +0.3 V Output Voltage 9O GND 9&& V Total power dissipation 3tot Ambient temperature 7A Storage temperature 7Stg Thermal Resistance ESD Integrity (according to MIL 883 Method 3015.7) except Pins Vpd1[2] and Vpd2[19] Wireless Components 300 mW -40 85 °C -50 125 °C 5thJA 170 K/W 9ESD 0.5 KV 5-2 Remarks in operation preliminary Specification, August 1999 PMB 2347 preliminary Reference 5.1.2 Operating Range Within the operational range the IC operates as described in the circuit description. The AC/DC characteristic limits are not guaranteed. Table 5-2 Operating Range, VCC1/2= 2.7V - 5.0V, TAMB=-40°C ... + 85°C typical Symbol Parameter Limit Values min Unit Item max Supply Voltage 9&&/2 2.7 5.0 V Input frequency RF ƒRF 250 2800 MHz Input frequency IF ƒIF 100 500 MHz Input reference frequency ƒRi 1 45 MHz CP-output current of PLL1 / ,CP1 / 4 +20% mA CP-output current of PLL2 / ,CP2 / 1 +20% mA CP-output voltages 9CP1/2 0.5 93'1/2 0.5 V Ambient temperature 7A -40 85 °C 5.1.3 Test Conditions 9&&1/2 = 3.6V Typical Supply Current ICC Table 5-3 Typical Supply Current ICC Parameter Symbol Limit Values min Supply Voltage 9&&/2 typ Unit Test Conditions V REXT = 12k Item max 3.6 Supply current: Note 1) PLL1 & PLL2 active ,CC1/2 -20% 8.0 +20% mA PLL1 active, PLL2 standby ,CC1/2 -20% 5.9 +20% mA PLL1 standby2, PLL2 active ,CC1/2 -20% 3.2 +20% mA PLL1 & PLL2 standby 2 ,CC1/2 120 µA PLL1 & PLL2 standby 1 ,CC1/2 <1 µA VCC1/2= 3.6V 1) ƒRF1 = 900MHz, VRF = 150mVrms, ƒRF2 = 420MHz, VRF2 = 150mVrms,ƒRI = 10MHz, VRI = 150mVrms, ICP1 = 4.0mA, ICP2 = 2.0mA, Iref = 100 µA Wireless Components 5-3 Specification, August 1999 PMB 2347 preliminary Reference 5.1.4 AC/DC Characteristics AC/DC characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production. Table 5-4 AC/DC Characteristics with VCC1/2=2.7 .. 5.0 V, Ambient temperature Tamb= -40°C to 85°C Symbol Limit Values min typ Unit Test Conditions L Item max Input Signals DA, CLK, EN (Schmitt-Trigger input stage) H-input voltage 9IH L-input voltage 0.7 9 CC 9CC V 9IL 0.3 9 CC V Input capacity &I 5 pF H-input current ,H 10 µA VI=VCC2=3.6V 2.3 L-input current ,L -10 µA VI=GND 2.4 9I 100 mVrms f= 4 - 45 MHz, VCC1=3.6V 2.10 V/µs VCC1=2.7 - 5.0 V Input Signal RI Input voltage 4 Slew rate Input capacity &I 3 pF H-input current ,H 30 µA VI=VCC1=3.6V L-input current 9I µA VI=GND mVrms f = 150-450 MHz 3.1 f = 450-2500 MHz 3.2 -30 2.13 Input Signals RF Input voltage 9I 3I Input voltage +6 9I 3I Input voltage -12 mVrms -20 +4 9I 3I dBm dBm mVrms -10 -2.5 f = 2500-2800 MHz dBm Input Signals IF Input voltage 9I 3I Input voltage +4 -25 -5 -15 5-4 4.1 f = 350 - 450 MHz 4.2 dBm mVrms -25 f = 100 - 350 MHz dBm mVrms 9I 3I Wireless Components -16 9I 3I Input voltage mVrms f = 450 - 600 MHz dBm Specification, August 1999 PMB 2347 preliminary Reference Table 5-4 AC/DC Characteristics with VCC1/2=2.7 .. 5.0 V, Ambient temperature Tamb= -40°C to 85°C (continued) Symbol Limit Values Unit min typ max Test Conditions Item VPD1=5.0V, VCP1=VPD1/2 IREF=100µA 5.1 Output Current ICP1 "1.2 mA" ,CP1 -20% 1.2 +20% mA "2.0 mA" ,CP1 -20% 2.0 +20% mA "2.8 mA" ,CP1 -20% 2.8 +20% mA "4.0 mA" ,CP1 -20% 4.0 +20% mA "Tristate" 5.2 5.3 5.4 *guaranteed by design /,CP1/ 0.1 10*) nA +20% mA 10*) nA 5.5 Output Current ICP2 "1.0 mA" ,CP2 "Tristate" /,CP2/ -20% 0.1 VPD2=3.6V, VCP1=VPD1/2 IREF=100µA *guaranteed by design Output Current Offset CP1 & CP2 CP Supply Voltage VPD1/2 2.7 3.6 5.0 V CP Current Offsett ,CP-OFF -4 0 +13 % VCP1/2 = VPD2/2 Magnitude Variation "+1.2 mA" ,CPMV 4 % "+2.0 mA" ,CPMV 4 % "+2.8 mA" ,CPMV 4 % "+4.0 mA" ,CPMV 4 % "-1.2 mA" ,CPMV 6 % "-2.0 mA" ,CPMV 6 % "-2.8 mA" ,CPMV 6 % 6 % "-4.0 mA" VPD1=5V, VCP1 = VPD1/2 IREF=100 µA 7.4 see ’Chargepump Specification’ for details on spurious suppression 7.8 Current Mismatch "1.2 mA" ,CPMM 0.7 % "2.0 mA" ,CPMM 1.3 % "2.8 mA" ,CPMM 1.8 % "4.0 mA" ,CPMM 1.5 % Wireless Components 5-5 VPD2=5V, VCP2 = VPD2/2 IREF=100 µA Specification, August 1999 PMB 2347 preliminary Reference Table 5-4 AC/DC Characteristics with VCC1/2=2.7 .. 5.0 V, Ambient temperature Tamb= -40°C to 85°C (continued) Symbol Limit Values min typ Unit Test Conditions L Item max Output Rext VRext 9Rext 1.2 V VCC2 = 3.6V, Rext=12k IRext ,Rext 100 µA VCC2 = 3.6V, Rext=12k 0.4 V VCC1 = 2.7 - 3.6V, IOL = 0.3 mA 10 ns VCC1 = 3.6V, CI = 10pF 10.1 Output Signal BSW at BSW/LD-Pin (n-channel open drain) L-output voltage 9OL Fall time WF 3 ■ This value is only guaranteed in lab. Wireless Components 5-6 Specification, August 1999 PMB 2347 preliminary Reference 5.2 Serial Control Data Format Timing WR tWHCL ≈ 9IH WF CLK 9IL tWLCL ≈ 9IL ≈ DA WDS 9IH WCLE 9IH 9IL ≈ EN WECL WWHEN ≈ ≈ 9IH PORT 9IL WDEP Table 5-5 Parameter Symbol Limit Values min. Clock frequency max. 15 ƒCL Unit MHz H-pulsewidth (CLK) WWHCL 30 ns L-pulsewidth (CLK) WWLCL 30 ns Data setup WDS 20 ns Setup time Clock-Enable WCLE 20 ns Setup time Enable-Clock WECL 20 ns H-pulsewidth (Enable) WWHEN 60 ns Rise, fall time tR, tR 10 µs Propagation delay time EN-PORT WDEP 1 µs Wireless Components 5-7 Specification, August 1999 PMB 2347 preliminary Reference 5.3 Serial Control Data Formats Table 5-6 Address of Data Formats Address Data Format Addressed PLL a2 a1 a0 0 0 0 Short Control Data Format PLL1 (RF) 0 1 0 Long Control Data Format PLL1 (RF) 1 0 0 A-/N-Counter PLL1 (RF) 1 1 0 R-Counter PLL1 (RF) 0 0 1 Short Control Data Format PLL2 (IF) 0 1 1 Long Control Data Format PLL2 (IF) 1 0 1 A-/N-Counter PLL2 (IF) 1 1 1 R-Counter PLL2 (IF) In general each PLL can independently be addressed without affecting the other PLL (See also Test Modes). 127(: MSB of all serial data is shifted first Table 5-7 Short Control Data Formats PLL 1 Bit PLL 2 Bit Function Bit Bit Function LSB 0 0 a0 Address LSB 0 1 a0 Address 1 0 a1 Address 1 0 a1 Address 2 0 a2 Address 2 0 a2 Address 3 c0 LD InActive 3 c0 reserved 4 c1 CP current 2 4 c1 reserved 5 c2 CP current 1 5 c2 CP current 6 MSB c3 PLLSel 6 MSB c3 reserved Table 5-8 Long Control Data Formats PLL 1 Bit PLL 2 Bit Function Bit Bit Function LSB 0 0 a0 Address LSB 0 1 a0 Address 1 1 a1 Address 1 1 a1 Address 2 0 a2 Address 2 0 a2 Address 3 c0 LD inactive 3 c0 reserved 4 c1 CP current 2 4 c1 reserved 5 c2 CP current 1 5 c2 CP current 1 6 c3 PLLSel 6 c3 Data-Reg Select 7 c4 PSC Div. Ratio 7 c4 PSC Div. Ratio Wireless Components 5-8 Specification, August 1999 PMB 2347 preliminary Reference Table 5-9 Long Control Data Formats (continued) PLL 2 PLL 1 Bit Bit Function Bit Bit Function 8 c5 reserved 8 c5 reserved 9 c6 CPP width 2 9 c6 CPP width 2 10 c7 CPP width 1 10 c7 CPP width 1 11 c8 standby 2 11 c8 standby 2 12 c9 standby 1 12 c9 standby 1 13 c10 CP polarity 13 c10 CP polarity 14 c11 Mode 2 14 c11 reserved 15 c12 Mode 1 15 c12 reserved 16 MSB c13 Sync/Async Mode 16 MSB c13 reserved Table 5-10 A/N-counter Data Formats PLL 1 Bit PLL 2 Bit Function Bit Bit Function LSB 0 0 a0 Address LSB 0 1 a0 Address 1 1 a1 Address 1 0 a1 Address 2 0 a2 Address 2 1 a2 Address 3 LSB LSB n0 n0 3 4 n1 4 n1 5 n2 5 n2 6 n3 6 n3 7 n4 7 n4 8 n5 8 n5 9 n6 9 n6 10 n7 10 n7 11 n8 11 n8 12 n9 12 n9 13 n10 13 n10 14 n11 14 n11 N1-Counter n12 15 16 MSB n13 16 MSB n13 17 LSB ac0 17 LSB ac0 18 ac1 18 ac1 19 ac2 19 ac2 20 ac3 21 ac4 15 22 MSB Wireless Components A1-Counter 20 N2-Counter n12 MSB A2-Counter ac3 ac5 5-9 Specification, August 1999 PMB 2347 preliminary Reference Table 5-11 R-counter Data Formats PLL 2 PLL 1 Bit Function Bit a0 Address LSB 0 1 a1 Address 1 2 1 a2 Address 3 LSB r0 4 r1 4 r1 5 r2 5 r2 6 r3 6 r3 7 r4 7 r4 8 r5 8 r5 9 r6 9 r6 10 r7 10 r7 11 r8 11 r8 12 r9 12 r9 13 r10 13 r10 14 r11 14 r11 15 r12 15 r12 r13 16 MSB Bit LSB 0 0 1 MSB 16 MSB R1-Counter Bit Function 1 a0 Address 1 a1 Address 2 1 a2 Address 3 LSB r0 MSB R2-Counter r13 Table 5-12 Programming of Operation and Test Modes c12 Mode 1 c11 Mode 2 c3 PLLSel Functional Mode Affected Output: Pin 11 = BSW/LD 0 0 0 Test 1 fvn1 (PLL1) 1 0 0 Test 2 frn1 (PLL1) 0 1 0 reserved frn1 (PLL1) 1 1 0 NORMAL OPERATION, LD of PLL1 active Lock Detect PLL1 0 0 1 Test 3 fvn2 (PLL2) 1 0 1 Test 4 frn2 (PLL2) 0 1 1 reserved frn2 (PLL2) 1 1 1 NORMAL OPERATION, LD of PLL2 active Lock Detect PLL2 Table 5-13 Programming of CP Current of PLL1 c2 CP current 1 c1 Mode 2 CP Current [mA] 0 0 1.2 mA 1 0 2.0 mA 0 1 2.8 mA 1 1 4.0 mA Wireless Components 5 - 10 Remark with 100µA reference current Specification, August 1999 PMB 2347 preliminary Reference Table 5-14 Programming of CP Current of PLL2 c2 CP current 1 CP Current [mA] 0 Tristate 1 1.0 mA Remark with 100µA reference current Table 5-15 Programming of Charge Pump Pulse Width of both PLLs c7 CPP width 1 c6 CPP width 2 Pulse Width [ns] typ. Remark 0 0 1.6 ns not recommended for PLL2 1 0 6.0 ns 0 1 9.0 ns 1 1 13.0 ns Table 5-16 Standby of Power Down Programming of both PLLs Control Bits Mode c9 standby 1 c8 standby 2 0 0 1 Affected Output Pins Z: High Impedance (Tristate) Pin 11 LD/fo Pin 3 CP1 Pin 18 CP2 standby1 off Z Z 0 standby2 off Z Z 0 1 standby1 off Z Z 1 1 Operation Mode active active active Table 5-17 Programming of Synchronous/Asynchronous Mode of PLL1 c13 Sync/Async Synchronous/Asynchronous Mode 0 Asynchronous Mode of PLL 1 1 Synchronous Mode of PLL 1 Table 5-18 Programming of PD Polarity of both PLLs Control Bit PD Polarity c10 PD Polarity 0 negative Polarity 1 positive Polarity Wireless Components 5 - 11 Specification, August 1999 PMB 2347 preliminary Reference Table 5-19 Programming of Prescaler Divide Ratio of both PLLs Prescaler Divide Ratio Control Bit c4 PSC Div. Ratio 0 PLL1: 32/33 PLL2: 8/9 1 PLL1: 64/65 PLL2: 16/17 Table 5-20 Programming of PLL Select PLL Select Control Bit c3 of PLL1 0 PLL1 (RF) 1 PLL2 (IF) Table 5-21 Programming of Data Register Select Control Bits IF Data Register Select c3 of PLL2 0 Data Register 1 1 Data Register 2 Wireless Components 5 - 12 Specification, August 1999 PMB 2347 preliminary Reference 5.4 Input Sensitives The following sections show the typical performance at +25°C. 1. Typical RF Sensitivity: The PLL setup is: Psc:64/65. N:3, A:0, IF-PLL is in standby mode. 9&& is 2.7 V. The testport open-drain pin is pulled to 2.0 V over 5k1. The cut-off frequency can be increased to typ. >3.45GHz by using a 9&& of 5.0 V 5 0 -5 -10 @ P % G > U H Z R 3 W X S Q , -15 -20 -25 -30 -35 -40 -45 50 300 550 800 10 50 130 0 1 550 1800 2 050 230 0 25 50 280 0 305 0 3300 , Q S X W )U H T X H Q F \ > 0 +] @ BA SELINE TOPLINE SPEC-5.98 2. Typical IF Sensitivity: The PLL setup is: Psc:16/17. N:3, A:1,RF-PLL is in standby mode. 9&& is 2.7 V. The testport open-drain pin is pulled to 2.0 V over 5k1. 5 0 -5 -10 @ P % G > U H Z R 3 W X S Q , -15 -20 -25 -30 -35 -40 -45 50 100 150 200 300 350 400 450 500 550 600 650 700 750 800 850 ,QSXW)UHTXHQF\>0+]@ . Wireless Components 250 BASELINE 5 - 13 TOPLINE SPEC-5.98 Specification, August 1999 PMB 2347 preliminary Reference 3. Typical Ri Sensitivity: The PLL setup is: R:3; RF-PLL is in standby mode. 9&& is 3.6V. The testport open-drain pin is pulled to 2.0 V over 5k1. 5 0 -5 -10 @ P % G > U H Z R 3 W X S Q , -15 -20 -25 -30 -35 -40 -45 1 6 11 16 21 26 31 36 41 46 , Q S X W )U H T X H Q F \ > 0 +] @ BA S +25’C Wireless Components 5 - 14 SPEC- 5.98 Specification, August 1999 PMB 2347 preliminary Reference 5.5 Charge Pump Currents Isnkmax Isnktyp Isnkmin ∆Vsrc VCP VPD/2 ∆Vsnk Isrcmin Isrctyp Isrcmax Figure 5-1 Definition of Charge Pump Currents Terms and Abbreviations: VPD ∆Vsrc/snk Isnkmax Isrcmax Isnktyp Isrctyp Isnkmin Isrcmin Supply Voltage of Charge Pump Offset Voltage from GND or VPD Maximum Sink Current @ VPD-∆VSRC Maximum Source Current @ GND+∆VSNK Typical Sink Current @ VPD/2 Typical Source Current @ VPD/2 Minimum Sink Current @ GND+∆VSNK Minimum Source Current @ VPD-∆VSRC Specification of Charge Pump Characteristics: Charge Pump Output Magnitude Variation CPMV: Isnk – Isnk max min --------------------------------------------------2 ---------------------------------------------------- ⋅ 100% Isnk + Isnk max min --------------------------------------------------2 Isrc – Isrc max min -----------------------------------------------2 ------------------------------------------------- ⋅ 100% Isrc + Isrc max min ------------------------------------------------2 Charge Pump Current Mismatch CPCM: Isnk – Isrc typ typ --------------------------------------------2 ---------------------------------------------- ⋅ 100% Isnk + Isrc typ typ ---------------------------------------------2 Spurious Suppression: Presuming a standard GSM-application - RF: 900MHz, PD frequency: 200kHz, Vcc: 2.7V, TA.: -40...+85’C - for spurious suppression better than 70dB, it is recommendet that ∆VPD should be within ∆VSNK and Vcc − ∆VSNK Wireless Components 5 - 15 Specification, August 1999 PMB 2347 preliminary Reference 5.6 Threshold Voltages of Schmitt-Trigger Input 7\SLFDO9LQ7KUHVKROGVRI:%XV 1,32 1,22 1,12 typ. High min. typ. Low max. 1,02 0,92 0,82 2,5 3 3,5 4 4,5 5 9&& Wireless Components 5 - 16 Specification, August 1999