INFINEON TDA5250D2

Wireless Components
ASK/FSK 868MHz Wireless Transceiver
TDA 5250 D2
Version 1.6
Specification July 2002
confidential
preliminary
confidential
Revision History
Current Version: Preliminary Specification V1.6 as of 09.07.02 describing design step D2
Previous Version: V1.5
Page
(in previous
Version)
Page
(in current
Version)
Subjects (major changes since last revision)
3-6, 3-23
3-6, 3-23
Data pin (Pin 28) tied to GND in powerdown mode
3-24 to 3-26
3-24 to 3-26
Clock output setup time
4-42
4-43
Section „Datarates and Sensitivity“ added
4-43
4-44
Explanation added
5-3 to 5-4
5-3 to 5-4
Clock output setup time
5-10
5-10
Clock DIV line
5-12
5-12
Bill of Material completed
ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S, ELIC®, FALC®54, FALC®56, FALC®-E1, FALC®-LH, IDEC®, IOM®,
IOM®-1, IOM®-2, IPAT®-2, ISAC®-P, ISAC®-S, ISAC®-S TE, ISAC®-P TE, ITAC®, IWE®, MUSAC®-A, OCTAT®-P, QUAT®-S, SICAT®, SICOFI®, SICOFI®2, SICOFI®-4, SICOFI®-4µC, SLICOFI® are registered trademarks of Infineon Technologies AG.
ACE™, ASM™, ASP™, POTSWIRE™, QuadFALC™, SCOUT™ are trademarks of Infineon Technologies AG.
Edition 07.02
Published by Infineon Technologies AG,
Balanstraße 73,
81541 München
© Infineon Technologies AG July 2002.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest
Infineon Technologies Office.
Infineon Technologies AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing
material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the
Infineon Technologies AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect its safety or effectiveness of that device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they
fail, it is reasonable to assume that the health of the user may be endangered.
TDA 5250 D2
preliminary
Product Info
confidential
Product Info
General Description
Features
The IC is a low power consumption Package
single chip FSK/ASK Transceiver for
half duplex low datarate communication in the 868-870MHz band. The IC
offers a very high level of integration
and needs only a few external components. It contains a highly efficient
power amplifier, a low noise amplifier
(LNA) with AGC, a double balanced
mixer, a complex direct conversion
stage, I/Q limiters with RSSI generation, an FSK demodulator, a fully integrated VCO and PLL synthesizer, a
tuneable crystal oscillator, an onboard
data filter, a data comparator (slicer),
positive and negative peak detectors,
a data rate detection circuit and a 2/3wire bus interface. Additionally there is
a power down feature to save battery
power.
■
Low supply current (Is = 9mA typ.
receive, Is = 12mA typ. transmit
mode)
■
On-chip low pass channel select filter and data filter with tuneable
bandwidth
■
Supply voltage range 2.1 - 5.5V
■
■
Power down mode with very low
supply current consumption
Data slicer with self-adjusting
threshold and 2 peak detectors
■
FSK and ASK modulation and
demodulation capability
FSK sensitivity <-109dBm, ASK
sensitivity < –109dBm
■
Transmit power up to +13dBm
■
Datarates up to 64kBit/s
■
Self-polling logic with ultra fast data
rate detection
■
Alarm Systems
■
Telemetry Systems
■
Electronic Metering
■
Home Automation Systems
■
■
Applications
Ordering Information
Fully integrated VCO and PLL
synthesizer and loop filter on-chip
with on chip crystal oscillator tuning
■
I2C/3-wire µController Interface
■
Low Bitrate Communication
Systems
■
Keyless Entry Systems
■
Remote Control Systems
Type
Ordering Code
TDA 5250
Wireless Components
Package
P-TSSOP-38-1
Product Info
Specification, July 2002
1
Table of Contents
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
2.4
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
3.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
3.2
Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3.3
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
3.4
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
3.4.1 Power Amplifier (PA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
3.4.2 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
3.4.3 Downconverter 1st Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
3.4.4 Downconverter 2nd I/Q Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
3.4.5 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
3.4.6 I/Q Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
3.4.7 I/Q Limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
3.4.8 FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
3.4.9 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
3.4.10 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
3.4.11 Peak Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
3.4.12 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
3.4.13 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
3.4.14 Timing and Data Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
3.4.15 Bus Interface and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
3.4.16 Wakeup Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
3.4.17 Data Valid Detection, Data Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
3.4.18 Sequence Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
3.4.19 Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
3.4.20 RSSI and Supply Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
4.1
LNA and PA Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
4.1.1 RX/TX Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
4.1.2 Power-Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
4.2
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
4.2.1 Synthesizer Frequency setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
4.2.2 Transmit/Receive ASK/FSK Frequency Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
4.2.3 Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
4.2.4 Calculation of the external capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
4.2.5 FSK-switch modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
4.2.6 Finetuning and FSK modulation relevant registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
4.2.7 Chip and System Tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
IQ-Filter 24
Data Filter 25
4.5
Limiter and RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
4.6
Data Slicer - Slicing Level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
4.6.1 RC Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
4.6.2 Peak Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
4.6.3 Peak Detector - Analog output signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
4.6.4 Peak Detector – Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
4.7
Data Valid Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
4.7.1 Frequency Window for Data Rate Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
4.7.2 RSSI threshold voltage - RF input power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
4.8
Calculation of ON_TIME and OFF_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
4.9
Example for Self Polling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
4.10
Sensitivity Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
4.10.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
4.10.2 Sensitivity depending on the ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
4.10.3 BER performance depending on Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
4.10.4 Datarates and Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
4.10.5 Sensitivity at Frequency Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
4.11
Default Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
5 TDA 5250 D2 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
5.1
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
5.1.4 Digital Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
5.2
Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
5.3
Test Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
5.4
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
2
Product Description
Contents of this Chapter
2.1
2.2
2.3
2.4
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
TDA 5250 D2
preliminary
Product Description
confidential
2.1 Overview
The IC is a low power consumption single chip FSK/ASK Transceiver for the frequency band 868-870 MHz. The IC combines a very high level of integration
and minimum external part count. The device contains a low noise amplifier
(LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesizer, a
crystal oscillator with FSK modulator, a limiter with RSSI generator, an FSK
demodulator, a data filter, a data comparator (slicer), a positive and a negative
data peak detector, a highly efficient power amplifier and a complex digital timing and control unit with I2C/3-wire microcontroller interface. Additionally there
is a power down feature to save battery power.
The transmit section uses direct ASK modulation by switching the power amplifier, and crystal oscillator detuning for FSK modulation. The necessary detuning
load capacitors are external. The capacitors for fine tuning are integrated. The
receive section is using a novel single-conversion/direct-conversion scheme
that is combining the advantages of both receive topologies. The IF is contained
on the chip, no RF channel filters are necessary as the channel filter is also on
the chip.
The self-polling logic can be used to let the device operate autonomously as a
master for a decoding microcontroller.
2.2 Applications
Wireless Components
■
Low Bitrate Communication Systems
■
Keyless Entry Systems
■
Remote Control Systems
■
Alarm Systems
■
Telemetry Systems
■
Electronic Metering
■
Home Automation Systems
2-2
Specification, July 2002
TDA 5250 D2
preliminary
Product Description
confidential
2.3 Features
Wireless Components
■
Low supply current (Is = 9 mA typ. receive, Is = 12mA typ. transmit mode,
both at 3 V supply voltage, 25°C)
■
Supply voltage range 2.1 V to 5.5 V
■
Operating temperature range -40°C to +85°C
■
Power down mode with very low supply current consumption
■
FSK and ASK modulation and demodulation capability without external circuitry changes, FM demodulation capability
■
Fully integrated VCO and PLL synthesizer and loop filter on-chip with onchip crystal oscillator tuning, therefore no additional external components
necessary
■
Differential receive signal path completely on-chip, therefore no external filters are necessary
■
On-chip low pass channel select and data filter with tuneable bandwith
■
Data slicer with self-adjusting threshold and 2 peak detectors
■
Self-polling logic with adjustable duty cycle and ultrafast data rate detection
and timer mode providing periodical interrupt
■
FSK and ASK sensitivity < -109 dBm
■
Adjustable LNA gain
■
Digital RSSI and Battery Voltage Readout
■
Provides Clock Out Pin for external microcontroller
■
Transmit power up to +13 dBm in 50Ω=load at 5V supply voltage
■
Maximum datarate up to 64 kBaud
■
I2C/3-wire microcontroller interface, working at max. 400kbit/s
■
meets the ETSI EN300 220 regulation and CEPT ERC 7003 recommendation
2-3
Specification, July 2002
TDA 5250 D2
preliminary
Product Description
confidential
2.4 Package Outline
P-TSSOP-38-1.EPS
Figure 2-1
Wireless Components
P-TSSOP-38-1 package outlines
2-4
Specification, July 2002
3
Functional Description
Contents of this Chapter
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
3.4.10
3.4.11
3.4.12
3.4.13
3.4.14
3.4.15
3.4.16
3.4.17
3.4.18
3.4.19
3.4.20
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Power Amplifier (PA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Downconverter 1st Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Downconverter 2nd I/Q Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
I/Q Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
I/Q Limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Peak Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Timing and Data Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Bus Interface and Register Definition . . . . . . . . . . . . . . . . . . . . . . . 3-14
Wakeup Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Data Valid Detection, Data Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Sequence Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
Clock Divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
RSSI and Supply Voltage Measurement . . . . . . . . . . . . . . . . . . . . 3-27
TDA 5250 D2
preliminary
Functional Description
confidential
3.1 Pin Configuration
VCC
1
38
CI1
BUSMODE
2
37
CI1x
LF
____
ASKFSK
__
RxTx
3
36
CQ1
4
35
CQ1x
5
34
CI2
LNI
6
33
CI2x
LNIx
7
32
CQ2
GND1
8
31
CQ2x
GNDPA
9
30
GND
PA
10
29
RSSI
VCC1
11
28
PDN
12
27
DATA
___
PWDDD
PDP
13
26
SLC
14
25
VDD
15
24
CLKDIV
______
RESET
___
EN
BUSDATA
16
23
XGND
BUSCLK
17
22
XSWA
VSS
18
21
XIN
XOUT
19
20
XSWF
TDA5250
5250D1_pin_conf.wmf
Figure 3-1
Wireless Components
Pin configuration
3-2
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
3.2 Pin Definition and Function
Table 3-1 Pin Definition and Function
Pin No.
Symbol
1
VCC
Equivalent I/O-Schematic
Function
Analog supply (antiparallel diodes
between VCC, VCC1, VDD)
1
11
15
2
BUSMODE
Bus mode selection (I²C/3 wire
bus mode selection)
350
2
3
LF
Loop filter and VCO control voltage
200
3
4
ASKFSK
ASK/FSK- mode switch input
350
4
5
RXTX
RX/TX-mode switch input/output
350
5
TX
6
LNI
RF input to differential Low Noise
Amplifier (LNA)
5k
6
1.1V 5k
180
180
PWDN
Wireless Components
7
PWDN
3-3
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
7
LNIx
8
Gnd1
Complementary RF input to differential LNA
see Pin 6
Ground return for LNA and Power
Amplifier (PA) driver stage
30
18
8
9
9
GNDPA
10
PA
Ground return for PA output stage
see Pin 8
PA output stage
10 Ω
10
9
GndPA
11
VCC1
12
PDN
Supply for LNA and PA
see Pin 1
Output of the negative peak
detector
50k
PWDN
350
50k
3k
12
13
PDP
Output of the positive peakdetector
50k
350
50k
3k
13
PWDN
14
SLC
Slicer level for the data slicer
1.2uA
350
50k
50k
50k
50k
50k
50k
14
1.2uA
15
VDD
16
BUSDATA
see Pin 1
Digital supply
Bus data in/output
15k
350
16
Wireless Components
3-4
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
17
BUSCLK
Bus clock input
350
17
18
VSS
19
XOUT
Ground for digital section
see Pin 8
Vcc
Crystal oscillator output, can also
be used as external reference frequency input.
4k
Vcc-860mV
19
150µA
20
XSWF
FSK modulation switch
21
125fF .....
4pF
250fF .....
8pF
20
23
21
XIN
22
XSWA
see Pin 20
22
ASK modulation/FSK center frequency switch
20
23
23
XGND
24
EN
see Pin 22
Crystal oscillator ground return
3-wire bus enable input
350
24
25
RESET
Reset of the entire system (to
default values), active low
110k
350
25
10p
Wireless Components
3-5
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
26
CLKDIV
Clock output
350
26
27
PWDDD
Power Down input (active high),
data detect output (active low)
30k
350
27
28
DATA
TX Data input, RX data output (RX
powerdown: pin 28 @ GND)
350
28
29
RSSI
RSSI output
S&H
350
29
16p
37k
30
GND
31
CQ2x
see Pin 8
Analog ground
Pin for external Capacitor
Q-channel, stage 2
Stage1:Vcc-630mV
Stage2: Vcc-560mV
31
32
CQ2
II
Q-channel, stage 2
33
CI2x
II
I-channel, stage 2
34
CI2
II
I-channel, stage 2
35
CQ1x
II
Q-channel, stage 1
36
CQ1
II
Q-channel, stage 1
37
CI1x
II
I-channel, stage 1
38
CI1
II
I-channel, stage 1
Wireless Components
3-6
Specification, July 2002
Figure 3-2
Wireless Components
3-7
ANT
PA
10
(LNA/PA)
7
(analog)
fRX= 1157.73MHz
fTX= 868.3MHz
VCO
:4
90°
0°
f = 289.433MHz
LF
3
LOOP
FILTER
MIXER
TX/RX
:12/16
Channel
Filter
Q
I
PHASE
DET.
Charge P.
TX/RX
RSSI
ASK
6-bit
SAR-ADC
XIN
21
XSWF
20
-Peak
Det
+Peak
Det
100k
Data
FILTER
XSWA
22
CRYSTAL Osc, FSKMod, Finetuning
ASK/FSK
fQ= 18.0896MHz
XOUT
19
ASK DATA
LIMITER
QUADRI
CORRELATOR
FSK
XGND
23
SLICER
FSK DATA
CLK
Bandgap
Reference
100k
100k
ASK/FSK
-
+
24
2
Gnd1
8
Gnd
30
(analog)
WAKEUP
LOGIC
CONTROLLER
INTERFACE
17
(LNA/PA)
16
Vss
18
(digital)
4
5
27
26
28
29
25
12
13
VCC
Data (RX/TX)
RSSI
RESET
PDN
PDP
ASKFSK
RXTX
PWDDD
CLKDIV
confidential
GndPA
9
PA
high/low
Gain
LP
FILTER
fIF= 289.433MHz
CQ1x
CQ1
CI1x
CI1
LIMITER
35
36
37
38
MIXER
(digital)
LNA
Channel
Filter
CQ2x
CQ2
CI2x
CI2
LNIx
6
MIXER
31
32
33
34
LNI
fRF= 868.3MHz
SLC
14
BUSDATA
single ended to
differential conv.
ANT
15
VDD
BUSCLK
1
VCC
BUSMODE
__
EN
11
VCC1
TDA 5250 D2
preliminary
Functional Description
3.3 Functional Block Diagram
TDA5250D1_blockdiagram_aktuell.wmf
Main Block Diagram
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
3.4 Functional Blocks
3.4.1
Power Amplifier (PA)
The power amplifier is operating in C-mode. It can be used in either high or low
power mode. In high-power mode the transmit power is approximately +13dBm
into 50 Ohm at 5V and +4dBm at 2.1V supply voltage. In low power mode the
transmit power is approximately -7dBm at 5V and -32dBm at 2.1V supply
voltage using the same matching network. The transmit power is controlled by
the D0-bit of the CONFIG register (subaddress 00H) as shown in the following
Table 3-2. The default output power mode is high power mode.
Table 3-2 Sub Address 00H: CONFIG
Bit
D0
Function
PA_PWR
Description
Default
0= low TX Power, 1= high TX Power
1
In case of ASK modulation the power amplifier is turned fully on and off by the
transmit baseband data, i.e. 100% On-Off-Keying.
3.4.2
Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB and
symmetrical inputs. It is possible to reduce the gain to 0 dB via logic.
Table 3-3 Sub Address 00H: CONFIG
Bit
D4
3.4.3
Function
LNA_GAIN
Description
0= low Gain, 1= high Gain
Default
1
Downconverter 1st Mixer
The Double Balanced 1st Mixer converts the input frequency (RF) in the range
of 868-870 MHz to down to the intermediate frequency (IF) at approximately
290MHz. The local oscillator frequency is generated by the PLL synthesizer that
is fully implemented on-chip as described in Section 3.4.5. This local oscillator
operates at approximately 1157MHz in receive mode providing the above
mentioned IF frequency of 290MHz. The mixer is followed by a low pass filter
with a corner frequency of approximately 350MHz in order to prevent RF and
LO signals from appearing the 290MHz IF.
Wireless Components
3-8
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
3.4.4
Downconverter 2nd I/Q Mixers
The Low pass filter is followed by 2 mixers (inphase I and quadrature Q) that
convert the 289MHz IF signal down to zero-IF. These two mixers are driven by
a signal that is generated by dividing the local oscillator signal by 4, thus
equalling the IF frequency.
3.4.5
PLL Synthesizer
The Phase Locked Loop synthesizer consists of two VCOs (i.e. transmit and
receive VCO), a divider by 4, an asynchronous divider chain with selectable
overall division ratio, a phase detector with charge pump and a loop filter and is
fully implemented on-chip. The VCOs are including spiral inductors and
varactor diodes. The center frequency of the transmit VCO is 868MHz, the
center frequency of the receive VCO is 1156MHz.
Generally in receive mode the relationship between local oscillator frequency
fosc, the receive RF frequency fRF and the IF frequency fIF and thus the
frequency that is applied to the I/Q Mixers is given in the following formula:
[3 – 1]
fosc = 4/3 fRF = 4 fIF
The VCO signal is applied to a divider by 4 which is producing approximately
289MHz signals in quadrature. The overall division ratio of the divider chain
following the divider by 4 is 12 in transmit mode and 16 in receive mode as the
nominal crystal oscillator frequency is 18.083MHz. The division ratio is
controlled by the RxTx pin (pin 5) and the D10 bit in the CONFIG register.
3.4.6
I/Q Filters
The I/Q IF to zero-IF mixers are followed by baseband 6th order low pass filters
that are used for RF-channel filtering.
OP
INTERNAL BUS
iq_filter.wmf
Figure 3-3
Wireless Components
One I/Q Filter stage
3-9
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
The bandwidth of the filters is controlled by the values set in the filter-register.
It can be adjusted between 50 and 350kHz in 50kHz steps via the bits D1 to D3
of the LPF register (subaddress 03H).
3.4.7
I/Q Limiters
The I/Q Limiters are DC coupled multistage amplifiers with offset-compensating
feedback circuit and an overall gain of approximately 80dB each in the
frequency range of 100Hz up to 350kHz. Receive Signal Strength Indicator
(RSSI) generators are included in both limiters which produce DC voltages that
are directly proportional to the input signal level in the respective channels. The
resulting I- and Q-channel RSSI-signals are summed to the nominal RSSI
signal.
3.4.8
FSK Demodulator
The output differential signals of the I/Q limiters are fed to a quadrature
correlator circuit that is used to demodulate frequency shift keyed (FSK)
signals. The demodulator gain is 2.4mV/kHz, the maximum frequency deviation
is ±300kHz as shown in Figure 3-4 below.
The demodulated signal is applied to the ASK/FSK mode switch which is
connected to the input of the data filter. The switch can be controlled by the
ASKFSK pin (pin 4) and via the D11 bit in the CONFIG register.
1,6
1,5
1,4
1,3
U /V
1,2
1,1
1
0,9
0,8
0,7
0,6
0,5
-350 -300 -250 -200 -150 -100 -50
0
50
100 150 200 250 300 350
f /kHz
Qaudricorrelator.wmf
Figure 3-4
Wireless Components
Quadricorrelator Demodulation Characteristic
3 - 10
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
3.4.9
Data Filter
The 2-pole data filter has a Sallen-Key architecture and is implemented fully onchip. The bandwidth can be adjusted between approximately 5kHz and 102kHz
via the bits D4 to D7 of the LPF register as shown in Table 4-10.
ASK / FSK
OTA
INTERNAL BUS
data_filter.wmf
Figure 3-5
3.4.10
Data Filter architecture
Data Slicer
The data slicer is a fast comparator with a bandwidth of 100kHz. The selfadjusting threshold is generated by a RC-network (LPF) or by use of one or both
peak detectors depending on the baseband coding scheme as described in
Section 4.6. This can be controlled by the D15 bit of the CONFIG register as
shown in the following table.
Table 3-4 Sub Address 00H: CONFIG
Bit
D15
3.4.11
Function
SLICER
Description
Default
0= Lowpass Filter, 1= Peak Detector
0
Peak Detectors
Two separate Peak Detectors are available. They are generating DC voltages
in a fast-attack and slow-release manner that are proportional to the positive
and negative peak voltages appearing in the data signal. These voltages may
be used to generate a threshold voltage for non-Manchester encoded signals,
for example. The time-constant of the fast-attack/slow-release action is
determined by external RC networks.
Wireless Components
3 - 11
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
3.4.12
Crystal Oscillator
The reference oscillator is an NIC oscillator type (Negative Impedance
Converter) with a crystal operating in serial resonance. The nominal operating
frequency of 18.083MHz and the frequencies for FSK modulation can be
adjusted via 3 external capacitors. Via microcontroller and bus interface the
chip-internal capacitors can be used for finetuning of the nominal and the FSK
modulation frequencies. This finetuning of the crystal oscillator allows to
eliminate frequency errors due to crystal or component tolerances.
3.4.13
Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable 1.2V reference
voltage for the device. A power down mode is available to switch off all
subcircuits that are controlled by the bidirectional Powerdown&DataDetect
PwdDD pin (pin 27) as shown in the following table. The supply current in this
mode is typically 100nA.
Table 3-5 PwdDD Pin Operating States
Wireless Components
PwdDD
Operating State
VDD
Ground/VSS
Powerdown Mode
Device On
3 - 12
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
3.4.14
Timing and Data Control Unit
BusMode
EN
BusCLK
BusData
The timing and data control unit contains a wake-up logic unit, an I2C/3-wire
microcontroller interface, a “data valid” detection unit and a set of configuration
registers as shown in the subsequent figure.
REGISTERS
I2C / 3Wire
INTERFACE
INTERNAL BUS
DATA VALID
DETECTOR
RSSI
6 B it
ADC
WAKEUP
LOGIC
A M P L ITU D E
th re s h o ld TH 3
RX DATA
FSK DATA
ASK DATA
BLOCK ENABLE
32kHz
RC-Osz.
DATA
VALID
FREQUENCY
window
TH1<TGATE<TH2
ENABLE
RF - BLOCK
18 MHz
XTAL-Osz.
CONTROL
LOGIC
CLKDiv
PwdDD
Data
ASK / FSK
AskFsk
RX / TX
POWER ON
SEQUENCER
RxTx
Reset
logic.wmf
Figure 3-6
Timing and Data Control Unit
The I2C / 3-wire Bus Interface gives an external microcontroller full control over
important system parameters at any time.
It is possible to set the device in three different modes: Slave Mode, Self Polling
Mode and Timer Mode. This is done by a state machine which is implemented
in the WAKEUP LOGIC unit. A detailed description is given in Section 3.4.16.
The DATA VALID DETECTOR contains a frequency window counter and an
RSSI threshold comparator. The window counter uses the incoming data signal
from the data slicer as the gating signal and the crystal oscillator frequency as
the timebase to determine the actual datarate. The result is compared with the
expected datarate.
The threshold comparator compares the actual RSSI level with the expected
RSSI level.
If both conditions are true the PwdDD pin is set to LOW in self polling mode as
you can see in Section 3.4.1.6. This signal can be used as an interrupt for an
external µP. Because the PwdDD pin is bidirectional and open drain driven by
an internal pull-up resistor it is possible to apply an external LOW thus enabling
the device.
Wireless Components
3 - 13
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
3.4.15
Bus Interface and Register Definition
The TDA5250 supports the I2C bus protocol (2 wire) and a 3-wire bus protocol.
Operation is selectable by the BusMode pin (pin 2) as shown in the following
table. All bus pins (BusData, BusCLK, EN, BusMode) have a Schmitt-triggered
input stage. The BusData pin is bidirectional where the output is open drain
driven.
Table 3-6 Bus Interface Format
BusMode
Function
2C
I Mode
3-wire Mode
Low
High
EN
High= inactive,
Low= active
BusCLK
BusData
Clock input
Data in/out
BusData
17
EN
24
FRONTEND
16
BusCLK
I2C / 3-wire
INTERFACE
INTERNAL BUS
BusMode
2
11100000
CHIP ADDRESS
i2c_3w_bus.wmf
Figure 3-7
Bus Interface
Note: The Interface is able to access the internal registers at any time, even in
POWER DOWN mode. There is no internal clock necessary for Interface
operation.
I2C Bus Mode
In this mode the BusMode pin (pin 2) = LOW and the EN pin (pin 24) = LOW.
Data Transition:
Data transition on the pin BusData can only occur when BusCLK is LOW.
BusData transitions while BusCLK is HIGH will be interpreted as start or stop
condition.
Wireless Components
3 - 14
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
Start Condition (STA):
A start condition is defined by a HIGH to LOW transition of the BusData line
while BusCLK is HIGH. This start condition must precede any command and
initiate a data transfer onto the bus.
Stop Condition (STO):
A stop condition is defined by a LOW to HIGH transition of the BusData line
while BusCLK is HIGH. This condition terminates the communication between
the devices and forces the bus interface into the initial state.
Acknowledge (ACK):
Indicates a successful data transfer. The transmitter will release the bus after
sending 8 bit of data. During the 9th clock cycle the receiver will set the SDA
line to LOW level to indicate it has received the 8 bits of data correctly.
Data Transfer Write Mode:
To start the communication, the bus master must initiate a start condition (STA),
followed by the 8bit chip address. The chip address for the TDA5250 is fixed as
„1110000“ (MSB at first). The last bit (LSB=A0) of the chip address byte defines
the type of operation to be performed:
A0=0, a write operation is selected and A0=1 a read operation is selected.
After this comparison the TDA5250 will generate an ACK and awaits the
desired sub address byte (00H...0FH) and data bytes. At the end of the data
transition the master has to generate the stop condition (STO).
Data Transfer Read Mode:
To start the communication in the read mode, the bus master must initiate a
start condition (STA), followed by the 8 bit chip address (write: A0=0), followed
by the sub address to read (80H, 81H), followed by the chip address
(read: A0=1). After that procedure the data of the selected register (80H, 81H)
is read out. During this time the data line has to be kept in HIGH state and the
chip sends out the data. At the end of data transition the master has to generate
the stop condition (STO).
Wireless Components
3 - 15
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
Bus Data Format in I2C Mode
Table 3-7 Chip address Organization
MSB
LSB
Function
1
1
1
0
0
0
0
0
Chip Address Write
1
1
1
0
0
0
0
1
Chip Address Read
Table 3-8 I2C Bus Write Mode 8 Bit
MSB CHIP ADDRESS (WRITE) LSB
STA
1
1
1
0
0
0
0
0
MSB SUB ADDRESS (WRITE)
LSB
MSB
DATA IN
LSB
00H...08H, 0DH, 0EH, 0FH
ACK S7 S6 S5 S4 S3 S2 S1 S0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STO
Table 3-9 I2C Bus Write Mode 16 Bit
MSB CHIP ADDRESS (WRITE) LSB
STA
1
1
1
0
0
0
0
0
MSB SUB ADDRESS (WRITE)
LSB
MSB
DATA IN
00H...08H, 0DH, 0EH, 0FH
ACK S7 S6 S5 S4 S3 S2 S1 S0 ACK D15 ... D8 ACK D7 D6
LSB
...
D0 ACK STO
Table 3-10 I2C Bus Read Mode
MSB CHIP ADDRESS (WRITE) LSB
STA
1
1
1
0
0
0
0
0
MSB SUB ADDRESS (READ)
80H, 81H
ACK S7 S6 S5 S4 S3 S2
MSB
R7
LSB
S1
MSB CHIP ADDRESS (READ) LSB
S0 ACK STA
DATA OUT FROM SUB ADDRESS
R6
R5
R4
R3
R2
1
1
R1
1
0
LSB
R0
0
0
0
ACK*
1
ACK
STO
* mandatory HIGH
3-wire Bus Mode
In this mode pin 2 (BusMode)= HIGH and Pin 16 (BusData) is in the data input/
output pin. Pin 24 (EN) is used to activate the bus interface to allow the transfer
of data to / from the device. When pin 24 (EN) is inactive (HIGH), data transfer
is inhibited.
Data Transition:
Data transition on pin 16 (BusData) can only occur if the clock BusCLK is LOW.
To perform a data transfer the interface has to be enabled. This is done by
setting the EN line to LOW. A serial transfer is done via BusData, BusCLK and
EN. The bit stream needs no chip address.
Wireless Components
3 - 16
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
Data Transfer Write Mode:
To start the communication the EN line has to be set to LOW. The desired sub
address byte and data bytes have to follow. The subaddress (00H...0FH)
determines which of the data bytes are transmitted. At the end of data transition
the EN must be HIGH.
Data transfer Read Mode:
To start the communication in the read mode, the EN line has to be set to LOW
followed by the sub address to read (80H, 81H). Afterwards the device is ready
to read out data. At the end of data transition EN must be HIGH.
Bus Data Format 3-wire Bus Mode
Table 3-11 3-wire Bus Write Mode
MSB SUB ADDRESS (WRITE)
00H...08H, 0DH, 0EH,0FH
S7
S6
S5
S4
S3
LSB
S2
S1
S0
MSB DATA IN X...0 (X=7 or 15)
DX
...
D5
D4
D3
LSB
D2
D1
D0
Table 3-12 3-wire Bus Read Mode
MSB SUB ADDRESS (READ)
80H, 81H
S7
S6
S5
S4
S3
LSB
S2
S1
S0
MSB DATA OUT FROM
SUB ADDRESS
R7
R6
R5
R4
LSB
R3
R2
R1
R0
Register Definition
Sub Addresses Overview
FILTER
ADC
RSSI [8 Bit]
I 2C
- SPI
INTERFACE
CONTROL
WAKEUP
CONFIG [16 Bit]
STATUS [8 Bit]
CLK_DIV [8 Bit]
BLOCK_PD [16Bit]
ON_TIME [16 Bit]
OFF_TIME [16 Bit]
COUNT_TH1 [16Bit]
COUNT_TH2 [16Bit]
RSSI_TH3 [8 Bit]
LPF [8 Bit]
XTAL
XTAL_TUNE [16Bit]
FSK [16Bit]
XTAL_CONFIG [8 Bit]
register_overview.wmf
Figure 3-8
Wireless Components
Sub Addresses Overview
3 - 17
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
Subaddress Organization
Table 3-13 Sub Addresses of Data Registers Write
MSB
0
0
0
0
0
0
0
0
0
0
0
0
LSB HEX
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
00h
01h
02h
03h
04h
05h
06h
07h
08h
0Dh
0Eh
0Fh
Function
Description
CONFIG
FSK
XTAL_TUNING
LPF
ON_TIME
OFF_TIME
COUNT_TH1
COUNT_TH2
RSSI_TH3
CLK_DIV
XTAL_CONFIG
BLOCK_PD
Bit Length
General definition of status bits
Values for FSK-shift
Nominal frequency
I/Q and data filter cutoff frequencies
ON time of wakeup counter
OFF time of wakeup counter
Lower threshold of window counter
Higher threshold of window counter
Threshold for RSSI signal
Configuration and Ratio of clock divider
XTAL configuration
Building Blocks Power Down
16
16
16
8
16
16
16
16
8
8
8
16
Table 3-14 Sub Addresses of Data Registers Read
MSB
1
1
LSB HEX
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Function
Description
80h STATUS
81h ADC
Bit Length
Results of comparison: ADC & WINDOW
ADC data out
8
8
Data Byte Specification
Table 3-15 Sub Address 00H: CONFIG
Bit
Function
D15
D14
D13
D12
SLICER
ALL_PD
TESTMODE
CONTROL
D11
D10
D9
D8
D7
D6
D5
D4
D3
ASK_NFSK
RX_NTX
CLK_EN
RX_DATA_INV
D_OUT
ADC_MODE
F_COUNT_MODE
LNA_GAIN
EN_RX
D2
D1
D0
MODE_2
MODE_1
PA_PWR
Description
Default
0= Lowpass, 1= Peak Detector
0= normal operation, 1= all Power down
0= normal operation, 1=Testmode
0= RX/TX and ASK/FSK external controlled, 1= Register
controlled
0= FSK, 1=ASK
0= TX, 1=RX
0= CLK off during power down, 1= always CLK on, ever in PD
0= no Data inversion, 1= Data inversion
0= Data out if valid, 1= always Data out
0= one shot, 1= continuous
0= one shot, 1= continuous
0= low gain, 1= high gain
0= disable receiver, 1= enable receiver (in self polling and
timer mode) *
0= slave mode, 1= timer mode
0= slave or timer mode, 1= self polling mode
0= low TX Power, 1= high TX Power
0
0
0
0
0
1
0
0
1
1
1
1
1
0
0
1
Note D3: Function is only active in selfpolling and timer mode. When D3 is set
to LOW the RX path is not enabled if PwdDD pin is set to LOW. A delayed
setting of D3 results in a delayed power ON of the RX building blocks.
Wireless Components
3 - 18
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
Table 3-17 Sub Address 02H: XTAL_TUNING
Table 3-16 Sub Address 01H: FSK
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
Value
FSK+5
FSK+4
FSK+3
FSK+2
FSK+1
FSK+0
8pF
4pF
2pF
1pF
500fF
250fF
D7
D6
D5
D4
D3
D2
D1
D0
FSK-5
FSK-4
FSK-3
FSK-2
FSK-1
FSK-0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
4pF
2pF
1pF
500fF
250fF
125fF
Sub Address
Function
Datafilter_3
Datafilter_2
Datafilter_1
Datafilter_0
IQ_Filter_2
IQ_Filter_1
IQ_Filter_0
not used
Table 3-20
Bit
Setting for
positive
frequency
shift: +FSK or
ASK-RX
not used
not used
Table 3-18
Bit
Description
not used
not used
not used
not used
not used
not used
TH1_11
TH1_10
TH1_9
TH1_8
TH1_7
TH1_6
TH1_5
TH1_4
TH1_3
TH1_2
TH1_1
TH1_0
Wireless Components
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
03H: LPF
Function
Value
Nominal_Frequ_5
Nominal_Frequ_4
Nominal_Frequ_3
Nominal_Frequ_2
Nominal_Frequ_1
Nominal_Frequ_0
8pF
4pF
2pF
1pF
500fF
250fF
Table 3-19
Description
Default
0
0
0
1
1
0
0
0
3dB cutoff
frequency of
data filter
3dB cutoff
frequency of
IQ-filter
Sub Address
Function
Setting for
negative
frequency
shift: -FSK
Default
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
0
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
06H: COUNT_TH1
ON_15 / OFF_15
ON_14 / OFF_14
ON_13 / OFF_13
ON_12 / OFF_12
ON_11 / OFF_11
ON_10 / OFF_10
ON_9 / OFF_9
ON_8 / OFF_8
ON_7 / OFF_7
ON_6 / OFF_6
ON_5 / OFF_5
ON_4 / OFF_4
ON_3 / OFF_3
ON_2 / OFF_2
ON_1 / OFF_1
ON_0 / OFF_0
Table 3-21
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
3 - 19
Sub Addresses
Function
Sub Address
Function
not used
not used
not used
not used
TH2_11
TH2_10
TH2_9
TH2_8
TH2_7
TH2_6
TH2_5
TH2_4
TH2_3
TH2_2
TH2_1
TH2_0
Description
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
Default
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
Setting for
nominal
frequency
ASK-TX
FSK-RX
04H / 05H: ON/OFF_TIME
Default
ON_TIME
Default
OFF_TIME
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
07H: COUNT_TH2
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
Table 3-22 Sub Address 08H: RSSI_TH3
Bit
Function
D7
D6
D5
D4
D3
D2
D1
D0
not used
SELECT
TH3_5
TH3_4
TH3_3
TH3_2
TH3_1
TH3_0
Description
0= VCC, 1= RSSI
Table 3-23 Sub Address 0DH: CLK_DIV
Default
Bit
Function
Default
1
1
1
1
1
1
1
1
D7
D6
D5
D4
D3
D2
D1
D0
not used
not used
DIVMODE_1
DIVMODE_0
CLKDIV_3
CLKDIV_2
CLKDIV_1
CLKDIV_0
0
0
0
0
1
0
0
0
Table 3-24 Sub Address 0EH: XTAL_CONFIG
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Function
FSK-Ramp 0
FSK-Ramp 1
Bipolar_FET
Description
Default
not used
not used
not used
not used
not used
0
0
0
0
0
0
0
1
only in bipolar mode
0= FET, 1=Bipolar
Table 3-25 Sub Address 0FH: BLOCK_PD
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
Function
Description
COMP_LOW
COMP_IN
COMP_HIGH
COMP_0,5*LOW
COMP_0,5*IN
COMP_0,5*HIGH
RSSI=TH3
RSSI>TH3
D7
D6
D5
D4
D3
D2
D1
D0
1 if data rate < TH1
1 if TH1 < data rate < TH2
1 if TH2 < data rate
1 if data rate < 0,5*TH1
1 if 0,5*TH1 < data rate < 0,5*TH2
1 if 0,5*TH2 < data rate
1 if RSSI value is equal TH3
1 if RSSI value is greater than TH3
Wireless Components
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Description
Bit
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Default
1= power down Band Gap Reference
1= power down RC Oscillator
1= power down Window Counter
1= power down ADC
1= power down Peak Detectors
1= power down Data Slicer
1= power down Data Filter
1= power down Quadri Correlator
1= power down Limiter
1= power down I/Q Filters
1= power down I/Q Mixer
1= power down 1st Mixer
1= power down LNA
1= power down Power Amplifier
1= power down PLL
1= power down XTAL Oscillator
Table 3-27 Sub Address 81H: ADC
Table 3-26 Sub Address 80H: STATUS
Function
Description
REF_PD
RC_PD
WINDOW_PD
ADC_PD
PEAK_DET_PD
DATA_SLIC_PD
DATA_FIL_PD
QUAD_PD
LIM_PD
I/Q_FIL_PD
MIX2_PD
MIX1_PD
LNA_PD
PA_PD
PLL_PD
XTAL_PD
3 - 20
PD_ADC
SELECT
RSSI_5
RSSI_4
RSSI_3
RSSI_2
RSSI_1
RSSI_0
ADC power down feedback Bit
SELECT feedback Bit
RSSI value Bit5
RSSI value Bit4
RSSI value Bit3
RSSI value Bit2
RSSI value Bit1
RSSI value Bit0
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
3.4.16
Wakeup Logic
3_modes.wmf
S LA V E M O D E
(d efau lt)
MODE_1 = 0
MODE_2 = 0
Figure 3-9
S E LF P O L LIN G
M ODE
T IM ER M O D E
MODE_1 = 1
MODE_2 = X
MODE_1 = 0
MODE_2 = 1
Wakeup Logic States
Table 3-28 MODE settings: CONFIG register
MODE_1
MODE_2
Mode
0
0
1
0
1
X
SLAVE MODE
TIMER MODE
SELF POLLING MODE
SLAVE MODE: The receive and transmit operation is fully controlled by an
external control device via the respective RxTx, AskFsk, PwdDD, and Data
pins. The wakeup logic is inactive in this case.
After RESET or 1st Power-up the chip is in SLAVE MODE. By setting MODE_1
and MODE_2 in the CONFIG register the mode may be changed.
SELF POLLING MODE: The chip turns itself on periodically to receive using a
built-in 32kHz RC oscillator. The timing of this is determined by the ON_TIME
and OFF_TIME registers, the duty cycle can be set between 0 and 100% in
31.25µs increments. The data detect logic is enabled and a 15µs LOW impulse
is provided at PwdDD pin (Pin 27), if the received data is valid.
ON_TIME
Action
RX ON: valid Data
PwdDD pin in
SELF POLLING MODE
OFF_TIME
ON_TIME
RX ON: invalid Data
t
t
min. 2.6ms
15µs
timing_selfpllmode.wmf
Figure 3-10
Timing for Self Polling Mode (ADC & Data Detect in one shot mode)
Note: The time delay between start of ON time and the 15µs LOW impulse is
2.6ms + 3 period of data rate.
Wireless Components
3 - 21
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
If ADC & Data Detect Logic are in continuous mode the 15µs LOW impulse is
applied at PwdDD after each data valid decision.
In self polling mode if D9=0 (Register 00h) and when PwdDD pin level is HIGH
the CLK output is on during ON time and off during OFF time. If D9=1, the CLK
output is always on.
TIMER MODE: Only the internal Timer (determined by the ON_TIME and
OFF_TIME registers) is active to support an external logic with periodical
Interrupts. After ON_TIME + OFF_TIME a 15µs LOW impulse is applied at the
PwdDD pin (Pin 27).
Action
ON_TIME
OFF_TIME
ON_TIME
Register 04H
Register 05H
Register 04H
PwdDD pin in
TIMER MODE
t
t
15µs
15µs
timing_timermode.wmf
Figure 3-11
Wireless Components
Timing for Timer Mode
3 - 22
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
3.4.17
Data Valid Detection, Data Pin
Data signals generate a typical spectrum and this can be used to determine if
valid data is on air.
Amplitude
Frequency & RSSI Window
DATA on air
no DATA on air
RSSI
Frequency
f
data_rate_detect.wmf
Figure 3-12
Frequency and RSSI Window
The “data valid” criterion is generated from the result of RSSI-TH3 comparison
and tGATE between TH1 and TH2 result as shown below. In case of Manchester
coding the 0,5*TH1 and 0,5*TH2 gives improved performance.
The use of permanent data valid recognition makes it absolutely necessary to
set the RSSI-ADC and the Window counter into continuous mode (Register
00H, Bit D5 = D6 = 1).
0,5*TH1
TGATE
TH1
0,5*TH2
TGATE
TH2
RSSI
TH3
DATA VALID
data_valid.wmf
Figure 3-13
Data Valid Circuit
D_OUT and RX_DATA_INV from the CONFIG register determine the output of
data at Pin 28. RxTxint and TX_ON are internally generated signals.
In RX and power down mode Data pin (Pin 28) is tied to GND.
RxTxint
RX_DATA_INV
RX DATA
Data
DATA VALID
28
D_OUT
TX DATA
TX ON
data_switch.wmf
Figure 3-14
Wireless Components
Data Input/Output Circuit
3 - 23
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
3.4.18
Sequence Timer
The sequence timer has to control all the enable signals of the analog
components inside the chip. The time base is the 32 kHz RC oscillator.
After the first POWER ON or RESET a 1 MHz clock is available at the clock
output pin. This clock output can be used by an external µP to set the system
into the desired state and outputs valid data after 500 µs (see Figure 3-15 and
Figure 3-16, tCLKSU)
There are two possibilities to start the device after a reset or first power on:
-
PWDDD pin is LOW: Normal operation timing is performed after tSYSSU (see
Figure 3-15).
-
PWDDD pin is HIGH (device in power down mode): A clock is offered at the
clock output pin until the device is activated (PWDDD pin is pulled to LOW).
After the first activation the time tSYSSU is required until normal operation
timing is performed (see Figure 3-16 ).
This could be used to extend the clock generation without device programming or activation.
Note: It is required to activate the device for the duration of tSYSSU after first
power on or a reset. Only if this is done the normal operation timing is
performed.
With default settings the clock generating units are disabled during PD,
therefore no clock is available at the clock output pin. It is possible to offer a
clock signal at the clock output pin every time (also during PD) if the CLK_EN
Bit in the CONFIG register is set to HIGH.
RESET
or 1st POWER ON
PWDDD = low
STATUS
XTAL EN
TX activ or RX activ
PD
TX activ
PD
RX activ
TX activ
RX activ
CLOCK FOR EXTERNAL µP
DC OFFSET COMPENSATION
if RX
PEAK DETECTOR EN
if RX
DATADETECTION EN
if RX
POWER AMP EN
if TX
t C LK S U
tCLKS U
0.5ms
t C LK S U
t TX S U
0.5ms
0.5ms
tT X S U
1.1ms
t TX S U
1.1ms
tS Y S S U
1.1ms
tRX SU
tR X S U
tDDS U
tD D S U
2.2ms
8ms
tR X S U
2.2ms
2.6ms
2.2ms
2.6ms
tD D S U
2.6ms
Sequenzer_Timing_pupstart.wmf
Figure 3-15
1st start or reset in active mode
Note: The time values are typical values
Wireless Components
3 - 24
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
RESET
or 1st POWER ON
PWDDD = high
PWDDD = low
STATUS
PD
XTAL EN
CLOCK FOR EXTERNAL µP
TX activ or RX activ
PD
TX activ
RX activ
if RX
DC OFFSET COMPENSATION
PEAK DETECTOR EN
if RX
DATADETECTION EN
if RX
POWER AMP EN
if TX
t C LK S U
0.5ms
t C LK S U
tT X S U
0.5ms
t TX S U
1.1ms
1.1ms
tR X S U
tS Y S S U
2.2ms
8ms
tR X S U
2.2ms
tD D S U
2.6ms
tD D S U
2.6ms
Sequenzer_Timing_pdstart.wmf
Figure 3-16
1st start or reset in PD mode
Note: The time values are typical values
This means that the device needs tDDSU setup time to start the data detection
after RX is activated. When activating TX it requires tTXSU setup time to enable
the power amplifier.
For timing information refer to Table 5-3.
For Test purposes a TESTMODE is provided by the Sequencer as well. In this
mode the BLOCK_PD register be set to various values. This will override the
Sequencer timing. Depending on the settings in Config Register 00H the
corresponding building blocks are enabled, as shown in the subsequent figure.
RC- OSC.
TX ON
XTAL FREQU.
SELECT
16
16
16
TESTMODE
ALL_PD
CLK_EN
INTERNAL BUS
BLOCK_PD
REGISTER
ASK/FSK
ENABLE / DISABLE
BUILDING BLOCKS
RX ON
2
SWITCH
32 kHz
TIMING
DECODE
RESET
sequencer_raw.wmf
Figure 3-17
Wireless Components
Sequencer‘s capability
3 - 25
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
3.4.19
Clock Divider
It supports an external logic with a programmable Clock at pin 26 (CLKDIV).
32 kHz
WINDOW COUNT COMPLETE
DIVMODE_0
DIVMODE_1
SWITCH
4 BIT COUNTER
18 MHz
DIVIDE
BY 2
INTERNAL BUS
CLKDiv
26
clk_div.wmf
Figure 3-18
Clock Divider
The Output Selection and Divider Ratio can be set in the CLK_DIV register.
Table 3-29 CLK_DIV Output Selection
D5
D4
0
0
1
1
0
1
0
1
Output
Output from Divider (default)
18.089MHz
32kHz
Window Count Complete
Note: Data are valid 500 µs after the crystal oscillator is enabled (see Figure 315 and Figure 3-16, tCLKSU).
Wireless Components
3 - 26
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
Table 3-30 CLK_DIV Setting
D3
D2
D1
D0
Total Divider Ratio
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
Output Frequency [MHz]
9,0
4,5
3,0
2,25
1,80
1,50
1,28
1,125
1,00 (default)
0,90
0,82
0,75
0,69
0,64
0,60
0,56
Note: As long as default settings are used, there is no clock available at the
clock output during Power Down. It is possible to enable the clock during Power
Down by setting CLK_EN (Bit D9) in the Config Register (00H) to HIGH.
3.4.20
RSSI and Supply Voltage Measurement
The input of the 6Bit-ADC can be switched between two different sources: the
RSSI voltage (default setting) or a resistor network dividing the Vcc voltage by
5.
Table 3-31 Source for 6Bit-ADC Selection (Register 08H)
SELECT
0
1
Input for 6Bit-ADC
Vcc / 5
RSSI (default)
To prevent wrong interpretation of the ADC information (read from Register
81H: ADC) you can use the ADC- Power Down feedback Bit (D7) and the
SELECT feedback Bit (D6) which correspond to the actual measurement.
Note: As shown in section 3.4.18 there is a setup time of 2.6ms after RX
activating. Thus the measurement of RSSI voltage does only make sense after
this setup time.
Wireless Components
3 - 27
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
Wireless Components
3 - 28
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
Wireless Components
3 - 29
Specification, July 2002
TDA 5250 D2
preliminary
Functional Description
confidential
Wireless Components
3 - 30
Specification, July 2002
4
Applications
Contents of this Chapter
4.1
4.1.1
4.1.2
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.3
4.4
4.5
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.7
4.7.1
4.7.2
4.8
4.9
4.10
4.11
LNA and PA Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
RX/TX Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Power-Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Synthesizer Frequency setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Transmit/Receive ASK/FSK Frequency Assignment . . . . . . . . . . . . 4-16
Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Calculation of the external capacitors . . . . . . . . . . . . . . . . . . . . . . . . 4-20
FSK-switch modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Finetuning and FSK modulation relevant registers . . . . . . . . . . . . . . 4-22
Chip and System Tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
IQ-Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
Limiter and RSSI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
Data Slicer - Slicing Level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
RC Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
Peak Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
Peak Detector - Analog output signal . . . . . . . . . . . . . . . . . . . . . . . . 4-30
Peak Detector – Power Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . 4-31
Data Valid Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
Frequency Window for Data Rate Detection . . . . . . . . . . . . . . . . . . 4-33
RSSI threshold voltage - RF input power . . . . . . . . . . . . . . . . . . . . . 4-35
Calculation of ON_TIME and OFF_TIME . . . . . . . . . . . . . . . . . . . . . 4-36
Example for Self Polling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
Sensitivity Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
Default Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45
TDA 5250 D2
preliminary
Applications
confidential
4.1 LNA and PA Matching
4.1.1
RX/TX Switch
VCC
C5
L1
50 O hm
SM A-co nn e cto r
D1
C1
C2
L2
PA
C3
R1
C4
C7
C9
LNI
D2
L3
C10
LN IX
TDA5250
R F I/O
R X/T X
R X/T X
C6
RX/TX_Switch.wmf
Figure 4-1
RX/TX Switch
The RX/TX-switch combines the PA-output and the LNA-input into a single 50
Ohm SMA-connector. Two pin-diodes are used as switching elements. If no
current flows through a pin diode, it works as a high impedance for RF with very
low capacitance. If the pin-diode is forward biased, it provides a low impedance
path for RF. (some Ω)
4.1.1.1
Switch in RX-Mode
The RX/TX-switch is set to the receive mode by either applying a high level or
an open to the RX/TX-jumper on the evalboard or by leaving it open. Then both
pin-diodes are not biased and therefore have a high impedance.
VCC
C5
L1
C1
50 O hm
S M A -c on n ec to r
C2
L2
C3
R1
PA
C4
C7
C9
LN I
L3
C10
LN IX
TDA5250
R F I/O
R X /TX
o pe n o r V C C
R X /TX
C6
RX_Mode.wmf
Figure 4-2
Wireless Components
RX-Mode
4-2
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
The RF-signal is able to run from the RF-input-SMA-connector to the LNAinput-pin LNI via C1, C2, C7, L3 and C9. R1 does not affect the matching circuit
due to its high resistance. The other input of the differential LNA LNIX can
always be AC-grounded using a large capacitor without any loss of
performance. In this case the differential LNA can be used as a single ended
LNA, which is easier to match. The S11 of the LNA at pin LNI on the evalboard
is 0.945 / -47° (equals a resistor of 1.43kOhm in parallel to a capacitor of 1.6pF)
for both high and low-gain-mode of the LNA. (pin LNIX AC-grounded) This
impedance has to be matched to 50 Ohm with the parts C9, L3, C7 and C2. C1
is DC-decoupling-capacitor. On the evalboard the most important matching
components are (shunt) L3 and (series) C2. The capacitors C7 and C9 are
mainly DC-decoupling-capacitors and may be used for some fine tuning of the
matching circuit. A good CAE tool (featuring smith-chart) may be used for the
calculation of the values of the components. However, the final values of the
matching components always have to be found on the board because of the
parasitics of the board, which highly influence the matching circuit at RF.
Measured Magnitude of S11 of evalboard:
S11_measured.pcx.
Figure 4-3
S11 measured
Above you can see the measured S11 of the evalboard. The –3dB-points are at
810MHz and 930MHz. So the 3dB-bandwidth is:
B = f U − f L = 930MHz − 810MHz = 120MHz
[4 – 1]
The loaded Q of the resonant circuit is:
QL =
f center 868,3MHz
=
= 7 .2
B
120 MHz
[4 – 2]
The unloaded Q of the resonant circuit is equal to the Q of the inductor due to
its losses.
QU = QINDUCTOR ≈ 36 @ 868MHz
Wireless Components
4-3
[4 – 3]
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
An approximation of the losses of the input matching network can be made with
the formula:
 Q
Loss = −20 ∗ log1 − L
 QU

7 .2 
 = −20 ∗ log1 −
 = 2dB
36 


[4 – 4]
The noise figure of the LNA-input-matching network is equal to its losses. The
input matching network is always a compromise of sensitivity and selectivity.
The loaded Q should not get too high because of 2 reasons:
more losses in the matching network and hence less sensitivity
tolerances of components affect matching too much. This will cause problems
in a tuning-free mass production of the application. A good CAE-tool will help to
see the effects of component tolerances on the input matching more accurate
by tweaking each value.
A very high selectivity can be reached by using SAW-filters at the expense of
higher cost and lower sensitivity which will be reduced by the losses of the
SAW-Filter of approx. 4dB.
Image-suppression:
Due to the quite high 1st-IF of the frontend, the image frequency is quite far
away. The image frequency of the receiver is at:
f IMAGE = f SIGNAL + 2 ∗ f IF = 868.3MHz + 2 * 289.4 = 1447.2MHz
[4 – 5]
The image suppression on the evalboard is about 16dB.
LO-leakage:
The LO of the 1st Mixer is at:
f LO = f RECEIVE *
4
4
= 868.3MHz ∗ = 1157.73MHz
3
3
[4 – 6]
The LO-leakage of the evalboard on the RF-input is about –98dBm. This is far
below the ETSI-radio-regulation-limit for LO-leakage.
Wireless Components
4-4
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.1.1.2
Switch in TX-Mode
The evalboard can be set into the TX-Mode by grounding the RX/TX-jumper on
the evalboard or programming the TDA5250 to operate in the TX-Mode. If the
IC is programmed to operate in the TX-Mode, the RX/TX-pin will act as an open
drain output at a logical LOW. Then a DC-current can flow from VCC to GND
via L1, L2, D1, R1 and D2.
The current is:
I PIN − DIODE =
Vcc − 2 ∗ VFORWARD , PIN − DIODE
[4 – 7]
R1
Now both pin-diodes are biased with a current of approx. [email protected] and have
a very low impedance for RF.
VCC
C5
L1
C1
50 O hm
S M A -c o n n e c to r
C2
L2
PA
C3
R1
C4
C7
C9
LNI
C10
L3
R X /T X
g ro u n d e d
(w ith ju m p e r o r
R X /T X -p in o f IC )
L N IX
TDA5250
R F I/O
R X /T X
C6
TX_Mode.wmf
Figure 4-4
TX_Mode
R1 does not influence the matching because of its very high resistance. Due to
the large capacitance of C1, C6 and C5 the circuit can be further simplified for
RF:
L1
50 O hm
S M A-connector
L2
C2
C3
PA
C4
C7
C9
LN I
L3
C 10
LN IX
TDA5250
R F I/O
TX_Mode_simplified.wmf
Figure 4-5
Wireless Components
TX_Mode_simplified
4-5
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
The LNA-matching is RF-grounded now, so no power is lost in the LNA-input.
The PA-matching consists of C2, C3 L2, C4 and L1.
When designing the matching of the PA, C2 must not be changed anymore
because its value is already fixed to the LNA-input-matching.
4.1.2
Power-Amplifier
The power amplifier operates in a high efficient class C mode. This mode is
characterized by a pulsed operation of the power amplifier transistor at a current
flow angle of θ<<π. A frequency selective network at the amplifier output
passes the fundamental frequency component of the pulse spectrum of the
collector current to the load. The load and its resonance transformation to the
collector of the power amplifier can be generalized by the equivalent circuit of
Figure 4-6. The tank circuit L//C//RL in parallel to the output impedance of the
transistor should be in resonance at the operating frequency of the transmitter.
VS
L
C
RL
Equivalent_power_wmf.
Figure 4-6
Equivalent power amplifier tank circuit
The optimum load at the collector of the power amplifier for “critical” operation
under idealized conditions at resonance is:
R LC =
VS 2
2 PO
[4 – 8]
A typical value of RLC for an RF output power of Po= 13mW is:
RLC =
Wireless Components
32
= 350Ω
2 ∗ 0.013
4-6
[4 – 9]
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
“Critical” operation is characterized by the RF peak voltage swing at the
collector of the PA transistor to just reach the supply voltage VS. The high
efficiency under “critical” operating conditions can be explained by the low
power loss at the transistor.
During the conducting phase of the transistor there is no or only a very small
collector voltage present, thus minimizing the power loss of the transistor
(iC*uCE). This is particularly true for low current flow angles of θ<<π. In practice
the RF-saturation voltage of the PA transistor and other parasitics will reduce
the “critical” RLC.
The output power Po will be reduced when operating in an “overcritical” mode
at a RL > RLC. As shown in Figure 4-7, however, power efficiency E (and
bandwidth) will increase by some degree when operating at higher RL. The
collector efficiency E is defined as
E=
PO
VS I C
[4 – 10]
The diagram of Figure 4-7 has been measured directly at the PA-output at
VS=3V. A power loss in the matching circuit of about 2dB will decrease the
output power. As shown in the diagram, 240 Ohm is the optimum impedance
for operation at 3V. For an approximation of ROPT and POUT at other supply
voltages those 2 formulas can be used:
ROPT ~ VS
[4 – 11]
POUT ~ ROPT
[4 – 12]
and
Wireless Components
4-7
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
Power_E_vs_RL.wmf
Figure 4-7
Output power Po (mW) and collector efficiency E vs. load resistor RL.
The DC collector current Ic of the power amplifier and the RF output power Po
vary with the load resistor RL. This is typical for overcritical operation of class C
amplifiers. The collector current will show a characteristic dip at the resonance
frequency for this type of “overcritical” operation. The depth of this dip will
increase with higher values of RL.
As Figure 4-8 shows, detuning beyond the bandwidth of the matching circuit
results in a significant increase of collector current of the power amplifier and in
some loss of output power. This diagram shows the data for the circuit of the
test board at the frequency of 868 MHz. The effective load resistor of this circuit
is RL= 240Ohm, which is the optimum impedance for operation at 3V. This will
lead to a dip of the collector current of approx. 20%.
pout_vs_frequ.wmf
Figure 4-8
Wireless Components
Power output and collector current vs. frequency
4-8
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
C4, L2 and C3||C2 are the main matching components which are used to
transform the 50 Ohm load at the SMA-RF-connector to a higher impedance at
the PA-output ([email protected]). L1 can be used for finetuning of the resonance
frequency but should not be too low in order to keep its loss low.
The transformed impedance of 240Ohm+j0 at the PA-output-pin can be verified
with a network analyzer using this measurement procedure:
1. Calibrate your network analyzer.
2. Connect a short, low-loss 50 Ohm cable to your network analyzer with an
open end on one side. Semirigid cable works best.
3. Use the „Port Extension“ feature of your network analyzer to shift the reference plane of your network analyzer to the open end of the cable.
4. Connect the center-conductor of the cable to the solder pad of the pin „PA“
of the IC. The shield has to be grounded. Very short connections must be
used. Do not remove the IC or any part of the matching-components!
5. Screw a 50Ohm-dummy-load on the RF-I/O-SMA-connector
6. The TDA5250 has to be in ASK-TX-Mode, Data-Input=LOW.
7. Be sure that your network analyzer is AC-coupled and turn on the power
supply of the IC.
8. Measure the S-parameter
Sparam_measured_200M.pcx
Figure 4-9
Wireless Components
Sparam_measured_200M
4-9
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
Above you can see the measurement of the evalboard with a span of 200MHz.
The evalboard has been optimized for 3V. The load is about 240+j0 at
868.3MHz.
A tuning-free realization requires a careful design of the components within the
matching network. A simple linear CAE-tool will help to see the influence of
tolerances of matching components.
Suppression of spurious harmonics may require some additional filtering within
the antenna matching circuit. Both can be seen in Figure 4-10 and Figure 4-11
The total spectrum of the evalboard can be summarized as:
Carrier fc
+9dBm
fc-18.1MHz
-62dBm
fc+18.1MHz
-66dBm
2nd harmonic
-40dBm
3rd harmonic
-44dBm
oberwellentx.tif
Figure 4-10
Wireless Components
Transmit Spectrum 13.2GHz
4 - 10
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
spektrum_10r_3v.tif
Figure 4-11
Transmit Spectrum 300MHz
Regarding CEPT ERC recommendation 70-03 and ETSI regulation EN 300220
both of the following figures show full compliance in case of ASK and FSK
modulation spectrum. Data signal is a Manchester encoded PRBS9 (Pseudo
Random Binary Sequence), RF output power is +9dBm at a supply voltage of
3V. With these settings ASK allows a maximum data rate of 25kBaud, in FSK
case 40kBaud are possible. See also Section 5.1.4
Wireless Components
4 - 11
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
ASK_25kBaud_Manch_PRBS9_10dBm_3V_Spectrum_CEPT_ERC7003.wmf
Figure 4-12
ASK Transmit Spectrum 25kBaud, Manch, PRBS9, 9dBm, 3V
FSK_40kBaud_Manch_PRBS9_10dBm_3V_Spectrum_CEPT_ERC7003.wmf
Figure 4-13
Wireless Components
FSK Transmit Spectrum 40kBaud, Manch, PRBS9, 9dBm, 3V
4 - 12
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.2 Crystal Oscillator
The equivalent schematic of the crystal with its parameters specified by the
crystal manufacturer can be taken from the subsequent figure.
Here also the load capacitance of the crystal CL, which the crystal wants to see
in order to oscillate at the desired frequency, can be seen.
L1
-R
C1
R1
CL
C0
Crystal.wmf
Figure 4-14
Crystal
L1:
C1 :
C0 :
motional inductance of the crystal
motional capacitance of the crystal
shunt capacitance of the crystal
Therefore the Resonant Frequency fs of the crystal is defined as:
fS =
1
[4 – 13]
2π L1 * CL
The Series Load Resonant Frequency fS‘ of the crystal is defined as:
f S `=
1
2π L1 * C1
* 1+
C1
C0 + C L
[4 – 14]
regarding Figure 4-14
fs’ is the nominal frequency of the crystal with a specified load when tested by
the crystal manufacturer.
Pulling Sensitivity of the crystal is defined as the magnitude of the relative
change in frequency relating to the variation of the load capacitor.
Wireless Components
4 - 13
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
δf S ´
fS
− C1
δD
=
=
2
δCL
δC L
2(C0 + CL )
[4 – 15]
Choosing CL as large as possible results in a small pulling sensitivity. On the
other hand a small CL keeps the influence of the serial inductance and the
tolerances associated to it small (see formula [4-17]).
Start-up Time
t Start ~
L1
− R − Rext
where: -R:
Rext:
[4 – 16]
is the negative impedance of the oscillator
(see fig. [4-15])
is the sum of all external resistances (e.g. R1 or any
other resistance that may be present in the circuit,
see figure [4-14]
The proportionality of L1 and C1 of the crystal is defined by formula [4-13]. For
a crystal with a small C1 the start -up time will also be slower. Typically the lower
the value of the crystal frequency, the lower the C1.
A short conclusion regarding crystal and crystal oscillator dependencies is
shown in the following table:
Table 4-1 Crystal and crystal oscilator dependency
Result
Relative
Tolerance
Maximum
Deviation
tStart-up
C1 >
>>
>>
<
C0 >
<
<
-
frequency of quartz >
>>>
>
<<
LOSC >
>>
>
-
CL >
>
<
-
Independent variable
The crystal oscillator in the TDA5250 is a NIC (negative impedance converter)
oscillator type. The input impedance of this oscillator is a negative impedance
in series to an inductance. Therefore the load capacitance of the crystal CL
(specified by the crystal supplier) is transformed to the capacitance Cv as
shown in formula [4-17].
Wireless Components
4 - 14
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
-R
LOSC
f, CL
CV
TDA 5250
QOSZ_NIC.wmf
Figure 4-15
CL =
Crystal Oscillator
1
1
− ω 2 LOSC
CV
CL :
ω:
LOSC:
↔ CV =
1
1
+ ω 2 LOSC
CL
[4 – 17]
crystal load capacitance for nominal frequency
angular frequency
inductivity of the crystal oscillator - typ: 2.7µH
With the aid of this formula it becomes obvious that the higher the serial capacitance CV is, the higher is the influence of LOSC.
The tolerance of the internal oscillator inductivity is much higher, so the inductivity is the dominating value for the tolerance.
FSK modulation and tuning are achieved by a variation of Cv.
In case of small frequency deviations (up to +/- 1000 ppm), the desired load
capacitances for FSK modulation are frequency depending and can be calculated with the formula below.
CL ±
2 ⋅ ( C 0 + CL )
∆f
CL −
+ C 0 ⋅ ---------- ⋅ æè 1 + --------------------------------ö
N⋅f
C1
= -------------------------------------------------------------------------------------⋅
(
+
2
C
∆f
0 C L )ö
1 ± ---------- ⋅ æ 1 + ------------------------------N⋅f è
C1
CL :
C0 :
C1 :
f:
N:
∆f:
Wireless Components
[4 – 18]
crystal load capacitance for nominal frequency
shunt capacitance of the crystal
motional capacitance of the crystal
crystal oscillator frequency
division ratio of the PLL
peak frequency deviation
4 - 15
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
With CL+ and CL- the necessary Cv+ for FSK HIGH and Cv- for FSK LOW can
be calculated.
Alternatively, an external AC coupled (10nF in series to 1kΩ) signal can be
applied at pin 19 (Xout). The drive level should be approximately 100mVpp.
4.2.1
Synthesizer Frequency setting
Generating ASK and FSK modulation 3 setable frequencies are necessary.
4.2.1.1
Possible crystal oscillator frequencies
The resulting possible crystal oscillator frequencies are shown in the following
Figure 4-16
.
RX:
TX:
FSK-
FSK
ASK
Deviation
f1
ASK
FSK+
Deviation
f
0
Nominal
Frequency
f2
free_reg.wmf
Figure 4-16
possible crystal oscillator frequencies
In ASK receive mode the crystal oscillator is set to frequency f2 to realize the
necessary frequency offset to receive the ASK signal at f0*N (N: division ratio
of the PLL).
To set the 3 different frequencies 3 different Cv are necessary. Via internal
switches 3 external capacitors can be combined to generate the necessary Cv
in case of ASK- or FSK-modulation. Internal banks of switchable capacitors
allow the finetuning of these frequencies.
4.2.2
Transmit/Receive ASK/FSK Frequency Assignment
Depending on whether the device operates in transmit or receive mode or
whether it operates in ASK or FSK the following cases can be distinguished:
Wireless Components
4 - 16
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.2.2.1
FSK-mode:
In transmit mode the two frequencies representing logical HIGH and LOW data
states have to be adjusted depending on the intended frequency deviation and
separately according to the following formulas:
fCOSC HI = (fRF + fDEV) / 48
fCOSC LOW = (fRF - fDEV) / 48
[4 – 19]
e.g.
fCOSC HI
= (868,3E6 + 50E3) / 48 = 18.08438MHz
fCOSC LOW = (868,3E6 - 50E3) / 48 = 18.08229MHz
with a frequency deviation of 50kHz.
Figure 4-17 shows the configuration of the switches and the capacitors to
achieve the 2 desired frequencies. Gray parts of the schematics indicate
inactive parts. For FSK modulation the ASK-switch is always open.
For FSK LOW the FSK-switch is closed and Cv2 and Ctune2 are bypassed. The
effective Cv- is given by:
CV − = C v1 + Ctune1
[4 – 20]
For finetuning Ctune1 can be varied over a range of 8 pF in steps of 125fF. The
switches of this C-bank are controlled by the bits D0 to D5 in the FSK register
(subaddress 01H, see Table 4-6).
For FSK HIGH the FSK-switch is open. So the effective Cv+ is given by:
( C v1 + C tune1 ) ⋅ ( C v2 + C tune2 )
Cv+ = ---------------------------------------------------------------------------C v1 + C tune1 + Cv2 + Ctune2
[4 – 21]
The C-bank Ctune2 can be varied over a range of 16 pF in steps of 250fF for
finetuning of the FSK HIGH frequency. The switches of this C-bank are
controlled by the bits D8 to D13 in the FSK register (subaddress 01H, see Table
4-6).
Wireless Components
4 - 17
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
L
XOUT 19
-R
f, CL
-R
f, CL
XIN 21
XIN 21
CV1
CV1
Ctune1
XSWF 20
Ctune1
XSWF 20
XSWA 22
XSWA 22
CV2
CV3
Ctune2
Ctune2
XGND 23
FSKswitch
ASKswitch
XGND 23
FSK LOW
FSKswitch
CV3
ASKswitch
CV2
L
XOUT 19
FSK HIGH
QOSC_FSK.wmf
Figure 4-17
FSK modulation
In receive mode the crystal oscillator frequency is set to yield a direct-to-zero
conversion of the receive data. Thus the frequency may be calculated as
fCOSC = fRF / 48,
[4 – 22]
e.g.
fCOSC = 868,3E6 / 48 = 18.0833MHz
which is identical to the ASK transmit case.
XOUT 19
L
-R
f, CL
XIN 21
CV1
Ctune1
XSWF 20
XSWA 22
CV3
Ctune2
ASKswitch
XGND 23
FSKswitch
CV2
QOSC_ASK.wmf
Figure 4-18
Wireless Components
FSK receive
4 - 18
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
In this case the ASK-switch is closed. The necessary Cvm is given by:
( C v1 + C tune1 ) ⋅ ( C v2 + C v3 + Ctune2 )
Cvm = -------------------------------------------------------------------------------------------Cv1 + C tune1 + C v2 + C v3 + C tune2
[4 – 23]
The C-bank Ctune2 can be varied over a range of 16 pF in steps of 250fF for
finetuning of the FSK receive frequency. In this case the switches of the C-bank
are controlled by the bits D0 to D5 of the XTAL_TUNING register (subaddress
02H, see Table 4-5).
4.2.2.2
ASK-mode:
In transmit mode the crystal oscillator frequency is the same as in the FSK
receive case, see Figure 4-18.
In receive mode a receive frequency offset is necessary as the limiters
feedback is AC-coupled. This offset is achieved by setting the oscillator
frequency to the FSK HIGH transmit frequency, see Figure 4-17.
4.2.3
Parasitics
For the correct calculation of the external capacitors the parasitic capacitances
of the pins and the switches (C20, C21, C22) have to be taken into account.
XOUT 19
L
-R
f, CL
XIN 21
CV1
C21
Ctune1
XSWF 20
XSWA 22
CV2
CV3
XGND 23
C22
C20
Ctune2
QOSC_parasitics.wmf
Figure 4-19
Wireless Components
parasitics of the switching network
4 - 19
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
Table 4-2 Typical values of parasitic capacitances
Name
Value
C20
4,5 pF
C21
FSK-: 2,8 pF / FSK+&ASK: 2.3pF
C22
1,3 pF
With the given parasitics the actual Cv can be calculated:
[4 – 24]
Cv- = C v1 + Ctune1 + C21
( C v1 + C tune1 ) ⋅ ( C v2 + C 20 + C tune2 )
Cv+ = -------------------------------------------------------------------------------------------+ C 21
C v1 + Ctune1 + Cv2 + C20 + C tune2
[4 – 25]
( C v1 + Ctune1 ) ⋅ ( C v2 + C20 + C v3 + C22 + C tune2 )
C vm = --------------------------------------------------------------------------------------------------------------------------+ C 21
C v1 + C tune1 + C v2 + C 20 + C v3 + C 22 + C tune2
[4 – 26]
Note: Please keep in mind also to include the Pad parasitics of the circuit board.
4.2.4
Calculation of the external capacitors
1. Determination of necessary crystal frequency using formula [4-19].
e.g. fFSK- = fCOSC LOW
2. Determine corresponding CLoad applying formula [4-18].
e.g. CL FSK- = CL ±
3. Necessary CV using formula [4-17].
e.g.
CV − =
1
1
+ (2πf FSK − ) * LOSC
2
C L , FSK −
4. When the necessary Cv for the 3 frequencies (Cv- for FSK LOW, Cv+ for FSK
HIGH and Cvm for FSK-receive) are known the external capacitors and the
internal tuning caps can be calculated using the following formulas:
Wireless Components
-FSK:
C v1 + C tune1 = C v- – C 21
[4 – 27]
+FSK:
( Cv1 + C tune1 ) ⋅ ( Cv+ – C 21 )
C v2 + Ctune2 = ---------------------------------------------------------------------– C 20
( C v1 + Ctune1 ) – ( C v+ – C 21 )
[4 – 28]
FSK_RX:
( C v1 + C tune1 ) ⋅ ( C vm – C 21 )
C v3 + C tune2 = ------------------------------------------------------------------------ – C 20 – Cv2 – C 22
( C v1 + Ctune1 ) – ( C vm – C 21 )
[4 – 29]
4 - 20
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
To compensate frequency errors due to crystal and component tolerance Cv1,
Cv2 and Cv3 have to be varied. To enable this correction, half of the necessary
capacitance variation has to be realized with the internal C-banks.
If no finetuning is intended it is recommended to leave XIN (Pin 21) open. So
the parasitic capacitance of Pin 21 has no effect.
Note: Please keep in mind also to include the Pad parasitics of the circuit board.
In the suitable range for the serial capacitor, either capacitors with a tolerance
of 0.1pF or 1% are available.
A spreadsheet, which can be used to predict the total frequency error by simply
entering the crystal specification, may be obtained from Infineon.
4.2.5
FSK-switch modes
The FSK-switch can be used either in a bipolar or in a FET mode. The mode of
this switch is controlled by bit D0 of the XTAL_CONFIG register (subaddress
0EH).
In the bipolar mode the FSK-switch can be controlled by a ramp function. This
ramp function is set by the bits D1 and D2 of the XTAL_CONFIG register
(subadress 0EH). With these modes of the FSK-switch the bandwidth of the
FSK spectrum can be influenced.
When working in the FET mode the power consumption can be reduced by
about 200 µA.
The default mode is bipolar switch with no ramp function (D0 = 1, D1 = D2 = 0),
which is suitable for all bitrates.
Table 4-3 Sub Address 0EH: XTAL_CONFIG
Wireless Components
D0
D1
D2
Switch mode
Ramp time
Max. Bitrate
0
n.a.
n.a.
FET
< 0.2 µs
> 32 kBit/s NRZ
1
0
0
bipolar (default)
< 0.2 µs
> 32 kBit/s NRZ
1
1
0
bipolar
4 µs
32 kBit/s NRZ
1
0
1
bipolar
8 µs
16 kBit/s NRZ
1
1
1
bipolar
12 µs
12 kBit/s NRZ
4 - 21
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.2.6
Finetuning and FSK modulation relevant registers
Case FSK-RX or ASK-TX (Ctune2):
Table 4-4
Bit
Sub Address 02H: XTAL_TUNING
Function
Value
Description
Default
Setting for
nominal
frequency
1
D5
Nominal_Frequ_5
8pF
D4
Nominal_Frequ_4
4pF
D3
Nominal_Frequ_3
2pF
D2
Nominal_Frequ_2
1pF
D1
Nominal_Frequ_1
500fF
D0
Nominal_Frequ_0
250fF
ASK-TX
FSK-RX
(Ctune2)
0
0
0
1
0
Case FSK-TX or ASK-RX (Ctune1 and Ctune2):
Table 4-5
Bit
Sub Address 01H: FSK
Function
Value
FSK+5
8pF
D13
D12
FSK+4
4pF
D11
FSK+3
2pF
D10
FSK+2
1pF
D9
FSK+1
500fF
D8
FSK+0
250fF
D5
FSK-5
4pF
D4
FSK-4
2pF
D3
FSK-3
1pF
D2
FSK-2
500fF
D1
FSK-1
250fF
D0
FSK-0
125fF
Description
Default
0
Setting for
positive
frequency
shift: +FSK
or ASK-RX
(Ctune2)
0
1
0
1
0
0
Setting for
negative
frequency
shift: -FSK
(Ctune1)
0
1
1
0
0
Default values
In case of using the evaluation board, the crystal with its typical parameters
(fp=18.08958MHz, C1=8fF, C0=2,08pF, CL=12pF) and external capacitors with
Cv1=4.7pF, Cv2=1.8pF, Cv3=12pF each are used the following default states
are set in the device.
Table 4-6
Wireless Components
Default oscillator settings
Operating state
Frequency
ASK-TX / FSK-RX
868.3 MHz
+FSK-TX / ASK-RX
+50 kHz
-FSK-TX
-50 kHz
4 - 22
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.2.7
Chip and System Tolerances
Quartz: fp=18.08958MHz; C1=8fF; C0=2,08pF; CL=12pF (typical values)
Cv1=4.7pF, Cv2=1.8pF, Cv3=12pF
Table 4-7 Internal Tuning
Part
Frequency
tolerance @
868MHz
Rel.
tolerance
Frequency set accuracy
+/- 3kHz
+/- 3.5ppm
Temperature (-40...+85C)
+/- 5kHz
+/- 6ppm
Supply Voltage(2.1...5.5V)
+/- 1.5kHz
+/- 1.5ppm
Total
+/- 9.5kHz
+/- 11ppm
Table 4-8 Default Setup (without internal tuning & without Pin21 usage)
Part
Frequency
tolerance @
868MHz
Rel.
tolerance
Internal capacitors (+/- 10%)
+/- 8kHz
+/- 9ppm
Inductivity of the crystal oscillator
+/- 18kHz
+/- 21ppm
Temperature (-40...+85C)
+/- 5kHz
+/- 6ppm
Supply Voltage (2.1...5.5V)
+/- 1kHz
+/- 1.5ppm
Total
+/- 32kHz
+/- 37.5ppm
Tolerance values in Table 4-9 are valid, if pin 21 is not connected. Establishing
the connection to pin 21 the tolerances increase by +/- 23.5ppm (internal
capacitors +/- 20ppm, frequency set accurancy +/- 3.5ppm), if internal tuning is
not used.
Concerning the frequency tolerances of the whole system also crystal
tolerances (tuning tolerances, temperature stability, tolerance of CL) have to be
considered.
In addition to the chip tolerances also the crystal and external component
tolerances have to be considered in the tuning and non-tuning case.
In case of internal tuning: The crystal on the evaluation board has a temperature
stability of +/- 20ppm (or +/- 17kHz), which must be added to the total
tolerances.
In case of default setup (without internal tuning and without usage of pin 21) the
temperature stability and tuning tolerance of the crystal as well as the tolerance
of the external capacitors (+/- 0.1pF) have to be added. The crystal on the
evaluation board has a temperature stability of +/- 20ppm (or +/- 17kHz) and a
tuning tolerance of +/- 10ppm (or +/- 8.5 kHz).The external capacitors add a
tolerance of +/- 4ppm (or +/- 3.5kHz).
Wireless Components
4 - 23
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
The frequency stabilities of both the receiver and the transmitter and the
modulation bandwidth set the limit for the bandwidth of the IQ filter. To achieve
a high receiver sensitivity and efficient suppression of adjacent interference
signals, the narrowest possible IQ bandwidth should be realized (see Section
4.3).
4.3 IQ-Filter
The IQ-Filter should be set to values corresponding to the RF-bandwidth of the
received RF signal via the D1 to D3 bits of the LPF register (subaddress 03H).
Table 4-9 3dB cutoff frequencies I/Q Filter
D3
D2
D1
nominal f-3dB in kHz
(programmable)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
not used
350
250
200
150 (default)
100
50
not used
resulting effective
channel
bandwidth in kHz
700
500
400
300
200
100
10
50kHz
100kHz
0
150kHz
- 10
200kHz
250kHz
-20
350kHz
-30
-40
-50
-60
-70
-80
10
10 0
10 0 0
10 0 0 0
f [ kHz]
iq_filter_curve.wmf
Figure 4-20
Wireless Components
I/Q Filter Characteristics
4 - 24
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
effective channel bandwidth
-f
f
f
3dB
IQ Filter
3dB
IQ Filter
f
iq_char.wmf
Figure 4-21
IQ Filter and frequency characteristics of the receive system
4.4 Data Filter
The Data-Filter should be set to values corresponding to the bandwidth of the
transmitted Data signal via the D4 to D7 bits of the LPF register (subaddress
03H).
Table 4-10 3dB cutoff frequencies Data Filter
Wireless Components
D7
D6
D5
D4
nominal f-3dB in kHz
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
5
7 (default)
9
11
14
18
23
28
32
39
49
55
64
73
86
102
4 - 25
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.5 Limiter and RSSI
The I/Q Limiters are DC coupled multistage amplifiers with offset-compensating
feedback circuit and an overall gain of approximately 80dB each in the
frequency range of 100Hz up to 350kHz. Receive Signal Strength Indicator
(RSSI) generators are included in both limiters which produce DC voltages that
are directly proportional to the input signal level in the respective channels. The
resulting I- and Q-channel RSSI-signals are summed to the nominal RSSI
signal.
I
Limiter
I- Filter
fg
33
C
RSSI
32
CQ2x
34
CQ2
35
Cc
CI2x
36
CQ1x
37
CQ1
CI1x
38
CI2
Cc
Cc
CI1
Cc
29 RSSI
31
Quadr.
Corr.
37k
Σ
Q- Filter
Q
Limiter
fg
Quadr.
Corr.
limiter input.wmf
Figure 4-22
Limiter and Pinning
The DC offset compensation needs 2.2ms after Power On or Tx/Rx switch. This
time is hard wired and independent from external capacitors CC on pins 31 to
38. The maximum value for this capacitors is 47nF.
RSSI accuracy settling time = 2.2ms + 5*RC=2.2ms+5*37k*2.2nF=2.6ms
R - internal resistor; C - external capacitor at Pin 29
Table 4-11 Limiter Bandwidth
Cc
f3dB
lower limit
[Hz]
f3dB
upper
limit
Comment
220
100
IQ Filter
setup time not
guaranteed
100
220
- ll -
setup time not
guaranteed
47
470
- ll -
Eval Board
22
1000
- ll -
10
2200
- ll -
[nF]
Wireless Components
4 - 26
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
v [dB]
80
0
f
f
f
3dB
IQ Filter
3dB
lower limit
f
3dB
Limiter
limiter_char.wmf
Figure 4-23
Limiter frequency characteristics
ADC
1300
1200
1100
1000
900
RSSI /mV
800
700
600
500
high gain
400
low gain
300
200
100
0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
RF /dB m
Figure 4-24
Wireless Components
Typ. RSSI Level (Eval Board) @3V
4 - 27
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.6 Data Slicer - Slicing Level
The data slicer is an analog-to-digital converter. It is necessary to generate a
threshold value for the negative comparator input (data slicer). The TDA5250
offers an RC integrator and a peak detector which can be selected via logic.
Independent of the choice, the peak detector outputs are always active.
4.6.1
RC Integrator
Table 4-12 Sub Address 00H: CONFIG
Bit
D15
Function
Description
SLICER
Default
0= LP, 1= Peak Detector
SET
0
0
Necessary external component (Pin14): CSLC
This integrator generates the mean value of the data filter output. For a stable
threshold value, the cut-off frequency has to be lower than the lowest signal
frequency. The cutoff frequency results from the internal resistance R=100kΩ
and the external capacitor CSLC on Pin14.
Cut-off frequency:
f
cut − off
1
< Min {f
2 π ⋅100 kΩ ⋅ C SLC
=
Signal
}
[4 – 30]
Component calculation: (rule of thumb)
TL – longest period of no signal change
C
SLC
≥
3 ⋅TL
100 k Ω
[4 – 31]
DataSlicer
+
-
Contr.
Logic
DATA
28
Slicer Threshold
+ Peak
Detector
PDP
13
100k
Data
Filter
Signal
100k
R
SLC
14
CSLC
100k
- Peak
Detector
PDN
12
Vcc
SLC_RC.wmf
Figure 4-25
Wireless Components
Slicer Level using RC Integrator
4 - 28
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.6.2
Peak Detectors
Table 4-13 Sub Address 00H: CONFIG
Bit
D15
Function
SLICER
Description
Default
0= LP, 1= Peak Detector
SET
0
1
The TDA5250 has two peak detectors built in, one for positive peaks in the
data stream and the other for the negative ones.
Necessary external components:
- Pin12: CN
- Pin13: CP
DataSlicer
+
Contr.
Logic
DATA
28
Slicer Threshold
+ Peak
Detector
PDP
13
Data
Filter
Signal
R1 100k
100k
CP
SLC
14
R
Vcc
R2 100k
CN
- Peak
Detector
PDN
12
Vcc
SLC_PkD.wmf
Figure 4-26
Slicer Level using Peak Detector
For applications requiring fast attack and slow release from the threshold value
it is reasonable to use the peak detectors. The threshold value is generated by
an internal voltage divider. The release time is defined by the internal resistance values and the external capacitors.
Wireless Components
τ
posPkD
τ
negPkD
4 - 29
= 100 k Ω ⋅ C p
[4 – 32]
= 100 k Ω ⋅ C
[4 – 33]
n
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
Signal
τ posPkD
Signal
Pos. Peak Detector (pin13)
Threshold SLC(pin14)
Neg. Peak Detector (pin12)
τ negPkD
t
PkD_timing.wmf
Figure 4-27
Peak Detector timing
Component calculation: (rule of thumb)
Cp ≥
Cn
4.6.3
≥
2 ⋅ TL1
100kΩ
[4 – 34]
TL1 – longest period of no signal change (LOW signal)
2 ⋅ TL2
100kΩ
[4 – 35]
TL2 – longest period of no signal change (HIGH signal)
Peak Detector - Analog output signal
The TDA5250 data output can be digital (pin 28) or in analog form by using the
peak detector output and changing some settings.
To get an analog data output the slicer must be set to lowpass mode (Reg. 0,
D15 = LP = 0) and the peak detector capacitor at pin 12 or 13 has to be changed
to a resistor of about 47kOhm.
DataSlicer
+
Contr.
Logic
DATA
28
Slicer Threshold
+ Peak
Detector
PDP
13
47k
100k
Data
Filter
Signal
100k
R
SLC
14
CSLC
100k
- Peak
Detector
PDN
12
Vcc
PkD_analog.wmf
Figure 4-28
Wireless Components
Peak Detector as analog Buffer (v=1)
4 - 30
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.6.4
Peak Detector – Power Down Mode
For a safe and fast threshold value generation the peak detector is turned on
by the sequencer circuit (see Section 3.4.18) only after the entire receiving
path is active.
In the off state the output of the positive peak detector is tied down to GND and
the output of the negative peak detector is pulled up to VCC.
Logic
Power Down Mode
0V
+ Peak
Detector
PDP
13
off
Data
Filter
CP
R1
100k
R2
100k
SLC
14
Vcc
CN
- Peak
Detector
PDN
12
off
Vcc
Vcc
PKD_PWDN.wmff
Figure 4-29
Peak detector - power down mode
Signal
Data Signal
Vcc
Neg. Peak Detector (pin12)
Threshold (pin14)
Pos. Peak Detector (pin13)
0
Power ON
Power Down
2,2ms
Power ON
Peak Detector Power ON
t
PkD_PWDN3.wmf
Figure 4-30
Wireless Components
Power down mode
4 - 31
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.7 Data Valid Detection
In order to detect valid data two criteria must be fulfilled.
One criteria is the data rate, which can be set in register 06h and 07h. The other
one is the received RF power level, which can be set in register 08h in form of
the RSSI threshold voltage. Thus for using the data valid detection FSK
modulation is recommended.
Timing for data detection looks like the following. Two settings are possible:
„Continuous“ and „Single Shot“, which can be set by D5 and D6 in register 00H.
Data
t
Sequenzer enables
data detection
t
Counter Reset
re se t
re se t
t
Gate time
Compare with single
TH and latch result
Compare with double
TH and latch result
(Frequency) Window
Count Complete
sta rt o f co n ve rsio n
co u nt
co u n t
t
co m p .
co m p .
t
co m p .
t
re a d y*
p o ssib le sta rt o f n e xt co n ve rsio n
t
Frequ_Detect_Timing_continuous.wmf
Figure 4-31
Frequency Detection timing in continuous mode
Note 1: Chip internal signal „Sequencer enables data detection“ has a LOW to
HIGH transition about 2.6ms after RX is activated (see Figure 3-15).
Note 2: The positive edge of the „Window Count Complete“ signal latches the
result of comparison of the analog to digital converted RSSI voltage with TH3
(register 08H). A logic combination of this output and the result of the
comparison with single/double THx defines the internal signal „data_valid“.
Figure 4-31 shows that the logic is ready for the next conversion after 3 periods
of the data signal.
Wireless Components
4 - 32
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
Timing in Single Shot mode can be seen in the subsequent figure:
Data
t
Sequenzer enables
data detection
t
Counter Reset
re se t
t
Gate time
co u nt
t
Compare with single
TH and latch result
co m p .
t
Compare with double
TH and latch result
co m p .
t
(Frequency) Window
Count Complete
re a d y*
sta rt o f co n ve rsio n
n o p o ssib le sta rt o f n e xt co n ve rsio n
b e cau se o f S in g le S h o t M o d e
t
Frequ_Detect_Timing_singleShot_wmf
Figure 4-32
4.7.1
Frequency Detection timing in Single Shot mode
Frequency Window for Data Rate Detection
The high time of data is used to measure the frequency of the data signal. For
Manchester coding either the data frequency or half of the data frequency have
to be detected corresponding to one high time or twice the high time of data
signal.
A time period of 3*2*T is necessary to decide about valid or invalid data.
T
2*T
DATA
t
0
0
1
0
T2
T1
possible
GATE 1
t
0
2*T2
2*T1
possible
GATE 2
t
0
1
window_count_timing.wmf
Figure 4-33
Wireless Components
Window Counter timing
4 - 33
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
Example to calculate the thresholds for a given data rate:
- Data signal manchester coded
- Data Rate: 2kbit/s
- fclk= 18,0896 MHz
Then the period equals to
2⋅T =
1
= 0,5ms
2kbit/s
[4 – 36]
respectively the high time is 0,25ms.
We set the thresholds to +-10% and get: T1= 0,225ms and T2= 0,275ms
The thresholds TH1 and TH2 are calculated with following formulas:
TH1 = T1⋅
f clk
4
[4 – 37]
TH2 = T2 ⋅
f clk
4
[4 – 38]
This yields the following results:
TH1~ 1017= 001111111001b
TH2~ 1243= 010011011011b
which have to be programmed into the D0 to D11 bits of the COUNT_TH1 and
COUNT_TH2 registers (subaddresses 06H and 07H), respectively.
Default values (window counter inactive):
TH1= 000000000000b
TH2= 000000000001b
Note: The timing window of +-10% of a given high time T in general does not
correspond to a frequency window +-10% of the calculated data frequency.
Wireless Components
4 - 34
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.7.2
RSSI threshold voltage - RF input power
The RF input power level is corresponding to a certain RSSI voltage, which can
be seen in Section 4.5. The threshold TH3 of this RSSI voltage can be
calculated with the following formula:
TH3
=
desired
RSSI
threshold
1.2V
voltage
⋅(2
6
− 1)
[4 – 39]
As an example a desired RSSI threshold voltage of 500mV results in
TH3~26=011010b, which has to be written into D0 to D5 of the RSSI_TH3
register (sub address 08H).
Default value (RSSI detection inactive):
TH3=111111b
Wireless Components
4 - 35
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.8 Calculation of ON_TIME and OFF_TIME
ON= (216-1)-(fRC*tON)
[4 – 40]
OFF=( 216-1)-(fRC*tOFF)
[4 – 41]
fRC= Frequency of internal RC Oszillator
Example: tON= 0,005s, tOFF= 0,055s, fRC= 32300Hz
ON= 65535-(32300*0,005) ~ 65373= 1111111101011101b
OFF= 65535-(32300*0,055) ~ 63758= 1111100100001110b
The values have to be written into the D0 to D15 bits of the ON_TIME and
OFF_TIME registers (subaddresses 04H and 05H).
Default values:
ON= 65215 = 1111111011000000b
OFF= 62335 = 1111001110000000b
tON ~10ms @ fRC= 32kHz
tOFF ~100ms @ fRC= 32kHz
Wireless Components
4 - 36
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.9 Example for Self Polling Mode
The settings for Self Polling Mode depend very much on the timing of the
transmitted Signal. To create an example we consider following data structure
transmitted in FSK.
4 F ra m e s
D a ta
D a ta
D a ta
D a ta
t [m s]
50m s
50m s
400m s
F ra m e d e ta ils
t [m s]
P re a m b le
D a ta
S yn c
t [m s]
S yn cro n isa tio n P re a m b le
data_timing011.wmf
Figure 4-34
Example for transmitted Data-structure
According to existing synchronization techniques there are some
synchronization bursts in front of the data added (code violation!). A minimum
of 4 Frames is transmitted. Data are preferably Manchester encoded to get
fastest respond out of the Data Rate Detection.
Target Application:
- received Signal has code violation as described before
- total mean current consumption below 1mA
- data reception within max. 400ms after first transmitted frame
Wireless Components
4 - 37
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
One possible Solution:
tON = 15ms, tOFF= 135ms
This gives 15ms ON time of a total period of 150ms which results in max. 0.9mA
mean current consumption in Self Polling Mode. The resulting worst case timing
is shown in the following figure:
C a se A :
D a ta
D a ta
D a ta
D a ta
t [m s]
50m s 15m s
135m s
µ P e n a b le s R e ce ive r
u n til D a ta co m p le te d
In te rru p t
due PwdDD
C a se B :
D a ta
D a ta
D a ta
D a ta
t [m s]
50m s
15m s
135m s
µ P e n a b le s R e ce ive r
u n til D a ta co m p le te d
In te rru p t
due PwdDD
C a se C :
D a ta
D a ta
D a ta
D a ta
t [m s]
50m s
15m s
... R e ce ive r e n a b le d
135m s
µ P e n a b le s R e ce ive r
u n til D a ta co m p le te d
In te rru p t
due PwdDD
data_timing021.wmf
Figure 4-35
3 possible timings
Description:
Assumption: the ON time comes right after the first frame (Case A). If OFF time
is 135ms the receiver turns on during Sync-pulses and the PwdDD- pulse
wakes up the µP.
If the ON time is in the center of the 50ms gap of transmission (Case B), the
Data Detect Logic will wake up the µP 135ms later.
If ON time is over just before Sync-pulses (Case C), next ON time is during Data
transmission and Data Detect Logic will trigger a PwdDD- pulse to wake up the
µP.
Note: In this example it is recommended to use the Peak Detector for slicer
threshold generation, because of its fast attack and slow release characteristic.
To overcome the data zero gap of 50ms larger external capacitors than noted
in Section 5.4 at pin12 and 13 are recommended. Further information on
calculating these components can be taken from Section 4.6.2.
Wireless Components
4 - 38
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.10 Sensitivity Measurements
4.10.1
Test Setup
The test setup used for the measurements is shown in the following figure. In
case of ASK modulation the Rohde & Schwarz SMIQ generator, which is a vector signal generator, is connected to the I/Q modulation source AMIQ. This
"baseband signal generator" is in turn controlled by the PC based software
WinQSIM via a GPIB interface. The AMIQ generator has a pseudo random
binary sequence (PRBS) generator and a bit error test set built in. The resulting
I/Q signals are applied to the SMIQ to generate a ASK (OOK) spectrum at the
desired RF frequency.
Data is demodulated by the TDA5250 and then sent back to the AMIQ to be
compared with the originally sent data. The bit error rate is calculated by the bit
error rate equipment inside the AMIQ.
Baseband coding in the form of Manchester is applied to the I signal as can be
seen in the subsequent figure.
P e rs o n a l C o m p u te r
S o ftw a re
W inIQSIM
G P IB /
R S 232
C lo ck
A M IQ B E R T
(B it E rro r R a te
T e s t S e t)
M a rke r O u tp u t
D a ta
R o h d e & S c h w a rz
I/Q M o d u la tio n S o u rc e
AM IQ
I
Q
M a n ch e ste r
E n co d e r
M a n ch e ste r
D e co d e r
D AT Aout
R o h d e & S c h w a rz
V e c to r S ig n a l G e n e ra to r
S M IQ 0 3
A S K / F S K R F S ig n a l
R F in
DUT
T ra n sce ive r T e stb o a rd
T D A5250
TestSetup.wmf
Figure 4-36
Wireless Components
BER Test Setup
4 - 39
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
In the following figures the RF power level shown is the average power level.
These investigations have been made on an Infineon evaluation board using a
data rate of 4 kBit/s with manchester encoding and a data filter bandwidth of
7 kHz. This is the standard configuration of our evaluation boards. All these
measurements have been performed with several evaluation boards, so that
production scattering and component tolerances are already included in these
results.
Regarding the data filter bandwidth it has to be mentioned that a data rate of
4 kBit/s using manchester encoding results in a data frequency of 2 kHz to
4 kHz depending on the occurring data pattern. The test pattern given by the
AMIQ is a pseudo random binary sequency (PRBS9) with a 9 bit shift register.
This pattern varies the resulting data frequency up to 4 kHz.
The best sensitivity performance can be achieved using a data filter bandwidth
of 1.25 times the maximum occuring data frequency.
The IQ filter setting is depending on the modulation type. ASK needs an IQ filter
of 50kHz, 50kHz deviation at FSK recommend a 100kHz IQ filter and 100kHz
deviation were measured with a 150kHz IQ filter
A very practicable configuration is to set the chip-internal adjustable IQ filter to
the sum of FSK peak deviation and maximum datafrequency. Concerning these
aspects the bandwidth should be chosen small enough. With respect to both,
the crystal tolerances and the tolerances of the crystal oscillator circuit of
receiver and transmitter as well, a too small IQ filter bandwidth will reduce the
sensitivity again. So a compromise has to be made. For further details on chip
tolerances see also Section 4.2.7
Wireless Components
4 - 40
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.10.2
Sensitivity depending on the ambient Temperature
Demonstrating a wide band of application possibilities the temperature behavior
must not be forgotten. In automotive systems the required temperature range is
from -40 °C to +85 °C. The receivers very good performance is documented
in the following graph. The selected supply voltage is 5V, the influence of the
supply voltage can be seen in the following Section 4.10.3
The IQ filter setting can be taken from the legend of Figure 4-37.
BER_Temp_5V.wmf
Figure 4-37
Temperature Behaviour
Figure 4-37 shows that ASK as well as FSK sensitivity is in the range of -110 to
-111dBm at 20°C ambient temperature for a BER of 2E-3.
Notice that the sensitivity variation in this temperature range of -40 °C to
+85 °C is only about 1.5 to 2 dB.
Wireless Components
4 - 41
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.10.3
BER performance depending on Supply Voltage
Due to the wide supply voltage range of this transeiver chip also the sensitivity
behaviour over this parameter is documented is the subsequent graph.
BER_VCC_20°C..wmf
Figure 4-38
BER supply voltage
Please notice the tiny sensitivity changes of 1.5 to 2.5dB, when variing the
supply voltage.
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4 - 42
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.10.4
Datarates and Sensitivity
The TDA 5250 can handle datarates up to 64kbit/s, as can be taken from the
following figure. (see also Section 5.1.4)
BER_Datarate.wmf
Figure 4-39
Wireless Components
Datarates and Sensitivity
4 - 43
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.10.5
Sensitivity at Frequency Offset
Applying the test setup in Figure 4-36 even a wide offset in the received
frequency spectrum results only in a slight decrease of receiving sensitivity. At
an offset of 100kHz one of the two 50kHz FSK peaks is at the 3dB border of the
IQ filter (150kHz), which is the reason for the decline of the sensitivity (see point
A in Figure 4-40).
A frequency offset of 50kHz (FSK deviation: 50kHz) increases the data jitter of
the demodulated signal and therefore results in little loss of sensitivity (see point
B in Figure 4-40).
In this case one of the peaks of the FSK-spectrum lies in the DC-blocking notch
of the baseband limiters.
BER_FrequOffset_FSK_3V..wmf
Figure 4-40
Wireless Components
BER Frequency Offset
4 - 44
Specification, July 2002
TDA 5250 D2
preliminary
Applications
confidential
4.11 Default Setup
Default setup is hard wired on chip and effective after a reset or return of power
supply.
Table 4-14 Default Setup
Parameter
Value
IQ-Filter Bandwidth
Comment
150kHz
Data Filter Bandwidth
7kHz
Limiter lower fg
470Hz
47nF
RC
10nF
Nom. Frequency Capacity intern (ASK TX,
FSK RX)
4.5pF
868.3MHz
FSK+ Frequency Capacity intern (FSK+,
ASK RX)
2.5pF
+50kHz
FSK- Frequency Capacity intern (FSK-)
1.5pF
-50kHz
LNA Gain
HIGH
Power Amplifier
HIGH
+10dBm
RSSI accuracy settling time
2.6ms
2.2nF
ADC measurement
RSSI
ON-Time
10ms
OFF-Time
100ms
Clock out RX PowerON
1MHz
Clock out TX PowerON
1MHz
Slicing Level Generation
Clock out RX PowerDOWN
-
Clock out TX PowerDOWN
-
XTAL modulation switch
XTAL modulation shaping
Wireless Components
IFXBoard
bipolar
off
RX / TX
-
Jumper
ASK/FSK
-
Jumper
PwdDD
PWDN
Jumper
removed
Operating Mode
Slave
4 - 45
Specification, July 2002
5
TDA 5250 D2 Reference
Contents of this Chapter
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.2
5.3
5.4
Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Test Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
TDA 5250 D2
preliminary
TDA 5250 D2 Reference
confidential
5.1 Electrical Data
5.1.1
Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even
momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Ratings
#
Parameter
Symbol
Limit Values
min
max
Unit
1
Supply Voltage
Vs
-0.3
5.8
V
2
Junction Temperature
Tj
-40
+125
°C
3
Storage Temperature
Ts
-40
+150
°C
4
Thermal Resistance
RthJA
114
K/W
5
ESD integrity, all pins
VESD
tbd
kV
5.1.2
tbd
Remarks
HBM
according to
MIL STD
883D,
method
3015.7
Operating Range
Within the operational range the IC operates as explained in the circuit description.
Table 5-2 Operating Range
#
Parameter
Symbol
Limit Values
min
max
Unit
1
Supply voltage
VS
2.1
5.5
V
2
Ambient temperature
TA
-40
85
°C
3
Receive frequency
fRX
868
870
MHz
4
Transmit frequency
fTX
868
870
MHz
Wireless Components
5-2
Test Conditions
L
Item
Specification, July 2002
TDA 5250 D2
preliminary
TDA 5250 D2 Reference
confidential
5.1.3
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient temperature range. Typical characteristics are the
median of the production.
Table 5-3 AC/DC Characteristics with TA = 25 °C, VVCC = 2.1 ... 5.5 V
#
Parameter
Symbol
Limit Values
min
typ
Unit
Test Conditions
L
Item
max
RECEIVER Characteristics
1
Supply current RX FSK
IRX_FSK
9
mA
3V, FSK, Default
2
Supply current RX FSK
IRX_FSK
9.5
mA
5V, FSK, Default
3
Supply current RX ASK
IRX_ASK
8.6
mA
3V, ASK, Default
4
Supply current RX ASK
IRX_ASK
9.1
mA
5V, ASK, Default
5
Sensitivity FSK
10-3 BER
RFsens
-109
dBm
[email protected], 4kBit/s
Manch. Data, Default
7kHz datafilter,
100kHz IQ filter
■
6
Sensitivity ASK
10-3 BER
RFsens
-109
dBm
ASK, 4kBit/s Manch.
data, Default setup
7kHz datafilter,
50kHz IQ filter
■
7
Power down current
IPWDN_RX
5
nA
5.5V, all power down
8
System setup time (1st
power on or reset)
tSYSSU
9
Clock Out setup time
tCLKSU
10
Receiver setup time
tRXSU
1.54
2.2
11
Data detection setup
time
tDDSU
1.82
12
RSSI stable time
tRSSI
1.82
13
Data Valid time
14
4
8
12
0.5
ms
ms
stable CLKDIV output
signal
2.86
ms
DATA out (valid or
invalid)
2.6
3.38
ms
Begin of Data
detection
2.6
3.38
ms
RFin -100dBm
see chapter 4.5
tData_Valid
3.35
ms
4kBit/s Manch.
detected (valid)
Input P1dB, high gain
P1dB
-48dBm
dBm
3V, Default, high gain
■
15
Input P1dB, low gain
P1dB_low
-32dBm
dBm
3V, Default, low gain
■
16
Selectivity
VBL_1MHz
50
dB
fRF+/-1MHz, Default,
RFsens+3dB
■
17
LO leakage
PLO
-98
dBm
1157.73MHz
■
Wireless Components
5-3
Specification, July 2002
TDA 5250 D2
preliminary
TDA 5250 D2 Reference
confidential
Table 5-3 AC/DC Characteristics with TA = 25 °C, VVCC = 2.1 ... 5.5 V
#
Parameter
Symbol
Limit Values
min
typ
Unit
Test Conditions
L
Item
max
TRANSMITTER Characteristics
1
Supply current TX, FSK
ITX
9.4
mA
2.1V, high power
1
2
Supply current TX, FSK
ITX
11.9
mA
3V, high power
1
3
Supply current TX, FSK
ITX
14.6
mA
5V, high power
1
4
Output power
Pout
6
dBm
2.1V, high power
■
5
Output power
Pout
9
dBm
3V, high power
■
6
Output power
Pout
13
dBm
5V, high power
■
7
Supply current TX, FSK
ITX
4.1
mA
2.1V, low power
1
8
Supply current TX, FSK
ITX
4.9
mA
3V, low power
1
9
Supply current TX, FSK
ITX
6.8
mA
5V, low power
1
10
Output power
Pout_low
-30
dBm
2.1V, low power
■
11
Output power
Pout_low
-22
dBm
3V, low power
■
12
Output power
Pout_low
-3
dBm
5V, low power
■
13
Power down current
IPWDN_TX
5
nA
14
Clock Out setup time
tCLKSU
0.5
15
Transmitter setup time
tTXSU
16
Spurious fRF+/-fclock
Pclock
17
Spurious fRF+/-fXTAL
P1st
18
Spurious 2nd harmonic
19
Spurious 3rd harmonic
5.5V, all power down
ms
stable CLKDIV output
signal
ms
PWDN-->PON or
RX-->TX
■
dBm
3V, 50Ohm Board,
Default (1MHz)
■
-66
dBm
3V, 50Ohm Board
■
P2nd
-40
dBm
3V, 50Ohm Board
■
P3rd
-50
dBm
3V, 50Ohm Board
■
0.77
1.1
1.43
1: without pin diode current (RX/TX-switch)
[email protected]; [email protected]; [email protected]
Wireless Components
5-4
Specification, July 2002
TDA 5250 D2
preliminary
TDA 5250 D2 Reference
confidential
Table 5-4 AC/DC Characteristics with TA = 25 °C, VVCC = 2.1 ... 5.5 V
#
Parameter
Symbol
Limit Values
min
typ
Unit
Test Conditions
L
Item
max
GENERAL Characteristics
1
Power down current
timer mode (standby)
IPWDN_32k
9
uA
3V, 32kHz clock on
2
Power down current
timer mode (standby)
IPWDN_32k
11
uA
5V, 32kHz clock on
3
Power down current
with XTAL ON
IPWDN_Xtl
750
uA
3V, CONFIG9=1
4
Power down current
with XTAL ON
IPWDN_Xtl
860
uA
5V, CONFIG9=1
5
32kHz oscillator freq.
f32kHz
6
XTAL startup time
tXTAL
0.5
ms
7
Load capacitance
CC0max
5
pF
■
8
Serial resistance of the
crystal
RRmax
Ω
■
9
Input inductance XOUT
LOSC
2.7
uH
■
10
FSK demodulator gain
GFSK
2.4
mV/
kHz
11
[email protected]
U-120dBm
0.35
V
default setup
■
12
[email protected]
U-100dBm
0.55
V
default setup
■
13
[email protected]
U-70dBm
1
V
default setup
■
14
[email protected]
U-50dBm
1.2
V
default setup
■
15
RSSI Gradient
GRSSI
14
mV/
dB
default setup
■
16
IQ-Filter bandwidth
f3dB_IQ
115
150
185
kHz
Default setup
■
17
Data Filter bandwidth
f3dB_LP
5.3
7
8.7
kHz
Default setup
■
18
Vcc-Vtune RX, Pin3
Vcc-tune,RX
0.5
1
1.6
V
fRef=18.08956MHz
19
Vcc-Vtune TX, Pin3
Vcc-tune,TX
0.5
1.1
1.6
V
fRef=18.08956MHz
Wireless Components
24
32
40
100
5-5
kHz
IFX Board with Crystal
Q1 as specified in
Section 5.4
■
Specification, July 2002
TDA 5250 D2
preliminary
TDA 5250 D2 Reference
confidential
5.1.4
Digital Characteristics
I2C Bus Timing
BusMode = LOW
tBUF
BusData
tHD.STA
tR
tSP
tF
tLOW
tHD.STA
BusCLK
tHD.DAT
tHIGH
tSU.DAT
tSU.STA
tSU.STO
tHIGH
EN
pulsed or
mandatory low
tSU.ENASDA
tSU.ENASDA
tSU.ENASDA
Figure 5-1
I2C Bus Timing
3-wire Bus Timing
BUS_MODE = HIGH
SDA
tSP
tLOW t
R
SCL
tSU.STA
tF
tHD.DAT
tHIGH
tSU.DAT
tSU.STO
BUS_ENA
tWHEN
Figure 5-2
Wireless Components
3-wire Bus Timing
5-6
Specification, July 2002
TDA 5250 D2
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TDA 5250 D2 Reference
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Table 5-5 Digital Characteristics with TA = 25 °C, VVdd = 2.1 ... 5.5 V
#
Parameter
Symbol
Limit Values
min
typ
max
Unit
Test Conditions
L
Item
1
Data rate TX ASK
fTX.ASK
10
25
kBaud
PRBS9,
[email protected]+10dBm
■
1
2
Data rate TX ASK
fTX.ASK
10
64
kBaud
PRBS9,
[email protected]
■
1
3
Data rate TX FSK
fTX.FSK
10
40
kBaud
PRBS9,
[email protected]+10dBm
@50kHz dev.
■
1
4
Data rate RX ASK
fRX.ASK
10
64
kBaud
PRBS9, Manch.
■
5
Data rate RX FSK
fRX.FSK
10
64
kBaud
PRBS9,
[email protected] dev.
■
6
Digital Inputs
High-level Input Voltage
Low-level Input Voltage
VIH
VIL
Vdd
0.2
V
V
RXTX Pin 5
TX operation, int. controlled
VOL
V
V
@Vdd=3V
Isink=800uA
Isink=3mA
■
0.4
1.15
tr
tf
ns
ns
V
V
@Vdd=3V
load 10pF
load 10pF
Isorce=350uA
Isink=400uA
■
35
30
Vdd-0.4
0.4
50
ns
Vdd=5V
■
0.4
V
3mA sink current
Vdd=5V
■
400
kHz
Vdd=5V
■
7
8
CLKDIV Pin 26
trise (0.1*Vdd to 0.9*Vdd)
tfall (0.9*Vdd to 0.1*Vdd)
Output High Voltage
Output Low Voltage
■
Vdd-0.2
0
VOH
VOL
Bus Interface Characteristics
9
Pulse width of spikes which
must be suppressed by the
input filter
tSP
10
LOW level output voltage at
BusData
VOL
11
SLC clock frequency
fSLC
0
12
Bus free time between
STOP and START condition
tBUF
1.3
µs
only I2C mode
Vdd=5V
■
13
Hold time (repeated) START
condition.
tHO.STA
0.6
µs
After this period, the first
clock pulse is generated,
only I2C
■
14
LOW period of BusCLK
clock
tLOW
1.3
µs
Vdd=5V
■
15
HIGH period of BusCLK
clock
tHIGH
0.6
µs
Vdd=5V
■
16
Setup time for a repeated
START condition
tSU.STA
0.6
µs
only I2C mode
■
Wireless Components
0
5-7
Specification, July 2002
TDA 5250 D2
preliminary
TDA 5250 D2 Reference
confidential
Table 5-5 Digital Characteristics with TA = 25 °C, VVdd = 2.1 ... 5.5 V
#
Parameter
Symbol
Limit Values
min
typ
Unit
Test Conditions
L
max
17
Data hold time
tHD.DAT
0
ns
Vdd=5V
■
18
Data setup time
tSU.DAT
100
ns
Vdd=5V
■
19
Rise, fall time of both BusData and BusCLK signals
tR, tF
20+
0.1Cb
ns
Vdd=5V
■
20
Setup time for STOP condition
tSU.STO
0.6
µs
only I2C mode
Vdd=5V
■
21
Capacitive load for each bus
line
Cb
pF
Vdd=5V
■
22
Setup time for BusCLK to
EN
0.6
µs
only 3-wire mode
Vdd=5V
■
0.6
µs
Vdd=5V
■
23
H-pulsewidth (EN)
tSU.SCLE
300
400
N
tWHEN
Item
2
1: limited by transmission channel bandwidth and depending on transmit power level;
ETSI regulation EN 300 220 fullfilled, see Section 4.1
2: Cb= capacitance of one bus line
Wireless Components
5-8
Specification, July 2002
TDA 5250 D2
preliminary
TDA 5250 D2 Reference
confidential
5.2 Test Circuit
The device performance parameters marked with ■ in Section 5.1.3 were measured on an Infineon evaluation board (IFX board).
TDA5250_v41.schematic.pdf
Figure 5-3
Wireless Components
Schematic of the Evaluation Board
5-9
Specification, July 2002
TDA 5250 D2
preliminary
TDA 5250 D2 Reference
confidential
5.3 Test Board Layout
Gerberfiles for this Testboard are available on request.
TDA5250_v41_layout.pdf
Figure 5-4
Layout of the Evaluation Board
Note: The LNA and PA matching network was designed for minimum required
space and maximum performance and thus via holes were deliberately placed
into solder pads.
In case of reproduction please bear in mind that this may not be suitable for all
automatic soldering processes.
Note 2: Please keep in mind not to layout the CLKDIV line directly in the neighborhood of the crystal and the associated components.
Wireless Components
5 - 10
Specification, July 2002
TDA 5250 D2
preliminary
TDA 5250 D2 Reference
confidential
5.4 Bill of Materials
Table 5-6 Bill of Materials
Wireless Components
Reference
Value
Specification
Tolerance
R1
4k7
0603
+/-5%
R2
10Ω
0603
+/-5%
R3
---
0603
+/-5%
R4
1M
0603
+/-5%
R5
4k7
0603
+/-5%
R6
4k7
0603
+/-5%
R7
4k7
0603
+/-5%
R8
6k8
0603
+/-5%
R9
180
0603
+/-5%
R10
180
0603
+/-5%
R11
270
0603
+/-5%
R12
15k
0603
+/-5%
R13
10k
0603
+/-5%
R14
180
0603
+/-5%
R15
180
0603
+/-5%
R16
1M
0603
+/-5%
R17
1M
0603
+/-5%
R18
1M
0603
+/-5%
R19
560
0603
+/-5%
R20
1k
0603
+/-5%
R21
10
0603
+/-5%
R22
0
0603
+/-5%
R23
10
0603
+/-5%
C1
22pF
0603
+/-1%
C2
1pF
0603
+/-0,1pF
C3
5,6pF
0603
+/-0,1pF
C4
2,2pF
0603
+/-0,1pF
C5
1nF
0603
+/-5%
C6
1nF
0603
+/-5%
C7
15pF
0603
+/-1%
C8
---
0603
+/-0,1pF
C9
47pF
0603
+/-1%
C10
22pF
0603
+/-1%
C11
---
0603
+/-5%
C12
10nF
0603
+/-10%
C13
10nF
0603
+/-10%
5 - 11
Specification, July 2002
TDA 5250 D2
preliminary
TDA 5250 D2 Reference
confidential
Table 5-6 Bill of Materials
Wireless Components
Reference
Value
Specification
Tolerance
C14
10nF
0603
+/-10%
C15
4.7pF
0603
+/-0,1pF
C16
1.8pF
0603
+/-0,1pF
C17
12pF
0603
+/-1%
C18
10nF
0603
+/-10%
C19
2,2nF
0603
+/-10%
C20
47nF
0603
+/-10%
C21
47nF
0603
+/-10%
C22
47nF
0603
+/-10%
C23
47nF
0603
+/-10%
C24
100nF
0603
+/-10%
C25
100nF
0603
+/-10%
C26
---
0603
+/-10%
C27
100nF
0603
+/-10%
C28
100nF
0603
+/-10%
C29
100nF
0603
+/-10%
C30
---
0603
+/-10%
L1
68nH
SIMID 0603-C
(EPCOS)
+/-2%
L2
12nH
SIMID 0603-C
(EPCOS)
+/-2%
L3
8.2nH
SIMID 0603-C
(EPCOS)
+/-0.2nH
IC1
TDA5250 D2
PTSSOP38
IC2
ILQ74
IC3
SFH6186
Q1
18.08958MHz
S1
1-pol.
T1
BC847B
SOT-23 (Infineon)
D1, D2
BAR63-02W
SCD-80 (Infineon)
X1, X2
SMA-socket
X5
SubD 25p.
5 - 12
Telcona:
C0=2,1pF
C1=8fF, CL=12pF
Specification, July 2002