PHILIPS BUK9728-55A

BUK9728-55A
N-channel TrenchMOS™ logic level FET
Rev. 02 — 10 June 2004
M3D308
Product data
1. Description
N-channel enhancement mode field-effect power transistor in a plastic package using
TrenchMOS™1 technology, featuring very low on-state resistance.
Product availability:
BUK9728-55A in SOT186A (TO-220F).
2. Features
■
■
■
■
TrenchMOS™ technology
Q101 compliant
150 °C rated
Logic level compatible.
3. Applications
■ Automotive and general purpose power switching:
◆ 12 V and 24 V loads
◆ Motors, lamps and solenoids.
4. Pinning information
Table 1:
Pinning - SOT186A, simplified outline and symbol
Pin
Description
1
gate (g)
2
drain (d)
3
source (s)
mb
mounting base;
isolated
Simplified outline
Symbol
mb
d
g
mbb076
1 2 3
MBK110
SOT186A (TO-220F)
1.
TrenchMOS is a trademark of Koninklijke Philips Electronics N.V.
s
BUK9728-55A
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
5. Quick reference data
Table 2:
Quick reference data
Symbol Parameter
Conditions
Typ
Max
Unit
-
55
V
VDS
drain-source voltage (DC)
ID
drain current (DC)
Tmb = 25 °C; VGS = 5 V
-
22
A
Ptot
total power dissipation
Tmb = 25 °C
-
26
W
Tj
junction temperature
-
150
°C
RDSon
drain-source on-state resistance
Tj = 25 °C; VGS = 5 V; ID = 15 A
23
28
mΩ
Tj = 25 °C; VGS = 4.5 V; ID = 15 A
-
30
mΩ
Min
Max
Unit
-
55
V
-
55
V
-
±10
V
6. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDS
drain-source voltage (DC)
VDGR
drain-gate voltage (DC)
VGS
gate-source voltage (DC)
VGSM
non-repetitive gate-source voltage
tp ≤ 50 µs
-
±15
V
ID
drain current (DC)
Tmb = 25 °C; VGS = 5 V;
Figure 2 and 3
-
22
A
-
16
A
-
90
A
RGS = 20 kΩ
Tmb = 100 °C; VGS = 5 V; Figure 2
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs;
Figure 3
Tmb = 25 °C; Figure 1
[1]
Ptot
total power dissipation
-
26
W
Tstg
storage temperature
−55
+150
°C
Tj
operating junction temperature
−55
+150
°C
Source-drain diode
IDR
reverse drain current (DC)
Tmb = 25 °C
-
22
A
IDRM
peak reverse drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs
-
90
A
unclamped inductive load; ID = 22 A;
VDS ≤ 55 V; VGS = 5 V; RGS = 50 Ω;
starting T j = 25 °C
-
180
mJ
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source avalanche
energy
[1]
IDM is limited by chip, not package.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13326
Product data
Rev. 02 — 10 June 2004
2 of 12
BUK9728-55A
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03ne36
120
03ne37
120
Pder
(%)
100
Ider
(%)
100
80
80
60
60
40
40
20
20
0
0
0
25
50
75
100
0
125
150 175
Tmb (oC)
25
50
75
100
125
150 175
o
Tmb ( C)
VGS ≥ 5 V
P tot
P der = ---------------------- × 100%
P
°
ID
I der = ------------------- × 100%
I
°
tot ( 25 C )
D ( 25 C )
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
03ne06
103
ID
(A)
102
RDSon = VDS/ ID
tp = 10 us
100 us
10
1 ms
δ=
P
tp D.C.
T
10 ms
1
100 ms
t
tp
T
10-1
1
102
10
VDS (V)
Tamb = 25 °C; IDM is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13326
Product data
Rev. 02 — 10 June 2004
3 of 12
BUK9728-55A
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
7. Thermal characteristics
Table 4:
Thermal characteristics
Symbol Parameter
Conditions
Min Typ Max Unit
Figure 4
-
-
4.7
K/W
-
55
-
K/W
Rth(j-mb)
thermal resistance from junction to
mounting base
Rth(j-a)
thermal resistance from junction to ambient vertical in still air
7.1 Transient thermal impedance
03ne07
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
0.05
10-1
T
T
10-2
10-5
tp
t
tp
Single Shot
10-6
δ=
P
0.02
10-4
10-3
10-2
10-1
1
tp (s)
10
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13326
Product data
Rev. 02 — 10 June 2004
4 of 12
BUK9728-55A
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
8. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS
VGS(th)
IDSS
drain-source breakdown
voltage
ID = 0.25 mA; VGS = 0 V
Tj = 25 °C
55
-
-
V
Tj = −55 °C
50
-
-
V
gate-source threshold voltage ID = 1 mA; VDS = VGS;
Figure 9
drain-source leakage current
Tj = 25 °C
1
1.5
2
V
Tj = 150 °C
0.6
-
-
V
Tj = −55 °C
-
-
2.3
V
Tj = 25 °C
-
0.05
10
µA
Tj = 150 °C
-
-
500
µA
-
2
100
nA
Tj = 25 °C
-
23
28
mΩ
Tj = 150 °C
-
-
51
mΩ
VGS = 4.5 V; ID = 15 A
-
-
30
mΩ
VGS = 10 V; ID = 15 A
-
21
25
mΩ
VGS = 5 V; VDD = 44 V;
ID = 15 A; Figure 14
-
27
-
nC
-
4.2
-
nC
-
11.7
-
nC
-
1200
1725
pF
-
210
250
pF
-
140
195
pF
-
14
-
ns
VDS = 55 V; VGS = 0 V
IGSS
gate-source leakage current
VGS = ±10 V; VDS = 0 V
RDSon
drain-source on-state
resistance
VGS = 5 V; ID = 15 A;
Figure 7 and 8
Dynamic characteristics
Qg(tot)
total gate charge
Qgs
gate-to-source charge
Qgd
gate-to-drain (Miller) charge
Ciss
input capacitance
Coss
output capacitance
Crss
reverse transfer capacitance
td(on)
turn-on delay time
tr
rise time
-
125
-
ns
td(off)
turn-off delay time
-
64
-
ns
tf
fall time
-
68
-
ns
Ld
internal drain inductance
from drain lead 6 mm from
package to centre of die
-
4.5
-
nH
Ls
internal source inductance
from source lead 6 mm from
package to source bond pad
-
7.5
-
nH
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Figure 12
VDD = 30 V; RL = 1.2 Ω;
VGS = 5 V; RG = 10 Ω
Source-drain diode
VSD
source-drain (diode forward)
voltage
IS = 15 A; VGS = 0 V;
Figure 15
-
0.85
1.2
V
trr
reverse recovery time
-
35
-
ns
Qr
recovered charge
IS = 20 A; dIS/dt = −100 A/µs
VGS = −10 V; VDS = 30 V
-
70
-
nC
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13326
Product data
Rev. 02 — 10 June 2004
5 of 12
BUK9728-55A
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03na86
160
ID
(A)
140
9
VGS (V) = 10
8
7
03na84
35
RDSon
(mΩ)
30
120
6
100
5
25
4
20
80
60
40
2.2
0
0
2
4
6
8
10
10
VDS (V)
Tj = 25 °C
2
4
6
8 V
10
GS (V)
Tj = 25 °C; ID = 15 A
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
RDSon
(mΩ)
15
3
20
03na87
55
3.6
50
VGS(V) = 3
3.2
3.8
4
Fig 6. Drain-source on-state resistance as a function
of gate-source voltage; typical values.
03nc24
2.2
a
2
1.8
3.4
1.6
45
1.4
40
1.2
35
1
30
0.8
5
0.6
25
0.4
20
0.2
0
15
0
10
20
30
40
50
60
70
-60
80 90
ID (A)
Tj = 25 °C
20
60
100
140
180
T (oC)
j
R DSon
a = --------------------------R DSon ( 25 °C )
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13326
Product data
-20
Rev. 02 — 10 June 2004
6 of 12
BUK9728-55A
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03aa33
2.5
VGS(th)
(V)
2
1.5
03aa36
10-1
ID
(A)
max
10-2
typ
10-3
min
max
10-4
min
1
typ
10-5
0.5
10-6
0
-60
0
60
120
Tj (°C)
180
0
1
2
VGS (V)
3
Tj = 25 °C; VDS = VGS
ID = 1 mA; VDS = VGS
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
03na85
35
gfs
(S)
30
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
03na88
3500
C (pF)
3000
2500
25
2000
20
1500
15
Ciss
1000
10
500
5
0
0
0
20
40
60
10-2
ID (A) 80
Tj = 25 °C; VDS = 25 V
1
VGS = 0 V; f = 1 MHz
Fig 11. Forward transconductance as a function of
drain current; typical values.
Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13326
Product data
10-1
Coss
Crss
10
102
VDS (V)
Rev. 02 — 10 June 2004
7 of 12
BUK9728-55A
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03ne20
100
03na83
6
ID
(A)
VGS
(V)
5
80
VDD= 14 V
4
60
VDD= 44 V
3
40
2
20
Tj = 150 oC
1
Tj = 25 oC
0
0
2
4
0
6
0
VGS (V)
10
20
QG (nC)
30
Tj = 25 °C; ID = 15 A
VDS = 25 V
Fig 13. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
Fig 14. Gate-source voltage as a function of gate
charge; typical values.
03ne21
100
IS
(A)
80
Tj = 150 oC
60
40
Tj = 25 oC
20
0
0.0
0.5
1.0
1.5
VSD (V)
VGS = 0 V
Fig 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13326
Product data
Rev. 02 — 10 June 2004
8 of 12
BUK9728-55A
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
9. Package outline
Plastic single-ended package; isolated heatsink mounted;
1 mounting hole; 3 lead TO-220 'full pack'
SOT186A
E
A
A1
P
q
D1
mounting
base
T
D
j
L2
L1
K
Q
b1
L
b2
1
2
3
b
c
w M
e
e1
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
UNIT
A
A1
b
b1
b2
c
D
D1
E
e
e1
j
K
mm
4.6
4.0
2.9
2.5
0.9
0.7
1.1
0.9
1.4
1.0
0.7
0.4
15.8
15.2
6.5
6.3
10.3
9.7
2.54
5.08
2.7
1.7
0.6
0.4
L
L1
14.4 3.30
13.5 2.79
L2
max.
P
Q
q
3
3.2
3.0
2.6
2.3
3.0
2.6
(2)
T
2.5
w
0.4
Notes
1. Terminal dimensions within this zone are uncontrolled. Terminals in this zone are not tinned.
2. Both recesses are ∅ 2.5 × 0.8 max. depth
OUTLINE
VERSION
SOT186A
REFERENCES
IEC
JEDEC
JEITA
3-lead TO-220F
EUROPEAN
PROJECTION
ISSUE DATE
02-03-12
02-04-09
Fig 16. SOT186A.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13326
Product data
Rev. 02 — 10 June 2004
9 of 12
BUK9728-55A
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
10. Revision history
Table 6:
Revision history
Rev Date
02
20040610
CPCN
Description
-
Product data (9397 750 13326)
Modifications:
•
01
20010213
-
Latest version of package outline imported into data sheet.
Product specification (9397 750 08002)
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13326
Product data
Rev. 02 — 10 June 2004
10 of 12
BUK9728-55A
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
11. Data sheet status
Level
Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
[3]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
12. Definitions
13. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [email protected].
Product data
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 13326
Rev. 02 — 10 June 2004
11 of 12
Philips Semiconductors
BUK9728-55A
N-channel TrenchMOS™ logic level FET
Contents
1
2
3
4
5
6
7
7.1
8
9
10
11
12
13
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
© Koninklijke Philips Electronics N.V. 2004.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 10 June 2004
Document order number: 9397 750 13326