PHILIPS PHB152NQ03LTA

PHP/B152NQ03LTA
N-channel TrenchMOS™ logic level FET
Rev. 01 — 05 March 2004
Product data
1. Product profile
1.1 Description
Logic level N-channel enhancement mode field-effect transistor in a plastic package
using TrenchMOS™ technology.
1.2 Features
■ Logic level threshold
■ Low gate charge
■ Low on-state resistance
■ Low thermal resistance.
1.3 Applications
■ DC-to-DC converters
■ Switched-mode power supplies.
1.4 Quick reference data
■ VDS ≤ 25 V
■ Ptot ≤ 150 W
■ ID ≤ 75 A
■ RDSon ≤ 4 mΩ.
2. Pinning information
Table 1:
Pinning - SOT78 (TO-220AB) and SOT404 (D2-PAK), simplified outlines and symbol
Pin Description
1
gate (g)
2
drain (d)
3
source (s)
mb
mounting base;
connected to drain (d)
Simplified outline
[1]
Symbol
mb
d
mb
g
MBB076
2
1
3
MBK116
MBK106
1 2 3
SOT78 (TO-220AB)
[1]
It is not possible to make connection to pin 2 of the SOT404 package.
SOT404 (D2-PAK)
s
PHP/B152NQ03LTA
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
3. Ordering information
Table 2:
Ordering information
Type number
Package
Name
Description
Version
PHP152NQ03LTA
TO-220AB
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3 leads SOT78
PHB152NQ03LTA
D2-PAK
Plastic single-ended surface mounted package; 3 leads (one lead cropped) SOT404
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage (DC)
25 °C ≤ Tj ≤ 175 °C
-
25
V
VDGR
drain-gate voltage (DC)
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
-
25
V
VGS
gate-source voltage
-
±20
V
ID
drain current (DC)
Tmb = 25 °C; VGS = 10 V; Figure 2 and 3
-
75
A
Tmb = 100 °C; VGS = 10 V; Figure 2
-
75
A
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3
-
240
A
Ptot
total power dissipation
Tmb = 25 °C; Figure 1
-
150
W
Tstg
storage temperature
−55
+175
°C
Tj
junction temperature
−55
+175
°C
Source-drain diode
IS
source (diode forward) current (DC) Tmb = 25 °C
-
75
A
ISM
peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs
-
240
A
-
560
mJ
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
unclamped inductive load; ID = 75 A;
tp = 0.46 ms; VDD ≤ 25 V; RGS = 50 Ω;
VGS = 10 V; starting Tj = 25 °C
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12829
Product data
Rev. 01 — 05 March 2004
2 of 13
PHP/B152NQ03LTA
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03aa16
120
003aaa630
120
Pder
(%)
Ider
(%)
80
80
40
40
0
0
0
50
100
150
0
200
Tmb (°C)
P tot
P der = ----------------------- × 100%
P
°
100
50
150
200
Tmb (°C)
ID
I der = ------------------- × 100%
I
°
tot ( 25 C )
D ( 25 C )
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
003aaa517
103
LImit RDSon = VDS / ID
ID
(A)
tp = 10 µs
100 µs
102
1 ms
DC
10 ms
10
100 ms
1
10-1
1
10
VDS (V)
102
Tmb = 25 °C; IDM is single pulse; VGS = 10 V
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12829
Product data
Rev. 01 — 05 March 2004
3 of 13
PHP/B152NQ03LTA
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
5. Thermal characteristics
Table 4:
Thermal characteristics
Symbol Parameter
Conditions
Rth(j-mb)
thermal resistance from junction to mounting base Figure 4
Rth(j-a)
thermal resistance from junction to ambient
Min
Typ
Max
Unit
-
-
1
K/W
SOT78
vertical in still air
-
60
-
K/W
SOT404
mounted on a printed-circuit
board; minimum footprint
-
50
-
K/W
5.1 Transient thermal impedance
003aaa518
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
10-1
0.05
δ=
P
0.02
tp
T
single pulse
t
tp
T
10-2
10-5
10-4
10-3
10-2
10-1
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12829
Product data
Rev. 01 — 05 March 2004
4 of 13
PHP/B152NQ03LTA
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
6. Characteristics
Table 5:
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS drain-source breakdown voltage
VGS(th)
IDSS
gate-source threshold voltage
drain-source leakage current
ID = 250 µA; VGS = 0 V
Tj = 25 °C
25
-
-
V
Tj = −55 °C
22
-
-
V
Tj = 25 °C
1
1.5
2
V
Tj = 175 °C
0.5
-
-
V
Tj = −55 °C
-
-
2.2
V
-
-
1
µA
ID = 1 mA; VDS = VGS; Figure 9
VDS = 25 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
-
-
500
µA
-
10
100
nA
Tj = 25 °C
-
4.2
5
mΩ
Tj = 175 °C
-
6.8
8.7
mΩ
Tj = 25 °C
-
3.4
4
mΩ
Tj = 175 °C
-
5.5
6.9
mΩ
-
36
-
nC
IGSS
gate-source leakage current
VGS = ±15 V; VDS = 0 V
RDSon
drain-source on-state resistance
VGS = 5 V; ID = 25 A; Figure 7 and 8
VGS = 10 V; ID = 25 A; Figure 7 and 8
Dynamic characteristics
Qg(tot)
total gate charge
ID = 50 A; VDD = 15 V; VGS = 5 V; Figure 13
Qgs
gate-source charge
-
13
-
nC
Qgd
gate-drain (Miller) charge
-
12
-
nC
Ciss
input capacitance
-
3140
-
pF
Coss
output capacitance
-
1040
-
pF
Crss
reverse transfer capacitance
-
354
-
pF
td(on)
turn-on delay time
-
37
-
ns
tr
rise time
-
87
-
ns
td(off)
turn-off delay time
-
71
-
ns
tf
fall time
-
46
-
ns
VGS = 0 V; VDS = 25 V; f = 1 MHz;
Figure 11
VDD = 15 V; ID = 25 A;
VGS = 5 V; RG = 5.6 Ω
Source-drain diode
VSD
source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12
trr
reverse recovery time
Qr
recovered charge
IS = 10 A; dIS/dt = −100 A/µs;
VGS = 0 V; VR = 25 V
0.85
1.2
V
50
-
ns
-
24
-
nC
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12829
Product data
-
Rev. 01 — 05 March 2004
5 of 13
PHP/B152NQ03LTA
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
003aaa519
40
ID
(A)
10 V
5V
003aaa520
40
2.8 V
3V
ID
(A)
VGS = 2.7 V
30
30
2.6 V
Tj = 175 °C
20
20
2.5 V
2.4 V
25 °C
10
10
2 .3 V
2.1 V
0
0
0.2
0.4
0.6
0
0.8
1
VDS (V)
Tj = 25 °C
0
VGS (V)
3
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
2.5 V
2.6 V
2.8 V
2.7 V
003aaa627
2
003aaa521
20
2.4 V
2
Tj = 25 °C and 175 °C; VDS > ID x RDSon
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
RDSon
1
a
(mΩ)
1.5
15
1
10
VGS = 3 V
0.5
5V
5
10 V
0
0
0
10
20
30
ID (A)
40
Tj = 25 °C
-60
60
120
Tj (°C)
180
R DSon
a = ---------------------------R DSon ( 25 °C )
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12829
Product data
0
Rev. 01 — 05 March 2004
6 of 13
PHP/B152NQ03LTA
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03aa33
2.5
max
ID
(A)
10-2
typ
10-3
VGS(th)
(V)
2
1.5
03aa36
10-1
min
min
1
10-5
0
10-6
0
60
max
10-4
0.5
-60
typ
120
Tj (°C)
180
0
1
2
VGS (V)
3
Tj = 25 °C; VDS = 5 V
ID = 1 mA; VDS = VGS
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
003aaa522
104
C
(pF)
Ciss
Coss
103
Crss
102
10-1
1
10
VDS (V)
102
VGS = 0 V; f = 1 MHz
Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12829
Product data
Rev. 01 — 05 March 2004
7 of 13
PHP/B152NQ03LTA
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
003aaa523
40
IS
(A)
003aaa524
10
VGS
(V)
8
30
Tj = 175 °C
6
20
4
25 °C
10
2
0
0
0.2
0.4
0.6
0.8
VSD (V)
1
0
40
60
80
QG (nC)
Tj = 25 °C and 175 °C; VGS = 0 V
ID = 50 A; VDD = 15 V
Fig 12. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
Fig 13. Gate-source voltage as a function of gate
charge; typical values.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12829
Product data
20
Rev. 01 — 05 March 2004
8 of 13
PHP/B152NQ03LTA
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
7. Package outline
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB
E
SOT78
A
A1
p
q
mounting
base
D1
D
L2
L1(1)
Q
b1
L
1
2
3
b
c
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
b1
c
D
D1
E
e
L
L1(1)
L2
max.
p
q
Q
mm
4.5
4.1
1.39
1.27
0.9
0.7
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
2.54
15.0
13.5
3.30
2.79
3.0
3.8
3.6
3.0
2.7
2.6
2.2
Note
1. Terminals in this zone are not tinned.
OUTLINE
VERSION
REFERENCES
IEC
SOT78
JEDEC
EIAJ
3-lead TO-220AB
SC-46
EUROPEAN
PROJECTION
ISSUE DATE
00-09-07
01-02-16
Fig 14. SOT78 (TO-220AB).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12829
Product data
Rev. 01 — 05 March 2004
9 of 13
PHP/B152NQ03LTA
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads
(one lead cropped)
SOT404
A
A1
E
mounting
base
D1
D
HD
2
Lp
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
D
max.
D1
E
e
Lp
HD
Q
mm
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
11
1.60
1.20
10.30
9.70
2.54
2.90
2.10
15.80
14.80
2.60
2.20
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
99-06-25
01-02-12
SOT404
Fig 15. SOT404 (D2-PAK).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12829
Product data
Rev. 01 — 05 March 2004
10 of 13
PHP/B152NQ03LTA
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
8. Revision history
Table 6:
Revision history
Rev Date
01
20040305
CPCN
Description
-
Product data. (9397 750 12829)
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12829
Product data
Rev. 01 — 05 March 2004
11 of 13
PHP/B152NQ03LTA
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
9. Data sheet status
Level
Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
10. Definitions
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
12. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
11. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [email protected]
Product data
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12829
Rev. 01 — 05 March 2004
12 of 13
Philips Semiconductors
PHP/B152NQ03LTA
N-channel TrenchMOS™ logic level FET
Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
5.1
6
7
8
9
10
11
12
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
© Koninklijke Philips Electronics N.V. 2004.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 05 March 2004
Document order number: 9397 750 12829