TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Rev. 02 — 03 July 2002 Product data 1. Description The TDA8768AH is a biCMOS 12-bit Analog-to-Digital Converter (ADC) optimized for GSM and EDGE cellular infrastructures, professional telecommunications and imaging, and advanced FM radio. It converts the analog input signal into 12-bit binary coded digital words at a maximum sampling rate of 70 MHz. All static digital inputs (SH, CE and OTC) are TTL and CMOS compatible and all outputs are CMOS compatible. A sine wave clock input signal can also be used. 2. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 12-bit resolution Sampling rate up to 70 MHz −3 dB bandwidth of 245 MHz 5 V power supplies and 3.3 V output power supply Binary or twos complement CMOS outputs In-range CMOS compatible output TTL and CMOS compatible static digital inputs TTL and CMOS compatible digital outputs Differential AC or PECL clock input; TTL compatible Power dissipation 550 mW (typical) Low analog input capacitance (typical 2 pF), no buffer amplifier required Integrated sample-and-hold amplifier Differential analog input External amplitude range control Voltage controlled regulator included −40 °C to +85 °C ambient temperature. 3. Applications ■ High-speed analog-to-digital conversion for: ◆ Cellular infrastructure (GSM and EDGE) ◆ Professional telecommunication ◆ Advanced FM radio ◆ Radar ◆ Imaging (camera scanner) ◆ Set Top Box (STB) ◆ Medical imaging. TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 4. Quick reference data Table 1: Quick reference data Symbol Parameter VCCA Min Typ Max Unit analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage 3.0 3.3 3.6 V ICCA analog supply current - 78 87 mA ICCD digital supply current - 27 30 mA ICCO output supply current fCLK = 20 MHz fi = 400 kHz - 3 4 mA INL integral non-linearity fCLK = 20 MHz fi = 400 kHz - ±2.6 ±4.5 LSB DNL differential non-linearity (no missing code) fCLK = 20 MHz fi = 400 kHz - ±0.5 +1.1 − 0.95 LSB fCLK(max) maximum clock frequency - - - - TDA8768AH/4 40 - TDA8768AH/5 55 TDA8768AH/7 70 - total power dissipation Ptot Conditions fCLK = 55 MHz fi = 20 MHz - MHz - MHz - - MHz 550 660 mW 5. Ordering information Table 2: Ordering information Type number TDA8768AH/4 TDA8768AH/5 Package Name Description Version QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2 40 TDA8768AH/7 55 70 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Sampling frequency (MHz) Rev. 02 — 03 July 2002 2 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 6. Block diagram VCCA1 VCCA3 VCCA4 2 n.c. FSref Vref 3 CLK 41 CLK VCCD1 VCCD2 36 35 37 15 OTC CE 19 18 6 to 10, 13, 14, 16 12 21 D11 VREF REFERENCE 11 MSB CLOCK DRIVER 22 D10 23 D9 24 D8 25 D7 AMP 26 D6 CMOS OUTPUTS VI VI 27 D5 43 42 data outputs 28 D4 ANALOG-TO-DIGITAL CONVERTER sampleand-hold LATCHES 29 D3 30 D2 31 D1 SH 32 D0 39 33 TDA8768A CMADC DEC 1 CMADC REFERENCE OVERFLOW/ UNDERFLOW LATCH 5 44 AGND1 4 AGND3 20 CMOS OUTPUT 40 38 17 34 AGND4 DGND1 DGND2 OGND LSB VCCO IR 005aaa024 Fig 1. Block diagram. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 3 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 7. Pinning information 34 OGND 35 CLK 36 CLK 37 VCCD1 38 DGND1 39 SH 40 AGND4 41 VCCA4 42 VI 43 VI 44 AGND1 7.1 Pinning CMADC 1 33 VCCO VCCA1 2 32 D0 VCCA3 3 31 D1 AGND3 4 30 D2 DEC 5 29 D3 TDA8768AH n.c. 6 n.c. 7 27 D5 n.c. 8 26 D6 n.c. 28 D4 D10 22 D11 21 IR 20 CE 19 OTC 18 DGND2 17 n.c. 16 VCCD2 15 23 D9 n.c. 14 24 D8 Vref 11 n.c. 13 25 D7 FSref 12 9 n.c. 10 FCE002 Fig 2. Pin configuration. 7.2 Pin description Table 3: Pin description Symbol Pin Description CMADC 1 regulator output common mode ADC input VCCA1 2 analog supply voltage 1 (+5 V) VCCA3 3 analog supply voltage 3 (+5 V) AGND3 4 analog ground 3 DEC 5 decoupling node n.c. 6 not connected n.c. 7 not connected n.c. 8 not connected n.c. 9 not connected n.c. 10 not connected VREF 11 reference voltage input FSREF 12 full-scale reference output © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 4 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Table 3: Pin description…continued Symbol Pin Description n.c. 13 not connected n.c. 14 not connected VCCD2 15 digital supply voltage 2 (+5 V) n.c. 16 not connected DGND2 17 digital ground 2 OTC 18 control input twos complement output; active HIGH CE 19 chip enable input (CMOS level; active LOW) IR 20 in-range output D11 21 data output; bit 11 (MSB) D10 22 data output; bit 10 D9 23 data output; bit 9 D8 24 data output; bit 8 D7 25 data output; bit 7 D6 26 data output; bit 6 D5 27 data output; bit 5 D4 28 data output; bit 4 D3 29 data output; bit 3 D2 30 data output; bit 2 D1 31 data output; bit 1 D0 32 data output; bit 0 (LSB) VCCO 33 output supply voltage (+3.3 V) OGND 34 output ground CLK 35 complementary clock input CLK 36 clock input VCCD1 37 digital supply voltage 1 (+5 V) DGND1 38 digital ground 1 SH 39 sample-and-hold enable input (CMOS level; active HIGH) AGND4 40 analog ground 4 VCCA4 41 analog supply voltage 4 (+5 V) VI 42 analog input voltage VI 43 complementary analog input voltage AGND1 44 analog ground 1 8. Limiting values Table 4: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCCA VCCD VCCO Parameter Min Max Unit analog supply voltage [1] −0.3 +7.0 V digital supply voltage [1] −0.3 +7.0 V output supply voltage [1] −0.3 +7.0 V © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Conditions Rev. 02 — 03 July 2002 5 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Table 4: Limiting values…continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter ∆VCC supply voltage difference Conditions Min Max Unit VCCA − VCCD −1.0 +1.0 V VCCD − VCCO −1.0 +4.0 V VCCA − VCCO −1.0 +4.0 V 0.3 VCCA V input voltage at pins 35 and 36 for differential clock drive (peak-to-peak value) - VCCD V IO output current - 10 mA Tstg storage temperature −55 +150 °C Tamb ambient temperature −40 +85 °C Tj junction temperature - 150 °C VI, VI input voltage at pins 42 and 43 VCLK(p-p) [1] referenced to AGND The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided that the supply voltage differences ∆VCC are respected. 9. Thermal characteristics Table 5: Thermal characteristics Symbol Parameter Condition Value Unit Rth(j-a) thermal resistance from junction to ambient in free air 75 K/W 10. Characteristics Table 6: Characteristics VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V; VCCO = V33 to V34 = 3.0 to 3.6 V; AGND and DGND shorted together; Tamb = −40 to 85 °C; VI(p-p) − VI(p-p) = 1.9 V; Vref = VCCA3−1.75 V; VI(CM) = VCCA3−1.6V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test [1] Min Typ Max Unit Supplies VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage 3.0 3.3 3.6 V ICCA analog supply current I - 78 87 mA ICCD digital supply current I - 27 30 mA ICCO output supply current I - 3 4 mA fCLK = 40 MHz; fi = 4.43 MHz C - 6.2 9 mA fCLK = 55 MHz; fi = 20 MHz - 9.5 12 mA fCLK = 20 MHz; fi = 400 kHz I Inputs © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 6 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Table 6: Characteristics…continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V; VCCO = V33 to V34 = 3.0 to 3.6 V; AGND and DGND shorted together; Tamb = −40 to 85 °C; VI(p-p) − VI(p-p) = 1.9 V; Vref = VCCA3−1.75 V; VI(CM) = VCCA3−1.6V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter CLK and CLK (referenced to VIL VIH Conditions Test [1] Min Typ Max Unit PECL mode; VCCD = 5 V I 3.19 - 3.52 V TTL mode C 0 - 0.8 V PECL mode; VCCD = 5 V I 3.83 - 4.12 V TTL mode C 2.0 - VCCD V DGND)[2] LOW-level input voltage HIGH-level input voltage IIL LOW-level input current VCLK or VCLK = 3.19 V C −10 - - µA IIH HIGH-level input current VCLK or VCLK = 3.83 V C - - 10 µA ∆VCLK(p-p) differential AC input voltage for switching (VCLK(p-p) − VCLK(p-p)) AC driving mode; DC voltage C level = 2.5 V 1 1.5 2.0 V Ri input resistance fCLK = 55 MHz D 2 - - kΩ Ci input capacitance fCLK = 55 MHz D - - 2 pF I 0 - 0.8 V OTC, SH and CE (referenced to DGND); see Tables 7 and 8 VIL LOW-level input voltage VIH HIGH-level input voltage I 2.0 - VCCD V IIL LOW-level input current VIL = 0.8 V I −20 - - µA IIH HIGH-level input current VIH = 2.0 V I - - 20 µA VI and VI (referenced to AGND); see Table 7, Vref = VCCA3 − 1.75 V IIL LOW-level input current SH = HIGH C - 10 - µA IIH HIGH-level input current SH = HIGH C - 10 - µA Ri input resistance fi = 20 MHz D - 14 - MΩ Ci input capacitance fi = 20 MHz D - 450 - fF VI(CM) common mode input voltage VI = VI; output code 2047 C VCCA3 VCCA3 − 1.6 VCCA3 V − 1.7 − 1.2 Voltage controlled regulator output CMADC Vo(CM) common mode output voltage I - VCCA3 − 1.6 - V IL load current I - 1 2 mA C - VCCA3 − 1.75 - V C - 0.3 10 µA C - 1.9 - V I - VCCA3 − 1.75 - V I 0 - 0.5 V Voltage input Vref [3] Vref full-scale fixed voltage Iref input current at Vref VI(p-p) − VI(p-p) input voltage amplitude (peak-to-peak value) fi = 20 MHz; fCLK = 55 Msps Vref = VCCA3 − 1.75 V VI(CM) = VCCA3 − 1.6 V Voltage controlled regulator output FSref Vo(ref) 1.9 V full-scale output voltage Outputs (referenced to OGND) Digital outputs D11 to D0 and IR (referenced to OGND) VOL LOW-level output voltage IOL = 2 mA © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 7 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Table 6: Characteristics…continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V; VCCO = V33 to V34 = 3.0 to 3.6 V; AGND and DGND shorted together; Tamb = −40 to 85 °C; VI(p-p) − VI(p-p) = 1.9 V; Vref = VCCA3−1.75 V; VI(CM) = VCCA3−1.6V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test [1] Min Typ Max Unit VOH HIGH-level output voltage IOH = − 0.4 mA I VCCO − 0.5 - VCCO V Io output current in 3-state output level between 0.5 V and VCCO I −20 - +20 µA SH = HIGH C - - 7 MHz TDA8768AH/4 C 40 - - MHz TDA8768AH/5 I 55 - - MHz Switching characteristics Clock frequency fCLK; see Figure 3 fCLK(min) minimum clock frequency fCLK(max) maximum clock frequency C 70 - - MHz tCLKH clock pulse width HIGH TDA8768AH/7 fi = 20 MHz C 6.8 - - ns tCLKL clock pulse width LOW fi = 20 MHz C 6.8 - - ns LSB Analog signal processing; 50% clock duty factor; VI − VI = 1.9 V; Vref = VCCA3 − 1.75 V; see Table 7 Linearity INL integral non-linearity fCLK = 20 MHz; fi = 400 kHz I - ±2.6 4.5 DNL differential non-linearity fCLK = 20 MHz; fi = 400 kHz (no missing code guaranteed) I - ±0.5 +1.1 LSB − 0.95 Oerr offset error VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 °C; output code = 2047 C −25 5 25 mV EG gain error amplitude; spread from device to device VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 °C C −7 - +7 %FS analog bandwidth −3 dB; full-scale input C 220 245 - MHz second harmonic TDA8768AH/4 (fCLK = 40 MHz) fi = 4.43 MHz C - −78 - dBFS fi = 10 MHz C - −77 - dBFS fi = 15 MHz C - −74 - dBFS fi = 20 MHz C - −71 - dBFS fi = 4.43 MHz C - −77 - dBFS fi = 10 MHz C - −77 - dBFS fi = 15 MHz C - −76 - dBFS fi = 20 MHz I - − 73 - dBFS fi = 4.43 MHz C - −76 - dBFS fi = 10 MHz C - −74 - dBFS fi = 15 MHz C - −70 - dBFS Bandwidth (fCLK = 55 MHz) [4] B Harmonics H2 second harmonic TDA8768AH/5 (fCLK = 55 MHz) second harmonic TDA8768AH/7 (fCLK = 70 MHz) © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 8 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Table 6: Characteristics…continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V; VCCO = V33 to V34 = 3.0 to 3.6 V; AGND and DGND shorted together; Tamb = −40 to 85 °C; VI(p-p) − VI(p-p) = 1.9 V; Vref = VCCA3−1.75 V; VI(CM) = VCCA3−1.6V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test [1] Min Typ Max Unit H3 third harmonic TDA8768AH/4 (fCLK = 40 MHz) fi = 4.43 MHz C - −74 - dBFS fi = 10 MHz C - −74 - dBFS fi = 15 MHz C - −74 - dBFS fi = 20 MHz C - −73 - dBFS fi = 4.43 MHz C - −74 - dBFS fi = 10 MHz C - −74 - dBFS fi = 15 MHz C - −74 - dBFS fi = 20 MHz I - −72 - dBFS fi = 4.43 MHz C - −74 - dBFS fi = 10 MHz C - −74 - dBFS fi = 15 MHz C - −73 - dBFS fi = 4.43 MHz C - −68 - dBFS fi = 10 MHz C - −68 - dBFS fi = 15 MHz C - −68 - dBFS fi = 20 MHz C - −68 - dBFS fi = 4.43 MHz C - −68 - dBFS fi = 10 MHz C - −68 - dBFS fi = 15 MHz C - −68 - dBFS fi = 20 MHz I - −68 - dBFS fi = 4.43 MHz C - −68 - dBFS fi = 10 MHz C - −67 - dBFS fi = 15 MHz C - −67 - dBFS shorted input; SH = HIGH; fCLK = 55 MHz C - 0.45 - LSB signal-to-noise ratio TDA8768AH/4 (fCLK = 40 MHz) fi = 4.43 MHz C - 64 - dBFS fi = 10 MHz C - 64 - dBFS fi = 15 MHz C - 64 - dBFS fi = 20 MHz C - 64 - dBFS signal-to-noise ratio TDA8768AH/5 (fCLK = 55 MHz) fi = 4.43 MHz C - 64 - dBFS fi = 10 MHz C - 64 - dBFS fi = 15 MHz C - 64 - dBFS fi = 20 MHz I - 64 - dBFS signal-to-noise ratio TDA8768AH/7 (fCLK = 70 MHz) fi = 4.43 MHz C - 64 - dBFS fi = 10 MHz C - 64 - dBFS fi = 15 MHz C - 63 - dBFS third harmonic TDA8768AH/5 (fCLK = 55 MHz) third harmonic TDA8768AH/7 (fCLK = 70 MHz) Total harmonic distortion[5] THD total harmonic distortion TDA8768AH/4 (fCLK = 40 MHz) total harmonic distortion TDA8768AH/5 (fCLK = 55 MHz) total harmonic distortion TDA8768AH/7 (fCLK = 70 MHz) Thermal noise (fCLK = 55 MHz) Nth(rms) thermal noise (RMS value) Signal-to-noise ratio [6] SNR © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 9 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Table 6: Characteristics…continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V; VCCO = V33 to V34 = 3.0 to 3.6 V; AGND and DGND shorted together; Tamb = −40 to 85 °C; VI(p-p) − VI(p-p) = 1.9 V; Vref = VCCA3−1.75 V; VI(CM) = VCCA3−1.6V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Test [1] Min Typ Max Unit fi = 4.43 MHz C - 72 - dBFS fi = 10 MHz C - 71 - dBFS fi = 15 MHz C - 71 - dBFS fi = 20 MHz C - 69 - dBFS fi = 4.43 MHz C - 72 - dBFS fi = 10 MHz C - 71 - dBFS fi = 15 MHz C - 71 - dBFS fi = 20 MHz I - 69 - dBFS fi = 4.43 MHz C - 70 - dBFS fi = 10 MHz C - 69 - dBFS fi = 15 MHz C - 69 - dBFS fi = 4.43 MHz C - 10.1 - bits fi = 10 MHz C - 10.1 - bits fi = 15 MHz C - 10.1 - bits fi = 20 MHz C - 10 - bits fi = 4.43 MHz C - 10.1 - bits fi = 10 MHz C - 10.1 - bits fi = 15 MHz C - 10 - bits fi = 20 MHz I - 10 - bits fi = 4.43 MHz C - 10 - bits fi = 10 MHz C - 10 - bits fi = 15 MHz C - 10 - bits Conditions Spurious free dynamic range; see Figure 7, 13 and 14 SFDR spurious free dynamic range TDA8768AH/4 (fCLK = 40 MHz) spurious free dynamic range TDA8768AH/5 (fCLK = 55 MHz) spurious free dynamic range TDA8768AH/7 (fCLK = 70 MHz) Effective number of bits ENOB [7] effective number of bits TDA8768AH/4 (fCLK = 40 MHz) effective number of bits TDA8768AH/5 (fCLK = 55 MHz) effective number of bits TDA8768AH/7 (fCLK = 70 MHz) Intermodulation; (fCLK = 55 MHz; fi = 20 MHz)[8] TTIR two-tone intermodulation rejection C - −68 - dB d3 third-order intermodulation distortion C - −70 - dB fi = 20 MHz; VI = ±16 LSB at C code 2047 - 10−14 - times/ sample Bit error rate (fCLK = 55 MHz) BER bit error rate Timing (CL = 10 pF)[9] td(s) sampling delay time C - 0.25 1 ns th(o) output hold time C 4 6.4 - ns td(o) output delay time C - 9.0 13 ns © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 10 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Table 6: Characteristics…continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V; VCCO = V33 to V34 = 3.0 to 3.6 V; AGND and DGND shorted together; Tamb = −40 to 85 °C; VI(p-p) − VI(p-p) = 1.9 V; Vref = VCCA3−1.75 V; VI(CM) = VCCA3−1.6V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test [1] Min Typ Max Unit 3-state output delay times; see Figure 4 tdZH enable HIGH C - 5.1 9.0 ns tdZL enable LOW C - 7.0 11 ns tdHZ disable HIGH C - 9.7 14 ns tdLZ disable LOW C - 9.5 13 ns [1] [2] [3] [4] [5] D = guaranteed by design; C = guaranteed by characterization; I = 100% industrially tested. The circuit has two clock inputs: CLK and CLK. There are 5 modes of operation: a) PECL mode 1: (DC level vary 1:1 with VCCD) CLK and CLK inputs are at differential PECL levels. b) PECL mode 2: (DC level vary 1:1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. c) PECL mode 3: (DC level vary 1:1 with VCCD) CLK input is at PECL level and sampling is taken on the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor. e) TTL mode 1: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLK pin has to be connected to the ground. The ADC input range can be adjusted with an external reference connected to Vref pin. This voltage has to be referenced to VCCA; see Figure 12. The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. Total Harmonic Distortion (THD) is obtained with the addition of the first five harmonics: 2 2 2 2 2 ( 2nd ) + ( 3rd ) + ( 4th ) + ( 5th ) + ( 6th ) THD = 20 log -------------------------------------------------------------------------------------------------------------------------------------2 F [6] [7] [8] [9] where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see Figure 6. Signal-to-noise ratio (SNR) takes into account all harmonics above five and noise up to nyquist frequency; see Figure 8. Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to SINAD is given by SINAD = ENOB × 6.02 + 1.76 dB; see Figure 5. Intermodulation measured relative to either tone with analog input frequencies of 20 and 20.1 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (−6 dB below full scale for each input signal). d3(IM3) is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product. Output data acquisition: the output data is available after the maximum delay of td; see Figure 3. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 11 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Table 7: Output coding with differential inputs (typical values to AGND); Vi(p-p) − Vi(p-p) = 1.9 V, Vref = VCCA3 − 1.75 V Code Vi(p-p) Vi(p-p) IR Binary outputs Twos complement outputs[1] D11 to D0 D11 to D0 Underflow <3.125 >4.075 0 000000000000 100000000000 0 3.125 4.075 1 000000000000 1 0 0 0 0 0 0 0 0 0 00 1 − − 1 000000000001 100000000001 ↓ − − ↓ ↓ ↓ 2047 3.6 3.6 1 011111111111 111111111111 ↓ − − ↓ ↓ ↓ 4094 − − 1 111111111110 011111111110 4095 4.075 3.125 1 111111111111 011111111111 Overflow >4.075 <3.125 0 111111111111 011111111111 [1] Twos complement reference is inverted MSB. Table 8: Mode selection OTC CE D0 to D11 and IR 0 0 binary; active 1 0 twos complement; active X[1] 1 high-impedance [1] X = don’t care. Table 9: Sample-and-hold selection SH Sample-and-hold 1 active 0 inactive; tracking mode tCLKH tCLKL HIGH CLK 50 % LOW sample N sample N + 1 sample N + 2 Vl t ds th HIGH DATA D0 to D11 DATA N−2 DATA N−1 DATA N DATA N+1 50 % LOW td MBG855 Fig 3. Timing diagram. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 12 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) V CCD 50 % CE 0V tdHZ tdZH HIGH 90 % output data 50 % LOW tdZL tdLZ HIGH output data 50 % LOW 10 % V CCO 3.3 kΩ S1 TDA8768A 15 pF CE TEST S1 t dLZ t dZL VCCO VCCO t dHZ OGND t dZH OGND MBG856 fCE = 100 kHz. Fig 4. Timing diagram and test conditions of 3-state output delay time. 005aaa011 10.4 ENOB (bits) 005aaa012 −58 THD (dBFS) −60 (1) 10.2 (2) 10 −62 (3) 9.8 −64 9.6 −66 9.4 −68 9.2 −70 (3) 9 (2) (1) −72 1 10 fi (MHz) 1 100 (1) 40 Msps (1) 40 Msps (2) 55 Msps (2) 55 Msps (3) 70 Msps (3) 70 Msps Fig 5. Effective number of bits (ENOB) as a function of input frequency (sample device). fi (MHz) 100 Fig 6. Total harmonic distortion (THD) as a function of input frequency (sample device). © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data 10 Rev. 02 — 03 July 2002 13 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 005aaa013 74 005aaa014 65.5 SFDR (dBFS) SNR (dBFS) 72 65 (3) (1) (1) 70 64.5 (3) 68 (2) (2) 64 66 63.5 64 63 62 62.5 60 62 1 10 100 fi (MHz) 10 1 (1) 40 Msps (1) 40 Msps (2) 55 Msps (2) 55 Msps (3) 70 Msps (3) 70 Msps Fig 7. Spurious free dynamic range (SFDR) as a function of input frequency (sample device). fi (MHz) 100 Fig 8. Signal-to-noise ratio (SNR) as a function of input frequency (sample device). 005aaa015 0 power spectrum (dB) -20 -40 -60 -80 -100 -120 -140 -160 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 measured output range (MHz) Fig 9. Single-tone; fi = 20 MHz; fCLK = 55 Msps. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 14 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 005aaa016 0 power spectrum (dB) -20 -40 -60 -80 -100 -120 -140 -160 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 measured output range (MHz) Fig 10. Two-tone; fi1 = 20 MHz; fi2 = 20.1 MHz; fCLK = 55 Msps. 005aaa017 2 1.5 output range (INL) 1 0.5 0 -0.5 -1 -1.5 -2 0 512 1024 1536 2048 2560 3072 3584 4096 output code Fig 11. Integral non-linearity (INL). © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 15 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 005aaa018 0.6 DNL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 output code Fig 12. Differential non-linearity (DNL). 005aaa019 80 SFDR (dBFS) 70 60 50 (1) 40 (2) (3) 30 20 -60 -50 -40 -30 -20 -10 0 Vi (dBFS) (1) fi = 4.43 MHz (2) fi = 20 MHz (3) SFDR = 80 dB Fig 13. SFDR as a function of input amplitude; FS = 1.9 V; fCLK = 40 MHz. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 16 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 005aaa020 80 SFDR (dBFS) 70 60 50 (2) 40 (1) 30 (3) 20 -60 -50 -40 -30 -20 -10 0 Vi (dBFS) (1) fi = 4.43 MHz (2) fi = 20 MHz (3) SFDR = 80 dB Fig 14. Spurious free dynamic range (SFDR) as a function of input amplitude; FSREF = 1.9 V; fCLK = 55 MHz. 005aaa021 72 (3) 70 10.5 (dB) bits (2) 68 005aaa022 2.6 11 2.4 (Vi - Vi)(p-p) (V) 2.2 10 2 66 9.5 64 9 1.8 1.6 (1) 1.4 62 8.5 1.2 60 8 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 1 2.1 2.2 Vref (V) 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 VCCA - Vref (V) (1) = SNR (2) = ENOB (3) = SFDR Fig 15. ENOB, SFDR and SNR as a function of Vref; fCLK = 55 MHz; fi = 4.43 MHz. Fig 16. ADC full-scale; VI(p-p) − VI(p-p) as a function of VCCA − Vref. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 17 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 11. Application information 11.1 Application diagrams 5V SH mode 100 nF 220 nF 5V 100 nF VI 1:1 CLK 100 Ω 100 Ω VI 5V 1 5V 10 nF 100 nF 44 43 42 41 40 39 38 37 36 35 34 100 nF 33 2 32 D0 (LSB) 3 31 D1 4 30 D2 5 29 D3 28 D4 100 nF n.c. 6 n.c. 7 27 D5 n.c. 8 26 D6 n.c. 9 25 D7 n.c. 10 24 D8 11 23 D9 Vref TDA8768A 12 13 14 15 16 17 18 19 20 21 22 n.c. n.c. n.c. IR D10 D11 (MSB) 5V 100 nF chip select input output format select FCE003 The analog, digital and output supplies should be separated and decoupled. Fig 17. Application diagram. TTL input CLK D MC100 ELT20 PECL TDA8768A CLK 270 Ω 270 Ω FCE168 Fig 18. Application diagram for differential clock input PECL compatible using a TTL to PECL translator. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 18 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) CLK TDA8768A TTL input CLK FCE169 Fig 19. Application diagram for TTL single-ended clock. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 19 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 11.2 Demonstration board B11 1 3 5 7 9 11 13 15 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 24 J2 CLK2 R4 50 VCC C6 330 nF VCCO 33 32 DO 31 D1 30 D2 29 D3 28 D4 27 D5 26 D6 25 D7 24 D8 23 D9 C15 10 nF VCCO FL3 C13 100 nF CLK C19 C8 330 nF VCCA 1 GND J4 2 1 n.c. Vref 17 S3 16 VCC FL2 C12 100 nF C18 10 nF C5 330 nF FL1 11 n.c. n.c. 9 10 7 8 n.c. n.c. DEC 6 18 P2 R7 VCCA 1 kΩ 1.2 kΩ R6 2.4 kΩ VCC VCC TM3 OUT IN 19 S2 B7 VCC IC1 C1 22 µF (20 V) S4 20 VCCD2 15 14 n.c 13 n.c 12 FSref C7 330 nF C14 100 nF J4 B5 21 VCCA FL4 5 kΩ 12 V 22 C11 100 nF C10 100 nF C16 10 nF S1 P1 BYD17G D3 5 1 MCLT1_6T_KK81 DGND2 n.c VCCA3 R9 100 Ω OTC IC2 TDA8768A AGDN3 J1 CE 4 TR1 CMADC C17 10 nF IR 3 VCCA R1 100 Ω D11 CLK 37 V CCD1 38 DGND1 39 SH 40 AGND4 41 V CCA4 42 V i 43 V i 44 AGND1 S5 VCCD CLK 36 VCCA1 10 nF D10 CMADC J3 C9 220 nF OGND 35 2 CLK1 IN 34 R3 50 Ω MC78MO5CDT 3 C2 4.7 µF (16 V) PMBT 2222A R2 82 Ω R8 750 Ω D1 LGT679 VCCO T1 GND BZV55C3V6 C3 1 µF D2 R5 4.7 kΩ C4 1 µF TP2 VCCO FCE733 C8 = close to TR1 pin. Fig 20. Demonstration board schematic. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 20 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) TM2 R1 J1 J3 C9 B4 1 1 S5 TR1 S1 R3 P1 34 1 R9 C7 FL4 IC1 R8 R2 T1 R5 1 C12 D1 C3 D2 1 R6 B5 P2 C4 J4 23 1 12 TP2 C2 D3 IC2 C14 B7 C11 TM3 C1 C10 S2 R7 S3 S4 FL2 J2 C5 B8 R4 B11 TM1 2 1 F68A21 MSD808 Fig 21. Component placement (top side). C6 FL3 C19 C15 C8 C13 C16 FL1 C17 C18 F68A22 MSD809 Fig 22. Component placement (underside). © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 21 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) FCE725 Fig 23. PCB layout (top layer). FCE726 Fig 24. PCB layout (ground layer). © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 22 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) FCE727 Fig 25. PCB layout (power plane). 12. Support information 12.1 Definitions 12.1.1 Non-linearities Integral Non-Linearity (INL).: It is defined as the deviation of the transfer function from a best fit straight line (linear regression computation). The INL of the code i is obtained from the equation: V in ( i ) – V in ( ideal ) INL ( i ) = ----------------------------------------------S where n i = 0 ⋅ ( 2 – 1 ) and S = slope of the ideal straight line = code width; i = code value. Differential Non-Linearity (DNL).: It is the deviation in code width from the value of 1LSB. V in ( i + 1 ) – V in ( i ) DNL ( i ) = --------------------------------------------–1 S where n i = 0 ⋅ (2 – 2) © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 23 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 12.1.2 Dynamic parameters (single tone) Figure 26 shows the spectrum of a full-scale input sine wave with frequency ft, conforming to coherent sampling (ft/fs = M/N, where M is the number of cycles and N is number of samples, M and N being relatively prime), and digitized by the ADC under test. FCE710 magnitude a1 SFDR a2 s a3 ak measured output range fs/2 Fig 26. Spectrum of full-scale input sine wave with frequency ft. Remark: in the following equations, Pnoise is the power of the terms which include the effects of random noise, non-linearities, sampling time errors, and “quantization noise”. Signal-to-noise and distortion (SINAD): The ratio of the output signal power to the noise plus distortion power for a given sample rate and input frequency, excluding the DC component: P signal SINAD [ db ] = 10 log -----------------------------------------P noise + distortion Effective Number of Bits (ENOB): It is derived from SINAD and gives the theoretical resolution an ideal ADC would require to obtain the same SINAD measured on the real ADC. A good approximation gives: ENOB = ( SINAD [ dB ] – ( 1 ⋅ 76 ) ) ⁄ ( 6 ⋅ 02 ) Total Harmonic Distortion (THD): The ratio of the power of the harmonics to the power of the fundamental. For k-1 harmonics the THD is: P harmonics THD [ dB ] = 10 log --------------------------P signal where 2 2 P harmonics = a 2 + a 3 + a P signal = a 2 k 2 1 The value of k is usually 6 (i.e. calculation of THD is done on the first 5 harmonics). © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 24 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Signal-to-Noise Ratio (SNR): The ratio of the output signal power to the noise power, excluding the harmonics and the DC component. P signal SNR [ dB ] = 10 log ----------------P noise Spurious Free Dynamic Range (SFDR): The number SFDR specifies available signal range as the spectral distance between the amplitude of the fundamental and the amplitude of the largest spurious (harmonic and non-harmonic, excluding DC component. a1 SFDR [ dB ] = 20 log ----------------max ( s ) 12.1.3 Intermodulation distortion Spectral analysis (dual-tone) 005aaa023 0 -20 (dB) IMD3 -40 -60 -80 -100 -120 -140 -160 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 measured output range (MHz) Fig 27. Spectral analysis (dual-tone) From a dual-tone input sinusoid (ft1 and ft2, these frequencies being chosen according to the coherence criterion), the intermodulation distortion products IMD2 and IMD3 (respectively, 2nd and 3rd-order components) are defined, as follows. IMD2 (IMD3): The ratio of the RMS value of either tone to the RMS value of the worst second (third) order intermodulation product. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 25 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) The total intermodulation distortion IMD is given by P intermod IMD [ dB ] = 10 log ----------------------P signal where, P intermod = a +a 2 (f im t1 2 (f im t1 – f t2 ) – a + 2 f t2 ) + a 2 ( 2 f t1 im 2 (f im t1 + f t2 ) + a – f t2 ) + a 2 ( 2 f t1 im 2 (f im t1 – 2 f t2 ) + f t2 ) P signal = a 2 ( f t1 ) + a 2 ( f t2 ) and a 2 (f ) im t is the power in the intermodulation component at frequency ft. 12.1.4 Noise Power Ratio (NPR) When using a notch-filtered broadband white-noise generator as the input to the ADC under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the in-notch power spectral density magnitudes for the FFT spectrum of the ADC output sample set. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 26 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 13. Package outline QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e E HE A A2 wM (A 3) A1 θ bp Lp pin 1 index L 12 44 1 detail X 11 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.10 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 10.1 9.9 0.8 12.9 12.3 12.9 12.3 1.3 0.95 0.55 0.15 0.15 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ o 10 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-08-01 SOT307-2 Fig 28. SOT307-2. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 27 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 14. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe, it is desirable to take normal precautions appropriate to handling integrated circuits. 15. Soldering 15.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 15.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C small/thin packages. 15.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 28 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 15.5 Package related soldering information Table 10: Suitability of surface mount IC packages for wave and reflow soldering methods Package[1] Soldering method Reflow[2] Wave BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable[3] suitable PLCC[4], SO, SOJ suitable suitable LQFP, QFP, TQFP not SSOP, TSSOP, VSO not recommended[6] [1] [2] [3] [4] [5] [6] suitable suitable For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data recommended[4][5] Rev. 02 — 03 July 2002 29 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 16. Revision history Table 11: Revision history Rev Date 02 20020703 CPCN Description - Product data (9397 750 09656); supersedes Preliminary specification TDA8768A_1 of 20020409 (9397 750 08323) Modifications: • • • 01 20020409 - Raise to Product Features list corrected Change value of INL in Table 6. Preliminary data; initial version. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Product data Rev. 02 — 03 July 2002 30 of 32 TDA8768A Philips Semiconductors 12-bit, 70 Msps Analog-to-Digital Converter (ADC) 17. Data sheet status Data sheet status[1] Product status[2] Definition Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 18. Definitions 19. Disclaimers Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: [email protected]. Product data Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09656 Rev. 02 — 03 July 2002 31 of 32 Philips Semiconductors TDA8768A 12-bit, 70 Msps Analog-to-Digital Converter (ADC) Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 11.1 11.2 12 12.1 12.1.1 12.1.2 12.1.3 12.1.4 13 14 15 15.1 15.2 15.3 15.4 15.5 16 17 18 19 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application information. . . . . . . . . . . . . . . . . . 18 Application diagrams . . . . . . . . . . . . . . . . . . . 18 Demonstration board . . . . . . . . . . . . . . . . . . . 20 Support information . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Non-linearities. . . . . . . . . . . . . . . . . . . . . . . . . 23 Dynamic parameters (single tone) . . . . . . . . . 24 Intermodulation distortion . . . . . . . . . . . . . . . . 25 Noise Power Ratio (NPR) . . . . . . . . . . . . . . . . 26 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 27 Handling information. . . . . . . . . . . . . . . . . . . . 28 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 28 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 28 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 29 Package related soldering information . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 30 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 31 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 © Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 03 July 2002 Document order number: 9397 750 09656