PHILIPS TDA8767H

INTEGRATED CIRCUITS
DATA SHEET
TDA8767
12-bit high-speed Analog-to-Digital
Converter (ADC)
Preliminary specification
Supersedes data of 1997 Jun 27
File under Integrated Circuits, IC02
1999 Feb 16
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
FEATURES
APPLICATIONS
• 12-bit resolution
• High-speed analog-to-digital conversion for:
• Sampling rate up to 30 MHz
– Video signal digitizing
• −3 dB bandwidth of 18 MHz
– High Definition TV (HDTV)
• No missing codes guaranteed
– Imaging (camera, scanner)
• 5 V power supplies
– Medical imaging
• Binary or two’s complement CMOS outputs
– Telecommunication
• In-range CMOS output
– Base-station receiver.
• TTL/CMOS compatible static digital inputs
• 3 to 5 V CMOS digital outputs
GENERAL DESCRIPTION
• TTL compatible clock input
The TDA8767 is a bipolar 12-bit Analog-to-Digital
Converter (ADC) for imaging or other applications.
It converts the analog input signal into 12-bit binary coded
digital words at a maximum sampling rate of 30 MHz.
All digital inputs and outputs are CMOS compatible.
• Power dissipation 335 mW (typ.)
• Low analog input capacitance (typ. 2 pF), no buffer
amplifier required
• No external sample-and-hold circuit required
• Differential or single analog Input
• External amplitude range control
• Voltage controlled regulator included.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA
analog supply voltage
4.75
5.0
5.25
V
VCCD
digital supply voltage
4.75
5.0
5.25
V
VCCO
output supply voltage
3.0
3.3
5.25
V
ICCA
analog supply current
−
40
tbf
mA
ICCD
digital supply current
−
22
tbf
mA
ICCO
output supply current
fclk = 4 MHz; fi = 400 kHz
−
3.2
tbf
mA
ILE
integral non-linearity
fclk = 4 MHz; fi = 400 kHz
−
±3.0
±4.0
LSB
DLE
differential non-linearity
fclk = 4 MHz; fi = 400 kHz;
no missing codes
−
±0.6
±1
LSB
fclk(max)
maximum clock frequency
TDA8767H/1
10
−
−
MHz
TDA8767H/2
20
−
−
MHz
TDA8767H/3
30
−
−
MHz
−
335
−
mW
Ptot
1999 Feb 16
total power dissipation
2
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
DESCRIPTION
VERSION
SAMPLING
FREQUENCY (MHz)
TDA8767H/1
TDA8767H/2
10
plastic quad flat package; 44 leads
(lead length 1.3 mm); body 10 × 10 × 1.75 mm
QFP44
TDA8767H/3
SOT307-2
20
30
BLOCK DIAGRAM
VCCA1 VCCA2 VCCA3 VCCA4
handbook, full pagewidth
2
9
3
VCCD1 VCCD2
CLK
41
36
37
15
TC
OE
18
19
21 D11
MSB
CLOCK DRIVER
22 D10
TDA8767
Vref
23 D9
11
24 D8
25 D7
AMP
26 D6
CMOS
OUTPUTS
VI
VI
27 D5
42
ANALOG-TO-DIGITAL
CONVERTER
43
LATCHES
29 D3
30 D2
sampleand-hold
SH
31 D1
32 D0
39
33
IN-RANGE
LATCH
44
10
AGND1
AGND2
4
AGND3
analog ground
20
CMOS
OUTPUT
40
38
17
34
AGND4
DGND1
DGND2
OGND
digital ground
Fig.1 Block diagram.
1999 Feb 16
data outputs
28 D4
3
LSB
VCCO
IR
MBH142
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
PINNING
SYMBOL
PIN
DESCRIPTION
SYMBOL
PIN
DESCRIPTION
n.c.
1
not connected
D9
23
data output; bit 9
VCCA1
2
analog supply voltage 1 (+5 V)
D8
24
data output; bit 8
VCCA3
3
analog supply voltage 3 (+5 V)
D7
25
data output; bit 7
AGND3
4
analog ground 3
D6
26
data output; bit 6
n.c.
5
not connected
D5
27
data output; bit 5
n.c.
6
not connected
D4
28
data output; bit 4
n.c.
7
not connected
D3
29
data output; bit 3
n.c.
8
not connected
D2
30
data output; bit 2
VCCA2
9
analog supply voltage 2 (+5 V)
D1
31
data output; bit 1
AGND2
10
analog ground 2
D0
32
data output; bit 0 (LSB)
Vref
11
reference voltage
VCCO
33
output supply voltage (3 to 5.25 V)
n.c.
12
not connected
OGND
34
output ground
n.c.
13
not connected
n.c.
35
not connected
n.c.
14
not connected
CLK
36
clock input
VCCD2
15
digital supply voltage 2 (+5 V)
VCCD1
37
digital supply voltage 1 (+5 V)
n.c.
16
not connected
DGND1
38
digital ground 1
DGND2
17
digital ground 2
SH
39
TC
18
output two’s complement
sample-and-hold enable input
(CMOS level; active HIGH)
OE
19
output enable input
(CMOS level; active LOW)
AGND4
40
analog ground 4
VCCA4
41
analog supply voltage 4 (+5 V)
42
complementary analog input voltage
IR
20
in-range output
VI
D11
21
data output; bit 11 (MSB)
VI
43
analog input voltage
D10
22
data output; bit 10
AGND1
44
analog ground 1
1999 Feb 16
4
Philips Semiconductors
Preliminary specification
34 OGND
n.c.
1
33 VCCO
VCCA1
2
32 D0
VCCA3
3
31 D1
AGND3
4
30 D2
n.c.
5
29 D3
TDA8767
26 D6
VCCA2
9
25 D7
AGND2 10
24 D8
Vref 11
23 D9
5
D10 22
D11 21
IR 20
28 D4
OE 19
TC 18
8
DGND2 17
n.c.
n.c. 16
27 D5
VCCD2 15
7
n.c. 14
n.c.
n.c. 13
6
n.c. 12
n.c.
Fig.2 Pin configuration.
1999 Feb 16
35 n.c.
36 CLK
37 VCCD1
38 DGND1
39 SH
TDA8767
40 AGND4
41 VCCA4
42 VI
handbook, full pagewidth
43 VI
44 AGND1
12-bit high-speed Analog-to-Digital
Converter (ADC)
MBH143
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCCA
analog supply voltage
note 1
−0.3
+7.0
V
VCCD
digital supply voltage
note 1
−0.3
+7.0
V
VCCO
output supply voltage
note 1
−0.3
+7.0
V
∆VCC
supply voltage difference
VCCA − VCCD
−1.0
+1.0
V
VCCO − VCCD
−1.0
+4.0
V
VCCA − VCCO
−1.0
+4.0
V
VI
input voltage
0.3
VCCA
V
Vi(p-p)
input voltage for differential clock
drive (peak-to-peak value)
−
VCCD
V
IO
output current
−
10
mA
Tstg
storage temperature
−55
+150
°C
Tamb
operating ambient temperature
0
70
°C
Tj
junction temperature
−
+150
°C
referenced to AGND
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided that the supply
voltage differences ∆VCC are respected.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
1999 Feb 16
PARAMETER
thermal resistance from junction to ambient in free air
6
VALUE (TYP.)
UNIT
75
K/W
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
CHARACTERISTICS
VCCA = V2 to V44, V9 to V10, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V;
VCCO = V33 to V34 = 3.0 to 5.25 V; AGND and DGND shorted together; Tamb = 0 to +70 °C; typical values measured at
VCCA = VCCD = 5 V and VCCO = 3.3 V; Vi(p-p) − Vi(p-p) = 2.0 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VCCA
analog supply voltage
4.75
VCCD
digital supply voltage
4.75
5.0
5.25
V
VCCO
output supply voltage
3.0
3.3
5.25
V
ICCA
analog supply current
−
40
tbf
mA
ICCD
digital supply current
−
22
tbf
mA
ICCO
output supply current
−
12
tbf
mA
fclk = 20 MHz; fi = 4.43 MHz
5.0
5.25
V
Inputs
CLK (REFERENCED TO DGND)
VIL
LOW-level input voltage
0
−
0.8
V
VIH
HIGH-level input voltage
2.0
−
VCCD
V
IIL
LOW-level input current
Vclk = 0.3VCCD
−400
−
−
µA
IIH
HIGH-level input current
Vclk = 0.7VCCD
−
−
100
µA
Vclk = VCCD
−
−
300
µA
Zi
input impedance
fclk = 30 MHz
−
2
−
kΩ
Ci
input capacitance
fclk = 30 MHz
−
2
−
pF
TC; SH AND OE (REFERENCED TO DGND); see Tables 3 and 4
VIL
LOW-level input voltage
0
−
0.8
V
VIH
HIGH-level input voltage
2.0
−
VCCD
V
IIL
LOW-level input current
VIL = 0.3VCCD
−400
−
−
µA
IIH
HIGH-level input current
VIH = 0.7VCCD
−
−
20
µA
VI AND VI (REFERENCED TO AGND; see Tables 1 AND 2); Vref = VCCA − 2 V
IIL
LOW-level input current
Vi = Vi
−
10
−
µA
IIH
HIGH-level input current
Vi = Vi
−
10
−
µA
Zi
input impedance
fi = 4.43 MHz
−
10
−
kΩ
Ci
input capacitance
fi = 4.43 MHz
−
2
−
pF
Vios(d)
input offset voltage in
differential mode
VI = VI; output code 2047
VCCA = 5 V
tbf
2.5
tbf
V
VCCA = 4.75 V
tbf
2.25
tbf
V
VCCA = 5.25 V
tbf
2.75
tbf
V
VCCA = 5 V
tbf
2.5
tbf
V
VCCA = 4.75 V
tbf
2.25
tbf
V
VCCA = 5.25 V
tbf
2.75
tbf
V
Vios(s)
1999 Feb 16
input offset voltage in single
mode
VI = Vios(s); output
code 2047
7
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
SYMBOL
PARAMETER
TDA8767
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Voltage controlled regulator input Vref (referenced to VCCA)
Vref(FS)
full scale fixed voltage
Vi(p-p) − Vi(p-p) input voltage amplitude
(peak-to-peak value)
Iref
VCCA = 5 V
−
3.175
−
V
differential mode
−
2.0
−
V
single mode; Vi = 2.5 V
−
2.0
−
V
−
10
−
µA
input current at Vref
Outputs (referenced to DGND)
DIGITAL OUTPUTS D11 TO D0 AND IR (REFERENCED TO DGND)
VOL
LOW-level output voltage
IOL = 2 mA
0
−
0.5
V
VOH
HIGH-level output voltage
IOH = −0.4 mA
VCCO − 0.5
−
VCCD
V
IO
output current in 3-state
0.5 V < VO < VCCO
−20
−
+20
µA
SH = HIGH
−
−
1
MHz
SH = LOW
−
−
1
kHz
TDA8767H/1
10
−
−
MHz
TDA8767H/2
20
−
−
MHz
TDA8767H/3
30
−
−
MHz
Switching characteristics
CLOCK FREQUENCY fclk (see Fig.3)
fclk(min)
minimum clock frequency
fclk(max)
maximum clock frequency
tCPH
clock pulse width HIGH
8.5
−
−
ns
tCPL
clock pulse width LOW
8.5
−
−
ns
Analog signal processing; 50% clock duty factor; Vi − Vi = 2.0 V; Vref = VCCA − 2 V; see Table 1
LINEARITY
ILE
integral non-linearity
fclk = 4 MHz; ramp input
−
±3.0
±4.0
LSB
DLE
differential non-linearity
fclk = 4 MHz; ramp input;
no missing codes
−
±0.6
±1
LSB
OFER
offset error
VCCA = VCCD = VCCO = 5 V;
Tamb = 25 °C; Vi = Vi; output
code = 2047
tbf
−
tbf
LSB
GER
gain error amplitude; spread
from device to device
VCCA = VCCD = VCCO = 5 V;
Tamb = 25 °C; Vi − Vi = 2.0 V
tbf
−
tbf
LSB
−1 dB
−
9
−
MHz
BANDWIDTH (fclk = 30 MHz); note 1
B
analog bandwidth
−3 dB
−
18
−
MHz
tSTLH
analog input settling time
LOW-to-HIGH transition
full scale square wave;
note 3
−
tbf
−
ns
tSTHL
analog input settling time
HICH-to-LOW transition
full scale square wave;
note 3
−
tbf
−
ns
total harmonic distortion
fclk = 30 MHz; fi = 4.43 MHz;
note 2
−
−64
−
dB
HARMONICS
THD
1999 Feb 16
8
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
SYMBOL
PARAMETER
TDA8767
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SIGNAL-TO-NOISE RATIO
S/N
signal-to-noise ratio
without harmonics;
fclk = 30 MHz; fi = 4.43 MHz
−
61
−
dB
−
−
2
ns
8
−
−
ns
−
12
15
ns
15
18
ns
Timing (CL = 15 pF); note 4; see Fig.3
tds
sampling delay time
th
output hold time
td
output delay time
VCCO = 4.75 V
VCCO = 3.15 V
3-state output delay times; see Fig.4
tdZH
enable HIGH
−
14
18
ns
tdZL
enable LOW
−
16
20
ns
tdHZ
disable HIGH
−
16
20
ns
tdLZ
disable LOW
−
14
18
ns
Notes to the characteristics
1. The −3 dB (or −1 dB) analog bandwidth is determined by the 3 dB (or 1 dB) reduction in the reconstructed output,
the input being a full-scale sine wave.
2. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:
F
THD = 20 log --------------------------------------------------------------------------------------------------------------2
2
2
2
2
(2nd) + (3rd) + (4th) + (5th) + (6th)
F being the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.
3. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square wave signal) in order to sample the signal and obtain correct output data (see Fig.5).
4. Output data acquisition: the output data is available after the maximum delay of td.
1999 Feb 16
9
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
Table 1
TDA8767
Output coding with differential inputs (typical values to AGND); VI(p-p) − VI(p-p) = 2.0 V; Vref = VCCA − 2 V
CODE
VI
VI
BINARY OUTPUTS
TWO’S COMPLEMENT
OUTPUTS
D11 to D0
D11 to D0
0
000000000000
100000000000
IR
underflow
<2.0
>3.0
0
2.0
3.0
1
000000000000
1 0 0 0 0 0 0 0 0 0 00
1
−
−
1
0 0 0 0 0 0 0 0 0 0 01
100000000001
↓
−
−
↓
↓
↓
2047
2.5
2.5
1
011111111111
111111111111
↓
−
−
↓
↓
↓
4094
−
−
1
111111111110
011111111110
4095
3.0
2.0
1
111111111111
011111111111
overflow
>3.0
<2.0
0
111111111111
011111111111
Table 2
Output coding with single input (typical values to AGND); VFS = 2.0 V (p-p); Vref = VCCA − 2 V
CODE
BINARY OUTPUTS
TWO’S COMPLEMENT
OUTPUTS
D11 to D0
D11 to D0
IR
VI
underflow
<1.5
0
000000000000
100000000000
0
1.5
1
000000000000
1 0 0 0 0 0 0 0 0 0 00
1
−
1
0 0 0 0 0 0 0 0 0 0 01
100000000001
↓
−
↓
↓
↓
2047
2.5
1
011111111111
111111111111
↓
−
↓
↓
↓
4094
−
1
111111111110
011111111110
4095
3.5
1
111111111111
011111111111
overflow
>3.5
0
111111111111
011111111111
Table 3 Mode selection
TC
OE
D0 to D11 and IR
0
0
binary; active
1
0
two’s complement; active
X(1)
1
high impedance
Note
1. Where: X = don’t care.
Table 4 Sample-and-hold selection
SH
SAMPLE-AND-HOLD
1
active
0
inactive; tracking mode
1999 Feb 16
10
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
t CPL
handbook, full pagewidth
t CPH
HIGH
CLK
50 %
LOW
sample N
sample N + 1
sample N + 2
Vl
t ds
th
HIGH
DATA
D0 to D11
DATA
N-2
DATA
N-1
DATA
N
DATA
N+1
50 %
LOW
td
MBG855
Fig.3 Timing diagram.
handbook, full pagewidth
V CCD
50 %
OE
0V
t dHZ
t dZH
HIGH
90 %
output
data
50 %
t dLZ
LOW
t dZL
HIGH
output
data
50 %
LOW
10 %
V CCD
3.3 kΩ
S1
TDA8767
15 pF
TEST
S1
t dLZ
t dZL
VCCD
VCCD
t dHZ
DGND
t dZH
DGND
OE
MBH144
fOE = 100 kHz.
Fig.4 Timing diagram and test conditions of 3-state output delay time.
1999 Feb 16
11
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
t STHL
t STLH
handbook, full pagewidth
code 1023
VI
50 %
50 %
code 0
5 ns
5 ns
CLK
MBD875
50 %
50 %
2 ns
2 ns
Fig.5 Analog input settling time diagram.
1999 Feb 16
12
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
APPLICATION INFORMATION
5V
handbook, full pagewidth
100 nF
220 nF
SH
mode
5V
100 nF
VI
1:1
IN
100 Ω
CLK(1)
VI
100 Ω
n.c.
VCCA
R1
(2)
4.7 µF
10
nF
n.c.
5V
100 nF
100 nF
100 nF
(3)
Vref
100 nF
33
2
32
D0 (LSB)
3
31
D1
4
30
D2
n.c.
5
29
D3
n.c.
6
28
D4
n.c.
7
27
D5
n.c.
8
26
D6
9
25
D7
10
24
D8
11
23
D9
R2
5V
44 43 42 41 40 39 38 37 36 35 34
1
5V
TDA8767H
12 13 14 15 16 17 18 19 20 21 22
MBH145
n.c.
n.c.
n.c.
5V
100 nF
n.c.
IR
D10
D11
(MSB)
chip select input (OE)
output format select (TC)
The analog, digital and output supplies should be separated and decoupled.
(1) At power-up a high level clock must be provided within less than 1 µs or a pull-up resistor must be connected between CLK and VCCD.
(2) R1, and R2 must be determined in order to obtain a middle voltage of 2.5 V; see Table 1. To ensure a sufficient analog input stability, the minimum
current into these resistors must be about 1 mA.
(3) Vref must be decoupled to VCCA.
Fig.6 Application diagram (differential input mode).
1999 Feb 16
13
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
5V
handbook, full pagewidth
100 nF
220 nF
SH
mode
5V
100 nF
VI
IN
50 Ω
CLK(1)
VI
n.c.
50 Ω
50 Ω
R1
n.c.
VCCA
(2)
R2
4.7
µF
10
nF
5V
100 nF
(3)
Vref
1
5V
100 nF
33
2
32
D0 (LSB)
3
31
D1
4
30
D2
n.c.
5
29
D3
n.c.
6
28
D4
n.c.
7
27
D5
n.c.
8
26
D6
9
25
D7
10
24
D8
11
23
D9
5V
100 nF
100 nF
44 43 42 41 40 39 38 37 36 35 34
TDA8767H
12 13 14 15 16 17 18 19 20 21 22
MBH146
n.c.
n.c.
n.c.
5V
100 nF
n.c.
IR
D10
D11
(MSB)
chip select input OE
output format select TC
The analog, digital and output supplies should be separated and decoupled.
(1) At power-up a high level clock must be provided within less than 1 µs or a pull-up resistor must be connected between CLK and VCCD.
(2) R1, and R2 must be determined in order to obtain a voltage of 2.5 V on VI and VI; see Table 1. To ensure a sufficient analog input stability, the
minimum current into these resistors must be about 1 mA.
(3) Vref must be decoupled to VCCA.
Fig.7 Application diagram (single input mode).
1999 Feb 16
14
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
PACKAGE OUTLINE
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
c
y
X
A
33
23
34
22
ZE
e
E HE
A A2
wM
(A 3)
A1
θ
bp
Lp
pin 1 index
L
12
44
1
detail X
11
wM
bp
e
ZD
v M A
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
2.10
0.25
0.05
1.85
1.65
0.25
0.40
0.20
0.25
0.14
10.1
9.9
10.1
9.9
0.8
12.9
12.3
12.9
12.3
1.3
0.95
0.55
0.15
0.15
0.1
Z D (1) Z E (1)
1.2
0.8
1.2
0.8
θ
o
10
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-02-04
97-08-01
SOT307-2
1999 Feb 16
EUROPEAN
PROJECTION
15
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
• For packages with leads on two sides and a pitch (e):
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1999 Feb 16
16
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not
PLCC(3),
SO, SOJ
suitable
suitable(2)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(3)(4)
suitable
SSOP, TSSOP, VSO
not recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Feb 16
17
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
NOTES
1999 Feb 16
18
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
NOTES
1999 Feb 16
19
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1999
SCA62
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/750/03/pp20
Date of release: 1999 Feb 16
Document order number:
9397 750 04713