PHILIPS P87C524EBAA

INTEGRATED CIRCUITS
87C524/87C528
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
Product specification
Replaces data sheets 87C524 of 1998 May 01 and 87C528 of 1998 May 01
IC28 Data Handbook
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
FEATURES
• 80C51 instruction set
– 512 × 8 RAM
– Memory addressing capability
64k ROM and 64k RAM
– Three 16-bit counter/timers
– On-chip watchdog timer with oscillator
– Full duplex UART
– I2C serial interface
DESCRIPTION
• Power control modes:
The 87C528 single-chip 8-bit microcontroller is manufactured in an
advanced CMOS process and is a derivative of the 80C51
microcontroller family. The 87C528 has the same instruction set as
the 80C51. Three versions of the derivative exist:
– Idle mode
– Power-down mode
– Warm start from power-down
• 83C528—32k bytes ROM
• 83C524—16k bytes ROM
• 80C528—ROMless version of the 83C528
• 87C528—32k bytes EPROM
• 83C524—16k bytes EPROM
• CMOS and TTL compatible
• Extended temperature ranges
• EPROM code protection
• OTP package available
• 16 MHz speed at VCC = 5 V
This device provides architectural enhancements that make it
applicable in a variety of applications in consumer, telecom and
general control systems, especially in those systems which need
large ROM and RAM capacity on-chip.
The 87C528 contains a 32k × 8 EPROM and the 87C524 contains a
16k x 8 EPROM. Both devices have a 512 × 8 RAM, four 8-bit I/O
ports, two 16-bit timer/event counters (identical to the timers of the
80C51), a 16-bit timer (identical to the timer 2 of the 80C52), a
watchdog timer with a separate oscillator, a multi-source,
two-priority-level, nested interrupt structure, two serial interfaces
(UART and I2C-bus), and on-chip oscillator and timing circuits.
In addition, the 87C524/87C528 has two software selectable modes
of power reduction—idle mode and power-down mode. The idle
mode freezes the CPU while allowing the RAM, timers, serial port,
and interrupt system to continue functioning. The power-down mode
saves the RAM contents but freezes the oscillator, causing all other
chip functions to be inoperative.
ORDERING INFORMATION
TEMPERATURE oC RANGE
AND PACKAGE
FREQ
(MHz)
Drawing
Number
P87C528EBP N
0 to +70, Plastic Dual In-line Package
16
SOT129-1
P87C528EBA A
0 to +70, Plastic Leaded Chip Carrier
16
SOT187-2
P87C528EBB B
0 to +70, Plastic Quad Flat Pack
16
SOT307-2
P87C528EFP N
–40 to +85, Plastic Dual In-line Package
16
SOT129-1
P87C528EFB B
–40 to +85, Plastic Quad Flat Pack
16
SOT307-2
P87C524EBA A
0 to +70, Plastic Leaded Chip Carrier
16
SOT187-2
16
SOT307-2
EPROM
P87C524EBB B
0 to +70, Plastic Quad Flat Pack
NOTE:
1. For ROM & ROMless devices, see data sheet P8X524/528.
1999 Jul 23
2
853-1687 22041
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
BLOCK DIAGRAM
FREQUENCY
REFERENCE
COUNTERS
T0
XTAL2 XTAL1
RAM
PROGRAM
MEMORY
(32K x 8
EPROM)
OSCILLATOR
AND
TIMING
DATA
MEMORY
(256 x 8)
T1
T2
T2EX
RST
AUX–RAM
DATA
MEMORY
(256 x 8)
TWO 16-BIT
TIMER/EVENT
COUNTERS
16-BIT TIMER/
EVENT COUNTER
WATCHDOG
TIMER
CPU
INTERNAL
INTERRUPTS
INT0 INT1
64K-BYTE BUS
EXPANSION
CONTROL
PROGRAMMABLE
SERIAL PORT
FULL DUPLEX UART
SYNCHRONOUS SHIFT
PROGRAMMABLE I/O
CONTROL
SERIAL IN
PARALLEL PORTS,
ADDRESS/DATA BUS
AND I/O PINS
EXTERNAL
INTERRUPTS
SERIAL OUT
BIT-LEVEL
I2C
INTERFACE
SDA
SCL
SHARED WITH
PORT 3
SU00166
LOGIC SYMBOL
VDD
VSS
PORT 0
XTAL1
ADDRESS AND
DATA BUS
XTAL2
RST
EA
SCL
SDA
RxD
TxD
INT0
INT1
T0
T1
WR
RD
PORT 2
ALE
PORT 3
SECONDARY FUNCTIONS
PSEN
PORT 1
T2
T2EX
ADDRESS BUS
SU00165
1999 Jul 23
3
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
PIN CONFIGURATIONS
87C524/87C528
PLASTIC LEADED CHIP CARRIER
PIN FUNCTIONS
40 VDD
T2/P1.0 1
6
T2EX/P1.1 2
39 P0.0/AD0
P1.2 3
38 P0.1/AD1
P1.3 4
37 P0.2/AD2
P1.4 5
36 P0.3/AD3
P1.5 6
35 P0.4/AD4
SCL/P1.6 7
34 P0.5/AD5
SDA/P1.7 8
33 P0.6/AD6
RST 9
32 P0.7/AD7
1
40
7
39
LCC
17
RxD/P3.0 10
TxD/P3.1 11
DUAL
IN-LINE
PACKAGE
18
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
31 EA
30 ALE
INT0/P3.2 12
29 PSEN
INT1/P3.3 13
28 P2.7/A15
T0/P3.4 14
27 P2.6/A14
T1/P3.5 15
26 P2.5/A13
WR/P3.6 16
25 P2.4/A12
RD/P3.7 17
24 P2.3/A11
XTAL2 18
23 P2.2/A10
XTAL1 19
22 P2.1/A9
VSS 20
21 P2.0/A8
29
SU00162
Function
NC*
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
P1.5
P1.6/SCL
P1.7/SDA
RST
P3.0/RxD
NC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
* NO INTERNAL CONNECTIONS
1999 Jul 23
4
28
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
NC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
NC*
EA
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
SU00163A
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
44
34
1
33
QFP
11
23
12
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Function
P1.5
P1.6/SCL
P1.7/SDA
RST
P3.0/RxD
NC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
NC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
* NO INTERNAL CONNECTIONS
1999 Jul 23
22
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
NC*
EA
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
NC*
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
SU00164
5
87C524/87C528
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
PIN DESCRIPTIONS
PIN NO.
MNEMONIC
DIP
LCC
QFP
TYPE
VSS
VDD
20
40
22
44
16
38
I
I
39–32
43–36
37–30
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s.
1–8
2–9
40–44
1–3
I/O
1
2
7
8
2
3
8
9
40
41
2
3
I
I
I/O
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7
which have open drain. Port 1 pins that have 1s written to them are pulled high by the
internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled
low will source current because of the internal pull-ups. (See DC Electrical Characteristics:
IIL). Port 1 can sink/source one TTL (4 LSTTL) inputs. Port 1 receives the low-order
address byte during program memory verification. Port 1 also serves alternate functions for
timer 2:
T2 (P1.0): Timer/counter 2 external count input (following edge triggered).
T2EX (P1.1): Timer/counter 2 trigger input.
SCL (P1.6): I2C serial port clock line.
SDA (P1.7): I2C serial port data line.
P2.0–P2.7
21–28
24–31
18–25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order
address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.
P3.0–P3.7
10–17
11,
13–19
5,
7–13
I/O
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
13
I
O
I
I
I
I
O
O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of
the SC80C51 family, as listed below:
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
RST
9
10
4
I/O
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to VSS permits a power-on reset using only an external
capacitor to VDD. After a watchdog timer overflow, this pin is pulled high while the internal
reset signal is active.
ALE
30
33
27
I/O
Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency, and can be used for external timing or clocking. Note that one ALE
pulse is skipped during each access to external data memory.
PSEN
29
32
26
O
Program Store Enable: The read strobe to external program memory. When the device is
executing code from the external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external data
memory. PSEN is not activated during fetches from internal program memory.
EA
31
35
29
I
External Access Enable: EA must be externally held low during RESET to enable the
device to fetch code from external program memory locations 0000H to 7FFFH. If EA is
held high during RESET, the device executes from internal program memory unless the
program counter contains an address greater than 7FFFH. EA is don’t care after RESET.
XTAL1
19
21
15
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
XTAL2
18
20
14
O
Crystal 2: Output from the inverting oscillator amplifier.
P0.0–0.7
P1.0–P1.7
1999 Jul 23
NAME AND FUNCTION
Ground: circuit ground potential.
Power Supply: +5 V power supply pin during normal operation, Idle mode and
Power-down mode.
6
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
Table 1.
SYMBOL
87C524/87C528
8XC524/8XC528 Special Function Registers
DESCRIPTION
DIRECT
ADDRESS
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB
LSB
RESET
VALUE
ACC*
Accumulator
E0H
E7
E6
E5
E4
E3
E2
E1
E0
00H
B*
B register
F0H
F7
F6
F5
F4
F3
F2
F1
F0
00H
DPTR:
DPH
DPL
Data pointer (2 bytes):
Data pointer high
Data pointer low
83H
82H
IE*#
Interrupt enable
A8H
00H
00H
AF
AE
AD
AC
AB
AA
A9
A8
EA
ES1
ET2
ES0
ET1
EX1
ET0
EX0
BF
BE
BD
BC
BB
BA
B9
B8
PS1
PT2
PS0
PT1
PX1
PT0
PX0
IP*#
Interrupt priority
B8H
–
87
86
85
84
83
82
81
80
P0*
Port 0
80H
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
97
96
95
94
93
92
91
90
P1*
Port 1
90H
SDA
SEL
–
–
–
–
T2EX
T2
A7
A6
A5
A4
A3
A2
A1
A0
A14
A13
A12
A11
A10
A9
A8
00H
x0000000B
FFH
FFH
P2*
Port 2
A0H
A15
B7
B6
B5
B4
B3
B2
B1
B0
P3*
Port 3
B0H
RD
WR
T1
T0
INT1
INT0
TxD
RxD
FFH
PCON
Power control
87H
SMOD
–
–
–
GF1
GF0
PD
IDL
0xxx0000B
D7
D6
D5
D4
D3
D2
D1
D0
PSW*
Program status word
D0H
CY
AC
F0
RS1
RS0
OV
F1
P
RCAP2H#
RCAP2L#
SBUF
Capture high
Capture low
Serial data buffer
CBH
CAH
99H
SCON*
Serial controller
98H
S1BIT#
I2C
D9H/RD
SDI
0
0
0
0
0
WR
SD0
X
X
X
X
X
DAH
INT
X
X
X
X
X
DF
DE
DD
DC
DB
S1INT#
S1SCS*#
SP
TCON*
Serial
data
Serial I2C interrupt
Serial I2C control
Stack pointer
Timer control
00H
00H
00H
xxxxxxxxB
9F
9E
9D
9C
9B
9A
99
98
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
00H
0
0
x0000000B
X
X
0xxxxxxxB
X
X
0xxxxxxxB
DA
D9
D8
D8H/RD
SDI
SCI
CLH
BB
RBF
WBF
STR
ENS
xxxx0000B
WR
SD0
SC0
CLH
X
X
X
STR
ENS
00xxxx00B
8F
8E
8D
8C
8B
8A
89
88
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
CF
CE
CD
CC
CB
CA
C9
C8
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
81H
88H
T2CON*#
Timer 2 control
C8H
TH0
TH1
TH2#
TL0
TL1
TL2#
T3#
Timer high 0
Timer high 1
Timer high 2
Timer low 0
Timer low 1
Timer low 2
Watchdog timer
8CH
8DH
CDH
8AH
8BH
CCH
FFH
TMOD
Timer mode
89H
WDCON#
Watchdog control
A5H
07H
00H
00H
00H
00H
00H
00H
00H
00H
00H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
A5H
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
1999 Jul 23
FFH
7
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
Table 2. Internal and External Program Memory Access with Security Bit Set
ACCESS TO INTERNAL
PROGRAM MEMORY
ACCESS TO EXTERNAL
PROGRAM MEMORY
MOVC in internal program memory
YES
YES
MOVC in external program memory
NO
YES
INSTRUCTION
the watchdog timer, the user program has to reload the watchdog
timer within periods that are shorter than the programmed watchdog
timer internal. This time interval is determined by an 8-bit value that
has to be loaded in register T3 while at the same time the prescaler
is cleared by hardware.
INTERNAL DATA MEMORY
The internal data memory is divided into three physically separated
segments: 256 bytes of RAM, 256 bytes of AUX-RAM, and a
128 bytes special function area. These can be addressed each in a
different way.
– RAM 0 to 127 can be addressed directly and indirectly as in the
80C51. Address pointers are R0 and R1 of the selected register
bank.
– RAM 128 to 255 can only be addressed indirectly as in the 80C51.
Address pointers are R0 and R1 of the selected register bank.
– AUX-RAM 0 to 255 is indirectly addressed in the same way as
external data memory with the MOVX instructions. Address
pointers are R0, R1 of the selected register bank and DPTR. An
access to AUX-RAM 0 to 255 will not affect ports P0, P2, P3.6
and P3.7.
Watchdog timer interval =
BIT-LEVEL I2C INTERFACE
This bit-level serial I/O interface supports the I2C-bus. P1.6/SCL and
P1.7/SDA are the serial I/O pins. These two pins meet the I2C
specification concerning the input levels and output drive capability.
Consequently, these pins have an open drain output configuration.
All the four modes of the I2C-bus are supported:
– master transmitter
– master receiver
– slave transmitter
– slave receiver
An access to external data memory locations higher than 255 will be
performed with the MOVX DPTR instructions in the same way as in
the 8051 structure, so with P0 and P2 as data/address bus and P3.6
and P3.7 as write and read timing signals. Note that these external
data memory cannot be accessed with R0 and R1 as address
pointer.
The advantages of the bit-level I2C hardware compared with a full
software I2C implementation are:
– the hardware can generate the SCL pulse
– Testing a single bit (RBF respectively, WBF) is sufficient as a
check for error free transmission.
TIMER 2
Timer 2 is functionally equal to the Timer 2 of the 8052AH. Timer 2 is
a 16-bit timer/counter. These 16 bits are formed by two special
function registers TL2 and TH2. Another pair of special function
register RCAP2L and RCAP2H form a 16-bit capture register or a
16-bit reload register. Like Timer 0 and 1, it can operate either as a
timer or as an event counter. This is selected by bit C/T2N in the
special function register T2CON. It has three operating modes:
capture, autoload, and baud rate generator mode which are selected
by bits in T2CON.
The bit-level I2C hardware operates on serial bit level and performs
the following functions:
– filtering the incoming serial data and clock signals
– recognizing the START condition
– generating a serial interrupt request SI after reception of a START
condition and the first falling edge of the serial clock
– recognizing the STOP condition
– recognizing a serial clock pulse on the SCL line
– latching a serial bit on the SDA line (SDI)
– stretching the SCL LOW period of the serial clock to suspend the
transfer of the next serial data bit
– setting Read Bit Finished (RBF) when the SCL clock pulse has
finished and Write Bit Finished (WBF) if there is no arbitration loss
detected (i.e., SDA = 0 while SDO = 1)
– setting a serial clock Low-to-High detected (CLH) flag
– setting a Bus Busy (BB) flag on a START condition and clearing
this flag on a STOP condition
– releasing the SCL line and clearing the CLH, RBF and WBF flags
to resume transfer of the next serial data bit
– generating an automatic clock if the single bit data register S1BIT
is used in master mode.
WATCHDOG TIMER T3
The watchdog timer consists of an 11-bit prescaler and an 8-bit timer
formed by special function register T3. The prescaler is incremented
by an on-chip oscillator with a fixed frequency of 1MHz. The
maximum tolerance on this frequency is –50% and +100%. The 8-bit
timer increments every 2048 cycles of the on-chip oscillator. When a
timer overflow occurs, the microcontroller is reset and a reset output
pulse of 16 × 2048 cycles of the on-chip oscillator is generated at pin
RST. The internal RESET signal is not inhibited when the external
RST pin is kept low by, for example, an external reset circuit. The
RESET signal drives port 1, 2, 3 into the high state and port 0 into
the high impedance state.
The watchdog timer is controlled by one special function register
WDCON with the direct address location A5H. WDCON can be read
and written by software. A value of A5H in WDCON halts the
on-chip oscillator and clears both the prescaler and timer T3. After
the RESET signal, WDCON contains A5H. Every value other than
A5H in WDCON enables the watchdog timer. When the watchdog
timer is enabled, it runs independently of the XTAL-clock.
The following functions must be done in software:
– handling the I2C START interrupts
– converting serial to parallel data when receiving
– converting parallel to serial data when transmitting
– comparing the received slave address with its own
– interpreting the acknowledge information
– guarding the I2C status if RBF or WBF = 0.
Timer T3 can be read on the fly. Timer T3 can only be written if
WDCON contains the value 5AH. A successful write operation to T3
will clear the prescaler and WDCON, leaving the watchdog enabled
and preventing inadvertent changes of T3. To prevent an overflow of
1999 Jul 23
[256 * (T3)] 2048
on * chip oscillator frequency
8
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
Additionally, if acting as master:
– generating START and STOP conditions
– handling bus arbitration
– generating serial clock pulses if S1BIT is not used.
87C524/87C528
IE: Interrupt Enable Register
This register is located at address A8H. Refer to Table 3.
IE SFR (A8H)
Three SFRs control the bit-level I2C interface: S1INT, S1BIT and
S1SCS.
7
6
5
4
3
2
1
0
EA
ES1
ET2
ES
ET1
EX1
ET0
EX0
IP: Interrupt Priority Register
This register is located at address B8H. Refer to Table 4.
INTERRUPT SYSTEM
The interrupt structure of the 8XC528 is the same as that used in the
80C51, but includes two additional interrupt sources: one for the
third timer/counter, T2, and one for the I2C interface. The interrupt
enable and interrupt priority registers are IE and IP.
IP SFR (B8H)
7
6
5
4
3
2
1
0
–
PS1
PT2
PS
PT1
PX1
PT0
PX0
Table 3. Description of IE Bits
MNEMONIC
BIT
FUNCTION
EA
IE.7
General enable/disable control:
0 = NO interrupt is enabled.
1 = ANY individually enabled interrupt will be accepted.
ES1
IE.6
Enable bit-level I2C I/O interrupt
ET2
IE.5
Enable Timer 2 interrupt
ES
IE.4
Enable Serial Port interrupt
ET1
IE.3
Enable Timer 1 interrupt
EX1
IE.2
Enable External interrupt 1
ET0
IE.1
Enable Timer 0 interrupt
EX0
IE.0
Enable External interrupt 0
Table 4. Description of IP Bits
MNEMONIC
BIT
FUNCTION
–
IP.7
Reserved.
PS1
IP.6
Bit-level I2C interrupt priority level
PT2
IP.5
Timer 2 interrupt priority level
PS
IP.4
Serial Port interrupt priority level
PT1
IP.3
Timer 1 interrupt priority level
PX1
IP.2
External Interrupt 1 priority level
PT0
IP.1
Timer 0 interrupt priority level
PX0
IP.0
External Interrupt 0 priority level
The interrupt vector locations and the interrupt priorities are:
Source
Vector
0003H
002BH
0053H
000BH
0013H
001BH
0023H
Priority within Level
Address
IE0
TF2+EXF2
SI (I2C)
TF0
IE1
TF1
RI+TI
1999 Jul 23
Highest
Lowest
9
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
OSCILLATOR CHARACTERISTICS
POWER-DOWN MODE
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol.
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
The power-down mode can be terminated by a RESET in the same
way as in the 80C51 or in addition by one of two external interrupts,
INT0 or INT1. A termination with an external interrupt does not affect
the internal data memory and does not affect the special function
registers. This makes it possible to exit power-down without
changing the port output levels. To terminate the power-down mode
with an external interrupt INT0 or INT1 must be switched to
level-sensitive and must be enabled. The external interrupt input
signal INT0 and INT1 must be kept low until the oscillator has
restarted and stabilized. An instruction following the instruction that
puts the device in the power-down mode will be executed. A reset
generated by the watchdog timer terminates the power-down mode
in the same way as an external RESET, and only the contents of the
on-chip RAM are preserved. The control bits for the reduced power
modes are in the special function register PCON.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-up reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-up, the voltage on
VDD and RST must come up at the same time for a proper start-up.
DESIGN CONSIDERATIONS
IDLE MODE
At power-on, the voltage on VDD and RST must come up at the
same time for a proper start-up.
In idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal reset algorithm takes control.
On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of
an unexpected write when idle is terminated by reset, the instruction
following the one that invokes idle should not be one that writes to a
port pin or to external memory.
Table 5 shows the state of I/O ports during low current operating
modes.
Table 5. External Pin Status During Idle and Power-Down Modes
PROGRAM MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
Idle
MODE
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power-down
Internal
0
0
Data
Data
Data
Data
Power-down
External
0
0
Float
Data
Data
Data
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER
Operating temperature under bias
RATING
UNIT
0 to +70, or
–40 to +85
°C
–65 to +150
°C
–0.5 to VDD +0.5
V
Input, output current on any two pins
±10
mA
Power dissipation
(based on package heat transfer limitations, not device power consumption)
1.0
W
Storage temperature range
Voltage on any other pin to VSS
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
1999 Jul 23
10
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C (VDD = 5 V ±10%), –40°C to +85°C (VDD = 5 V ±10%), VSS=0 V
TEST
SYMBOL
PARAMETER
PART TYPE
CONDITIONS
LIMITS
MIN
MAX
UNIT
VIL
Input low voltage,
except EA, P1.6/SCL, P1.7/SDA
0°C to 70°C
–40°C to +85°C
–0.5
–0.5
0.2VCC–0.1
0.2VCC–0.15
V
V
VIL1
Input low voltage to EA
0°C to 70°C
–40°C to +85°C
0
0
0.2VCC–0.3
0.2VCC–0.35
V
V
VIL2
Input low voltage to P1.6/SCL, P1.7/SDA5
–0.5
0.3 V
V
VIH
Input high voltage,
except XTAL1, RST, P1.6/SCL, P1.7/SDA
0°C to 70°C
–40°C to +85°C
0.2VCC+0.9
0.2VCC+1.0
VCC+0.5
VCC+0.5
V
V
VIH1
Input high voltage, XTAL1, RST
0°C to 70°C
–40°C to +85°C
0.7VCC
0.7VCC+0.1
VCC+0.5
VCC+0.5
V
V
VIH2
Input high voltage, P1.6/SCL, P1.7/SDA5
3.0
6.0
V
mA1
0.45
V
0.45
V
0.4
V
VOL
Output low voltage, ports 1, 2, 3, except
P1.6/SCL, P1.7/SDA1
IOL = 1.6
VOL1
Output low voltage, port 0, ALE, PSEN1
IOL = 3.2 mA1
mA1
VOL2
Output low voltage, P1.6/SCL, P1.7/SDA
IOL = 3.0
VOH
Output high voltage, ports 1, 2, 3
IOH = –60 µA
IOH = –25 µA
2.4
0.75VCC
V
V
VOH1
Output high voltage, Port 0 in external bus mode,
ALE, PSEN, RST
IOH = –800 µA
IOH = –300 µA
2.4
0.75VCC
V
V
IIL
Logical 0 input current, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA
0°C to 70°C
–40°C to +85°C
VIN = 0.45 V
–50
–75
µA
µA
ITL
Logical 1-to-0 transition current, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA
0°C to 70°C
–40°C to +85°C
See Note 3
–650
–750
µA
µA
IIL1
Input leakage current, port 0
VIN = VIL or VIH
±10
µA
IIL2
Input leakage current, P1.6/SCL, P1.7/SDA
0 V<Vi<6.0 V
0 V<VCC<6.0 V
±10
µA
µA
ICC
Power supply current:
25
35
5
6
50
mA
300
kΩ
10
pF
Active mode @ 16 MHz
Idle mode @ 16 MHz
See Note 4
0oC to 70oC
–40oC to +85oC
0oC to 70oC
–40oC to +85oC
Power down mode
RRST
Internal reset pull-down resistor
CIO
Pin Capacitance
50
mA
µA
NOTES:
1. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and ports 1 and 3. The
noise is due to external bus capacitance discharging into the port and port 2 pins when these pins make 1-to-0 transactions during bus
operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be
desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. Under steady state
(non-transient) conditions, IOL must be externally limited as follows: 10 mA per port pin, port 0 total (all bits) 26 mA, ports 1, 2, and total each
(all bits) 15 mA.
2. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the
address bits are stabilizing.
3. Pins of ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2 V.
4. See Figures 10 through 13 for ICC test conditions.
5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 1.5 V will be recognized as a
logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.
1999 Jul 23
11
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
AC ELECTRICAL CHARACTERISTICS1, 2
SYMBOL
FIGURE
PARAMETER
16MHz CLOCK
VARIABLE CLOCK
MIN
MIN
MAX
UNIT
3.5
16
MHz
MAX
1/tCLCL
1
Oscillator frequency:
87C528
Speed Versions
P878C528EXX
tLHLL
1
ALE pulse width
tAVLL
1
tLLAX
1
tLLIV
1
ALE low to valid instruction in
tLLPL
1
ALE low to PSEN low
23
tPLPH
1
PSEN pulse width
143
tPLIV
1
PSEN low to valid instruction in
tPXIX
1
Input instruction hold after PSEN
tPXIZ
1
Input instruction float after PSEN
38
tCLCL–25
ns
tAVIV
1
Address to valid instruction in
208
5tCLCL–105
ns
tPLAZ
1
PSEN low to address float
10
10
ns
85
2tCLCL–40
ns
Address valid to ALE low
8
tCLCL–55
ns
Address hold after ALE low
28
tCLCL–35
ns
150
4tCLCL–100
tCLCL–40
ns
3tCLCL–45
83
ns
3tCLCL–105
0
ns
0
ns
ns
Data Memory
tRLRH
2, 3
RD pulse width
275
6tCLCL–100
ns
tWLWH
2, 3
WR pulse width
275
tRLDV
2, 3
RD low to valid data in
tRHDX
2, 3
Data hold after RD
tRHDZ
2, 3
Data float after RD
55
2tCLCL–70
ns
tLLDZ
2, 3
ALE low to valid data in
350
8tCLCL–150
ns
tAVDV
2, 3
Address to valid data in
398
9tCLCL–165
ns
tLLWL
2, 3
ALE low to RD or WR low
138
3tCLCL+50
ns
tAVWL
2, 3
Address valid to WR low or RD low
120
4tCLCL–130
ns
tQVWX
2, 3
Data valid to WR transition
3
tCLCL–60
ns
tWHQX
2, 3
Data hold after WR
13
tRLAZ
2, 3
RD low to address float
tWHLH
2, 3
RD or WR high to ALE high
23
6tCLCL–100
148
ns
5tCLCL–165
0
0
238
3tCLCL–50
ns
tCLCL–50
0
103
tCLCL–40
ns
ns
0
ns
tCLCL+40
ns
External Clock
tCHCX
6
High time
20
20
ns
tCLCX
6
Low time
20
20
ns
tCLCH
6
Rise time
20
20
ns
tCHCL
6
Fall time
20
20
ns
tXLXL
4
Serial port clock cycle time
750
12tCLCL
ns
tQVXH
4
Output data setup to clock rising edge
492
10tCLCL–133
ns
tXHQX
4
Output data hold after clock rising edge
8
2tCLCL–117
ns
tXHDX
4
Input data hold after clock rising edge
0
tXHDV
4
Clock rising edge to input data valid
Shift Register
0
492
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
1999 Jul 23
12
ns
10tCLCL–133
ns
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
AC ELECTRICAL CHARACTERISTICS – I2C INTERFACE
SYMBOL
PARAMETER
INPUT
OUTPUT
I2C SPECIFICATION
≥ 4.0µs
SCL TIMING CHARACTERISTICS
tHD;STA
START condition hold time
≥ 14 tCLCL1
Note 2
tLOW
SCL LOW time
≥ 16 tCLCL
Note 2
SCL HIGH time
≥ 14 tCLCL
≥ 80 tCLCL
tHIGH
tRC
tFC
SCL rise time
SCL fall time
≤
≤
1
1µs1
Note 5
≤
0.3µs1
0.3µs6
≥ 4.7µs
3
≥ 4.0µs
≤ 1.0µs
≤ 0.3µs
SDA TIMING CHARACTERISTICS
tSU;DAT1
Data set-up time
tHD;DAT
Data hold time
≥ 250ns
Note 2
≥ 250ns
≥ 0ns
Note 2
≥ 0ns
1
tSU;STA
Repeated START set-up time
≥ 14 tCLCL
Note 2
≥ 4.7µs
tSU;STO
STOP condition set-up time
≥ 14 tCLCL1
Note 2
≥ 4.0µs
tBUF
Bus free time
≥ 14 tCLCL
Note 2
≥ 4.7µs
tRD
SDA rise time
≤ 1µs4
Note 5
≤ 1.0µs
1
tFD
SDA fall time
≤ 0.3µs4
≤ 0.3µs 6
≤ 0.3µs
NOTES:
1. At fCLK = 3.5MHz, this evaluates to 14 × 286ns = 4µs, i.e., the bit-level I2C interface can respond to the I2C protocol for fCLK ≥ 3.5 MHz.
2. This parameter is determined by the user software, it has to comply with the I2C.
3. This value gives the autoclock pulse length which meets the I2C specification for the specified XTAL clock frequency range. Alternatively, the
SCL pulse may be timed by software.
4. Spikes on SDA and SCL lines with a duration of less than 4 × fCLK will be filtered out.
5. The rise time is determined by the external bus line capacitance and pull-up resistor, it must be ≤ 1µs.
6. The maximum capacitance on bus lines SDA and SCL is 400pF.
1999 Jul 23
13
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
EXPLANATION OF THE AC SYMBOLS
P – PSEN
Q – Output data
R – RD signal
t – Time
V – Valid
W – WR signal
X – No longer a valid logic level
Z – Float
Examples: tAVLL = Time for address valid to ALE low.
tLLPL = Time for ALE low to PSEN low.
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
tLHLL
ALE
tAVLL
tLLPL
tPLPH
tLLIV
tPLIV
PSEN
tLLAX
A0–A7
PORT 0
tPXIZ
tPLAZ
tPXIX
A0–A7
INSTR IN
tAVIV
PORT 2
A0–A15
A8–A15
SU00006
Figure 1. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV
tLLWL
tRLRH
RD
tAVLL
tLLAX
tRLAZ
PORT 0
tRHDZ
tRLDV
tRHDX
A0–A7
FROM RI OR DPL
DATA IN
A0–A7 FROM PCL
INSTR IN
tAVWL
tAVDV
PORT 2
P2.0–P2.7 OR A8–A15 FROM DPH
A0–A15 FROM PCH
SU00007
Figure 2. External Data Memory Read Cycle
1999 Jul 23
14
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
ALE
tWHLH
PSEN
tWLWH
tLLWL
WR
tLLAX
tAVLL
A0–A7
FROM RI OR DPL
PORT 0
tWHQX
tQVWX
DATA OUT
A0–A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00069
Figure 3. External Data Memory Write Cycle
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
tXLXL
CLOCK
tXHQX
tQVXH
OUTPUT DATA
0
1
WRITE TO SBUF
2
3
4
5
6
7
tXHDX
tXHDV
SET TI
INPUT DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CLEAR RI
SET RI
SU00027
Figure 4. Shift Register Mode Timing
1999 Jul 23
15
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
repeated START condition
START or repeated START condition
START condition
tSU;STA
STOP condition
tRD
0.7 VCC
SDA
(INPUT/OUTPUT)
0.3 VCC
tBUF
tFD
tRC
tFC
tSU;STO
0.7 VCC
SCL
(INPUT/OUTPUT)
0.3 VCC
tSU;DAT3
tHD;STA
tLOW
tHIGH
tSU;DAT1
tHD;DAT
tSU;DAT2
SU00107A
Figure 5. Timing SIO1 (I2C) Interface
VCC–0.5
0.7VCC
0.2VCC–0.1
0.45V
tCHCL
tCHCX
tCLCH
tCLCX
tCLCL
SU00009
Figure 6. External Clock Drive
VDD–0.5
0.45V
VLOAD+0.1V
0.2VDD+0.9
TIMING
REFERENCE
POINTS
VLOAD
0.2VDD–0.1
VLOAD–0.1V
SU00011
SU00167
Figure 7. AC Testing Input/Output
Figure 8. Float Waveform
30
MAX ACTIVE MODE
25
20
TYP ACTIVE MODE
15
10
MAX IDLE MODE
5
TYP IDLE MODE
4 MHz
8 MHz 12 MHz
FREQ AT XTAL1
16 MHz
SU00168
Figure 9. ICC vs. FREQ.
Valid only within frequency specifications of the device under test
1999 Jul 23
VOL+0.1V
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from load
voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL
level occurs. IOH/IOL ≥ ±20mA.
NOTE:
AC inputs during testing are driven at VDD –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.
ICC mA
VOH–0.1V
16
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
VDD
VDD
IDD
IDD
VDD
VDD
VDD
RST
VDD
RST
VDD
EA
P0
P0
EA
(NC)
XTAL2
CLOCK SIGNAL
XTAL1
P1.6
(NC)
XTAL2
P1.6
*
CLOCK SIGNAL
XTAL1
P1.7
*
*
P1.7
*
VSS
VSS
SU00169
SU00170
Figure 10. IDD Test Condition, Active Mode
All other pins are disconnected
VCC–0.5
Figure 11. IDD Test Condition, Idle Mode
All other pins are disconnected
0.7VCC
0.2VCC–0.1
0.45V
tCHCL
tCHCX
tCLCH
tCLCX
tCLCL
SU00009
Figure 12. Clock Signal Waveform for
IDD Tests in Active and Idle Modes
tCLCH = tCHCL = 5ns
VDD
IDD
VDD
RST
VDD
EA
(NC)
P0
XTAL2
P1.6
*
XTAL1
P1.7
*
VSS
SU00171
Figure 13. IDD Test Condition, Power Down Mode
All other pins are disconnected. VDD = 2V to 5.5V
NOTE:
* Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins does not
exceed the IOL1 specifications.
1999 Jul 23
17
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
Note that the EA/VPP pin must not be allowed to 90 above the
maximum specified VPP level for any amount of time. Even a narrow
glitch above that voltage can cause permanent damage to the
device. The VPP source should be well regulated and free of glitches
and overshoot.
EPROM CHARACTERISTICS FOR 87C528
The 87C528 is programmed by using a modified Quick-Pulse
Programming algorithm. It differs from older methods in the value
used for VPP (programming supply voltage) and in the width and
number of the ALE/PROG pulses.
The 87C528 contains two signature bytes that can be read and used
by an EPROM programming system to identify the device. The
signature bytes identify the device as an 87C528 manufactured by
Philips.
Program Verification
If lock bit 2 has not been programmed, the on-chip program memory
can be read out for program verification. The address of the program
memory locations to be read is applied to ports 1, 2 and 3 as shown
in Figure 16. The other pins are held at the ‘Verify Code Data’ levels
indicated in Table 6. The contents of the address location will be
emitted on port 0. External pull ups are required on port 0 for this
operation.
Table 6 shows the logic levels for reading the signature byte, and for
programming the program memory, the encryption table, and the
lock bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figures 14 and 15. Figure 16 shows the
circuit configuration for normal program memory verification.
If the encryption table has been programmed, the data presented at
port 0 will be the exclusive NOR of the program byte with one of the
encryption bytes. The user will have to know the encryption table
contents in order to correctly decode the verification data. The
encryption table itself cannot be read out.
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in
Figure 14. Note that the 87C528 is running with a 4 to 6MHz
oscillator The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
Reading the Signature Bytes
The signature bytes are read by the same procedure as a normal
verification of locations 030H and 031 H, except that P3.6 and P3.7
need to be pulled to a logic low. The values are:
The address of the EPROM location to be programmed is applied to
ports 1, 2 and 3, as shown in Figure 14. The code byte to be
programmed into that location is applied to port 0. RST, PSEN and
pins of ports 2 and 3 specified in Table 6 are held at the ’Program
Code Data’ levels indicated in Table 6. The ALE/PROG is pulsed
low 25 times as shown in Figure 15.
(030H) = 15H indicates manufactured by Philips
(031H) = 9BH indicates 87C528
Program Lock Bits
To program the encryption table, repeat the 25 pulse programming
sequence for addresses 0 through 3FH, using the ‘Pgm Encryption
Table’ levels. Do not forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.
The 87C528 has 3 programmable lock bits that will provide different
levels of protection for the on-chip code and data (see Table 7).
Erasing the EPROM also erases the encryption array and the
program lock bits, returning the part to full functionality.
To program the lock bits, repeat the 25 pulse programming
sequence using the ‘Pgm Lock Bit’ levels. After one lock bit is
programmed, further programming of the code memory and
encryption table is disabled. However, the other lock bit can still be
programmed.
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 6, and
which satisfies the timing specifications, is suitable.
Table 6. EPROM Programming Modes
RST
PSEN
ALE/PROG
EA/VPP
P2.7
P2.6
P3.7
P3.6
Read signature
MODE
1
0
1
1
0
0
0
0
Program code data
1
0
0*
VPP
1
0
1
1
Verify code data
1
0
1
1
0
0
1
1
Pgm encryption table
1
0
0*
VPP
1
0
1
0
Pgm lock bit 1
1
0
0*
VPP
1
1
1
1
Pgm lock bit 2
1
0
0*
VPP
1
1
0
0
Pgm lock bit 3
1
0
0*
VPP
0
1
0
1
NOTES:
1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. VPP = 12.75 V ±0.25 V.
3. Vcc = 5 V ±10% during programming and verification.
* ALE/PROG receives 25 programming pulses while VPP is held at 12.75 V. Each programming pulse is low for 100 µs (±10 µs) and high for a
minimum of 10 µs.
1999 Jul 23
18
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
in Figure 16. The other pins are held at the ‘Verify Code Data’ levels
indicated in Table 6. The contents of the address location will be
emitted on port 0. External pull-ups are required on port 0 for this
operation.
EPROM CHARACTERISTICS FOR 87C524
The 87C524 is programmed by using a modified Quick-Pulse
Programming algorithm. It differs from older methods in the value
used for VPP (programming supply voltage) and in the width and
number of the ALE/PROG pulses.
If the encryption table has been programmed, the data presented at
port 0 will be the exclusive NOR of the program byte with one of the
encryption bytes. The user will have to know the encryption table
contents in order to correctly decode the verification data. The
encryption table itself cannot be read out.
The 87C524 contains two signature bytes that can be read and used
by an EPROM programming system to identify the device. The
signature bytes identify the device as an 87C524 manufactured by
Philips.
Program Lock Bits
The 87C524 has 3 programmable lock bits that will provide different
levels of protection for the on-chip code and data (see Table 7).
Table 6 shows the logic levels for reading the signature byte, and for
programming the program memory, the encryption table, and the
lock bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figures 14 and 15. Figure 16 shows the
circuit configuration for normal program memory verification.
Erasing the EPROM also erases the encryption array and the
program lock bits, returning the part to full functionality.
Quick-Pulse Programming
Reading the Signature Bytes
The signature bytes are read by the same procedure as a normal
verification of locations 030H and 031H, except that P3.6 and P3.7
need to be pulled to a logic low. The values are:
The setup for microcontroller quick-pulse programming is shown in
Figure 14. Note that the 87C524 is running with a 4 to 6 MHz
oscillator. The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
(030H) = 15H indicates manufactured by
Philips
(031H) = 9DH indicates 87C524
The address of the EPROM location to be programmed is applied to
ports 1, 2 and 3, as shown in Figure 14. The code byte to be
programmed into that location is applied to port 0. RST, PSEN and
pins of ports 2 and 3 specified in Table 6 are held at the ‘Program
Code Data’ levels indicated in Table 6. The ALE/PROG is pulsed
low 25 times as shown in Figure 15.
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 6, and
which satisfies the timing specifications, is suitable.
To program the encryption table, repeat the 25 pulse programming
sequence for addresses 0 through 3FH, using the ‘Pgm Encryption
Table’ levels. Do not forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.
Erasure Characteristics
Erasure of the EPROM begins to occur when the chip is exposed to
light with wavelengths shorter than approximately 4,000 angstroms.
Since sunlight and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about
1 week in sunlight, or 3 years in room level fluorescent lighting)
could cause inadvertent erasure. For this and secondary effects,
it is recommended that an opaque label be placed over the
window. For elevated temperature or environments where solvents
are being used, apply Kapton tape Fluorglas part number 2345–5, or
equivalent.
To program the lock bits, repeat the 25 pulse programming
sequence using the ‘Pgm Lock Bit’ levels. After one lock bit is
programmed, further programming of the code memory and
encryption table is disabled. However, the other lock bit can still be
programmed.
Note that the EA/VPP pin must not be allowed to go above the
maximum specified VPP level for any amount of time. Even a narrow
glitch above that voltage can cause permanent damage to the
device. The VPP source should be well regulated and free of glitches
and overshoot.
The recommended erasure procedure is exposure to ultraviolet light
(at 2537 angstroms) to an integrated dose of at least 15W-sec/cm2.
Exposing the EPROM to an ultraviolet lamp of 12,000uW/cm2 rating
for 20 to 39 minutes, at a distance of about 1 inch, should be
sufficient.
Program Verification
If lock bit 2 has not been programmed, the on-chip program memory
can be read out for program verification. The address of the program
memory locations to be read is applied to ports 1, 2 and 3 as shown
Erasure leaves the array in an all 1s state.
Trademark phrase of Intel Corporation.
1999 Jul 23
87C524/87C528
19
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
Table 7. Program Lock Bits
PROGRAM LOCK BITS1,2
LB1
LB2
LB3
PROTECTION DESCRIPTION
1
U
U
U
No Program Lock features enabled. (Code verify will still be encrypted by the Encryption Array if programmed.)
2
P
U
U
MOVC instructions executed from external program memory are disabled from fetching code bytes from
Internal memory, EA is jumped and latched on Reset, and further programming of the EPROM Is disabled.
3
P
P
U
Same as 2, also verify is disabled.
4
P
P
P
Same as 3, external execution is disabled. Internal data RAM is not accessible.
NOTES:
1. P - programmed. U - unprogrammed.
2. Any other combination of the lock bits is not defined.
+5 V
VCC
A0–A7
P0
P1
1
RST
EA/VPP
1
P3.6
ALE/PROG
1
P3.7
87C524/8
XTAL2
4–6 MHz
XTAL1
PGM DATA
+12.75 V
25 100 µs PULSES TO GROUND
PSEN
0
P2.7
1
P2.6
0
A8–A13
P2.0–P2.5
VSS
A14
P3.4
SU00172
Figure 14. Programming Configuration
25 PULSES
1
ALE/PROG:
0
10µs MIN
1
ALE/PROG:
100µs+10
0
SU00018
Figure 15. PROG Waveform
+5 V
VCC
A0–A7
P0
P1
PGM DATA
1
RST
EA/VPP
1
1
P3.6
ALE/PROG
1
1
P3.7
87C524/8
XTAL2
4–6 MHz
XTAL1
PSEN
0 ENABLE
P2.6
0
P2.0–P2.5
VSS
0
P2.7
P3.4
A8–A13
A14
SU00173
Figure 16. Program Verification
1999 Jul 23
20
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
Tamb = 21°C to +27°C, Vcc = 5 V±10%, VSS = 0 V (See Figure 17)
SYMBOL
PARAMETER
VPP
Programming supply voltage
IPP
Programming supply current
1/tCLCL
MIN
MAX
12.5
13.0
V
50
mA
6
MHz
Oscillator frequency
4
tAVGL
Address setup to PROG low
48tCLCL
tGHAX
Address hold after PROG
48tCLCL
tDVGL
Data setup to PROG low
48tCLCL
tGHDX
Data hold after PROG
48tCLCL
tEHSH
P2.7 (ENABLE) high to VPP
48tCLCL
tSHGL
VPP setup to PROG low
10
tGHSL
VPP hold after PROG
10
tGLGH
PROG width
90
tAVQV
Address to data valid
tELQZ
ENABLE low to data valid
tEHQZ
Data float after ENABLE
0
tGHGL
PROG high to PROG low
10
UNIT
µs
µs
µs
110
48tCLCL
48tCLCL
PROGRAMMING*
VERIFICATION*
ADDRESS
ADDRESS
P1.0–P1.7
P2.0–P2.5
48tCLCL
µs
tAVQV
DATA IN
PORT 0
DATA OUT
tDVGL
tAVGL
tGHDX
tGHAX
ALE/PROG
tGHGL
tGLGH
tSHGL
tGHSL
LOGIC 1
LOGIC 1
EA/VPP
LOGIC 0
tEHSH
tELQV
tEHQZ
P2.7
ENABLE
SU00174
NOTE:
*
FOR PROGRAMMING VERIFICATION SEE FIGURE 14.
FOR VERIFICATION CONDITIONS SEE FIGURE 16.
Figure 17. EPROM Programing and Verification
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
1999 Jul 23
21
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
DIP40: plastic dual in-line package; 40 leads (600 mil)
1999 Jul 23
22
87C524/87C528
SOT129-1
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
PLCC44: plastic leaded chip carrier; 44 leads
1999 Jul 23
87C524/87C528
SOT187-2
23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
1999 Jul 23
24
SOT307-2
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
NOTES
1999 Jul 23
25
87C524/87C528
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 07-99
Document order number:
1999 Jul 23
26
9397 750 06229