74LVT125; 74LVTH125 3.3 V quad buffer; 3-state Rev. 06 — 6 March 2006 Product data sheet 1. General description The 74LVT125; 74LVTH125 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device combines low static and dynamic power dissipation with high speed and high output drive. The 74LVT125; 74LVTH125 device is a quad buffer that is ideal for driving bus lines. The device features four output enable inputs (1OE, 2OE, 3OE and 4OE), each controlling one of the 3-state outputs. 2. Features n n n n n n n n n n Quad bus interface 3-state buffers Output capability: +64 mA and −32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted No bus current loading when output is tied to 5 V bus Power-up 3-state Latch-up protection: u JESD78: exceeds 500 mA n ESD protection: u MIL STD 883 method 3015: exceeds 2000 V u Machine model: exceeds 200 V 3. Quick reference data Table 1. Quick reference data GND = 0 V; Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit tPLH LOW-to-HIGH propagation delay nA to nY CL = 50 pF; VCC = 3.3 V - 2.7 - ns tPHL HIGH-to-LOW propagation CL = 50 pF; VCC = 3.3 V delay nA to nY - 2.9 - ns 74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state Table 1. Quick reference data …continued GND = 0 V; Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit Ci input capacitance VI = 0 V or 3.0 V - 4 - pF Co output capacitance outputs disabled; VO = 0 V or 3.0 V - 8 - pF ICC quiescent supply current outputs disabled; VCC = 3.6 V - 0.13 - mA 4. Ordering information Table 2. Ordering information Type number Package Temperature range Name Description Version 74LVT125D −40 °C to +85 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LVT125DB −40 °C to +85 °C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74LVT125PW −40 °C to +85 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74LVT125BQ −40 °C to +85 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm 74LVTH125D −40 °C to +85 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LVTH125DB −40 °C to +85 °C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74LVTH125PW −40 °C to +85 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74LVTH125BQ −40 °C to +85 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm 74LVT_LVTH125_6 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 06 — 6 March 2006 2 of 16 74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state 5. Functional diagram 2 1A 1 1OE 5 2A 4 2OE 9 3A 1Y 3 2 1 1 2Y 3 EN1 5 6 6 4 3Y 9 8 8 10 10 3OE 12 4A 12 4Y 11 11 13 13 4OE mna229 mna228 Fig 1. Logic symbol Fig 2. IEC logic symbol nY nA nOE mna227 Fig 3. Logic diagram 6. Pinning information terminal 1 index area 14 VCC 1OE 6.1 Pinning 1 14 VCC 1A 2 13 4OE 1A 2 13 4OE 1Y 3 12 4A 1Y 3 12 4A 2OE 4 11 4Y 2OE 4 125 2A 5 GND(1) 2Y 6 1 1OE GND 7 3A 8 3Y 001aac476 11 4Y 10 3OE 9 9 8 6 3Y 2Y 10 3OE 7 5 GND 2A 125 3A 001aac477 Transparent top view (1) The die substrate is attached to the exposed die pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO14, SSOP14 and TSSOP14 74LVT_LVTH125_6 Product data sheet Fig 5. Pin configuration DHVQFN14 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 06 — 6 March 2006 3 of 16 74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state 6.2 Pin description Table 3. Pin description Symbol Pin Description 1OE 1 1 output enable input (active LOW) 1A 2 1 data input 1Y 3 1 data output 2OE 4 2 output enable input (active LOW) 2A 5 2 data input 2Y 6 2 data output GND 7 ground (0 V) 3Y 8 3 data output 3A 9 3 data input 3OE 10 3 output enable input (active LOW) 4Y 11 4 data output 4A 12 4 data input 4OE 13 4 output enable input (active LOW) VCC 14 supply voltage 7. Functional description 7.1 Function table Table 4. Function table[1] Control Input Output nOE nA nY L L L H H X Z H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 74LVT_LVTH125_6 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 06 — 6 March 2006 4 of 16 74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit −0.5 +4.6 V [1] −0.5 +7.0 V [1] −0.5 +7.0 V VCC supply voltage VI input voltage VO output voltage IIK input clamping current VI < 0 V - −50 mA IOK output clamping current VO < 0 V - −50 mA IO output current output in LOW-state - 128 mA output in HIGH-state - −64 mA −65 +150 °C - 150 °C output in OFF-state or HIGH-state Tstg storage temperature Tj junction temperature [2] [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Conditions Typ Max Unit VCC supply voltage 2.7 - 3.6 V VI input voltage 0 - 5.5 V VIH HIGH-state input voltage 2.0 - - V VIL LOW-state input voltage - - 0.8 V IOH HIGH-state output current - - −32 mA IOL LOW-state output current none - - 32 mA current duty cycle ≤ 50 %; f ≥ 1 kHz - - 64 mA 0 - 10 ns/V −40 - +85 °C ∆t/∆V input transition rise and fall rate Tamb ambient temperature in free air 74LVT_LVTH125_6 Product data sheet Min © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 06 — 6 March 2006 5 of 16 74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 Conditions Min Typ Max −0.9 −1.2 Unit °C[1] VIK input clamping voltage IIK = −18 mA; VCC = 2.7 V - VOH HIGH-state output voltage IOH = −100 µA; VCC = 2.7 V to 3.6 V VCC − 0.2 VCC − 0.1 - V IOH = −8 mA; VCC = 2.7 V 2.4 2.5 - V IOH = −32 mA; VCC = 3.0 V 2.0 2.2 - V IOL = 100 µA - 0.1 0.2 V IOL = 24 mA - 0.3 0.5 V IOL = 16 mA - 0.25 0.4 V IOL = 32 mA - 0.3 0.5 V IOL = 64 mA - 0.4 0.55 V - 1 10 µA - ±0.1 ±1 µA VOL LOW-state output voltage V VCC = 2.7 V VCC = 3.0 V ILI input leakage current all input pins VCC = 0 V or 3.6 V; VI = 5.5 V control pins VCC = 3.6 V; VI = VCC or GND data pins IOFF IHOLD power-off leakage current bus hold current data input VCC = 3.6 V [2] VI = VCC - 0.1 1 µA VI = 0 V - −1 −5 µA - 1 ±100 µA VI = 0.8 V 75 150 - µA VI = 2.0 V −75 −150 - µA ±500 - - µA - 60 125 µA - ±1 ±100 µA output HIGH: VO = 3.0 V - 1 5 µA output LOW: VO = 0.5 V - −1 −5 µA - 0.13 0.19 mA VCC = 0 V; VI or VO = 0 V to 4.5 V VCC = 3 V [3] VCC = 0 V to 3.6 V VI = 3.6 V IEX external current into output output in HIGH-state when VO > VCC; VO = 5.5 V and VCC = 3.0 V IO(pu/pd) power-up/power-down output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don’t care IOZ OFF-state output current VCC = 3.6 V; VI = VIH or VIL ICC quiescent supply current [4] VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs HIGH outputs LOW outputs disabled 74LVT_LVTH125_6 Product data sheet [5] - 2 7 mA - 0.13 0.19 mA © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 06 — 6 March 2006 6 of 16 74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit - 0.1 0.2 mA ∆ICC additional quiescent supply current per input pin; VCC = 3 V to 3.6 V; one input at VCC − 0.6 V and other inputs at VCC or GND Ci input capacitance VI = 0 V or 3.0 V - 4 - pF Co output capacitance outputs disabled; VO = 0 V or 3.0 V - 8 - pF [6] [1] Typical values are measured at VCC = 3.3 V and Tamb = 25 °C. [2] Unused pins at VCC or GND. [3] This is the bus hold overdrive current required to force the input to the opposite logic state. [4] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.0 V to 3.6 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only. [5] ICC is measured with outputs pulled to VCC or GND. [6] This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Conditions Min Typ Max Unit VCC = 2.7 V - - 4.5 ns VCC = 3.0 V to 3.6 V 1.0 2.7 4.0 ns VCC = 2.7 V - - 4.9 ns VCC = 3.0 V to 3.6 V 1.0 2.9 3.9 ns VCC = 2.7 V - - 6.0 ns VCC = 3.0 V to 3.6 V 1.0 3.4 4.7 ns VCC = 2.7 V - - 6.5 ns VCC = 3.0 V to 3.6 V 1.1 3.4 4.7 ns VCC = 2.7 V - - 5.7 ns VCC = 3.0 V to 3.6 V 1.8 3.7 5.1 ns VCC = 2.7 V - - 4.0 ns VCC = 3.0 V to 3.6 V 1.3 2.6 4.5 ns Tamb = −40 °C to +85 °C[1] tPLH LOW-to-HIGH propagation delay nAn to nY see Figure 6 HIGH-to-LOW propagation delay nAn to nY see Figure 6 tPHL tPZH output enable time nOE to nY tPZL output disable time nOE to nY tPHZ tPLZ [1] output enable time nOE to nY output disable time nOE to nY see Figure 7 see Figure 7 see Figure 7 see Figure 7 Typical values are at VCC = 3.3 V and Tamb = 25 °C. 74LVT_LVTH125_6 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 06 — 6 March 2006 7 of 16 74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state 12. Waveforms VI nA input VM VM GND tPLH tPHL VOH VM nY output VM VOL mnb072 VM = 1.5 V. VOL and VOH are typical voltage output drop that occur with the output load. Fig 6. Propagation delay input (nA) to output (nY) VI nOE input VM GND tPZL tPLZ VCC VM nY output VOL + 0.3 V VOL t PZH t PHZ VOH nY output VM VOH − 0.3 V 0V 001aac475 VM = 1.5 V. VOL and VOH are typical voltage output drop that occur with the output load. Fig 7. Enable and disable times of 3-state outputs 74LVT_LVTH125_6 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 06 — 6 March 2006 8 of 16 74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae235 Test data is given in Table 9. Definitions test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 8. Load circuitry for switching times Table 9. Test data Input Load VI fi tW 2.7 V ≤ 10 MHz 500 ns CL RL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL ≤ 2.5 ns 50 pF 500 Ω GND 74LVT_LVTH125_6 Product data sheet VEXT tr, tf 6V open © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 06 — 6 March 2006 9 of 16 74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state 13. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. Package outline SOT108-1 (SO14) 74LVT_LVTH125_6 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 06 — 6 March 2006 10 of 16 74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 10. Package outline SOT337-1 (SSOP14) 74LVT_LVTH125_6 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 06 — 6 March 2006 11 of 16 74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 11. Package outline SOT402-1 (TSSOP14) 74LVT_LVTH125_6 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 06 — 6 March 2006 12 of 16 74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 12. Package outline SOT762-1 (DHVQFN14) 74LVT_LVTH125_6 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 06 — 6 March 2006 13 of 16 74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state 14. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVT_LVTH125_6 20060306 Product data sheet - 74LVT125_5 (9397 750 14703) • Modifications: Section 4: Added type numbers 74LVTH125D, 74LVTH125DB, 74LVTH125PW and 74LVTH125BQ. 74LVT125_5 20050210 Product data sheet - 74LVT125_4 (9397 750 14552) 74LVT125_4 20050207 Product data sheet - 74LVT125_3 (9397 750 13535) 74LVT125_3 20040624 Product data sheet - 74LVT125_2 (9397 750 03514) 74LVT125_2 19980219 Product specification - 74LVT125_1 74LVT125_1 - - - - 74LVT_LVTH125_6 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 06 — 6 March 2006 14 of 16 74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.semiconductors.philips.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Philips Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Philips Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, Philips Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — Philips Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Philips Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Philips Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Philips Semiconductors accepts no liability for inclusion and/or use of Philips Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — Philips Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.semiconductors.philips.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Philips Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 74LVT_LVTH125_6 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 06 — 6 March 2006 15 of 16 Philips Semiconductors 74LVT125; 74LVTH125 3.3 V quad buffer; 3-state 18. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: [email protected]. Date of release: 6 March 2006 Document identifier: 74LVT_LVTH125_6