PHILIPS PCD5090

INTEGRATED CIRCUITS
DATA SHEET
PCD5090; PCA5097
DECT baseband controllers
Objective specification
File under Integrated Circuits, IC17
1996 Oct 17
Philips Semiconductors
Objective specification
DECT baseband controllers
PCD5090; PCA5097
INTRODUCTION
This data sheet details the specific features of the:
PCD5090/xxx; DSP-ROM, with external ROM
PCA5097/xxx; DSP-ROM, with Field Electronically
Erasable Programmable Read Only Memory
(FEEPROM).
• On-chip reference voltage
FEATURES
• On-chip supply for electret microphone
General
• Very low ohmic buzzer output
• The PCx509x is designed for GAP-compliant handsets
and simple base stations
• IOM-2interface (Siemens registered trademark)
• Serial interface to external ADPCM CODEC (PCD5032)
• Serial interface to synthesizer for frequency
programming
• Embedded 80C51 microcontroller with twice the
performance of the classic architecture, up to
128 kbytes external memory or 64 kbytes FEEPROM
program memory and 3 kbytes of data memory on chip.
In addition there is 1 kbyte of on-chip data memory that
is shared with on-chip Burst Mode Logic (BML) and
DSP, the System Data RAM (SDR).
• Programmable timing of radio-control signals
• Programmable polarity of radio-control signals
• Easy interfacing with radio circuits, operating at other
supply voltage
• Programmable GMSK pulse shaper
• 80C51 ports P0, P1, P2 and P3 available for interfacing
to display, keyboard, I2C-bus, interrupt sources and/or
external memory. External program memory is
addressable up to 128 kbytes (PCD5090/xxx and
PCA5097/xxx).
• On-chip comparator for use as bit-slicer
• Power-on reset
• Low supply voltage (2.7 to 5.5 V)
• SACMOS technology.
• Portable Part (PP) and Fixed Part (FP) modes
• TDMA frame (de)multiplexing; transmission or reception
can be programmed for any slot
DSP software features
• Ciphering, scrambling, CRC checking/generation,
protected B-fields
• Speech filters
• ADPCM encoding and decoding complying with G.721
• Programmable gain in speech paths
• Speech and data buffering space for six handsets
• Side tone and soft mute
• Local call and B-field loop-back
• Ringer and tone (DTMF) generator
• Two interrupt lines for BML and DSP to interrupt 80C51
• Dial tone detection
• On-chip, three-channel time-multiplexed 8-bit
Analog-to-Digital Converter (ADC) for RSSI
measurement and battery voltage measurement. One
channel available for other purposes.
• Echo cancellation
• Automatic gain control
• Telephone Answering Machine (TAM) switch
• On-chip 8-bit DAC for frequency adjustment of
13.824 MHz on-chip crystal oscillator
• Conference call (PCD5090/400)
• Hands-free operation (PCD5090/311).
• Phase error measurement and phase error correction by
hardware
For each DSP software version a separate manual is
available, in which detailed information is provided on how
parameters must be set.
• Digital-to-Analog Converters (DACs) and ADCs for
dynamic earpiece and dynamic or electret microphone
1996 Oct 17
2
Philips Semiconductors
Objective specification
DECT baseband controllers
PCD5090; PCA5097
ORDERING INFORMATION
TYPE
NUMBER
PCD5090H
PCA5097H
PCD5090HZ
1996 Oct 17
PACKAGE
NAME
DESCRIPTION
VERSION
QFP100
plastic quad flat package; 100 leads (lead length 1.95 mm); body
14 × 20 × 2.8 mm
SOT317-2
LQFP100
plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm
SOT407-1
3
1996 Oct 17
4
CLK100
XTAL1
XTAL2
GP_CLK7
DPLL_DATA
T_GMSK
R_SLICED
SLICE_CTR
R_PWR
R_ENABLE
REF_CLK
SYNTH_LOCK
S_ENABLE
S_CLK
S_DATA
VCO_BND_SW
S_PWR
ANT_SW0
ANT_SW1
T_ENABLE
T_PWR_RMP
T_DATA
R_DATAP
R_DATAM
PGM
WEN
SDI
SC
OEN
SDO/A16
PSE
EA
ALE
EN_WATCHDOG
RESET_OUT
IB-BUS
VDD
4fs
POWER-ON RESET
(POR)
ANALOG VOLTAGE
REFERENCE
(AVR)
VDDA
DIGITAL
SIGNAL
PROCESSOR
(DSP)
4fs
VBGP
VDD
DIGITAL
NOISE
SHAPER
(DNS)
ANALOG
VOLTAGE
SOURCE
(AVS)
VANLO
VADC
Vref
108fs
108fs
2×
VSS
2×
VDD
VSSA
ARF
MUX
3:1
SUBTRACT
PEAK-HOLD
AUXILIARY ADC (AAD)
CODEC
ATS
Σ∆
1-BIT ADC
ARD
BUZZER BUFFER
(ABB)
AMP
SPEECH INTERFACE
IOM/ADPCM
(SPI)
ARA
VDDA
TEST CONTROL BLOCK
(TCB)
1-BIT ADC
VDDA
VDD
VSS_RF VDD_RF
DIGITAL
DECIMATING
FILTER
(DDF)
MICROCONTROLLER
I2C-BUS
PORT 3
8
PORT 3.0 to
PORT 3.7
Fig.1 Functional blocks and signals in PCx509x.
M_RESET
RESET
GENERATOR
(RGE)
WATCHDOG
TIMER
(WDT)
XTAL
OSCILLATOR
(XOSC)
PORT 2
8
PORT 2.0 to
PORT 2.7
MICROCONTROLLER_RAM
(256 BYTES)
DIGITAL
CONTROL
OF
ANALOG
(DCA)
SYSTEM
DATA
RAM
(SDR)
(1 kBYTE)
VDD
AB-MICROCONTROLLER
INTERFACE (ABCIF)
AUX-RAM
(3 kBYTES)
PORT 1
8
PORT 1.0 to
PORT 1.7
ISB BUS
CONTROLLER
(IBC)
BURST
MODE
LOGIC
(BML)
FEEPROM
(64 kBYTES)
PORT 0
8
PORT 0.0 to
PORT 0.7
TIMING CONTROL
BLOCK
(TICB)
LEVEL
SHIFTER
VDD
PGMFEE
80CL51- CORE
VDD_FEE
CLOCK
GENERATOR
(CLG)
VDD
AGM
VDDA
VDD_RF
VDD
VSS_FEE
Vref
MGE610
CDC-on
VBAT
RSSI_AN
VANLI
Vref
VMIC
MICP
MICM
LIFP
LIFM
EARP
EARM
BZP
BZM
DO
DI
FS1
DCK
CLK3
TST1
TST2
digital pins
analog pins
supply pins
DECT baseband controllers
handbook, full pagewidth
Philips Semiconductors
Objective specification
PCD5090; PCA5097
BLOCK DIAGRAM
1996 Oct 17
7
8
9
10
T_GMSK
VCO_BND_SW
SYNTH_LOCK
S_ENABLE
5
99
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDD_RF
VDD_FEE
SLICE_CTR
R_PWR
R_DATAP
R_DATAM
R_ENABLE
RSSI_AN
VANLI
VBAT
CLK3
DCK
DI
26
25
24
23
22
21
20
L
−
−
−
−
I
I/O
O
I
I
I
O
I
I
O
ISP2DRF3
ANAIOD2
−
ISF2DPES
ISF2UPES
DIPP0PES
input
−
ISP2DPES
ANAIOD1
−
L
ANAIOD1
ANAIOD1
−
ISP2DRF3
ANAIOD2
−
−
H
ISP2DRF3
ISP2DRF3
supply
supply
supply
ISP4DRF3
ISP2DRF3
ISP2DRF3
H
L
−
O
running
−
H
L
ISP2DRF3
DIPP0RF3
−
L
ISP2DRF3
ANAIOD1
ISF2DRF3
ISP2DRF3
ISP2DRF3
ISP2DPES
ISP2DRF3
ISP2DRF3
PIN TYPE
L
L
off
L
H
H
H
H
STATE
AFTER
RESET
O
O
O
O
O
I
O
O
O
O
O
O
O
O
I/O
antenna switch 1 output
ADPCM or IOM data input
ADPCM output or IOM data clock input/output
(ISF2UPES in PCD5090/xxx, PCA5097/xxx)
3.456 MHz clock output for external ADPCM codec
analog input for battery voltage measurement
analog input to A/D converter
analog input for RSSI measurement
enable receiver output
negative input for receiver data
positive input for receiver data
switch receiver power output
switch slicer time constant output
positive supply voltage for FEEPROM program memory
positive supply voltage for RF interface level shifters
negative supply voltage for RF interface level shifters
13.824 MHz reference clock for synthesizer output
switch synthesizer power output
clock for serial synthesizer interface output
serial synthesizer data output
synthesizer enable output
synthesizer lock input
VCO band switch output
GMSK modulated transmitter data output
unmodulated transmitter data output
switch transmitter power output
enable transmitter output
100 Hz signal related to DECT frame timing output
antenna switch 0 output
PIN DESCRIPTION
DECT baseband controllers
19
18
17
16
12
13
14
15
VSS_RF
11
10
9
8
7
6
5
4
3
2
1
100
REF_CLK
13
6
T_DATA
S_PWR
5
T_PWR_RMP
11
4
T_ENABLE
12
3
CLK100
S_CLK
2
S_DATA
1
ANT_SW0
LQFP100
PIN
QFP100
ANT_SW1
SYMBOL
PINNING
Philips Semiconductors
Objective specification
PCD5090; PCA5097
1996 Oct 17
37
38
39
40
41
LIFP
VSSA
MICM
MICP
VMIC
6
55
56
57
P1.4
P1.5
51
GP_CLK7
P1.3
50
P1.2
54
49
P1.1
PGM
48
P1.0
52
47
EN_WATCHDOG
53
46
EARP
R_SLICED
45
EARM
55
54
53
52
51
50
49
48
47
46
45
44
I/O
I/O
I/O
I
O
O
O
I/O
I/O
I/O
I
O
H
H
ISQ2CPES
ISQ2CPES
ISQ2CPES
DIDP0PES
−
H
ISP2DPES
ISP2DPES
ISP2DPES
ISQ2CPES
ISQ2CPES
ISQ2CPES
L
L
L
H
H
H
ANAIOD1
DIUP0PES
−
ANAIOD1
supply
ANAIOR1
ANAIOD1
ANAIOD1
ANAIOR1
ANAIOR1
supply
ANAIOD1
1.4 V
1.4 V
−
O
1.25 V
−
2.0 V
off
0.7 V
O
O
O
I
0.7 V
−
−
I
0.7 V
ANAIOD1
DIDP0PES
−
0.7 V
ANAIOD1
DIDP0PES
−
ANAIOD1
−
1.0 V
ANAIOD1
ISI8DPES
ISF2DPES
ISF2UPES
PIN TYPE
running
off
input
STATE
AFTER
RESET
I
I
I
I
O
I
O
O
I/O
I/O
bidirectional 80C51 port pin
bidirectional 80C51 port pin
bidirectional 80C51 port pin
FEEPROM programming mode; can be left open-circuit for
PCA5090 and PCD5090/xxx
R_DATA comparator output
data after clock recovery network
general purpose 6.912 MHz output
bidirectional 80C51 port pin
bidirectional 80C51 port pin
bidirectional 80C51 port pin
watchdog enable input
positive output to earpiece
negative output to earpiece
positive supply voltage for analog circuits
bandgap output voltage (+1.25 V)
reference voltage (+2 V)
positive microphone supply voltage (+2 V)
positive input from microphone
negative input from microphone
negative supply voltage for analog circuits
positive input from line interface
negative input from line interface
test input 1
test input 2
analog output from D/A converter
crystal oscillator input
crystal oscillator output
ADPCM or IOM data output
8 kHz framing input/output
(ISF2UPES in PCD5090/xxx, PCA5097/xxx)
PIN DESCRIPTION
DECT baseband controllers
DPLL_DATA
42
43
41
43
44
VDDA
40
39
38
37
34
33
VBGP
42
36
36
LIFM
Vref
35
35
TST1
32
31
30
33
32
XTAL1
29
28
34
31
XTAL2
TST2
30
DO
27
VANLO
29
LQFP100
PIN
QFP100
FS1
SYMBOL
Philips Semiconductors
Objective specification
PCD5090; PCA5097
1996 Oct 17
60
61
62
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
BZM
BZP
VSS2
VSS_FEE
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P2.0
7
P2.1
P2.2
SDO/A16
OEN
SC
SDI
WEN
P2.3
P2.4
80
79
78
77
76
−
−
I/O
I/O
I
I
I
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DIDP0PES
DIDP0PES
DIUP0PES
−
−
−
H
ISQ2CPES
ISQ2CPES
DIDP0PES
−
H
ISP4DPES
ISQ2CPES
ISQ2CPES
ISQ2CPES
ISQ2CPES
ISQ2CPES
ISQ2CPES
ISQ2CPES
ISQ2CPES
ISQ2CPES
ISQ2CPES
ISQ2CPES
supply
supply
ANAIOD2
ANAIOD2
supply
ISI8DPES
ISI8DPES
PIN TYPE
H or L
L
H
H
H
H
H
H
H
H
H
H
H
−
−
I/O
L
O
L
−
O
off
−
off
STATE
AFTER
RESET
I/O
I/O
I/O
bidirectional 80C51 port pin
bidirectional 80C51 port pin
FEEPROM Write enable;
can be left open-circuit for PCA5090, PCD5090/xxx
FEEPROM shift data input;
can be left open-circuit for PCA5090, PCD5090/xxx
FEEPROM shift clock;
can be left open-circuit for PCA5090, PCD5090/xxx
FEEPROM output enable;
tie to VDD for PCA5090, PCD5090/xxx
PCA5090,PCA5097: FEEPROM shift data output
PCD5090/xxx, PCA5097/xxx: FEEPROM shift data out/address
bit 16 for 128 kbytes external program memory
bidirectional 80C51 port pin
bidirectional 80C51 port pin
bidirectional 80C51 port pin
bidirectional 80C51 port pin
bidirectional 80C51 port pin
bidirectional 80C51 port pin
bidirectional 80C51 port pin
bidirectional 80C51 port pin
bidirectional 80C51 port pin
bidirectional 80C51 port pin
bidirectional 80C51 port pin
negative supply voltage
negative supply voltage
positive buzzer output
negative buzzer output
positive supply voltage
bidirectional 80C51 port pin
bidirectional 80C51 port pin
PIN DESCRIPTION
DECT baseband controllers
75
74
73
72
71
70
69
68
67
66
65
64
63
59
57
58
59
60
VDD2
56
P1.7
58
LQFP100
PIN
QFP100
P1.6
SYMBOL
Philips Semiconductors
Objective specification
PCD5090; PCA5097
1996 Oct 17
86
87
88
96
97
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P2.7
PSE
ALE
EA
VSS1
VDD1
P0.7
P0.6
P0.5
P0.4
P0.3
8
P0.2
P0.1
P0.0
M_RESET
RESET_OUT
−
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DIDP0PES
ISF2DPES
−
H
ISP2DPES
ISQ2CPES
ISP2DPES
ISQ2CPES
ISP2DPES
ISQ2CPES
ISP2DPES
ISQ2CPES
ISP2DPES
ISQ2CPES
ISP2DPES
ISQ2CPES
ISP2DPES
ISQ2CPES
ISP2DPES
ISQ2CPES
supply
off
H
off
H
off
H
off
H
off
H
off
H
off
H
off
H
−
I/O
−
−
supply
ISQ4CPES
ISF2DPES
−
ISQ2CPES
ISQ2CPES
ISQ2CPES
ISQ2CPES
PIN TYPE
H
H
H
H
H
STATE
AFTER
RESET
I
O
O
I/O
I/O
I/O
I/O
reset output
master reset input (Schmitt-trigger)
bidirectional 80C51 port pin
(ISQ2CPES in PCD5090/xxx, PCA5097/xxx)
bidirectional 80C51 port pin
(ISQ2CPES in PCD5090/xxx, PCA5097/xxx)
bidirectional 80C51 port pin
(ISQ2CPES in PCD5090/xxx, PCA5097/xxx)
bidirectional 80C51 port pin
(ISQ2CPES in PCD5090/xxx, PCA5097/xxx)
bidirectional 80C51 port pin
(ISQ2CPES in PCD5090/xxx, PCA5097/xxx)
bidirectional 80C51 port pin
(ISQ2CPES in PCD5090/xxx, PCA5097/xxx)
bidirectional 80C51 port pin
(ISQ2CPES in PCD5090/xxx, PCA5097/xxx)
bidirectional 80C51 port pin
(ISQ2CPES in PCD5090/xxx, PCA5097/xxx)
positive supply voltage
negative supply voltage
external access enable (80C51)
address latch enable (80C51)
program store enable (80C51)
bidirectional 80C51 port pin
bidirectional 80C51 port pin
bidirectional 80C51 port pin
PIN DESCRIPTION
DECT baseband controllers
98
95
94
93
92
91
90
89
85
84
83
82
84
P2.6
81
LQFP100
83
QFP100
PIN
P2.5
SYMBOL
Philips Semiconductors
Objective specification
PCD5090; PCA5097
Philips Semiconductors
Objective specification
81 P2.3
82 P2.4
83 P2.5
84 P2.6
85 P2.7
86 PSE
87 ALE
88 EA
90 VDD1
89 VSS1
91 P0.7
92 P0.6
93 P0.5
94 P0.4
PCD5090; PCA5097
95 P0.3
96 P0.2
97 P0.1
98 P0.0
handbook, full pagewidth
99 M_RESET
100 RESET_OUT
DECT baseband controllers
ANT_SW1
1
80
WEN
ANT_SW0
2
79
SDI
CLK100
3
78
SC
T_ENABLE
4
77
OEN
T_PWR_RMP
5
76
SDO/A16
T_DATA
6
75
P2.2
T_GMSK
7
74
P2.1
VCO_BND_SW
8
73
P2.0
SYNTH_LOCK
9
72
P3.7
S_ENABLE 10
71
P3.6
S_DATA 11
70
P3.5
S_CLK 12
69
P3.4
S_PWR 13
68
P3.3
REF_CLK 14
67
P3.2
66
P3.1
65
P3.0
64
VSS_FEE
SLICE_CTR 18
63
VSS2
R_PWR 19
62
BZP
R_DATAP
20
61
BZM
R_DATAM
21
60
VDD2
R_ENABLE
22
59
P1.7
RSSI_AN
23
58
P1.6
VANLI
24
57
P1.5
VBAT
25
56
P1.4
CLK3
26
55
P1.3
DCK
27
54
PGM
DI
28
53
R_SLICED
FS1
29
52
DPLL_DATA
DO
30
51
GP_CLK7
VSS_RF 15
Fig.2 Pin configuration of PCX509x (QFP100).
1996 Oct 17
9
P1.2 50
P1.1 49
P1.0 48
EN_WATCHDOG 47
EARP 46
EARM 45
VDDA 44
VBGP 43
Vref 42
VMIC 41
MICP 40
VSSA 38
LIFP 37
LIFM 36
TST1 35
TST2 34
VANLO 33
XTAL1 32
XTAL2 31
MICM 39
PCA5097
PCD5090
VDD_RF 16
VDD_FEE 17
MGE575
Philips Semiconductors
Objective specification
76 SC
77 SDI
78 WEN
79 P2.3
81 P2.5
80 P2.4
82 P2.6
83 P2.7
84 PSE
85 ALE
86 EA
87 VSS1
88 VDD1
89 P0.7
90 P0.6
91 P0.5
92 P0.4
PCD5090; PCA5097
93 P0.3
94 P0.2
95 P0.1
96 P0.0
97 M_RESET
98 RESET_OUT
handbook, full pagewidth
99 ANT_SW1
100 ANT_SW0
DECT baseband controllers
CLK100
1
75 OEN
T_ENABLE
2
74 SDO/A16
T_PWR_RMP
3
73 P2.2
T_DATA
4
72 P2.1
T_GMSK
5
71 P2.0
VCO_BND_SW
6
70 P3.7
SYNTH_LOCK
7
69 P3.6
S_ENABLE
8
68 P3.5
S_DATA
9
67 P3.4
S_CLK 10
66 P3.3
S_PWR 11
65 P3.2
REF_CLK 12
64 P3.1
PCD5090
VSS_RF 13
63 P3.0
VDD_RF 14
62 VSS_FEE
VDD_FEE 15
61 VSS2
SLICE_CTR 16
60 BZP
R_PWR 17
59 BZM
R_DATAP 18
58 VDD2
R_DATAM 19
57 P1.7
R_ENABLE 20
56 P1.6
RSSI_AN 21
55 P1.5
VANLI 22
54 P1.4
VBAT 23
53 P1.3
CLK3 24
52 PGM
DCK 25
Fig.3 Pin configuration of PCD5090/xxx only (LQFP100).
1996 Oct 17
10
DPLL_DATA 50
GP_CLK7 49
P1.2 48
P1.1 47
P1.0 46
EN_WATCHDOG 45
EARP 44
EARM 43
VDDA 42
VBGP 41
Vref 40
VMIC 39
MICP 38
MICM 37
VSSA 36
LIFP 35
LIFM 34
TST1 33
TST2 32
VANLO 31
XTAL1 30
XTAL2 29
DO 28
DI 26
FS1 27
51 R_SLICED
MGD744
Philips Semiconductors
Objective specification
DECT baseband controllers
PCD5090; PCA5097
A-fields and B-fields are stored in separate buffers. In this
way, two traffic bearers, each with their private A-fields,
can share the same B-field buffer as is required in case of
bearer hand-over or local call.
FUNCTIONAL DESCRIPTION
DECT controller system description
The PCX509x is a family of single-chip controllers,
designed for use in Digital Enhanced Cordless
Telecommunications (DECT) systems. The family is
designed for minimal component-count and minimum
power consumption. All controllers include an embedded
80C51 microcontroller with on-chip memory and I2C-bus.
The Philips DECT RF-Interface is implemented. The Burst
Mode Logic performs the time-critical MAC layer functions
for applications in DECT handsets and base stations.
The ADPCM transcoding is in compliance with the CCITT
recommendation G.721 and includes receive and transmit
filters.
The blocks DSP and CODEC support speech processing
functions such as A/D- and D/A conversion, filtering,
ADPCM encoding and decoding, 8-bit A-law PCM to 14-bit
linear PCM conversion and its reverse, echo cancelling,
tone generation, etc.
PCA5097
This chip is intended for program development. It contains
64 kbytes of internal program memory (FEEPROM) for the
80C51 and DSP program RAM.
Power-on reset logic and power management functions
further reduce power consumption and external
components. The chip is intended to support stand-alone
systems only. There are no provisions to build clusters of
base stations. There are no provisions for external
controllers to exert control over the embedded 80C51 or to
have direct access to the on-chip data memories.
PCD5090/xxx
This chip is intended for handset and base station
applications. The DSP program is now fixed in a ROM, for
which several ROM codes (/xxx) are available (handset,
analog base, digital base). An external program memory
for the 80C51 of 128 kbytes ROM can be handled.
The DECT controller consists of a number of functional
blocks that operate more or less autonomously and
communicate with each other via the System Data RAM
(SDR). Blocks have access to SDR via the Internal System
Bus (ISB). The ISB consists of an 8-bit data, a 10-bit
address bus and a number of bus-request/bus-grant
signals. Access to the ISB is controlled by ISB bus
Controller (IBC). The IBC acknowledges bus requests on
the basis of a priority scheme.
PCA5097/xxx
This is the same as PCD5090/xxx, but there is 64 kbytes
internal program memory (FEEPROM) for the 80C51.
The DSP program is preprogrammed in ROM.
This chip is meant for development purpose only.
The embedded controller 80C51 is to be programmed by
the user. It must contain DECT software from
Man-Machine-Interface (MMI) to the DECT protocols TBC,
CBC and DBC (refer to figures 10, 11, 12 and 13 in
“prETS 300 175-2:1992 section 6”).
All software is available from Philips Semiconductors.
Hardware state machines in the Burst Mode Logic (BML)
and the Speech Interface (SPI) execute the lower blocks in
the TBC, CBC and DBC. The 80C51 has control over the
BML and the SPI via tables in SDR. The BML saves serial
data, received via R_DATAP/M, in buffer areas in SDR.
The position of buffers in SDR is fixed by the 80C51
software by means of tables previously mentioned.
1996 Oct 17
11
Philips Semiconductors
Objective specification
DECT baseband controllers
PCD5090; PCA5097
handbook, full pagewidth
EARPIECE
RADIO
CIRCUITS
PCx509x
MICROPHONE
MGE586
a. Handset.
handbook, full pagewidth
RADIO
CIRCUITS
LINE
INTERFACE
(e.g. PCD1070)
PCx509x
a/b line
MGD745
b. Base with analog interface and echo cancellation; up to 6 portables can be handled.
handbook, full pagewidth
EARPIECE
RADIO
CIRCUITS
PCx509x
MICROPHONE
2
2 x IOM or
2 x ADPCM-CODEC or
a combination
MGD746
c. Base with digital interface and analog handset connected; up to 6 portables can be handled.
Fig.4 Block diagrams of DECT systems with PCx509x.
1996 Oct 17
12
Philips Semiconductors
Objective specification
DECT baseband controllers
PCD5090; PCA5097
PACKAGE OUTLINES
QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT317-2
c
y
X
80
A
51
81
50
ZE
Q
e
E HE
A
A2
(A 3)
A1
θ
wM
pin 1 index
Lp
bp
L
31
100
detail X
30
1
wM
bp
e
ZD
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
Q
v
w
y
mm
3.20
0.25
0.05
2.90
2.65
0.25
0.40
0.25
0.25
0.14
20.1
19.9
14.1
13.9
0.65
24.2
23.6
18.2
17.6
1.95
1.0
0.6
1.4
1.2
0.2
0.15
0.1
Z D (1) Z E(1)
0.8
0.4
1.0
0.6
θ
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-02-04
SOT317-2
1996 Oct 17
EUROPEAN
PROJECTION
13
o
7
0o
Philips Semiconductors
Objective specification
DECT baseband controllers
PCD5090; PCA5097
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SOT407-1
c
y
X
A
51
75
50
76
ZE
e
Q
E HE
A A2
(A 3)
A1
w M
θ
bp
Lp
L
pin 1 index
100
detail X
26
1
25
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.20
0.05
1.5
1.3
0.25
0.28
0.16
0.18
0.12
14.1
13.9
14.1
13.9
0.5
HD
HE
16.25 16.25
15.75 15.75
L
Lp
Q
v
w
y
1.0
0.75
0.45
0.70
0.57
0.2
0.12
0.1
Z D (1) Z E (1)
θ
1.15
0.85
7
0o
1.15
0.85
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-12-19
SOT407-1
1996 Oct 17
EUROPEAN
PROJECTION
14
o
Philips Semiconductors
Objective specification
DECT baseband controllers
PCD5090; PCA5097
SOLDERING
Wave soldering
Introduction
Wave soldering is not recommended for LQFP or QFP
packages. This is because of the likelihood of solder
bridging due to closely-spaced leads and the possibility of
incomplete solder penetration in multi-lead devices.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Reflow soldering
Even with these conditions:
Reflow soldering techniques are suitable for all LQFP and
QFP packages.
• Do not consider wave soldering LQFP packages
LQFP48 (SOT313-2), LQFP64 (SOT314-2) or
LQFP80 (SOT315-1).
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
• Do not consider wave soldering QFP packages
QFP52 (SOT379-1), QFP100 (SOT317-1),
QFP100 (SOT317-2), QFP100 (SOT382-1) or
QFP160 (SOT322-1).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1996 Oct 17
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
15
Philips Semiconductors
Objective specification
DECT baseband controllers
PCD5090; PCA5097
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Short-form specification
The data in this specification is extracted from a full data sheet with the same type
number and title. For detailed information see the relevant data sheet or data handbook.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 Oct 17
16