PHILIPS UMA1005

INTEGRATED CIRCUITS
DATA SHEET
UMA1005T
Dual low-power frequency
synthesizer
Preliminary specification
Supersedes data of September 1992
File under Integrated Circuits, IC03
Philips Semiconductors
November 1994
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
FEATURES
GENERAL DESCRIPTION
• Fast locking by ‘Fractional-N’ divider
The UMA1005T is a low-power, high-performance dual
frequency synthesizer fabricated in CMOS technology.
Fractional-N division with selectable modulo 5 or 8 is
implemented in the main synthesizer.
• Auxiliary synthesizer
• Digital phase comparator with proportional and integral
charge pump output
The detectors and charge pumps are designated to
achieve 10 to 5000 kHz channel spacing using
fractional-N decreases the channel spacing by a factor
5 or 8. Together with an external standard 2, 3 or 4 ratio
prescaler the main synthesizer can operate in the GHz
frequency range.
• High-speed serial input
• Low-power consumption
• Programmable charge pump currents
• Supply voltage range 2.9 to 5.5 V.
Channel selection and programming is realized by a
high-speed 3-wire serial interface.
APPLICATIONS
• Mobile telephony
• Portable battery-powered radio equipment.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
UMA1005T
November 1994
NAME
DESCRIPTION
VERSION
SSOP20
plastic shrink small outline package; 20 leads; body width 4.4 mm
SOT266-1
2
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
BLOCK DIAGRAM
/1 page = 296 mm (Datasheet)
4
DATA
5
CLOCK
6
STROBE
27 mm
SERIAL INPUT + PROGRAM LATCHES
EM
PR
2
NM1
12
NM2
NM3
NM4
4
8
FMOD
NF
3
2
INM1
FRACTIONAL
ACCUMULATOR
MAIN DIVIDERS
INM2
3
PRESCALER
FEEDBACK
CN
15
8
2
UMA1005T
NR
INR
CK
2
2
2
2
INTEGRAL
OUTPUT
CHARGE
PUMP
AUXILIARY
REFERENCE
SELECT
AUXILIARY
OUTPUT
CHARGE
PUMP
2
AUXILIARY
PHASE
DETECTOR
4 1
17
AUXILIARY DIVIDER
Fig.1 Block diagram.
November 1994
10
PHI
RA
PHA
12
8
INA
11
9
EA
EA
PHP
4
SA
NA
RF
RN
SPEED-UP
OUTPUT
CHARGE
PUMP
MAIN
REFERENCE
SELECT
REFERENCE DIVIDER
PA
FB2
2
12
7
13
CL
SM
EM + EA
FB1
NORMAL
OUTPUT
CHARGE
PUMP
MAIN
PHASE
DETECTOR
2
19
16
FRD
EM
18
3
1
14
V DDD
V DDA
20
V SS
12
V SSA
LOCK
MEA668 - 1
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
PINNING
SYMBOL PIN
DESCRIPTION
VDDD
1
digital supply voltage
INM1
2
main divider positive input; rising edge
active
INM2
3
main divider negative input; falling
edge active
DATA
4
serial data input line
CLOCK
5
serial clock input line
STROBE
6
serial strobe input line
INR
7
reference divider input line; rising edge
active
INA
8
auxiliary divider input line; rising edge
active
1/2 page (Datasheet)
V DDD
1
20 V SS
INM1
2
19
FB2
INM2
3
18
FB1
DATA
4
17
LOCK
CLOCK
5
16
RF
UMA1005T
STROBE
6
15
RN
INR
7
14
V DDA
integral phase detector output
INA
8
13
PHP
12
analog ground; internally connected to
VSS
RA
9
12
V SSA
PHA 10
11
PHI
PHP
13
proportional phase detector output
VDDA
14
analog supply voltage
RN
15
main current setting input; resistor to
VSS
RF
16
fractional compensation current setting
input; resistor to VSS
LOCK
17
lock detector output
FB1
18
feedback output 1 for prescaler
modulus control
FB2
19
feedback output 2 for prescaler
modulus control
VSS
20
common ground connection
RA
9
auxiliary current setting; resistor to VSS
PHA
10
auxiliary phase detector output
PHI
11
VSSA
November 1994
MEA667
Fig.2 Pin configuration.
4
22 mm
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
is reset when programming the D word. The data for NM4,
CN and PR is stored by the B word temporary registers.
When the A word is loaded, the data of these temporary
registers is loaded together with the A word into the work
registers which avoids false temporary main divider input.
CN is only loaded from the temporary registers when a
short 24-bit A0 word is used. CN will be directly loaded by
programming a long 32-bit A1 word. The flag LONG in the
D word determines whether A0 (LONG = 0) or A1
(LONG = 1) format is applicable.
FUNCTIONAL DESCRIPTION
Serial programming input
The serial input is a 3-wire input (CLOCK, STROBE and
DATA) to program all counter ratios, DACs, selection and
enable bits. The programming data is structured into
24 or 32-bit words. Each word includes 1 or 4 address
bits. Figure 3 shows the timing diagram of the serial input.
When the STROBE = LOW, the clock driver is enabled
and on the positive edges of the CLOCK the signal on the
DATA input is clocked into a shift register. When the
STROBE = HIGH, the clock is disabled and the data in the
shift register remains stable. Depending on the
1 or 4 address bits the data is latched into different
working registers or temporary registers. In order to fully
program the synthesizer, 4 words must be sent:
The A word contains new data for the main divider. The
A word is loaded only when a main divider synchronization
signal is also active, to avoid phase jumps when
reprogramming the main divider. The synchronization
signal is generated by the main divider. It disables the
loading of the A word each main divider cycle during
maximum 300 main divider input cycles. To make sure
that the A word will be correctly loaded the STROBE signal
must be HIGH for at least 300 main divider input cycles.
Programming the A word also means that the main charge
pumps on outputs PHP and PHI are set into the speed-up
mode as long as the STROBE remains HIGH.
1. D word.
2. C word.
3. B word.
4. A word.
Figure 4 shows the format and the contents of each word.
The E word is for testing purposes only. The E (test) word
handbook, full pagewidth
data
valid
UMA1005T
data
change
VH
DATA
D0
D1
D30
D31
VL
t suDA
t hDA
t HC
t LC
VH
CLOCK
VL
t suST
t hST
VH
STROBE
VL
clock enabled
shift in data
Fig.3 Serial input timing sequence.
November 1994
5
clock disabled
store data
MBE121
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
andbook, full pagewidth
MSB
LSB
word
D0
D31
A1
0
NF
NM2
NM1
NM3
CN
NM2
D23
A0
D0
0
NF
NM1
B
1
0
0
0
C
1
0
0
1
D
1
0
1
0
E
1
1
1
1
PR = ‘01’
NM2
NM3
NM4
CN
0
0
0
NA
0
0
0
NR
NM2
CK
CL
PR
PR
PA
SM
EM
SA
F
EA M
O
D
TEST BITS
D23
D0
MBE122
address bits
Fig.4 Serial input word format.
November 1994
L
O
N
G
6
‘01’
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
Table 1
UMA1005T
Description of symbols used in Fig.4
SYMBOL
BITS(1)
FUNCTION
NM1
12
number of main divider cycles when prescaler is programmed in ratio
R1 (FB1 = 1; FB2 = 0); note 2
NM2
8 if PR = 01
number of main divider cycles when prescaler is programmed in ratio
R2 (FB1 = 0; FB2 = 0); note 2
NM3
4 if PR = 1X
number of main divider cycles when prescaler is programmed in ratio
R3 (FB1 = 0; FB2 = 1); note 2
NM4
4 if PR = 11 or 00
number of main divider cycles when prescaler is programmed in ratio
R4 (FB1 = 1; FB2 = 1); note 2
4 if PR ≠ 01
PR
2
prescaler type in use:
PR = 01; modulus 2 prescaler
PR = 10; modulus 3 prescaler
PR = 11; modulus 4 prescaler
PR = 00; modulus 4 prescaler (inhibit ratio 3)
NF
3
fractional-N increment
FMOD
1
fraction-N modulus selection flag:
1 = modulo 8
0 = modulo 5
LONG
1
A word format selection flag:
0 = 24-bit A0 format
1 = 32-bit A1 format
CN
8
binary current setting factor for main charge pumps
CL
2
binary acceleration factor for proportional charge pump current
CK
4
binary acceleration factor for integral charge pump current
EM
1
main divider enable flag
EA
1
auxiliary divider enable flag
SM
2
reference select for main phase detector
SA
2
reference select for auxiliary phase detector
NR
9
reference divider ratio
NA
9
auxiliary divider ratio
PA
1
auxiliary prescaler mode:
PA = 0; divide-by-4
PA = 1; divide-by-1
Notes
1. X = don’t care.
2. Not including reset cycles and fractional-N effects.
in the input stage are switched off. A fixed divide by 4 is
enabled if PA = 0. This divider has been optimized to
accept a high-frequency (90 MHz at a supply voltage
range of 4.75 to 5.5 V) input signal. If PA = 1 this divider is
disabled and the input signal is fed directly to the second
Auxiliary variable divider
The input signal on INA is amplified to a logic level by a
single ended input buffer, which accepts LOW level AC
coupled input signals. This input stage is enabled if the
serial control bit EA = 1. Disabling means that all currents
November 1994
7
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
stage, which is a 9-bit programmable divider with standard
input frequency (30 MHz). The division ratio can be
expressed as:
UMA1005T
auxiliary reference signals, the opposite output will be
used for the auxiliary phase detector, reducing the
possibility of unwanted interactions. For this reason the
programmable divider produces a symmetric output pulse
for even ratios and a 1 input cycle asymmetric pulse for
odd ratios.
If PA = 0; N = 4 × NA.
If PA = 1; N = NA; with NA = 4 to 511.
Reference variable divider (Fig.5)
Main variable divider
The input signal on INR is amplified to a logic level by a
single ended input buffer, which accepts LOW level AC
coupled input signals. This input stage is enabled by the
OR function of the serial input bits EA and EM. Disabling
means that all currents in the input stage are switched off.
The reference divider consists of a programmable divider
by NR (NR = 4 to 511) followed by a 3-bit binary counter.
The 2-bit SM determines which of the 4 output pulses is
selected as main phase detector input. The 2-bit SA
determines the selection of the auxiliary phase detector
signal. To obtain the best time spacing for the main and
The input signals on INM1 and INM2 are amplified to a
logic level by a balanced input comparator giving a
common mode rejection. This input stage is enabled when
serial control bit EM = 1. Disabling means that all currents
in the comparator are switched off. The main divider is
built-up by a 12-bit counter plus a sign bit. Depending on
the serial input values of NM1, NM2, NM3, NM4 and the
prescaler select PR, the counter will select a prescaler
ratio during a number of input cycles in accordance with
the information in Table 2.
MAIN SELECT
book, full pagewidth
SM = ‘00’
SM = ‘01’
SM = ‘10’
main
phase
detector
SM = ‘11’
reference
input
divide by NR
2
2
2
AUXILIARY SELECT
SA = ‘11’
SA = ‘10’
SA = ‘01’
SA = ‘00’
MBE123
Fig.5 Reference variable divider.
November 1994
8
auxiliary
phase
detector
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
Table 2
UMA1005T
Selection of prescaler ratio
COUNTER
STATUS
PRESCALER RATIO(1)
FB1
FB2
(−NM1 − 1) to 0
1
0
R1
(−NM1 − 1) to −1
1
0
R1(2)
1 to NM2
0
0
R2
0 to NM2
0
0
R2(2)
0 to NM3
0
1
R3; if PR = 1X
0 to NM4
1
1
R4; if PR = 11 or 00
Notes
1. X = don’t care.
2. When the fractional accumulator overflows.
The total division ratio from prescaler to the phase detector expressions are given in Table 3.
Table 3
Total division from prescaler to phase detector expressions
CONDITION
EXPRESSION
N = (NM1 + 2) × R1 + NM2 × R2
PR = 01
N′ = (NM1 + 1) × R1 + (NM2 + 1) × R2; note 1
N = (NM1 + 2) × R1 + NM2 × R2 + (NM3 + 1) × R3
PR = 10
N′ = (NM1 + 1) × R1 + (NM2 + 1) × R2 + (NM3 + 1) × R3; note 1
N = (NM1 + 2) × R1 + NM2 × R2 + (NM3 + 1) × R3 + (NM4 + 1) × R4
PR = 11
N′ = (NM1 + 1) × R1 + (NM2 + 1) × R2 + (NM3 + 1) × R3 + (NM4 + 1) × R4; note 1
N = (NM1 + 2) × R1 + NM2 × R2 + (NM4 + 1) × R4
PR = 00
N′ = (NM1 + 1) × R1 + (NM2 + 1) × R2 + (NM4 + 1) × R4; note 1
Note
1. When the fractional accumulator overflows.
When the prescaler ratio is R2 = R1 + 1 the total division ratio N′ = N + 1.
Table 4
Modulus prescaler
BIT CAPACITY
PR
MODULUS PRESCALER
NM1
NM2
NM3
NM4
00
4
12
4
−
4
01
2
12
8
−
−
10
3
12
4
4
−
11
4
12
4
4
4
November 1994
9
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
The loading of the work registers NM1, NM2, NM3, NM4
and PR is synchronized with the state of the main counter,
to avoid extra phase disturbance when switching over to
another main divider ratio as is explained in Section “Serial
programming input”.
equation:
( V DDA – 0.5 ) – 237 I R
R = -----------------------------------------------------------IR
The current can be set to zero by connecting the
corresponding pin to VDDA.
At the completion of a main divider cycle, a main divider
output pulse is generated which will drive the main phase
comparator. Also the fractional accumulator is
incremented with NF. The accumulator works modulo Q.
Q is preset by the serial control bit FMOD to 8 when
FMOD = 1. Each time the accumulator overflows, the
feedback to the prescaler will select one cycle using
prescaler ratio R2 instead of R1.
Auxiliary output charge pumps
The auxiliary charge pumps on pin PHA are driven by the
auxiliary phase detector and the current value is
determined by the external resistor (Rext) at pin RA. The
active charge pump current is typically: |IPHA| = 8 × IRA.
As shown above, this will increase the overall division ratio
by 1 if R2 = R1 + 1. The mean division ratio over Q main
NF
divider cycles will then be: NQ = N + -------Q
Main output charge pumps and fractional
compensation currents
The main charge pumps on pins PHP and PHI are driven
by the main phase detector and the current value is
determined by the current at pin RN and via a number of
DACs which are driven by registers of the serial input. The
fractional compensation current is determined by the
current at pin RF, the contents of the fractional
accumulator FRD and a number of DACs driven by
registers from the serial input. The timing for the fractional
compensation is derived from the reference divider. The
current is on during 1 input reference cycle before and
1 cycle after the output signal to the phase comparator.
Figure 7 shows the waveforms for a typical case.
Programming a fraction means the prescaler with main
divider will divide by N or N + 1.
The output of the main divider will be modulated with a
fractional phase ripple. This phase ripple is proportional to
the contents of the fractional accumulator FRD, which is
used for fractional current compensation.
Phase detectors (Fig.6)
The auxiliary and main phase detectors are a 2 D-type
flip-flop phase and frequency detector. The flip-flops are
set by the negative edges of output signals of the dividers.
The reset inputs are activated when both flip-flops have
been set and when the reset enable signal is active (LOW).
Around zero phase error this has the effect of delaying the
reset for 1 reference input cycle. This avoids non-linearity
or dead band around zero phase error. The flip-flops drive
on-chip charge pumps. A pull-up current from the charge
pump indicates that the VCO frequency shall be increased
while a pull-down pulse indicates that the VCO frequency
shall be decreased.
When the serial input A word is loaded, the output circuits
are in the ‘speed-up mode’ as long as the STROBE is
HIGH, else the ‘normal mode’ is active.
NORMAL MODE
In the ‘normal mode’ the current output at PHP is:
IPHP(N) = Ipump10 + Icomp10.
Where:
CN × I RN
I pump10 = ----------------------- ; charge pump current.
29
Current settings
FRD × I RF
I comp10 = --------------------------; fractional compensation current.
128
The UMA1005T has 3 current setting pins RA, RN and RF.
The active charge pump currents and the fractional
compensation currents are linearly dependent on the
current in the current setting pins. This current IR can be
set by an external resistor to be connected between the
current setting pin (pin 9) and VSS. The typical value for R
(current setting resistor) can be calculated with the
November 1994
UMA1005T
In ‘normal mode’ the current at output PHI is zero.
10
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
handbook, full pagewidth
L
‘1’
INR
REFERENCE
DIVIDER
R
D
Q
C
VDDA
R
P
P-type
charge pump
R
AUXILIARY
AND MAIN
DIVIDER
‘1’
X
D
PH
C
Q
N-type
charge pump
N
V SSA
INR
L
R
X
P
N
MBE124
PH
Fig.6 Phase detector structure with timing.
November 1994
11
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
SPEED-UP MODE
In ‘speed-up mode’ the current in output PHP is:
IPHP(S) = IPHP(N) + Ipump11 + Icomp11.
Where:
Ipump11 = Ipump10 × 2(CL + 1); charge pump current.
Icomp11 = Icomp10 × 2(CL + 1); fractional compensation
current.
In ‘speed-up mode’ the current in output PHI is:
IPHI(S) = Ipump21 + Icomp21.
Where:
Ipump21 = Ipump11 × CK; charge pump current.
Icomp21 = Icomp11 × CK; fractional compensation current.
Figure 7 shows that for a proper fractional compensation
the area of the fractional compensation current pulse must
be equal to the area of the charge pump ripple output. This
means that the current setting on the inputs RN and RF
I RN
29 × Q × f VCO
must have following ratio: ------- = ------------------------------------------------ .
I RF
64 × CN × f i ( max ) 2
Where:
Q = fractional-N modulus.
fVCO = fi(max)1 × N; input frequency of the prescaler.
fi(max)1 = maximum input frequency of the main divider
(pins INM1 and INM2).
fi(max)2 = maximum input frequency of the reference
divider (pin INR).
Lock detect
The output LOCK is HIGH when the auxiliary phase
detector and the main phase detector indicate a lock
condition. The lock condition is defined as a phase
difference of less than ±1 cycle on the reference input INR.
The lock condition is also fulfilled when the relative counter
is disabled (EM = 0 or EA = 0 respectively) for the main or
auxiliary counter respectively.
November 1994
12
UMA1005T
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
handbook, full pagewidth INR
INM
N
N
N 1
N
N 1
detector output
2
contents
accumulator
4
1
3
0
fractional
compensation
current
pulse-width
modulation
mA
t1
outputs
PHP and PHI
µA
MBE125
pulse-level
modulation
Fig.7 Waveforms for NF = 2 and fraction = 0.4.
November 1994
t2
13
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDDD
digital supply voltage
−0.5
6.5
V
VDDA
analog supply voltage
−0.5
6.5
V
VI
voltage on any input
−0.5
VDD + 0.5 V
In
DC current into any input or output
−10
+10
mA
Ptot
total power dissipation
−
25
mW
Tstg
storage temperature
−65
+150
°C
Tamb
operating ambient temperature
−40
+70
°C
DC CHARACTERISTICS
VDDD = VDDA = 2.9 to 5.5 V; Tamb = −40 to +70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
IDDD(stb)
digital standby supply
current
EM = EA = 0; inputs on
VDD or 0
−
−
5
µA
IDDD
operating digital supply
current
note 1
−
−
5
mA
IDDA(stb)
analog standby supply
current
VRA = VDDA; VRF = VDDA;
VRN = VDDA
−
−
10
µA
IDDA
operating analog supply
current
note 1
−
−
0.6
mA
Digital inputs CLK, DATA and STROBE
VIH
HIGH level input voltage
0.7VDD
−
VDD
V
VIL
LOW level input voltage
0
−
0.3VDD
V
Digital outputs FB1, FB2 and LOCK
VOL
LOW level output voltage
IO = 2 mA; note 2
−
−
0.4
V
VOH
HIGH level output voltage
IO = −2 mA; note 2
VDD − 0.4
−
−
V
IRA = −62.5 µA;
VPHA = 1⁄2VDD; note 2
400
500
600
µA
IRA = −25 µA; VPHA = 1⁄2VDD
160
200
240
µA
Charge pump PHA
IPHA
output current
∆I PHA
--------------I PHA
relative output current
variation
IRA = −62.5 µA;
notes 2 and 3
−
2
6
%
∆IPHA M
output current matching
IRA = −62.5 µA;
VPHA = 1⁄2VDD;
notes 2 and 4
−
−
±50
µA
November 1994
14
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
SYMBOL
PARAMETER
UMA1005T
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Charge pump PHP; normal mode (notes 5, 6 and 7); VRF = VDD
IPHP(N)
∆IPHP(N)
output current
relative output current
variation
∆IPHP(N M) output current matching
IRN = −62.5 µA;
VPHP = 1⁄2VDD; note 2
440
550
660
µA
IRN = −25 µA; VPHP = 1⁄2VDD
175
220
265
µA
IRN = −62.5 µA; note 3
−
2
6
%
IRN = −62.5 µA;
VPHP = 1⁄2VDD;
notes 2 and 4
−
−
±50
µA
IRN = −62.5 µA;
VPHP = 1⁄2VDD; note 2
2.20
2.75
3.30
mA
IRN = −25 µA; VPHP = 1⁄2VDD
0.85
1.1
1.35
mA
Charge pump PHP; speed-up mode (notes 5, 6 and 8); VRF = VDD
IPHP(S)
output current
∆IPHP(S)
relative output current
variation
IRN = −62.5 µA;
notes 2 and 3
−
2
6
%
∆IPHP(S M)
output current matching
IRN = −62.5 µA;
VPHP = 1⁄2VDD;
notes 2 and 4
−
−
±250
µA
IRN = −62.5 µA;
VPHI = 1⁄2VDD; note 2
4.4
5.5
6.6
mA
IRN = −25 µA; VPHI = 1⁄2VDD
1.75
2.2
2.65
mA
Charge pump PHI; speed-up mode (notes 5, 6 and 9); VRF = VDD
IPHI(S)
output current
∆IPHI(S)
relative output current
variation
IRN = −62.5 µA;
notes 2 and 3
−
2
8
%
∆IPHI(S M)
output current matching
IRN = −62.5 µA;
−
VPHI = 1⁄2VDD; notes 2 and 4
−
±500
µA
Fractional compensation PHP; normal mode (notes 5, 10 and 11); VRN = VDD; VPHP = 1⁄2VDD
IPHP(F N)
fractional compensation
output current PHP as a
function of FRD
IRF = −62.5 µA;
FRD = 1 to 7;
notes 2 and 12
−675
−500
−325
nA
IRF = −25 µA; FRD = 1 to 7;
note 12
−270
−200
−130
nA
Fractional compensation PHP; speed-up mode (notes 5, 11 and 13); VRN = VDD; VPHP = 1⁄2VDD
IPHP(F S)
fractional compensation
output current PHP as a
function of FRD
November 1994
IRN = −62.5 µA;
FRD = 1 to 7;
notes 2 and 12
−3.35
−2.50
−1.65
µA
IRN = −25 µA; FRD = 1 to 7;
note 12
−1.35
−1.00
−0.65
µA
15
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
SYMBOL
PARAMETER
UMA1005T
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Fractional compensation PHI; speed-up mode (notes 5, 11 and 14); VRN = VDD; VPHP = 1⁄2VDD
IPHI(F)
fractional compensation
output current PHI as a
function of FRD
IRN = −62.5 µA;
FRD = 1 to 7;
notes 2 and 12
−5.4
−4.0
−2.6
µA
IRN = −25 µA; FRD = 1 to 7;
note 12
−2.15
−1.60
−1.05
µA
Charge pump leakage currents; charge pump not active
IPHP(LO)
output leakage current PHP normal mode;
VPHP = 0.7 to VDDA − 0.8 V
note 5
−
10
750
nA
IPHI(LO)
output leakage current PHI
normal mode;
VPHI = 0.7 to VDDA − 0.8 V
note 5
−
10
100
nA
IPHA(LO)
output leakage current PHA VPHA = 0.7 to VDDA − 0.8 V
−
10
750
nA
Notes
1. Operational conditions:
a) Main and auxiliary divider enabled (EM = EA = 1).
b) NA = 125.
c) NR = 125.
d) NM1 = 60.
e) NM2 = 63.
f) fi(max)1 = fi(max)2 = 15 MHz.
g) fi(max)3 = 60 MHz.
h) Lock condition.
i) Normal mode; note 5
j) IRN = IRF = IRA = 25 µA.
k) CN = 255.
l) PA = 0.
2. Limited supply voltage range 4.5 to 5.5 V.
3. The relative output current variation is defined as:
I2 – I1
∆I O
--------- = 2 × ------------------ ; with V1 = 0.7 V; V2 = VDD − 0.8 V (see Fig.8).
I2 + I1
IO
4. The output current matching is measured when both (positive and negative current) sections of the output charge
pumps are on.
5. When a serial ‘A’ word is programmed, the main charge pumps on PHP and PHI are in the ‘speed-up mode’ as long
as STROBE = HIGH, otherwise the main charge pumps are in the ‘normal mode’.
6. Monotonicity is guaranteed with CN = 0 to 255.
CN
7. Typical output current: I PHP(N) = – I RN × --------- ; specification condition: CN = 255.
29
November 1994
16
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
( CL + 1 )
2
+1
8. Typical output current: I PHP(S) = – I RN × CN × ------------------------------- ; specification conditions:
29
a) CN = 255; CL = 1 or,
b) CN = 75; CL = 3.
9. Typical output current: I PHI = – I RN × CN × 2
( CL + 1 )
CK
× -------- ; specification conditions:
29
a) CN = 160; CL = 3; CK = 1 or,
b) CN = 160; CL = 2; CK = 2 or,
c) CN = 160; CL = 1; CK = 4 or,
d) CN = 160; CL = 0; CK = 8.
FRD
10. Typical fractional compensation output current: I PHP(F N) = I RF × ------------- ; specification condition: FRD = 1 to 7.
128
11. The compensation current specified does not include the leakage current of this output.
12. FRD is the value of the 3-bit fractional accumulator.
( CL + 1 )
2
+1
13. Typical fractional compensation output current: I PHP(F S) = I RF × FRD × ------------------------------- ; specification conditions:
128
FRD = 1 to 7; CL = 1.
14. Typical fractional compensation output current: I PHI(F) = I RF × FRD × 2
a) FRD = 1 to 7; CL = 1; CK = 2 or,
b) FRD = 1 to 7; CL = 2; CK = 1.
November 1994
17
( CL + 1 )
CK
× ---------- ; specification conditions:
128
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
handbook, full pagewidth
UMA1005T
Io
I2
I1
V1
V2
Vo
I2
I1
MBE126
Fig.8 Relative output current variation.
AC CHARACTERISTICS
VDDD = VDDA = 2.9 to 5.5 V; Tamb = −40 to +70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Main divider (inputs INM1 and INM2)
fi(max)1
maximum input frequency
note 1
10
−
−
MHz
30
−
−
MHz
∆VINM(p-p)
differential input signal
amplitude VINM1 − VINM2
(peak-to-peak value)
600
−
−
mV
VCM
common mode range for
VINM1 and VINM2
1
−
VDD − 1
V
tpd
propagation delay time
from INM1 and INM2 to FB1
and FB2
−
−
60
ns
−
18
30
ns
35 : 65
−
65 : 35
resistive; note 2
5
−
−
kΩ
capacitive; note 2
−
−
5
pF
msr
mark-to-space ratio for
differential input signals
Zi(min)
minimum input impedance
November 1994
note 1
18
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
SYMBOL
PARAMETER
UMA1005T
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Reference divider (input INR)
fi(max)2
maximum input frequency
note 1
Vi(p-p)
input signal amplitude
AC coupled (peak-to-peak
value)
Zi(min)
minimum input impedance
15
−
−
MHz
30
−
−
MHz
300
−
−
mV
resistive; note 2
5
−
−
kΩ
capacitive; note 2
−
−
5
pF
Auxiliary divider (input INA)
fi(max)3
maximum input frequency
Vi(p-p)
input signal amplitude AC
coupled (peak-to-peak
value)
Zi(min)
minimum input impedance
prescaler enabled; PA = 0
35
−
−
MHz
prescaler enabled; PA = 0;
note 1
90
−
−
MHz
prescaler disabled; PA = 1
15
−
−
MHz
prescaler disabled; PA = 1;
note 1
30
−
−
MHz
300
−
−
mV
resistive; note 2
5
−
−
kΩ
capacitive; note 2
−
−
5
pF
Serial interface (inputs DATA, CLOCK and STROBE); see Fig.3
fclk
clock frequency
−
−
10
MHz
tHC
clock HIGH time
30
−
−
ns
tLC
clock LOW time
30
−
−
ns
tsuDA
DATA set-up time
30
−
−
ns
thDA
DATA hold time
30
−
−
ns
tsuST
STROBE set-up time
30
−
−
ns
thST
STROBE hold time
30
−
−
ns
Notes
1. Limited supply voltage range 4.5 to 5.5 V.
2. Periodically sampled; not 100% tested.
November 1994
19
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
PACKAGE OUTLINE
6.75
6.40
handbook, full pagewidth
4.5
4.3
6.6
6.2
0.1 S
S
A
0.6 (4x)
0.2
20
11
1.4
1.2
0.6
0.5
0.15
0
pin 1
index
1
0.8
0.3
10
detail A
0.65
0.32
0.20
1.5
1.2
0.20
0.13
0 to 10o
MBC237 - 1
0.13 M
(20x)
Dimensions in mm.
Fig.9 Plastic shrink small outline package; 20 leads; body width 4.4 mm (SSOP20; SOT266-1).
November 1994
20
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
SOLDERING
Plastic small-outline packages
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
BY WAVE
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
November 1994
21
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
NOTES
November 1994
22
UMA1005T
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
NOTES
November 1994
23
UMA1005T
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SCD35
© Philips Electronics N.V. 1994
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Document order number:
Date of release: November 1994
9397 743 40011