AN11557 BGU8052 1900MHz LNA improved IRL Rev. 1 — 3 September 2015 1900 MHz LNA Document information Info Content Keywords BGU8052, 1900 MHz, LNA, BTS Abstract This application note provides circuit schematic, layout, BOM and typical evaluation board performance of a 1900 MHz LNA with the use of the BGU8052. The design has been tuned for better input return loss. For the 1500 to 2700 MHz wireless communication bands. The performance is given at 3.3 and 5 V supply supporting small cell respectively large cell applications. Ordering info Demonstrator boards OM7893, 12NC: 9340 690 55598 Contact information For more information, please visit: http://www.nxp.com AN11557 NXP Semiconductors 1900 MHz LNA Revision history Rev Date Description 1 First publication 20150903 Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] AN11557 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 2 of 22 AN11557 NXP Semiconductors 1900 MHz LNA 1. Introduction NXPs semiconductors BGU805x series is a family of integrated low noise amplifiers for the 300 MHz to 6000 MHz range. The series consists of the: • BGU8051 recommended for 300 MHz - 1500 MHz • BGU8052 recommended for 1500 MHz – 2700 MHz • BGU8053 recommended for 2500 MHz – 6000 MHz The BGU805X series is a low noise high linearity amplifier family intended for wireless infrastructure applications like BTS, RRH, small cells, but can also be used in other general low noise applications, e.g. active antennas for automotive. Being manufactured in NXPs high performance QUBiC RF Gen 8 SiGe:C technology, the BGU805X combines high gain, ultra-low noise and high linearity with the process stability and ruggedness which are the characteristics of SiGe:C technology. BGU805X series comes in the industry standard 2 x 2 x 0.75 mm 8 terminal plastic thin small outline package HVSON8 (SOT1327). The LNA is ESD protected on all terminals. The 3 types can all use the same PCB layout topology. This enables design in simplicity using one PCB layout for designing LNA’s covering the frequency range from 300MHz to 6000 MHz with one single PCB layout design. In application note AN11416 the use of the BGU8052 is describes as a wideband LNA for the 1500 to 2700 MHz range with compromised input return loss. In this application note a design procedure is described to improve the input return loss for better filter integration, without NF degradation. Design can be suited for the wireless communication bands from 1700 to 2700 MHz. In Fig 1, the evaluation board described in this application note is shown. a. Front side Fig 1. b. Back side BGU8052 1900 MHz evaluation board AN11557 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 3 of 22 AN11557 NXP Semiconductors 1900 MHz LNA 2. Product description The BGU8052 is a fully integrated low noise amplifier with integrated bias circuit. The MMIC is internally matched to 50 Ω. The BGU8052 also features an integrated shutdown circuit to enable fast turn on/off settling time, enabling switched (time domain duplexing TDD) applications. The device bias current can be set by the value of an external bias resistor RBIAS, which connects the supply voltage to the VBIAS pin, or by an external control voltage applied directly to VBIAS pin 1. This adjustable bias current gives flexibility in biasing the device for the optimum performance on NF or linearity. This feature can be useful in case more than one BGU8052 are cascaded. This bias resistor value changes the bias current directly which can be used to trade of linearity for power saving in battery operated applications. The BGU8052 key features and benefits at 1900MHz are; Low noise performance: NF = 0.53 dB High linearity performance: IP3O = 35 dBm High output power at 1dB gain compression PL1dB = 19 dBm High input return loss RLin = 25 dB High out return loss RLout = 15dB Unconditionally stable up to 20 GHz Max RF input power of +20 dBm ESD protection on all pins Fast turn on and off to support TDD system. Fig 2. BGU8052 Pin description In Fig 2 the pin out of the BGU8052 is given, the n.c. and i.c pin are recommended to connect to ground, which is the case on the evaluation boards. 3. 1900 MHz LNA improved input return loss evaluation board. The 1900MHz improved return-loss evaluation board simplifies the RF evaluation of the BGU8052. The EVB enables testing the device RF performance and requires no additional support circuitry. The EVB is fabricated on a 35 x 20 x 1mm 4 layer PCB that uses 0.2 mm (8 mill) R4003C for the RF performance. The board is fully assembled with AN11557 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 4 of 22 AN11557 NXP Semiconductors 1900 MHz LNA the BGU8052, including the external components. The board is supplied with two SMA connectors to connect input and output to the RF test equipment. The EVB is also enabled with the possibility to evaluate the BGU8052 at different bias currents. 3.1 Application circuit The BGU8052 has been characterized for S-parameter and Noise-parameters at different bias settings. This data can be downloaded from NXPs website as a zip file, BGU8052_S_N_par.zip. The S2P files you can find in this zip file have been used as a small signal model to design this 1900MHz LNA. The high-pass matching structure that is created by means of L2 and C8, improves the input return loss for better filter integration. Additionally it has the advantage that it cuts of the low frequency gain which increases the stability. The application board circuit diagram that is implemented on the EVB is shown in Fig 3 C5 GND VCT RL(sd) VCC VBIAS X3 C6 R1 Rbias R2 RFin C1 C8 L2 L1 1 8 2 7 3 6 4 5 C4 RFout C2 C7 BGU805x Fig 3. BGU8052 1900 MHz imp RL application board circuit diagram As already indicated the bias current of the BGU8052 can be set by the value RBIAS. The evaluation boards are supplied with a 5.1 kΩ bias resistor (ICC = 48 mA +/-5 mA @ VCC=5V). If however it is required to evaluate the BGU8052 at different bias currents, resistor R1 which is 0 Ω can be removed and an external control voltage can be applied to VBIAS (Vb pin) on the bias header X3, see Fig 3. By applying this separate bias voltage on the VBIAS pin of the bias header X3, the ICC current can be swept without changing RBIAS. With bias voltage window from 1.5 to 6 V on VBIAS while keeping the VCC pin on 5 V, ICC can be varied from 5-60 mA. In Fig 4 the relation between Icc and RBIAS at VCC = 5 V as well as the relation between ICC and VBIAS with RBIAS = 5k1 is shown. In Fig 4 you can also find the bias resistor values when applying the BGU8052 at lower supply voltages. Which indicates the BGU805x series can also be biased with lower voltage e.g. 3.3V which makes it excellent suitable for small cells. In paragraph 4.1 typical performance of the LNA @ 3.3V 48mA is also included. AN11557 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 5 of 22 AN11557 NXP Semiconductors 1900 MHz LNA (1) Blue curve corresponds with the left Y axis and the lower X axis. Giving the ICC versus the value of RBIAS. (2) Red curve corresponds with the right Y axis and the upper X axis. Giving the ICC versus the voltage applied to the Vb pin with RBIAS = 5k1 in place. Fig 4. Relation of ICC with RBIAS and Vb 3.2 PCB Layout information AN11557 Application note • A good PCB layout is an essential part of an RF circuit design. The LNA evaluation board can serve as a guideline for laying out a board using the BGU8052. • The evaluation board uses micro strip coplanar ground structures for controlled impedance lines for the high frequency input and output lines. • VCC is decoupled by C4 and C6 decoupling capacitors, C4 should be located as close as possible to the device, to avoid AC leakage via the bias lines. For long bias lines it may be necessary to add decoupling capacitors along the line further away from the device. • The self-resonance frequency of inductor L1 should be chosen above frequency band of interest for good choking. In this case the Murata LQW15 series has been used. • Inductor L2 and capacitor C8 are creating the high pass matching structure and are in that sense critical. • C1 and C2 are DC blocking capacitors, and not critical, C1 might not be necessary if a previous stage is not driving DC current. If C1 however is used and it should be <100pF for short turn on/off time. • Proper grounding of the GND pins is also essential for good RF performance. Either connect the GND pins directly to the ground plane or through vias, or do All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 6 of 22 AN11557 NXP Semiconductors 1900 MHz LNA 2 both, which is recommended. The layout and component placement of the BGU8052 evaluation board is given in Fig 5 R1 C6 Rb R2 C5 L1 C8 C4 IC1 C2 C7 C1 L2 C3 Fig 5. BGU8052 1900MHz evaluation board component placement 3.2.1 PCB stack and recommended footprint. The PCB material used to implement the LNA is a 0.2 mm (8 mil) RO4003C low loss printed circuit board which is merged to a 0.51 mm (20 mil) prepreg and a 0.254 mm (10 mil) FR4 layer for mechanical stiffness. See Fig 6a The official drawing of the recommended footprint can be found via following link, sot1327-1_fr.pdf. If micro strip coplanar PCB technology is used it is recommended to use at least 4 ground-via holes of 300um this is also used on the EVBs as shown in Fig 6b. AN11557 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 7 of 22 AN11557 NXP Semiconductors 1900 MHz LNA Through via 35um (1 oz.) Copper + 0.3um gold plating RO4003C, 0.2 mm (8 mil) 35um (1 oz.) Copper Prepreg 0.51 mm (20 mil) 35um (1 oz.) Copper FR4, 0.254mm (10 mil) 35um (1 oz.) Copper + 0.3um gold plating c. Cross section of the PCB Layer stack. Fig 6. d. Recommended footprint. PCB stack and footprint information. 3.3 Bill of materials Table 1 gives the bill of materials as is used on the EVB. Table 1. BOM Designator Description Footprint Value Supplier Name/type Comment/function IC1 BGU8052 PCB 20x35x1mm C1,C2 Capacitor 0402 100pF KOVO RO4003C PCB v 1.3 Various DC block C4 Capacitor 0402 1nF Various RF decoupling C5 Capacitor 0806 4.7uF Various Optional C6 Capacitor 0806 4.7uF Various LF Decoupling C7 Capacitor 0402 10pF Various Decoupling C8 Capacitor 0402 3.0pF Various Input match L1 Inductor 0402 15nH Murata LQW15 Bias choke/Output match L2 Inductor 0402 5.1nH Murata LQW15 Input match R1 Resistor 0402 0Ohm Various R2 Resistor 0402 10Ohm Various stability Rbias Resistor 0402 5k1 Various Bias setting X1,X2 SMA RF Johnson, End launch RF connections connector SMA 142-0701-841 DC header Molex, PCB header, right angle, 1 row 4 way X3 AN11557 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 DC connections © NXP B.V. 2015. All rights reserved. 8 of 22 AN11557 NXP Semiconductors 1900 MHz LNA 4. Measurement results 4.1 Typical board performance The values given in Table 2 are typical values of >25 boards measured. Table 2. Typical board performance using the BOM given in Table 1 F=1900MHz; Vcc=5V;Tamb=25°C; input and output 50Ω;Rbias=5.1kΩ. Symbol Parameter Conditions Typ Typ Unit VCC Supply voltage 5 3.3 V Icc Supply current 48.2 48.9 mA Gass Associated gain 18.4 18.2 dB NF Noise figure 0.53 0.59 dB PL((1dB) Output power at 1dB gain compression 19.1 15.6 dBm IP3O Output third-order intercept point 35 33 dBm RLin Input return loss 25.4 26.0 dB RLout Output return loss 15.3 15.7 dB ISL Isolation 23.1 23.1 dB Ts(pon) Power-on settling time Pi = -20dBm; SHDN(pin 6) from High to Low 100 100 ns Ts(poff) Power-off settling time Pi = -20dBm; SHDN(pin 6) from Low to High 40 40 μs [1] [1] 2-tone; tone spacing = 1MHz; Pi = -15dBm per tone Board losses have been de-embedded. AN11557 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 9 of 22 AN11557 NXP Semiconductors 1900 MHz LNA 4.2 S_Parameters The measured S-parameters are given in Fig 7. For the measurements, a typical BGU8052 1900 MHz EVB is used. All the S-parameter measurements have been carried out using the setup in Fig 13a VCC = 5 V; TAMB = 25 °C; ICC = 48 mA Fig 7. AN11557 Application note BGU8052 1900 MHz LNA S-parameters All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 10 of 22 AN11557 NXP Semiconductors 1900 MHz LNA 4.3 1dB Gain compression point. The measured Gain versus input power is given in Fig 8 for the measurements, a typical BGU8052 1900 MHz EVB is used. All the P1dB measurements have been carried out using the setup in Fig 13a. Trc1 S21 dB Mag 1 dB / Ref 15 dB Ca? PCal 1 •Trac Stat: Trc1 S21 0.9 dBm Cmp In: 18.3 dBm Cmp Out: S21 19 18 Cmp 17 16 15 14 13 12 11 Ch1 Base Pwr Start -12 dBm Base Freq 1.9 GHz Stop 8 dBm (1) VCC = 5V; TAMB = 25 °C; ICC = 48 mA (2) Pi1dB = 0.9 dBm; PL1dB = 18.3 dBm Fig 8. AN11557 Application note BGU8052 1900 MHz LNA 1dB gain compression All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 11 of 22 AN11557 NXP Semiconductors 1900 MHz LNA 4.4 Noise figure The measured noise figure are given in Fig 9 . For the measurements, a typical BGU8052 1900MHz EVB is used. The noise figure measurement have been carried out using the setup in Fig 13b VCC = 5 V; TAMB = 25 °C; ICC = 48 mA (1) Measured at the evaluation boards SMA connectors PCB losses are not de-embedded. Fig 9. AN11557 Application note BGU8052 1900 MHz LNA typical noise figure performance. All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 12 of 22 AN11557 NXP Semiconductors 1900 MHz LNA 4.5 3rd order intercept point, output referred The evaluation board provided in the customer evaluation kit is automatically measured on linearity using the set-up shown in Fig 13a. Alternatively the setup given in Fig 13c can be used, which is done for the spectrum plot in Fig 10. For the measurements, a typical BGU8052 1900 MHz EVB is used. *RBW 20 kHz *VBW 300 Hz Ref 5 dBm *Att 20 dB 1 SWT 680 ms 2 0 -10 1 AP CLRWR -20 -30 Marker 2 [T1 ] 1.38 dBm 1.900996795 GHz TOI 40.67 Marker 1 [T1 ] 1.31 1.899995192 Marker 3 [T1 ] -76.82 1.898993590 Marker 4 [T1 ] -77.83 1.901998397 dBm dBm GHz A dBm GHz dBm GHz -40 -50 3DB -60 -70 3 4 -80 -90 Center 1.9005 GHz 500 kHz/ Span 5 MHz (1) IP3O LSB = (76.82+1.31)/2+1.31 = 40.4 dBm; IP3O USB = (77.28+1.35)/2+1.35 = 40.7 dBm (2) IP3i = IP3O -Gain = 40.5 - 18.4 = 22.1 dBm Fig 10. BGU8052 1900 MHz LNA Typical OIP3 spectrum AN11557 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 13 of 22 AN11557 NXP Semiconductors 1900 MHz LNA 4.6 Power on/off settling time. The power on/off settling time curves shown in Fig 11 and Fig 12 are being measured using the setup shown in Fig 13d and described in paragraph 5.5. a. Ton 104 ns b. Toff 43 ns Yellow curve SHDN control voltage Blue curve output of the detector diode Fig 11. Power on/off settling time using the SHDN pin(6) a. Ton 1.24 µs b. Toff 452 ns Yellow curve VBIAS control voltage Blue curve output of the detector diode Fig 12. Power on/off settling time using the VBIAS pin(1) AN11557 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 14 of 22 AN11557 NXP Semiconductors 1900 MHz LNA Table 3. Typical power on/off settling time Measured on BGU8052 1900MHz EVB. Control pin Power on Power off Units SHDN 0.104 0.04 µs VBIAS 1.2 0.45 µs 5. Measurement methods and setups. 5.1 Required Measurement Equipment In order to measure the evaluation board, the following is necessary: 2 (channel) DC Power Supply up to 100 mA at 5 V, to set VCC and eventual Vbias. Two RF signal generators capable of generating RF signals up to 2 GHz An RF spectrum analyzer that covers at least the operating frequencies and a few of the harmonics. Up to 6 GHz should be sufficient. A network analyzer for measuring gain, return loss and reverse isolation Noise figure analyser and noise source Proper RF cables with male SMA connectors. 5.2 Connection and setup The typical values shown in this report have been measured on the fully automated test setups shown in Fig 13 Please follow the steps below for a step-by-step guide to operate the LNA evaluation board and testing the device functions. 1. Connect the DC power supply to the VCC and GND terminals. Set the power supply to 5V 2. Connect the RF signal generator and the spectrum analyzer to the RF input and the RF output of the evaluation board, respectively. Do not turn on the RF output of the signal generator yet, set it to approximately -30 dBm output power at the center frequency of the wanted frequency band and set the spectrum analyzer at the same center frequency and a reference level of 0 dBm. 3. Turn on the DC power supply and it should read approximately 48 mA. 4. Enable the RF output of the generator: The spectrum analyzer displays a tone around -11.5 dBm. 5. Instead of using a signal generator and spectrum analyzer one can also use a network analyzer in order to measure gain as well as in- and output return loss and P1dB (see Fig 13a) 6. For noise figure evaluation, either a noise figure analyzer or a spectrum analyzer with noise option can be used. The use of a 5 dB noise source, like the Agilent 364B, is recommended. When measuring the noise figure of the evaluation board, any kind of adaptors, cables etc. between the noise source and the evaluation board should be minimized, since this affects the noise figure (see Fig 13 b). AN11557 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 15 of 22 AN11557 NXP Semiconductors 1900 MHz LNA ZVA24 Power supply (TTi QL355TD) Combiner Vcc(5V) GND Vbias (var) RF_out RF_in BGU805x LNA EVB a. S_ parameter; P1dB and IP3O test setup b. Noise figure test setup SMA100A SMA100A Agilent 33250A Function / Arbitrary Waveform Generator SMA100A Power supply (TTi QL355TD) FSU 6dB attenuators for better generator isolation Power supply (TTi QL355TD) Hameg Oscilloscope HMO 3524 Vcc(5V) Vshdn(2V) Combiner Vcc(5V) GND GND Vbias (var) CH1:50Ω input Z (trigger) RF_in RF_out RF_out RF_in BGU805x LNA EVB CH2:50Ω input Z Agilent 0.01-18GHz Schottky Detector Model 8473B BGU805x LNA EVB c. Third order intercept point test setup d. Power on/off settling time test setup Fig 13. Characterization measurements setups. 5.3 Noise figure measurement setup In Fig 13b the noise figure measurement set-up is shown, this is intended as a guide only, substitutions can be made. For sub 1 dB noise figure levels like the BGU8052 has it is recommended to perform the noise-measurements in a Faraday’s cage or at least put the DUT in a shielded environment. This is recommended to avoid any interference of cellular frequencies that are in the same frequency range. A spectrum analyzer with noise option. A 5dB ENR noise source was used. To achieve the lowest possible setup noise figure an external pre amplifier is also recommended. The Noise figure value in AN11557 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 16 of 22 AN11557 NXP Semiconductors 1900 MHz LNA Fig 9 is the value measured at the evaluation board SMA connectors. Correcting for the connector and PCB loss will end up in 0.1dB lower noise figure. 5.4 Third order intercept The bias choke L1 on the application board is determined empirically in order to get the best OIP3 as well as keeping good output return loss. The low ohmic source impedance provided by the matching circuit L1 and C8 also improves the linearity. In [1] the effect on linearity of SiGe BiCMOS BJTs and the advantage of using low source impedances at the low frequencies of the 2nd order mixing terms is described. When measuring the high OIP3 values it is essential check the capabilities of the used measurement equipment. Be aware that the measurement set-up itself is not generating dominating IM3 levels. Advised is to do a THRU measurement without a DUT first. 5.5 Power on/off settling time When using the BGU8052 in TDD applications power on/off switching can be controlled via both the SHDN pin as well as the Vbias pin. It is preferred to use the SHDN pin. Both pins require less than 1 mA driving current which means they are CMOS compatible. This enables LNA switching directly via a micro controller. There is an alternative way of switching the LNA, by switching the overall supply. In this case the switching time is limited by the time constant created by C6 x RBIAS. So additional to lowering the value of C1 the decoupling capacitor C6 (4.7 µF) also has to be decreased to values <10 nF. Please note that lowering the low frequency decoupling capacitor makes the circuit more sensitive to VCC modulation of the 2nd order mixing products. The setup used to measure the power on/off settling time is shown in Fig 13d. This can be used as a guidance to determine the power on/off settling time. The waveform generator is used to provide the control voltage on either the SHDN pin (6) or the VBIAS pin (1). Set the waveform generator Agilent 33250 to square mode and the output amplitude to required voltage for the used control pin, with 50 Ω output impedance. Set the RF signal generator output level to -25dBm at 450MHz and increase its level until the peak detector output level is about 5mV on 1mV/division, the signal generator RF output level is approximately -20 dBm. A peak detector is needed to detect the high frequency AC signal at the output of the DUT, representing it as a DC voltage equal to the peak level of the applied AC signal. It is very important to keep the cables as short as possible at input and output of the LNA so the propagation delay difference on cables between the two channels is minimized. It is also critical to set the oscilloscope input impedance to 50 Ω on channel 2 so the diode detector can discharge quickly to avoid a false result on the Turn OFF time testing. AN11557 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 17 of 22 AN11557 NXP Semiconductors 1900 MHz LNA 6. References [1] Vladimir Aparin, Lawrence E. Larson, “Linearization of monolithic LNAs Using LowFrequency Low-Impedance Input Termination”. IEEE 0-7 803-8 108-4/03 ©2003 7. Customer Evaluation Kit In the customer evaluation kit you will find; • One 1900MHz improved return loss EVB • 10 loose samples. a. b. Fig 14. BGU8052 1900 MHz imp RL customer evaluation KIT AN11557 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 18 of 22 AN11557 NXP Semiconductors 1900 MHz LNA 8. Legal information 8.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 8.2 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or AN11557 Application note customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Evaluation products — This product is provided on an “as is” and “with all faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of noninfringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. 8.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 19 of 22 AN11557 NXP Semiconductors 1900 MHz LNA 9. List of figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. BGU8052 1900 MHz evaluation board ............. 3 BGU8052 Pin description .................................. 4 BGU8052 1900 MHz imp RL application board circuit diagram................................................... 5 Relation of ICC with RBIAS and Vb ....................... 6 BGU8052 1900MHz evaluation board component placement....................................... 7 PCB stack and footprint information.................. 8 BGU8052 1900 MHz LNA S-parameters ........ 10 BGU8052 1900 MHz LNA 1dB gain compression.................................................... 11 BGU8052 1900 MHz LNA typical noise figure performance. ................................................... 12 BGU8052 1900 MHz LNA Typical OIP3 spectrum ......................................................... 13 Power on/off settling time using the SHDN pin(6)............................................................... 14 Power on/off settling time using the VBIAS pin(1) ........................................................................ 14 Characterization measurements setups.......... 16 BGU8052 1900 MHz imp RL customer evaluation KIT ................................................. 18 AN11557 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 20 of 22 AN11557 NXP Semiconductors 1900 MHz LNA 10. List of tables Table 1. Table 2. Table 3. BOM .................................................................. 8 Typical board performance using the BOM given in Table 1 .......................................................... 9 Typical power on/off settling time .................... 15 AN11557 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2015 © NXP B.V. 2015. All rights reserved. 21 of 22 AN11557 NXP Semiconductors 1900 MHz LNA 11. Contents 1. 2. 3. 3.1 3.2 3.2.1 3.3 4. 4.1 4.2 4.3 4.4 4.5 4.6 5. 5.1 5.2 5.3 5.4 5.5 6. 7. 8. 8.1 8.2 8.3 9. 10. 11. Introduction ......................................................... 3 Product description ............................................ 4 1900 MHz LNA improved input return loss evaluation board.................................................. 4 Application circuit ............................................... 5 PCB Layout information ..................................... 6 PCB stack and recommended footprint.............. 7 Bill of materials ................................................... 8 Measurement results .......................................... 9 Typical board performance................................. 9 S_Parameters .................................................. 10 1dB Gain compression point. ........................... 11 Noise figure ...................................................... 12 3rd order intercept point, output referred ........... 13 Power on/off settling time. ................................ 14 Measurement methods and setups. ................ 15 Required Measurement Equipment.................. 15 Connection and setup ...................................... 15 Noise figure measurement setup ..................... 16 Third order intercept ......................................... 17 Power on/off settling time ................................. 17 References ......................................................... 18 Customer Evaluation Kit ................................... 18 Legal information .............................................. 19 Definitions ........................................................ 19 Disclaimers....................................................... 19 Trademarks ...................................................... 19 List of figures..................................................... 20 List of tables ...................................................... 21 Contents ............................................................. 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in the section 'Legal information'. © NXP B.V. 2015. All rights reserved. For more information, visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 3 September 2015 Document identifier: AN11557