INTEGRATED CIRCUITS DATA SHEET 74LVCH32374A 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state Product specification File under Integrated Circuits, IC24 1999 Nov 24 Philips Semiconductors Product specification 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state 74LVCH32374A FEATURES DESCRIPTION • 5 V tolerant inputs/outputs for interfacing with 5 V logic The 74LVCH32374A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. • Wide supply voltage range from 1.2 to 3.6 V • CMOS low power consumption The inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, the outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 or 5 V environment. • MULTIBYTE flow-trough standard pin-out architecture • Low inductance multiple power and ground pins for minimum noise and ground bounce • Direct interface with TTL levels The 74LVCH32374A is a 32-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. The 74LVCH32374A consists of 4 sections of eight edge-triggered flip-flops. A clock (nCP) input and an output enable input (nOE) are provided per 8-bit section. • Bus hold on data inputs • Typical output ground bounce voltage: VOLP < 0.8 V at VCC = 3.3 V and Tamb = 25 °C • Typical output undershoot voltage: VOHV > 2 V at VCC = 3.3 V and Tamb = 25 °C • Power off disables outputs, permitting live insertion The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH nCP transition. • Packaged in plastic fine-pitch ball grid array package. When input nOE is LOW, the contents of the flip-flops are available at the outputs. When input nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. The 74LVCH32374A bus hold data input circuits eliminate the need for external pull-up resistors to hold unused inputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER CONDITIONS CL = 50 pF; VCC = 3.3 V TYPICAL UNIT tPHL/tPLH propagation delay nCP to nQn 3.8 ns fmax maximum clock frequency 150 MHz CI input capacitance 5.0 pF CPD power dissipation capacitance per buffer 30 pF VI = GND to VCC; note 1 Note 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; Σ (CL × VCC2 × fo) = sum of the outputs. 1999 Nov 24 2 Philips Semiconductors Product specification 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state 74LVCH32374A FUNCTION TABLE See note 1. INPUTS OUTPUTS nOE nCP nDn INTERNAL FLIP-FLOPS Load and read register L ↑ l L L L ↑ h H H Load register and disable outputs H ↑ l L Z H ↑ h H Z OPERATING MODE nQn Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH CP transition. ORDERING INFORMATION PACKAGE TYPE NUMBER 74LVCH32374AEC TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE −40 to +85 °C 96 LFBGA96 plastic SOT536-1 PINNING SYMBOL DESCRIPTION nDn data inputs nCP clock inputs nQn flip-flop outputs GND ground (0 V) nOE output enable inputs (active LOW) VCC DC supply voltage 1999 Nov 24 3 Philips Semiconductors Product specification 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state 74LVCH32374A MNA497 handbook, full pagewidth 6 1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D7 3D1 3D3 3D5 3D7 4D1 4D3 4D5 4D6 5 1D0 1D2 1D4 1D6 2D0 2D2 2D4 2D6 3D0 3D2 3D4 3D6 4D0 4D2 4D4 4D7 4 1CP GND VCC GND GND VCC GND 2CP 3CP GND VCC GND GND VCC GND 4CP 3 1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE 2 1Q0 1Q2 1Q4 1Q6 2Q0 2Q2 2Q4 2Q6 3Q0 3Q2 3Q4 3Q6 4Q0 4Q2 4Q4 4Q7 1 1Q1 1Q3 1Q5 1Q7 2Q1 2Q3 2Q5 2Q7 3Q1 3Q3 3Q5 3Q7 4Q1 4Q3 4Q5 4Q6 A B C D E F G H J K L M N P R T Fig.1 Pin configuration. handbook, full pagewidth 1D0 D Q 2D0 1Q0 CP D FF 1 2CP 1OE 2OE to 7 other channels D Q to 7 other channels 4D0 3Q0 CP D Q 4Q0 CP FF 17 FF 25 3CP 4CP 3OE 4OE to 7 other channels to 7 other channels Fig.2 Logic symbol. 1999 Nov 24 2Q0 FF 9 1CP 3D0 Q CP 4 MNA498 Philips Semiconductors Product specification 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state handbook, halfpage 74LVCH32374A VCC data input to internal circuit MNA473 Fig.3 Bus hold circuit. 1999 Nov 24 5 Philips Semiconductors Product specification 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state 74LVCH32374A RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER CONDITIONS UNIT MIN. VCC DC supply voltage VI DC input voltage VO DC output voltage maximum speed performance 2.7 low-voltage applications Tamb operating ambient temperature tr,tf (∆t/∆f) input rise and fall times MAX. 3.6 V 1.2 3.6 V 0 5.5 V HIGH or LOW state 0 VCC V 3-state 0 5.5 V see DC and AC characteristics per device −40 +85 °C VCC = 1.2 to 2.7 V 0 20 ns/V VCC = 2.7 to 3.6 V 0 10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. −0.5 MAX. VCC DC supply voltage VI DC input voltage note 1 −0.5 +6.5 V IIK DC input diode current VI < 0 − −50 mA IOK DC output diode current VO > VCC or VO < 0; note 1 − ±50 mA VO DC output voltage HIGH or LOW state; note 1 −0.5 VCC + 0.5 V 3-state; note 1 −0.5 +6.5 V IO DC output source or sink current VO = 0 to VCC − ±50 mA ICC, IGND DC VCC or GND current − ±100 mA Tstg storage temperature −65 +150 °C PD power dissipation per package − 1000 mW temperature range −40 to +85 °C; note 2 +6.5 UNIT Notes 1. The input and output voltage ratings may be exceeded, if the input and output current ratings are observed. 2. Above 70 °C the value of PD derates linearly with 1.8 mW/K. 1999 Nov 24 6 V Philips Semiconductors Product specification 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state 74LVCH32374A DC CHARACTERISTICS Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb (°C) TEST CONDITIONS SYMBOL OTHER VIH −40 to +85 PARAMETER HIGH-level input voltage VCC (V) − − V − − V − − GND V 2.7 to 3.6 − − 0.8 V 1.2 VOH VOL LOW-level input voltage HIGH-level output voltage LOW-level output voltage TYP.(1) MAX. MIN. VCC 2.7 to 3.6 2.0 VIL UNIT 1.2 VI = VIH or VIL IO = −12 mA 2.7 VCC − 0.5 − − V IO = −100 µA 3.0 VCC − 0.2 VCC − V IO = −18 mA 3.0 VCC − 0.6 − − V IO = −24 mA 3.0 VCC − 0.8 − − V IO = 12 mA 2.7 − − 0.40 V IO = 100 µA 3.0 − − 0.20 V IO = 24 mA VI = VIH or VIL 3.0 − − 0.55 V II input leakage current VI = 5.5 V or GND; note 2 3.6 − ±0.1 ±5 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 5.5 V or GND 3.6 − 0.1 ±5 µA Ioff power off leakage supply current VI or VO = 5.5 V 0.0 − 0.1 ±10 µA ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 − 0.1 40 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 0.6 V; IO = 0 2.7 to 3.6 − 5 500 µA IBHL bus hold LOW sustaining current VI = 0.8 V; notes 3, 4 and 5 3.0 75 − − µA IBHH bus hold HIGH sustaining current VI = 2.0 V; notes 3, 4 and 5 3.0 −75 − − µA IBHLO bus hold LOW overdrive current notes 3, 4 and 6 3.6 500 − − µA IBHHO bus hold HIGH overdrive current notes 3, 4 and 6 3.6 −500 − − µA Notes 1. All typical values are at VCC = 3.3 V and Tamb = 25 °C. 2. For bus hold parts the bus hold circuit is switched off when VI exceeds VCC allowing 5.5 V on the input terminal. 3. Valid for data inputs of bus hold parts (LVCH32-A) only. 4. For data inputs only; control inputs do not have a bus hold circuit. 5. The specified sustaining current at the data input holds the input below the specified VI level. 6. The specified overdrive current at the data input forces the data input to the opposite logic input level. 1999 Nov 24 7 Philips Semiconductors Product specification 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state 74LVCH32374A AC CHARACTERISTICS GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω. Tamb = −40 to +85 °C TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW propagation delay nCP to nQn see Figs 4 and 7 3-state output enable time nOE to nQn see Figs 6 and 7 3-state output disable time nOE to nQn see Figs 6 and 7 nCP pulse width HIGH see Figs 4 and 7 tsu set-up time nDn to nCP see Figs 5 and 7 th hold time nDn to nCP see Figs 5 and 7 fmax maximum clock frequency see Figs 4 and 7 VCC (V) MIN. TYP.(1) UNIT MAX. 2.7 1.5 − 6.4 ns 3.0 to 3.6 1.5 3.8 5.4 ns 2.7 1.5 − 6.6 ns 3.0 to 3.6 1.5 3.6 5.6 ns 2.7 1.5 − 6.5 ns 3.0 to 3.6 1.5 3.9 5.5 ns 2.7 3.0 − − ns 3.0 to 3.6 3.0 1.5 − ns 2.7 2.0 − − ns 3.0 to 3.6 1.9 0.3 − ns 2.7 1.5 − − ns 3.0 to 3.6 +1.1 −0.3 − ns 2.7 80 − − MHz 3.0 to 3.6 100 − − MHz Note 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. AC WAVEFORMS 1/fmax handbook, full pagewidth VI nCP input VM VM GND tW t PHL t PLH VOH VM nQn output VOL MNA499 VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. Fig.4 Clock (nCP) to output (nQn) propagation delays, the clock pulse width and the maximum clock frequency. 1999 Nov 24 8 Philips Semiconductors Product specification 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state 74LVCH32374A VI handbook, full pagewidth VM nCP input GND tsu tsu th th VI VM nDn input GND VOH VM nQn output VOL MNA500 VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. Fig.5 Set-up and hold times for inputs (nDn) to inputs (nCP). VI handbook, full pagewidth nOE input VM GND t PLZ t PZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs disabled outputs enabled MNA478 VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V. VX = VOL + 0.3 V at VCC ≥ 2.7 V; VX = VOL + 0.1 V at VCC < 2.7 V. VY = VOH − 0.3 V at VCC ≥ 2.7 V; VY = VOH − 0.1 V at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. Fig.6 3-state output enable and disable times. 1999 Nov 24 9 Philips Semiconductors Product specification 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state 74LVCH32374A S1 handbook, full pagewidth VCC PULSE GENERATOR VI RL 500 Ω VO 2 × VCC open GND D.U.T. CL 50 pF RT RL 500 Ω MNA479 TEST S1 VCC Definitions for test circuit: RL = load resistor. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. VI tPLH/tPHL open tPLZ/tPZL 2 × VCC <2.7 V tPHZ/tPZH GND 2.7 to 3.6 V 2.7 V VCC Fig.7 Test circuitry for switching times. 1999 Nov 24 10 Philips Semiconductors Product specification 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state 74LVCH32374A PACKAGE OUTLINE LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1 D ball A1 index area A2 A E A1 detail X b A ∅w M ZD e y v A ZE T R P N M L K J H G F E D C B A e X 1 2 3 4 5 6 DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b D E e v w y ZD ZE mm 1.5 0.41 0.31 1.2 0.9 0.51 0.41 5.6 5.4 13.6 13.4 0.8 0.2 0.15 0.1 0.93 0.58 0.93 0.58 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ 5 10 mm scale EUROPEAN PROJECTION ISSUE DATE 98-11-25 99-06-03 SOT536-1 1999 Nov 24 0 11 Philips Semiconductors Product specification 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. 74LVCH32374A The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 1999 Nov 24 12 Philips Semiconductors Product specification 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state 74LVCH32374A Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Nov 24 13 Philips Semiconductors Product specification 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state NOTES 1999 Nov 24 14 74LVCH32374A Philips Semiconductors Product specification 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state NOTES 1999 Nov 24 15 74LVCH32374A Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 245004/01/pp16 Date of release: 1999 Nov 24 Document order number: 9397 750 06467