Preliminary Information ® X86C64 Z8 Microcontroller Family Compatible X86C64 64K 8192 x 8 Bit E2 Micro-Peripheral FEATURES DESCRIPTION • The X86C64 is an 8K x 8 E2PROM fabricated with advanced CMOS Textured Poly Floating Gate Technology. The X86C64 features a Multiplexed Address and Data bus allowing direct interface to a variety of popular single-chip microcontrollers operating in expanded multiplexed mode without the need for additional interface circuitry. • • • • • • • CONCURRENT READ WRITE™ —Dual Plane Architecture Isolates Read/Write Functions Between Planes Allows Continuous Execution of Code From One Plane While Writing in the Other Plane Multiplexed Address/Data Bus —Direct Interface to Popular 8-bit Microcontrollers, e.g. Zilog Z8 Family High Performance CMOS —Fast Access Time, 120 ns —Low Power 60 mA Maximum Active 200 µA Maximum Standby Software Data Protection Block Protect Register —Individually Set Write Lock Out in 1K Blocks Toggle Bit —Early End of Write Detection Page Mode Write —Allows up to 32 Bytes to be Written in One Write Cycle High Reliability —Endurance: 10,000 Write Cycle —Data Retention: 100 Years FUNCTIONAL DIAGRAM The X86C64 is internally configured as two independent 4K x 8 memory arrays. This feature provides the ability to perform nonvolatile memory updates in one array and continue operation out of code stored in the other array; effectively eliminating the need for an auxiliary memory device for code storage. To write to the X86C64, a three byte command sequence must precede the byte(s) being written. The X86C64 also provides a second generation software data protection scheme called Block Protect. Block Protect can provide write lockout of the entire device or selected 1K blocks. There are eight, 1K x 8 blocks that can be write protected individually in any combination required by the user. Block Protect, in addition to Write Control input, allows the different segments of the memory to have varying degrees of alterability in normal system operation. WC CE A12 R/W DS SEL A8–A11 AS CONTROL LOGIC L A T C H E S X D E C O D E SOFTWARE DATA PROTECT A12 1K BYTES 1K BYTES 1K BYTES 1K BYTES A12 M U X 1K BYTES 1K BYTES 1K BYTES 1K BYTES Y DECODE I/O & ADDRESS LATCHES AND BUFFERS A/D0–A/D7 3819 FHD F02 Z8® is a registered trademark of Zilog Corporation CONCURRENT READ WRITE™ is a trademark of Xicor, Inc. © Xicor, 1991 Patents Pending 3819-2.1 7/29/96 T0/C1/D1 SH 1 Characteristics subject to change without notice X86C64 PIN DESCRIPTIONS PIN CONFIGURATION Address/Data (A/D0–A/D7) DIP/SOIC Multiplexed low-order addresses and data. The addresses flow into the device while AS is LOW. After AS transitions from a LOW to HIGH the addresses are latched. Once the addresses are latched these pins input data or output data depending on DS, R/W, and CE. NC 1 24 VCC A12 2 23 R/W NC 3 22 AS NC 4 21 A8 Addresses (A8–A12) WC 5 20 A9 High order addresses flow into the device when AS = VIL and are latched when AS goes HIGH. SEL 6 19 A11 A/D0 7 18 DS A/D1 8 17 A10 A/D2 9 16 CE A/D3 10 15 A/D7 A/D4 11 14 A/D6 VSS 12 13 A/D5 Chip Enable (CE) The Chip Enable input must be HIGH to enable all read/ write operations. When CE is LOW and AS is HIGH, the X86C64 is placed in the low power standby mode. X86C64 Data Strobe (DS) 3819 FHD F01 When used with a Z8 the DS input is tied directly to the DS output of the microcontroller. PIN NAMES Symbol Read/Write (R/W) AS A/D0–A/D7 A8–A12 DS R/W CE WC SEL VSS VCC When used with a Z8 the R/W input is tied directly to the R/W output of the microcontroller. Address Strobe (AS) Addresses flow through the latches to address decoders when AS is LOW and are latched when AS transitions from a LOW to HIGH. Device Select (SEL) Must be connected to VSS. Write Control (WC) Description Address Strobe Address Inputs/Data I/O Address Inputs Data Strobe Input Read/Write Input Chip Enable Write Control Device Select—Connect to VSS Ground Supply Voltage 3819 PGM T01 The Write Control allows external circuitry to abort a page load cycle once it has been initiated. This input is useful in applications in which a power failure or processor RESET could interrupt a page load cycle. In this case, the microcontroller might drive all signals HIGH, causing bad data to be latched into the E2PROM. If the Write Control input is driven HIGH (before tTBLC Max) after Read/Write (R/W) goes HIGH, the write cycle will be aborted. When WC is LOW (tied to VSS) the X86C64 will be enabled to perform write operations. When WC is HIGH normal read operations may be performed, but all attempts to write to the device will be disabled. 2 X86C64 PRINCIPLES OF OPERATION DEVICE OPERATION The X86C64 is a highly integrated peripheral device for a wide variety of single-chip microcontrollers. The X86C64 provides 8K bytes of 5-volt E2PROM which can be used either for Program Storage, Data Storage or a combination of both in systems based upon Von Neumann (86XX) architectures. The X86C64 incorporates the interface circuitry normally needed to decode the control signals and demultiplex the Address/Data bus to provide a “ Seamless” interface. Zilog Z8 operation requires the microcontroller’s AS, DS and R/W outputs tied to the X86C64 AS, DS and R/W inputs respectively. The rising edge of AS will latch the addresses for both a read and write operation. The state of R/W output determines the operation to be performed, with the DS signal acting as a data strobe. If R/W is HIGH and CE HIGH (read operation) data will be output on A/D0–A/D7 after DS transitions LOW. If R/W is LOW and CE is HIGH (write operation) data presented at A/D0–A/D7 will be strobed into the X86C64 on the LOW to HIGH transition of DS. The interface inputs on the X86C64 are configured such that it is possible to directly connect them to the proper interface signals of the appropriate single-chip microcontroller. Typical Application The X86C64 is internally organized as two independent planes of 4K bytes of memory with the A12 input selecting which of the two planes of memory are to be accessed. While the processor is executing code out of one plane, write operations can take place in the other plane, allowing the processor to continue execution of code out of the X86C64 during a byte or page write to the device. P10 P11 P12 P13 2 The X86C64 also features an advanced implementation of the Software Data Protection scheme, called Block Protect, which allows the device to be broken into 8 independent sections of 1K bytes. Each of these sections can be independently enabled for write operations; thereby allowing certain sections of the device to be secured so that updates can only occur in a controlled environment (e.g. in an automotive application, only at an authorized service center). The desired set-up configuration is stored in a nonvolatile register, ensuring the configuration data will be maintained after the device is powered down. 3 P14 P15 P16 XTAL P17 P00 EXTAL P01 P02 P03 P04 P07 AS DS R/W Z8 21 22 7 8 23 24 25 9 10 11 26 27 13 14 28 13 14 15 21 20 15 16 17 19 17 20 2 16 5 9 8 22 18 7 23 6 A/D0 A/D1 A/D2 24 VCC A/D3 A/D4 A/D5 A/D6 A/D7 A8 A9 A10 A11 A12 CE WC AS DS R/W SEL VSS X86C64 12 3819 FHD F03 The X86C64 also features a Write Control input (WC), which serves as an external control over the completion of a previously initiated page load cycle. The X86C64 also features the industry standard 5-volt E2PROM characteristics such a byte or page mode write and toggle-bit polling. 3 X86C64 MODE SELECTION CE DS R/W Mode I/O Power VSS VIL VIH VIH X X VIL X X VIH VIL Standby Standby Read Write High Z High Z DOUT DIN Standby (CMOS) Standby (TTL) Active Active 3819 PGM T08 PAGE WRITE OPERATION requirements. The falling edge of DS starts a timer delaying the internal programming cycle 100 µs. Therefore, each successive write operation must begin within 100 µs of the last byte written. The following waveforms illustrate the sequence and timing requirements. Regardless of the microcontroller employed, the X86C64 supports page mode write operations. This allows the microcontroller to write from one to thirty-two bytes of data to the X86C64. Each individual write within a page write operation must conform to the byte write timing Page Write Timing Sequence for DS Controlled Operation OPERATION BYTE 1 BYTE 0 BYTE 2 LAST BYTE READ (1)(2) AFTER tWC READY FOR NEXT WRITE OPERATION CE AS A/D0–A/D7 A8–A12 AIN AIN DIN A12=n DIN A12=n AIN AIN DIN A12=n DIN A12=n AIN AIN DIN ADDR A12=x AIN Next Address DS R/W tBLC tWC 3819 FHD FHD F07 3819 F07 Notes: (1) For each successive write within a page write cycle A5–A12 must be the same. (2) Although it is not illustrated, the microcontroller may interleave read operations between the individual byte writes within the page write operation. Two responses are possible. a. Reading from the same plane being written (A12 of Read = A12 of Write) is effectively a Toggle Bit Polling operation. b. Reading from the opposite plane being written (A12 of Read ≠ A12 of Write) true data will be returned, facilitating the use of a single memory component as both program and data store. 4 X86C64 Toggle Bit Polling When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations. Due to the dual plane architecture, reads for polling must occur in the plane that was written; that is, the state of A12 during write must match the state of A12 during polling. Because the X86C64 typical write timing is less than the specified 5 ms, Toggle Bit Polling has been provided to determine the early end of write. During the internal programming cycle I/O6 will toggle from one to zero and zero to one on subsequent attempts to read the device. Toggle Bit Polling DS Control OPERATION LAST BYTE WRITTEN I/O6=X I/O6=X I/O6=X I/O6=X AIN AIN AIN AIN X68C64 READY FOR NEXT OPERATION CE AS A/D0–A/D7 A8–A12 AIN DIN A12=n DOUT A12=n DOUT A12=n DOUT A12=n DOUT A12=n AIN ADDR DS R/W 3819 FHD F08 5 X86C64 DATA PROTECTION Setting write lockout is accomplished by writing a five byte command sequence opening access to the Block Protect Register (BPR). After the fifth byte is written the user writes to the BPR selecting which blocks to protect or unprotect. All write operations, both the command sequence and writing the data to the BPR, must conform to the page write timing requirements. The X86C64 provides two levels of data protection through software control. There is a global software data protection feature similar to the industry standard for E2PROMs and a new Block Protect write lock out protection providing a second level data security option. Writing with SDP WRITE AA TO X555 Block Protect Register Format MSB 7 PERFORM BYTE OR PAGE WRITE OPERATIONS WRITE 55 TO XAAA LSB 6 5 4 3 2 1 0 BLOCK ADDRESS 0000–03FF 0400–07FF 0800–0BFF 0C00–0FFF 1000–13FF 1400–17FF 1800–1BFF 1C00–1FFF WAIT tWC WRITE A0 TO X555 1 = Protect, 0 = Unprotect Block Specified EXIT ROUTINE 3819 FHD F11 X = A12: Setting BPR Command Sequence A12 = 1 IF DATA TO BE WRITTEN IS WITHIN ADDRESS 1000 TO 1FFF. A12 = 0 IF DATA TO BE WRITTEN IS WITHIN ADDRESS 0000 TO 0FFF. WRITE AA TO X555 3819 FHD F09 WRITE C0 TO XAAA Software Data Protection Software data protection (SDP) is employed to protect the entire array against inadvertent writes. To write to the X86C64, a three byte command sequence must precede the byte(s) being written. WRITE 55 TO XAAA All write operations, both the command sequence and any data write operations must conform to the page write timing requirements. WRITE BPR MASK VALUE TO ANY ADDRESS WRITE A0 TO X555 WAIT tWC Block Protect Write Lockout The X86C64 provides a second level of data security referred to as Block Protect write lockout. This is accessed through an extension of the SDP command sequence. Block Protect allows the user to lock out writes to 1K x 8 blocks of memory. Unlike SDP which prevents inadvertent writes, but still allows easy system access to writing the memory, Block Protect will lock out all attempts unless it is specifically disabled by the host. This could be used to set a higher level of protection in a system where a portion of the memory is used for Program Store and another portion is used as Data Store. WRITE AA TO X555 EXIT ROUTINE X = A12: A12 = 1 IF PROGRAM BEING EXECUTED IS WITHIN 0000 TO 0FFF. A12 = 0 IF PROGRAM BEING EXECUTED RESIDES WITHIN 1000 TO 1FFF. 3819 FHD F12 6 X86C64 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias X86C64 ........................................ –10°C to +85°C X86C64I ..................................... –65°C to +135°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS ............................... –1.0V to +7V D.C. Output Current ............................................ 5 mA Lead Temperature (Soldering, 10 Seconds) ............................. 300°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Supply Voltage Limits Commercial Industrial Military 0°C –40°C –55°C 70°C +85°C +125°C X86C64 5V ± 10% 3819 PGM T03 3819 PGM T02 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions CE = VIL, All I/O’s = Open, Other Inputs = VCC, AS = VIL CE = VSS, All I/O’s = Open,Other Inputs = VCC – 0.3V CE = VIH, All I/O’s = Open, Other Inputs = VIH VIN = GND to VCC VOUT = GND to VCC, DS = VIH ICC VCC Current (Active) 60 mA ISB1(CMOS) VCC Current (Standby) 500 µA ISB2(TTL) VCC Current (Standby) 6 mA ILI ILO VlL(1) VIH(1) VOL VOH Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 10 10 0.8 VCC + 0.5 0.4 µA µA V V V V –1.0 2.0 2.4 IOL = 2.1 mA IOH = –400 µA 3819 PGM T04 CAPACITANCE TA = 25°C, F = 1.0MHZ, VCC = 5V Symbol CI/O(2) CIN(2) Test Max. Units Conditions Input/Output Capacitance Input Capacitance 10 6 pF pF VI/O = 0V VIN = 0V 3819 PGM T05 POWER-UP TIMING Symbol Parameter Max. Units tPUR(2) tPUW(2) Power-Up to Read Power-Up to Write 1 5 ms ms 3819 PGM T06 Notes: (1) VIL MIN and VIH MAX are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. 7 X86C64 A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels EQUIVALENT A.C. TEST CIRCUIT 0V to 3.0V 5.0V 10ns 1923Ω Output 1.5V 3819 PGM T07 1370Ω 100pF 3819 FHD F04 A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) DS Controlled Read Cycle Symbol Parameter Min. PWASL tAS tAH tACC tDHR tCS PWDSH tDSS tDSH tRWS tHZ(3) tLZ(3) Address Strobe Pulse Width Address Setup Time Address Hold Time Data Access Time Data Hold Time CE Setup Time DS Pulse Width DS Setup Time DS Hold Time R/W Setup Time DS High to High Z Output DS Low to Low Z Output 80 20 30 Max. 120 0 7 150 30 20 20 50 0 Units ns ns ns ns ns ns ns ns ns ns ns ns 3819 PGM T09 DS Controlled Read Cycle CE tCS PWASL tDSH tDSH tDSS AS tAS tAH AIN A/D0–A/D7 DOUT tACC tDHR A8–A12 A8–A12 tHZ tRWS R/W tDSH DS PWDSH Note: (3) This parameter is periodically sampled and not 100% tested. 8 3819 FHD F05 X86C64 DS Controlled Write Cycle Symbol Parameter Min. PWASH tAS tAH tDSW tDHW tCS PWDSH tWC tDSS tRWS tDSH tBLC Address Strobe Pulse Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time CE Setup Time DS Pulse Width Write Cycle Time Enable Setup Time R/W Setup Time DS Hold Time Byte Load Time (Page Write) 80 20 30 50 30 7 120 Max. 5 30 20 20 0.5 100 Units ns ns ns ns ns ns ns ms ns ns ns µs 3819 PGM T10 DS Controlled Write Cycle CE tCS PWASH tDSH tDSH tDSS AS tAH tAS AIN A/D0–A/D7 DIN tDSW tDHW A8–A12 A8–A12 tDSH tRWS R/W DS PWDSH Note: 3819 FHD F06 (4) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. 9 X86C64 PACKAGING INFORMATION 24-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 1.265 (32.13) 1.230 (31.24) 0.557 (14.15) 0.530 (13.46) PIN 1 INDEX PIN 1 0.080 (2.03) 0.065 (1.65) 1.100 (27.94) REF. 0.162 (4.11) 0.140 (3.56) SEATING PLANE 0.030 (0.76) 0.015 (0.38) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.065 (1.65) 0.040 (1.02) 0.022 (0.56) 0.014 (0.36) 0.625 (15.87) 0.600 (15.24) 0° 15° TYP. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 3926 FHD F03 10 X86C64 PACKAGING INFORMATION 24-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) PIN 1 INDEX PIN 1 0.014 (0.35) 0.020 (0.50) 0.598 (15.20) 0.610 (15.49) (4X) 7° 0.092 (2.35) 0.105 (2.65) 0.003 (0.10) 0.012 (0.30) 0.050 (1.27) 0.050" TYPICAL 0.010 (0.25) X 45° 0.020 (0.50) 0.050" TYPICAL 0° – 8° 0.009 (0.22) 0.013 (0.33) 0.420" 0.015 (0.40) 0.050 (1.27) FOOTPRINT 0.030" TYPICAL 24 PLACES NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 3926 FHD F24 11 X86C64 ORDERING INFORMATION X86C64 X X X VCC Limits Blank = 5V ± 10% Device Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +128°C Package P = 24-Lead Plastic DIP S = 24-Lead Plastic SOIC LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 12