Features • Six High-side and Six Low-side Drivers • Outputs Freely Configurable as Switch, Half Bridge or H-bridge • Capable to Switch all Kinds of Loads such as DC Motors, Bulbs, Resistors, Capacitors • • • • • • • • • • • • and Inductors 0.6A Continuous Current per Switch Low-side: RDSon < 1.5Ω versus Total Temperature Range High-side: RDSon < 2.0Ω versus Total Temperature Range Very Low Quiescent Current Is < 20 µA in Standby Mode Outputs Short-circuit Protected Overtemperature Prewarning and Protection Undervoltage Protection Various Diagnosis Functions such as Shorted Output, Open Load, Overtemperature and Power Supply Fail Serial Data Interface Operation Voltage up to 40V Daisy Chaining Possible SO28 Power Package 40-V Dual Hex Output Driver with Serial Input Control T6816 1. Description The T6816 is a fully protected driver interface designed in 0.8 µm BCDMOS technology. It is especially suitable for truck or bus applications and the industrial 24-V supply. It controls up to 12 different loads via a 16-bit dataword. Each of the six high-side and six low-side drivers is capable to drive currents up to 600 mA. The drivers are freely configurable and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC is also designed to easily build H-bridges to drive DC motors in motion-control applications. Protection is guaranteed in terms of short-circuit conditions, overtemperature and undervoltage. Various diagnosis functions and a very low quiescent current in standby mode open a wide range of applications. Automotive qualification referring to conducted interferences, EMC protection and 2 kV ESD protection gives added value and enhanced quality for the exacting requirements of automotive applications. 4595F–BCD–02/08 Figure 1-1. Block Diagram HS3 HS2 HS1 15 13 13 15 Fault Detect 3 12 Fault Detect Fault Detect HS5 HS4 12 3 Fault Detect HS6 2 2 Fault Detect 28 28 5 Fault Detect 10 DI VS VS 26 6 GND Osc CLK CS INH 25 S C T S I 24 O L D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 P S F I N H S C D H S 6 L S 6 VS Control Input Register Output Register 17 7 S R R logic H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 Thermal protection T P L S 1 UV protection Power-on reset 18 DO VCC Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect 8 9 20 21 22 23 GND GND GND GND GND GND GND VCC 19 16 LS1 2 14 LS2 4 11 LS3 LS4 1 LS5 VCC 27 LS6 T6816 4595F–BCD–02/08 T6816 2. Pin Configuration Figure 2-1. Pinning SO28 HS6 LS6 DI CLK CS 28 27 26 25 24 GND GND GND GND VCC DO 23 22 21 INH LS1 HS1 20 19 18 17 16 15 9 10 11 12 13 14 VS LS3 HS3 HS2 LS2 T6816 Lead frame Table 2-1. Pin 1 2 3 4 5 LS5 HS5 HS4 LS4 VS 6 7 8 GND GND GND GND Pin Description Symbol Function 1 LS5 Low-side driver output 5; Power-MOS open drain with internal reverse diode; short-circuit protection; diagnosis for short and open load 2 HS5 High-side driver output 5; Power-MOS open drain with internal reverse diode; short-circuit protection; diagnosis for short and open load 3 HS4 High-side driver output 4; see pin 2 4 LS4 Low-side driver output 4; see pin 1 5 VS Power supply output stages HS4, HS5, HS6, internal supply; external connection to pin 10 necessary 6, 7, 8, 9 GND Ground; reference potential; internal connection to pin 20-23; cooling tab 10 VS Power supply output stages HS1, HS2 and HS3 11 LS3 Low-side driver output 3; see pin 1 12 HS3 High-side driver output 3; see pin 2 13 HS2 High-side driver output 2; see pin 2 14 LS2 Low-side driver output 2; see pin 1 15 HS1 High-side driver output 1; see pin 2 16 LS1 Low-side driver output 1; see pin 1 17 INH Inhibit input; 5V logic input with internal pull down; low = standby, high = normal operating 18 DO Serial data output; 5V CMOS logic level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first). Output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on one data output line only. 19 VCC Logic supply voltage (5V) 20-23 GND Ground; see pin 6-9 24 CS Chip select input; 5V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled 25 CLK Serial clock input; 5V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz) 26 DI Serial data input; 5V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first 27 LS6 Low-side driver output 6; see pin 1 28 HS6 High-side driver output 6; see pin 2 3 4595F–BCD–02/08 3. Functional Description 3.1 Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3-1. Data Transfer Input Data Protocol CS DI SRR LS1 HS1 2 LS2 3 HS2 4 LS3 5 HS3 LS4 HS4 LS5 6 7 8 9 HS5 10 LS6 11 HS6 12 OLD 0 1 13 TP SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 SLS4 SHS4 SLS5 SHS5 SLS6 SHS6 SCD SCT 14 SI 15 CLK DO Table 3-1. 4 INH PSF Input Data Protocol Bit Input Register Function 0 SRR Status register reset (high = reset; the bits PSF, SCD and overtemperature shutdown in the output data register are set to low) 1 LS1 Controls output LS1 (high = switch output LS1 on) 2 HS1 Controls output HS1 (high = switch output HS1 on) 3 LS2 See LS1 4 HS2 See HS1 5 LS3 See LS1 6 HS3 See HS1 7 LS4 See LS1 8 HS4 See HS1 9 LS5 See LS1 10 HS5 See HS1 11 LS6 See LS1 12 HS6 See HS1 13 OLD Open load detection (low = on) 14 SCT Programmable time delay for short circuit (shutdown delay high/low = 12 ms/1.5 ms) 15 SI Software inhibit; low = standby, high = normal operation (data transfer is not affected by standby function because the digital part is still powered) T6816 4595F–BCD–02/08 T6816 Table 3-2. Bit Output (Status) Register Function Temperature prewarning: high = warning (overtemperature shutdown see remark below) 0 TP 1 Status LS1 Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) 2 Status HS1 Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) 3 Status LS2 Description see LS1 4 Status HS2 Description see HS1 5 Status LS3 Description see LS1 6 Status HS3 Description see HS1 7 Status LS4 Description see LS1 8 Status HS4 Description see HS1 9 Status LS5 Description see LS1 10 Status HS5 Description see HS1 11 Status LS6 Description see LS1 12 Status HS6 Description see HS1 13 SCD Short circuit detected: set high, when at least one output is switched off by a short circuit condition 14 INH Inhibit: this bit is controlled by software (bit SI in input register) and hardware inhibit (pin 17). High = standby, low = normal operation 15 PSF Power supply fail: undervoltage at pin VS detected Note: Table 3-3. Output Data Protocol Bit 0 to 15 = high: overtemperature shutdown Status of the Input Register after Power on Reset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (SI) (SCT) (OLD) (HS6) (LS6) (HS5) (LS5) (HS4) (LS4) (HS3) (LS3) (HS2) (LS2) (HS1) (LS1) (SRR) H H H L L L L L L L L L L L L L 5 4595F–BCD–02/08 3.2 Power Supply Fail In case of undervoltage at pin VS, an internal timer is started. When the undervoltage delay time (tdUV) programmed by the SCT bit is reached, the power supply fail bit (PSF) in the output register is set and all outputs are disabled. When normal voltage is present again, the outputs are enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the input register. 3.3 Open-load Detection If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current IHS1-6, ILS1-6). If VVS – VHS1-6 or VLS1-6 is lower than the open-load detection threshold (open-load condition), the corresponding bit of the output in the output register is set to high. Switching on an output stage with OLD bit set to low disables the open-load function for this output. 3.4 Overtemperature Protection If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word: with CS = high to low, the state of TP appears at pin DO. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the state of the input and output registers. If the junction temperature exceeds the thermal shutdown threshold, Tj switch off, the outputs are disabled and all bits in the output register are set high. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold, Tj switch on, and when a high has been written to the SRR bit in the input register. Thermal prewarning and shutdown threshold have hysteresis. 3.5 Short-circuit Protection The output currents are limited by a current regulator. Current limitation takes place when the overcurrent limitation and shutdown threshold (IHS1-6, ILS1-6) are reached. Simultaneously, an internal timer is started. The shorted output is disabled when during a permanent short the delay time (tdSd) programmed by the short-circuit timer bit (SCT) is reached. Additionally, the short-circuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is set during a short, the shorted output is disabled immediately and SCD bit is set. By writing a high to the SRR bit in the input register, the SCD bit is reset and the disabled outputs are enabled. 3.6 Inhibit There are two ways to inhibit the T6816: 1. Set bit SI in the input register to zero 2. Switch pin 17 (INH) to 0V In both cases, all output stages are turned off but the serial interface stays active. The output stages can be activated again by bit SI = 1 or by pin 17 (INH) switched back to 5V. 6 T6816 4595F–BCD–02/08 T6816 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All values refer to GND pins Parameter Pin Symbol Value Unit Supply voltage 5, 10 VVS –0.3 to +40 V Supply voltage t < 0.5 s; IS ≥ –2 A 5, 10 VVS –1 V ∆VVS 150 mV IVS 1.4 A Supply voltage difference ⏐ VS_pin5 – VS_pin10⏐ Supply current 5, 10 Supply current t < 200 ms 5, 10 IVS 2.6 A Logic supply voltage 19 VVCC –0.3 to +7 V Input voltage 17 VINH –0.3 to +17 V 24 to 26 VDI, VCLK, VCS –0.3 to VVCC +0.3 V 18 VDO –0.3 to VVCC +0.3 V –10 to +10 mA mA Logic input voltage Logic output voltage 17, 24 to 26 IINH, IDI, ICLK, ICS Output current 18 IDO –10 to +10 Output current 1 to 4, 11 to 16, 27 and 28 ILS1 to ILS6 IHS1 to IHS6 Internal limited, see output specification 2, 3, 12, 13, 15, 28 towards 5, 10 IHS1 to IHS6 17 A Junction temperature range Tj –40 to +150 °C Storage temperature range TSTG –55 to +150 °C Input current Reverse conducting current (tPulse = 150 µs) 5. Thermal Resistance All values refer to GND pins Parameter Test Conditions Pin Symbol Junction pin Measured to GND 6 to 9, 20 to 23 Junction ambient Min. Typ. Max. Unit RthJP 25 K/W RthJA 65 K/W Max. Unit 40 V 5.5 V VVCC V 2 MHz 150 °C 6. Operating Range All values refer to GND pins Parameter Test Conditions Supply voltage Logic supply voltage Logic input voltage Serial interface clock frequency Junction temperature range Note: Pin Symbol Min. 5, 10 VVS VUV(1) 19 VVCC 4.5 17, 24 to 26 VINH, VDI, VCLK, VCS –0.3 25 fCLK Tj –40 Typ. 5 1. Threshold for undervoltage detection. 7 4595F–BCD–02/08 7. Noise and Surge Immunity Parameter Test Conditions Conducted interferences ISO 7637-1 Interference Suppression VDE 0879 Part 2 ESD (Human Body Model) MIL-STD-883D Method 3015.7 2 kV ESD (Machine Model) EOS/ESD - S 5.2 150V Note: Value Level 4(1) Level 5 1. Test pulse 5: VSmax = 40V 8. Electrical Characteristics 7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pin Symbol 5, 10 Min. Typ. Max. Unit Type* IVS 40 µA A 20 µA A 1.2 mA A 1 Current Consumption 1.1 Quiescent current (VS) VVS < 28V, INH or bit SI = low 1.2 Quiescent current (VCC) 4.5V < VVCC < 5.5V, INH or bit SI = low 19 IVCC 1.3 Supply current (VS) VVS < 28V normal operating, all output stages off 5, 10 IVS 1.4 Supply current (VS) VVS < 28V normal operating, all output stages on, no load 5, 10 IVS 10 mA A 1.5 Supply current (VCC) 4.5V < VVCC < 5.5V, normal operating pin 19 IVCC 150 µA A 45 kHz A 2 2.1 3 0.8 Internal Oscillator Frequency Frequency (timebase for delay timers) fOSC 19 19 VVCC 3.4 3.9 4.4 V A 19 tdPor 30 95 160 µs A 5.5 7.0 V A V A 21 ms A Undervoltage Detection, Power-on Reset 3.1 Power-on reset threshold 3.2 Power-on reset delay time 3.3 Undervoltage detection threshold 5, 10 VUV 3.4 Undervoltage detection hysteresis 5, 10 ∆VUV 3.5 Undervoltage detection delay 5, 10 tdUV 7 4 After switching on VVCC 0.4 Thermal Prewarning and Shutdown 4.1 Thermal prewarning 17 TjPWset 125 145 165 °C A 4.2 Thermal prewarning 17 TjPWreset 105 125 145 °C A 4.3 Thermal prewarning hysteresis K A 4.4 Thermal shutdown °C A ∆TjPW 17 Tj switch off 20 150 170 190 *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 8 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level T6816 4595F–BCD–02/08 T6816 8. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters 4.5 Thermal shutdown 4.6 Thermal shutdown hysteresis ∆Tj switch off 4.7 Ratio thermal shutdown/thermal prewarning Tj switch off/ TjPW set 1.05 1.17 A 4.8 Ratio thermal shutdown/thermal prewarning Tj switch on/ TjPW reset 1.05 1.2 A 5 Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 17 Tj switch on 130 150 170 °C A K A 20 Output Specification (LS1-LS6, HS1-HS6) 5.1 On resistance IOut = 600 mA 1, 4, 11, 14, 16, 27 RDS OnL 1.5 Ω A 5.2 On resistance IOut = –600 mA 2, 3, 12, 13, 15, 28 RDS OnH 2.0 Ω A 5.3 Output clamping voltage ILS1-6 = 50 mA 1, 4, 11, 14, 16, 27 VLS1-6 60 V A 5.4 Output leakage current VLS1–6 = 40V all output stages off 1, 4, 11, 14, 16, 27 ILS1-6 10 µA A 5.5 Output leakage current VHS1-6 = 0V all output stages off 2, 3, 12, 13, 15, 28 IHS1-6 µA A 5.7 Inductive shutdown energy 1-4, 11-16, 27, 28 Woutx 15 mJ D 5.8 Output voltage edge steepness 1-4, 11-16, 27, 28 dVLS1-6/dt dVHS1-6/dt 50 200 400 mV/µs A 5.9 Overcurrent limitation and shutdown threshold 1-4, 11-16, 27 ILS1-6 650 950 1250 mA A 5.10 Overcurrent limitation and shutdown threshold 2, 3, 12,13, 15, 28 IHS1-6 –1250 –950 –650 mA A 5.11 Overcurrent shutdown delay time Input register bit 14 (SCT) = low tdSd 1.0 1.5 2.0 ms A 5.12 Open load detection current Input register bit 13 (OLD) = low, output off 1, 4, 11,14, 16, 27 ILS1-6 60 200 µA A 5.13 Open load detection current Input register bit 13 (OLD) = low, output off 2, 3, 12, 13 15, 28 IHS1-6 –150 –30 µA A 40 –10 *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level 9 4595F–BCD–02/08 8. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters 5.14 Open load detection current ratio 5.15 Open load detection threshold Input register bit 13 (OLD) = low, output off 5.16 Open load detection threshold Input register bit 13 (OLD) = low, output off 5.17 Output switch on delay(1) RLoad = 1 kΩ 5.18 Output switch off delay(1) RLoad = 1 kΩ 6 Test Conditions Pin Symbol Min. Typ. Max. Unit Type* ILS1-6/IHS1-6 1.2 1, 4, 11,14, 16, 27 VLS1-6 0.6 2 V A 2, 3, 12, 13 15, 28 VVS – VHS1-6 0.6 2 V A tdon 0.5 ms A tdoff 1 ms A V A 0.7 × VVCC V A A Inhibit Input 0.3 × VVCC 6.1 Input voltage low level threshold 17 VIL 6.2 Input voltage high level threshold 17 VIH 6.3 Hysteresis of input voltage 17 ∆VI 100 700 mV A 6.4 Pull-down current 17 IPD 10 80 µA A 0.3 × VVCC V A 0.7 × VVCC V A 7 VINH = VVCC Serial Interface - Logic Inputs DI, CLK, CS 7.1 Input voltage low-level threshold 24-26 VIL 7.2 Input voltage high-level threshold 24-26 VIH 7.3 Hysteresis of input voltage 24-26 ∆VI 50 500 mV A 7.4 Pull-down current pin DI, CLK VDI, VCLK = VVCC 25, 26 IPDSI 2 50 µA A 7.5 Pull-up current pin CS VCS= 0V 24 IPUSI –50 –2 µA A 0.5 V A V A µA A 8 Serial Interface - Logic Output DO 8.1 Output voltage low level IOL = 3 mA 18 VDOL 8.2 Output voltage high level IOL = –2 mA 18 VDOH VVCC –0.7V 8.3 Leakage current (tri-state) VCS = VVCC, 0V < VDO < VVCC 18 IDO –10 10 *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 10 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level T6816 4595F–BCD–02/08 T6816 9. Serial Interface - Timing Parameters Test Conditions Timing Chart No. Symbol DO enable after CS falling edge CDO = 100 pF 1 DO disable after CS rising edge CDO = 100 pF DO fall time CDO = 100 pF DO rise time DO valid time Min. Typ. Max. Unit tENDO 200 ns 2 tDISDO 200 ns – tDOf 100 ns CDO = 100 pF – tDOr 100 ns CDO = 100 pF 10 tDOVal 200 ns CS setup time 4 tCSSethl 225 ns CS setup time 8 tCSSetlh 225 ns CS high time Input register bit 14 (SCT) = high 9 tCSh 16 ms CS high time Input register bit 14 (SCT) = low 9 tCSh 2 ms CLK high time 5 tCLKh 225 ns CLK low time 6 tCLKl 225 ns CLK period time – tCLKp 500 ns ns CLK setup time 7 tCLKSethl 225 CLK setup time 3 tCLKSetlh 225 ns DI setup time 11 tDIset 40 ns DI hold time 12 tDIHold 40 ns 11 4595F–BCD–02/08 Figure 9-1. Serial Interface Timing with Chart Numbers 1 2 CS DO 9 CS 4 7 CLK 5 3 6 8 DI 11 CLK 10 12 DO Inputs DI, CLK, CS: High level = 0.7 × VCC, low level = 0.2 × VCC Output DO: High level = 0.8 × VCC, low level = 0.2 × VCC 12 T6816 4595F–BCD–02/08 T6816 10. Application Figure 10-1. Application Circuit VCC U5021M WATCHDOG Enable HS2 Trigger Reset HS1 15 HS3 HS4 13 HS5 HS6 3 12 2 28 VS BYT41D Microcontroller 5 V S Fault Detect Fault Detect 10 DI 26 6 Osc CLK CS INH 25 S C T S I 24 17 O L D H S 6 L S 6 L S 5 H S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 VS Control logic Input Register Output Register P S F I N H S C D H S 6 L S 6 7 S R R H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 T P 18 DO UV protection Fault Detect Fault Detect Fault Detect 20 Power-on Reset 21 VCC VCC 16 LS1 14 LS2 4 11 LS3 LS4 VS 10.1 1 LS5 27 22 23 Fault Detect Fault Detect 9 Thermal protection VCC Fault Detect 8 VS VBatt 24V GND GND GND GND GND GND GND GND 19 V CC VCC + Fault Detect Fault Detect Fault Detect + Fault Detect VCC 5V LS6 VS Application Notes It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: electrolythic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current IHSX (see: Absolute Maximum Ratings). Recommended value for capacitors at VCC: electrolythic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to GND pins. 13 4595F–BCD–02/08 11. Ordering Information Extended Type Number Package Remarks T6816-TIQY SO28 Power package, taped and reeled, Pb-free 12. Package Information Package SO28 Dimensions in mm 9.15 8.65 18.05 17.80 7.5 7.3 2.35 1.27 28 0.25 0.25 0.10 0.4 10.50 10.20 16.51 15 technical drawings according to DIN specifications 1 14 14 T6816 4595F–BCD–02/08 T6816 13. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 4595F-BCD-02/08 • Put datasheet in the newest template • Pb-free logo on page 1 deleted • Section 8 “Electrical Characteristics” number 5 on page 9 changed 4595E-BCD-09/05 • Pb-free logo on page 1 added • Section 1 “Description” on page 1 changed • Ordering Information on page 14 changed 4595D-BCD-05/05 • Put datasheet in a new template • Table “Electrical Characteristics” rows 5.15 and 5.16 changed 4595C-BCD-04/04 • Put datasheet in a new template • Table “Absolute Maximum Ratings” on page 7 changed • Table “Electrical Characteristics” on page 10 changed 15 4595F–BCD–02/08 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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