REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Change boilerplate to allow for class V criteria. Add class V devices to this SMD. Editorial changes throughout. 97-01-27 Monica L. Poelking B Correct figure 5. Update boilerplate. - jak 00-10-24 Thomas M. Hess REV SHEET REV B B B SHEET 15 16 17 REV STATUS OF SHEETS PMIC N/A REV B B B B B B B B B B B B B B SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PREPARED BY Monica L. Poelking STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216 CHECKED BY Monica L. Poelking APPROVED BY Michael A. Frye DRAWING APPROVAL DATE 89-11-06 REVISION LEVEL B MICROCIRCUIT, DIGITAL, ADVANCED CMOS, OCTAL BUFFER/LINE DRIVER WITH THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON SIZE CAGE CODE A 67268 5962-89847 SHEET 1 DSCC FORM 2233 APR 97 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. OF 17 5962-E251-00 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following examples. For device classes M and Q: 5962 - Federal stock class designator \ RHA designator (see 1.2.1) 89847 01 Device type (see 1.2.2) R X Case outline (see 1.2.4) Lead finish (see 1.2.5) V R X Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) / \/ Drawing number For device class V: 5962 - Federal stock class designator \ RHA designator (see 1.2.1) 89847 01 Device type (see 1.2.2) / \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number 01 54ACT241 02 54ACT11241 Circuit function Octal buffer/line driver with three-state outputs, TTL compatible inputs Octal buffer/line driver with three-state outputs, TTL compatible inputs 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as listed below. Since the device class designator has been added after the original issuance of this drawing, device classes M and Q designators will not be included in the PIN and will not be marked on the device. Device class M Q or V Device requirements documentation Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Certification and qualification to MIL-PRF-38535 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-89847 A REVISION LEVEL B SHEET 2 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter L R S 2 3 Descriptive designator GDIP3-T24 or CDIP4-T24 GDIP1-T20 or CDIP2-T20 GDFP2-F20 or CDFP3-F20 CQCC1-N20 CQCC1-N28 Terminals Package style 24 20 20 20 28 Dual-in-line package Dual-in-line package Flat pack Square leadless chip carrier Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC).............................................................................. DC input voltage range (VIN)............................................................................ DC output voltage range (VOUT) ....................................................................... Input clamp diode current (IIK) ......................................................................... Output clamp diode current (IOK) ..................................................................... DC output current (IOUT)................................................................................... DC VCC or GND current (ICC, IGND) ................................................................... Storage temperature range (TSTG).................................................................... Maximum power dissipation (PD).................................................................... Lead temperature (soldering, 10 seconds)....................................................... Thermal resistance, junction-to-case (θJC) ....................................................... Junction temperature (TJ)................................................................................ -0.5 V dc to +6.0 V dc -0.5 V dc to VCC + 0.5 V dc -0.5 V dc to VCC + 0.5 V dc ±20 mA ±20 mA ±50 mA ±100 mA -65°C to +150°C 500 mW +260°C See MIL-STD-1835 +175°C 4/ 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (VCC) ............................................................................. Input voltage range (VIN) ................................................................................. Output voltage range (VOUT)............................................................................ Maximum low level input voltage (VIL) ............................................................. Maximum high level input voltage (VIH) ........................................................... Case operating temperature range (TC)........................................................... Input rise and fall rate (∆t/∆V): ........................................................................ Maximum high level output current (IOH)......................................................... Maximum low level output current (IOL) .......................................................... 1/ 2/ 3/ 4/ +4.5 V dc to +5.5 V dc +0.0 V dc to VCC +0.0 V dc to VCC 0.8 V 2.0 V -55°C to +125°C 8 ns/V -24 mA +24 mA Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability.. Unless otherwise noted, all voltages are referenced to GND. The limits for the parameters specified herein shall apply over the full specified VCC range and case temperature range of -55°C to +125°C. Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-89847 A REVISION LEVEL B SHEET 3 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 MIL-STD-973 MIL-STD-1835 - Test Method Standard Microcircuits. Configuration Management. Interface Standard For Microcircuit Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings (SMD's). Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents which are DOD adopted are those listed in the issue of the DODISS cited in the solicitation. Unless otherwise specified, the issues of documents not listed in the DODISS are the issues of the documents cited in the solicitation. ELECTRONIC INDUSTRIES ALLIANCE (EIA) JEDEC Standard No. 20 - Standardized for Description of 54/74ACXXXX and 54/74ACTXXXX Advanced High-Speed CMOS Devices. (Applications for copies should be addressed to the Electronics Industries Alliance, 2001 Eye Street, NW, Washington, DC 20006.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents may also be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-89847 A REVISION LEVEL B SHEET 4 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Ground bounce load circuit and waveforms. The ground bounce load circuit and waveforms shall be as specified on figure 4. 3.2.6 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 5. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-STD-973. 3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 37 (see MIL-PRF-38535, appendix A). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-89847 A REVISION LEVEL B SHEET 5 TABLE I. Electrical performance characteristics. Test and MIL-STD-883 test method 1/ High level output voltage 3006 Low level output voltage 3007 Symbol VOH VOL Test conditions 2/ -55°C ≤ TC ≤ +125°C +4.5 V ≤ VCC ≤ +5.5 V unless otherwise specified For all inputs affecting output under test, VIN = 2.0 V or 0.8 V For all other inputs, VIN = VCC or GND, IOH = -50 µA For all inputs affecting output under test, VIN = 2.0 V or 0.8 V For all other inputs, VIN = VCC or GND, IOH = -24 mA For all inputs affecting output under test, VIN = 2.0 V or 0.8 V For all other inputs, VIN = VCC or GND, IOH = -50 mA 4/ For all inputs affecting output under test, VIN = 2.0 V or 0.8 V For all other inputs, VIN = VCC or GND, IOL = 50 µA For all inputs affecting output under test, VIN = 2.0 V or 0.8 V For all other inputs, VIN = VCC or GND IOL = 24 mA Device type and device class All All VCC Min 4.5 V Three-state output leakage current low IOZL 5/ 5/ 3020 1, 2, 3 5.4 4.5 V 3.7 5.5 V 4.7 5.5 V 3.85 Max V 4.5 V 5.5 V 1, 2, 3 0.1 0.1 All V 4.5 V 1, 3 0.4 2 0.5 1 0.4 All M, Q 5.5 V Unit 4.4 5.5 V All M, Q IOZH Limits 3/ All All All V Three-state output leakage current high 3021 Group A subgroups 2, 3 0.5 1, 3 0.4 2 0.5 1 0.4 2, 3 0.5 V For all inputs affecting output under test, VIN = 2.0 V or 0.8 V For all other inputs, VIN = VCC or GND IOL = 50 mA 4/ All All 5.5 V 1, 2, 3 1.65 OE1 or OE2 = 2.0 V or 0.8 V For all other inputs, VIN = VCC or GND VOUT = 5.5 V All V 5.5 V 1 0.5 2 10.0 All M, Q OE1 or OE2 = 2.0 V or 0.8 V All 1 -0.5 For all other inputs, V 2 -10.0 VIN = VCC or GND VOUT = GND All M, Q 1 -0.5 2, 3 -10.0 5.5 V µA 1 0.5 2, 3 10.0 See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-89847 A REVISION LEVEL B SHEET 6 TABLE I. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ Symbol Test conditions 2/ -55°C ≤ TC ≤ +125°C +4.5 V ≤ VCC ≤ +5.5 V unless otherwise specified Positive input clamp voltage 3022 Negative input clamp voltage 3022 VIC+ VCC = GND For input under test, IIN = 1.0 mA Device type and Device class All V VIC- VCC = open For input under test, IIN = -1.0 mA Input current high 3010 IIH For input under test, VIN = VCC For all other inputs, VIN = VCC or GND Input current low 3009 IIL For input under test, VIN = GND For all other inputs, VIN = VCC or GND Input capacitance 3012 Output capacitance 3012 Power dissipation capacitance Quiescent supply current delta, TTL input levels 3005 CIN Quiescent supply current, outputs high 3005 ICCH Quiescent supply current, outputs low 3005 ICCL Quiescent supply current, outputs three-state 3005 ICCZ COUT CPD 6/ ∆ICC 7/ See 4.4.1c TC = +25°C See 4.4.1c TC = +25°C See 4.4.1c TC = +25°C For input under test, VIN = VCC - 2.1 V For all other inputs, VIN = VCC or GND OE1 = GND and OE2 = VCC For all inputs, VIN = VCC OE1 = GND and OE2 = VCC For all inputs, VIN = GND OE1 = VCC and OE2 = GND For all inputs, VIN = VCC or GND VCC Group A subgroups Limits 3/ Min Max Unit 0.0 V 1 0.4 1.5 V All V Open 1 -0.4 -1.5 V All V All M, Q All V All M, Q 5.5 V 1 2 1 2, 3 1 2 0.1 1.0 0.1 1.0 -0.1 -1.0 µA 1 -0.1 2, 3 -1.0 All All All V All All All V GND 4 8.0 5.5 V 4 15.0 5.0 V 4 70 5.5 V 3 1.6 1, 2 1.0 1, 2, 3 1.6 1 2.0 2 40.0 1, 2, 3 160.0 1 2.0 All M, Q All V All M, Q All V All M, Q All V All M, Q 5.5 V 5.5 V 5.5 V 5.5 V µA pF mA µA µA 2 40.0 1, 2, 3 160.0 1 2.0 2 40.0 1, 2, 3 160.0 µA See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-89847 A REVISION LEVEL B SHEET 7 TABLE I. Electrical performance characteristics - Continued. Test and ML-STD-883 test method 1/ Symbol Low level ground bounce noise VGBL 8/ 9/ High level ground bounce noise VGBH 8/ 9/ Latch-up input/output over-voltage ICC (O/V1) 10/ Latch-up input/output positive overcurrent ICC (O/I1+) 10/ Latch-up input/output negative overcurrent ICC (O/I1-) 10/ Latch-up supply over-voltage ICC (O/V2) 10/ Functional tests 3014 Propagation delay time, data to output, mAn to mYn 3003 11/ tPHL Test conditions 2/ -55°C ≤ TC ≤ +125°C +4.5 V ≤ VCC ≤ +5.5 V unless otherwise specified VLD = 2.5 V IOL = +24 mA (See figure 5), See 4.4.1d VLD = 2.5 V IOH = -24 mA (See figure 5) , See 4.4.1d tw ≥ 100 µs, tcool ≥ tw 5 µs ≤ tr ≤ 5 ms 5 µs ≤ tf ≤ 5 ms Vtest = 6.0 V VCCQ = 5.5 V Vover = 10.5 V, See 4.4.1d tw ≥ 100 µs, tcool ≥ tw 5 µs ≤ tr ≤ 5 ms 5 µs ≤ tf ≤ 5 ms Vtest = 6.0 V VCCQ = 5.5 V Itrigger = +120 mA , See 4.4.1d tw ≥ 100 µs, tcool ≥ tw 5 µs ≤ tr ≤ 5 ms 5 µs ≤ tf ≤ 5 ms Vtest = 6.0 V VCCQ = 5.5 V Itrigger = -120 mA, See 4.4.1d tw ≥ 100 µs, tcool ≥ tw 5 µs ≤ tr ≤ 5 ms 5 µs ≤ tf ≤ 5 ms Vtest = 6.0 V VCCQ = 5.5 V Vover = 9.0 V, See 4.4.1d VIL = 0.40 V VIH = 2.40 V Verify output VOUT See 4.4.1b CL = 50 pF RL = 500Ω See figure 5 12/ tPLH CL = 50 pF RL = 500Ω See figure 5 12/ Device type and Device class All V VCC Group A subgroups Limits 3/ Min Unit Max 4.5 V 4 2000 mV All V 4.5 V 4 2000 mV All V 5.5 V 2 200 mA All V 5.5 V 2 200 mA All V 5.5 V 2 200 mA All V 5.5 V 2 100 mA All All 4.5 V 7, 8 L H 5.5 V 7, 8 L H 4.5 V 9, 11 10 9 10, 11 9 10, 11 9, 11 10 9 10, 11 9 10, 11 1.0 1.0 1.0 1.0 1.5 1.5 1.0 1.0 1.0 1.0 1.5 1.5 9.0 10.0 9.0 10.0 8.5 9.5 9.0 10.0 9.0 10.0 9.0 10.7 All V 01 M, Q 02 M, Q All V 01 M, Q 02 M, Q 4.5 V ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-89847 A REVISION LEVEL B SHEET 8 TABLE I. Electrical performance characteristics - Continued. Test and ML-STD-883 test method 1/ Propagation delay time, output enable, OE1 and OE2 to mYn 3003 Symbol tPZH Test conditions 2/ -55°C ≤ TC ≤ +125°C +4.5 V ≤ VCC ≤ +5.5 V unless otherwise specified CL = 50 pF RL = 500Ω See figure 5 12/ tPZL CL = 50 pF RL = 500Ω See figure 5 12/ Propagation delay time, output disable, OE1 and OE2 to mYn 3003 tPHZ CL = 50 pF RL = 500Ω See figure 5 12/ tPLZ CL = 50 pF RL = 500Ω See figure 5 12/ Device type and Device class All V 01 M, Q 02 M, Q All V 01 M, Q 02 M, Q All V 01 M, Q 02 M, Q All V 01 M, Q 02 M, Q VCC 4.5 V 4.5 V 4.5 V 4.5 V Group A subgroups 9, 11 10 9 10, 11 9 10, 11 9, 11 10 9 10, 11 9 10, 11 9, 11 10 9 10, 11 9 10, 11 9, 11 10 9 10, 11 9 10, 11 Limits 3/ Min Max 1.0 1.0 1.0 1.0 1.5 1.5 1.0 1.0 1.0 1.0 1.5 1.5 1.0 1.0 1.0 1.0 1.5 1.5 1.0 1.0 1.0 1.0 1.5 1.5 9.0 11.5 9.0 11.5 11.3 13.0 10.0 12.5 10.0 12.5 11.5 11.9 10.5 12.5 10.5 12.5 10.6 11.4 10.5 12.5 10.5 12.5 11.2 12.0 Unit ns ns ns ns 1/ For tests not listed in the referenced MIL-STD-883, (e.g. ∆ICC), utilize the general test procedure under the conditions listed herein. All inputs and outputs shall be tested, as applicable, to the tests in table I herein. 2/ Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits, to the tests in table I herein. Output terminals not designated shall be high level logic, low level logic, or open, except as follows: a. VIC (pos) tests, the GND terminal can be open. TC = +25°C. b. VIC (neg) tests, the VCC terminal shall be open. TC = +25°C. c. All ICC tests, the output terminal shall be open. When performing these tests, the current meter shall be placed in the circuit such that all current flows through the meter. Additional detailed information on qualified devices (i.e. pin for pin conditions and testing sequence) is available from the qualifying activity (DSCC-VQC) upon request. 3/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum and maximum limits, as applicable, listed herein. All devices shall meet or exceed the limits specified in table I, as applicable, at 4.5 V ≤ VCC ≤ 5.5 V. 4/ Transmission driving tests are performed at VCC = 5.5 V with a 2 ms duration maximum. This test may be performed using VIN = VCC or GND. When VIN = VCC or GND is used, the test is guaranteed for VIN = 2.0 V or 0.8 V. 5/ For the IOZH and IOZL tests, three-state outputs are required. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-89847 A REVISION LEVEL B SHEET 9 TABLE I. Electrical performance characteristics - Continued. 6/ Power dissipation capacitance (CPD) determines the no load power consumption, PD = (CPD + CL) (VCC x VCC) f + (ICC x VCC) + (n x d x ∆ICC x VCC). The dynamic current consumption, IS = (CPD + CL) VCCf + ICC + (n x d x ∆ICC). For both PD and IS: n is the number of device inputs at TTL levels; f is the frequency of the input signal; d is the duty cycle of the input signal; and CL is the external output load capacitance. 7/ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. This test may be performed either one input at a time (preferred method) or with all input pins simultaneously at VIN = VCC - 2.1 V (alternate method). Class V shall use the preferred method. When the test is performed using the alternate test method, the maximum limit is equal to the number of inputs at a high TTL input level times 1.6 mA, and the preferred method and limits are guaranteed. 8/ This test is for qualification only. Ground bounce tests are performed on a nonswitching (quiescent) output and are used to measure the magnitude of induced noise caused by other simultaneously switching outputs. The test is performed on a low noise bench test fixture with all outputs fully dc loaded (IOL maximum and IOH maximum = i.e, ±24 mA) and 50 pF of load capacitance (see figure 5). The loads must be located as close as possible to the device output. Inputs are then conditioned with 1 MHz pulse (tr = tf = 3.5 ±1.5ns) switching simultaneously and in phase such that one output is forced low and all others (possible) are switched. The low level ground bounce noise is measured at the quiet output using a F.E.T. oscilloscope probe with at least 1 MΩ impedance. Measurement is taken from the peak of the largest positive pulse with respect to the nominal low level output voltage (see figure 5). The device inputs are then conditioned such that the output under test is at a high nominal VOH level. The high level ground bounce measurement is then measured from nominal VOH level to the largest negative peak. This procedure is repeated such that all outputs are tested at a high and low level with a maximum number of outputs switching. 9/ When used in asynchronous TTL compatible systems, ground bounce (VGBL and VGBH) = 2,000 mV can be a possible problem. 10/ See JEDEC STD. 17 for electrically induced latch-up test methods and procedures. The values listed for Vtrigger, Itrigger and Vover, are to be accurate within ±5 percent. 11/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic patterns used for fault detection. Functional tests shall be performed in sequence as approved by the qualifying activity on qualified devices. H ≥ 2.5 V, L < 2.5; high inputs = 3.0 V and low inputs = 0.4 V. The input voltage levels have the allowable tolerances in accordance with MIL-STD-883 already incorporated. The VIH level used for functional testing shall be 3.0 V ±0 percent. 12/ AC limits at VCC = 5.5 V are equal to limits at VCC = 4.5 V and guaranteed by testing at VCC = 4.5 V. Minimum AC limits for VCC = 5.5 V are 1.0 ns and guaranteed by guardbanding the VCC = 4.5 V minimum limits to 1.5 ns. For propagation delay tests, all paths must be tested. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-89847 A REVISION LEVEL B SHEET 10 Device type 01 Case outlines R, S, 2 Terminal number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 02 L 3 Terminal symbol OE1 1A1 4Y2 2A1 3Y2 3A1 2Y2 4A1 1Y2 GND 1A2 4Y1 2A2 3Y1 3A2 2Y1 4A2 1Y1 OE2 VCC ----------------- 1Y1 2Y1 3Y1 4Y1 GND GND GND GND 1Y2 2Y2 3Y2 4Y2 OE2 4A2 3A2 2A2 1A2 VCC VCC 4A1 3A1 2A1 1A1 OE1 --------- NC VCC 4A1 3A1 2A1 1A1 OE1 NC 1Y1 2Y1 3Y1 4Y1 GND GND NC GND GND 1Y2 2Y2 3Y2 4Y2 NC OE2 4A2 3A2 2A2 1A2 VCC Pin description Terminal symbol Description mAn (m = 1 to 4, n = 1 to 2) Data inputs mYn (m = 1 to 4, n = 1 to 2) Data outputs OE1 Output enable control inputs (active low) OE2 Output enable control inputs (active high) FIGURE 1. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-89847 A REVISION LEVEL B SHEET 11 Device types 01 and 02 Inputs OE1 L L H Outputs OE2 mAn mYn H H L L H X L H Z H = High voltage level. L = Low voltage level. X = Irrelevant Z = High impedance FIGURE 2. Truth table. FIGURE 3. Logic diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-89847 A REVISION LEVEL B SHEET 12 NOTE: Resistance and capacitance tolerances = 10 %. FIGURE 4. Ground bounce load circuit and waveforms. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-89847 A REVISION LEVEL B SHEET 13 NOTES: 1. Preferred method – used for device type 02: When measuring tPLH and tPHL : S1 = open When measuring tPLZ and tPZL : S1 = 2 X VCC When measuring tPHZ and tPZH : S1 = GND 2. Alternate method – used for device type 01: When measuring tPHZ, tPZH, tPLH and tPHL : S1 = open When measuring tPLZ and tPZL : S1 = 2 X VCC 3. CL = 50 pF minimum or equivalent (includes test jig and probe capacitance) 4. RL = 500Ω or equivalent, RT = 50Ω or equivalent 5. Input signal from pulse generator: VIN = 0.0 V to 3.0 V; PRR ≤ 10 MHz; tr ≤ 3 ns; tf ≤ 3 ns; measured from 0.3 V to 2.7 V and from 2.7 V to 0.3 V, respectively; duty cycle = 50 percent. 7. Timing parameters shall be tested at a minimum input frequency of 1 MHz. 8. The outputs are measured one at a time with one transition per measurement. FIGURE 5. Switching waveforms and test circuit. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-89847 A REVISION LEVEL B SHEET 14 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. (2) TA = +125°C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein. 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.3.1 Electrostatic discharge sensitivity qualification inspection . Electrostatic discharge sensitivity (ESDS) testing shall be performed in accordance with MIL-STD-883, method 3015. ESDS testing shall be measured only for initial qualification and after process or design changes which may affect ESDS classification. 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of MIL-PRF-38535 permits alternate in-line control testing. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4.1 Group A inspection a. Tests shall be as specified in table II herein. b. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 2 herein. The test vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2, herein. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-89847 A REVISION LEVEL B SHEET 15 c. CIN COUT and CPD shall be measured only for initial qualification and after process or design changes which may affect capacitance. CIN and COUT shall be measured between the designated terminal and GND at a frequency of 1 MHz. CPD shall be tested in accordance with the latest revision of JEDEC Standard No. 20 and table I herein. For CIN COUT and CPD, test all applicable pins on five devices with zero failures. d. Latch-up and ground bounce tests are required for device class V. These tests shall be performed only for initial qualification and after process or design changes which may affect the performance of the device. Latch-up tests shall be considered destructive. For latch-up and ground bounce tests, test all applicable pins on five devices with zero failures. TABLE II. Electrical test requirements. Test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Subgroups (in accordance with MIL-PRF-38535, table III) Device class M Device class Q Device class V Interim electrical parameters (see 4.2) --- --- 1 Final electrical parameters (see 4.2) 1, 2, 3, 7, 8, 9 1/ 1/ 1, 2, 3, 7 8, 9, 10, 11 2/ 1, 2, 3, 7, 8, 9, 10, 11 Group A test requirements (see 4.4) 1, 2, 3, 4, 7, 9, 10, 11 2/ 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 Group C end-point electrical parameters (see 4.4) 1, 2, 3 1, 2, 3 1, 2, 3, 7,8, 9, 10, 11 Group D end-point electrical parameters (see 4.4) 1, 2, 3 1, 2, 3 1, 2, 3 Group E end-point electrical parameters (see 4.4) 1, 7, 9 1, 7, 9 1, 7, 9 1/ PDA applies to subgroup 1. 2/ PDA applies to subgroups 1 and 7. 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein. 4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883: a. Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. b. TA = +125°C, minimum. c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-89847 A REVISION LEVEL B SHEET 16 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table II herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25°C ±5°C, after exposure, to the subgroups specified in table II herein. c. When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied. 4.5 Methods of inspection. Methods of inspection shall be specified as follows: 4.5.1 Voltage and current. Unless otherwise specified, all voltages given are referenced to the microcircuit GND terminal. Currents given are conventional current and positive when flowing into the referenced terminal. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.1.2 Substitutability. Device class Q devices will replace device class M devices. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished in accordance with MIL-STD-973 using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus when a system application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0674. 6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43216-5000, or telephone (614) 692-0674. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-89847 A REVISION LEVEL B SHEET 17 . STANDARD MICROCIRCUIT DRAWING SOURCE APPROVAL BULLETIN DATE: 00-10-24 Approved sources of supply for SMD 5962-89847 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. Standard microcircuit drawing PIN 1/ Vendor CAGE number 5962-8984701RA 27014 01295 54ACT241DMQB SNJ54ACT241J 5962-8984701SA 27014 01295 54ACT241FMQB SNJ54ACT241W 5962-89847012A 27014 01295 54ACT241LMQB SNJ54ACT241FK 5962-8984701VRA 27014 54ACT241J-QMLV 5962-8984701VSA 27014 54ACT241W-QMLV 5962-8984701V2A 27014 54ACT241E-QMLV 5962-8984702LA 3/ SNJ54ACT11241J 5962-89847023A 3/ SNJ54ACT11241FK Vendor similar PIN 2/ 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the Vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ Not available from an approved source of supply. Vendor CAGE number Vendor name and address 27014 National Semiconductor 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, CA 95052-8090 Point of contact: 5 Foden Road South Portland, ME 04106 01295 Texas Instruments Incorporated 13500 N. Central Expressway P.O. Box 655303 Dallas, TX 75265 Point of contact: 6412 Highway 75 South Sherman, TX 75090-0084 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.