6-Bit Successive Approximation ADC Datasheet SAR6 V 1.5
001-13587 Rev. *G
6-Bit Successive Approximation ADC
Copyright © 2002-2012 Cypress Semiconductor Corporation. All Rights Reserved.
PSoC® Blocks
Resources
Digital
Analog CT
Pins (per
External I/O
and Clock)
API Memory (Bytes)
Analog SC
Flash
RAM
CY8C29/27/26/25/24/22x13, CY8CLED04/08/16, CY8CLED0xD, CY8CLED0xG, CY8CTST120, CY8CTMG120,
CY8CTMA120, CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28x43, CY8C28x52
0
0
1
58
0
1
See AN2239, ADC Selection Guide for other converters.
For one or more fully configured, functional example projects that use this user module go to
www.cypress.com/psocexampleprojects.
Features and Overview
6-bit resolution
Single PSoC block
Conversion time of 25 µs, typical
API optimized to help minimize aperture jitter
The SAR6 User Module converts an input voltage to a digital code, using a single switched-capacitor
analog PSoC block. It features typical conversion times of 25 μs, producing a 2’s complement value in the
closed interval of [-32..+31] for each sample. The SAR6 Application Programming Interface (API) provides
a time-equalized function, so that synchronous sampling can be managed by a timing loop for minimum
aperture jitter.
Figure 1.
SAR6 Block Diagram
Cypress Semiconductor Corporation
Document Number: 001-13587 Rev. *G
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Revised October 8, 2012
6-Bit Successive Approximation ADC
Functional Description
The acronym SAR stands for “successive approximation register." In this case, the register holding the
result of the conversion is the PSoC block’s CR0 register. The basic operating principle is the formation of
a series of approximations by scaling the reference voltage, RefHigh, and subtracting it from the input
voltage. When the scaled reference matches the input voltage, the difference is zero, or equal to analog
ground within the limits of 6-bit resolution.
Binary search reduces the number of approximations required and thus, the total conversion time. This
procedure first determines the sign of the input voltage by setting the five ACap MAGNITUDE bits in figure
below to zero, while holding BCap at its maximum fixed value. A comparator in the switched-cap PSoC
block drives the column comparator bus. Because the inverting terminal of the opamp is used when the
comparator output is high, the input voltage is negative with respect to AGND. The procedure then sets
SIGN, so that the reference voltage impressed across the ACap opposes the input voltage across BCap.
The second approximation sets ACap to half its maximum capacitance, by turning the most significant
MAGNITUDE bits on. The resulting value on the comparator bus determines whether the next adjustment
to ACap will be up or down by a quarter, to either ¼ or ¾ of its maximum value. Down to ¼ entails turning
the previous MAGNITUDE bit off and the next most significant bit on. Up to ¾ leaves the previous
MAGNITUDE bit "as is" and sets the next most significant bit on. The binary search continues to refine its
approximation of the input voltage in this way, until the SIGN and all 5 MAGNITUDE bits are determined.
The result is converted into a 1-byte 2’s complement value.
Figure 2.
Simplified Schematic of the SAR6
In the ideal case,
Equation 1
As a result:
Equation 2
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6-Bit Successive Approximation ADC
BCap is fixed at its maximum value of 31. Thus, the output code represents, in absolute terms, a
comparison of the input to the reference voltage scaled by ±(0..31)/31.
Φ1 and Φ2 are two clock signals generated from the analog block's input clock. Their frequency is equal to
the input clock frequency divided by four. Φ1 and Φ2 have the same frequency but are 180º out of phase.
For more information on Φ1 and Φ2 see the PSoC Technical Reference Manual.
DC and AC Electrical Characteristics
The following values are indicative of expected performance and based on initial characterization data.
Unless otherwise specified in the table below, TA = 25ºC, Vdd = 5.0V, Power HIGH, OpAmp bias LOW,
output referenced to 2.5V external Analog Ground on P2[4] with 1.25 external Vref on P2[6].
Table 1.
5.0V SAR6 DC and AC Electrical Characteristics
Parameter
Typical
Limit
Units
Conditions and Notes
INPUT
Input Range
--
Vss to Vdd
Ref Mux = Vdd/2 ± Vdd/2
Input Capacitance
3
--
pF
Input Impedance
1/(C*clk)1
--
Ω
tconvert, Conversion Time
--
20
µs
12 MHz CPU, fclock = 250 kHz
24 MHz CPU, fclock = 333 kHz
fclock, Internal Update Rate
--
32 to 333
kHz
Column Clock ÷4
Resolution
--
6
Bits
DNL
.25
--
LSB
INL
.75
--
LSB
VOS, Offset Voltage6
8
--
mV
Including Reference Gain Error
1.5
--
% FSR
Excluding Reference Gain Error3
0.4
--
% FSR
Low Power
140
--
µA
Med Power
510
--
µA
High Power
1890
--
µA
DC Accuracy
Column Clock 1.33 MHz
Gain Error
Operating Current
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6-Bit Successive Approximation ADC
The following values are indicative of expected performance and based on initial characterization data.
Unless otherwise specified in the table below, all limits guaranteed for TA = 25ºC, Vdd = 3.3V, Power
HIGH, OpAmp bias LOW, output referenced to 1.64V external Analog Ground on P2[4] with 1.25 external
Vref on P2[6].
Table 2.
3.3V SAR6 DC and AC Electrical Characteristics
Parameter
Typical
Limit
Units
Conditions and Notes
INPUT
Input Range
--
Vss to Vdd
Ref Mux = Vdd/2 ± Vdd/2
Input Capacitance
3
--
pF
Input Impedance
1/(C*clk)1
--
Ω
tconvert, Conversion Time
--
20
µs
12 MHz CPU, fclock = 250 kHz
fclock, Internal Update Rate
--
32 to 333
kHz
Column Clock ÷4
Resolution
--
6
Bits
DNL
.25
--
LSB
INL
.75
--
LSB
VOS, Offset Voltage6
8
--
mV
Including Reference Gain Error
3.5
--
% FSR
Excluding Reference Gain Error3
2.4
--
% FSR
Low Power
140
--
µA
Med Power
500
--
µA
High Power
1840
--
µA
DC Accuracy
Column Clock 1.33 MHz
Gain Error
Operating Current
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6-Bit Successive Approximation ADC
Unless otherwise specified in the table below, all limits guaranteed for TA = -40ºC to +85ºC, Vdd = 4.75V to
5.5V, Power HIGH, OpAmp bias LOW, output referenced to 2.5V external Analog Ground on P2[4] with
1.25 external Vref on P2[6].
Table 3.
5.0V SAR6 DC and AC Electrical Characteristics
Typical4
Parameter
Limit5
Units
Conditions2,3 and Notes
INPUT
Input Range3
--
Vss to Vdd
Vdd/2 +/- Vdd/2
Input Capacitance4
0.8
--
pF
Input Impedance5,6
1/(C*clk)1
--
Ω
Resolution
--
6
Bits
2s Complement
tconvert, Conversion Time
--
20
µs
12 MHz CPU, fclock = 250 kHz
24 MHz CPU, fclock = 333 kHz
fclock, Internal Update Rate7
--
32 to 333
kHz
Resolution
--
6
Bits
INL
.03
.08
LSB
DNL
.02
.05
LSB
Monotonicity
--
½
Bit
Gain Error
1.0
2.5
%FSR
VOS, Offset Voltage6
8
43
mV
Low Power
125
--
µA
Med Power
280
--
µA
High Power
780
1000
µA
DC ACCURACY
OPERATING CURRENT8
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6-Bit Successive Approximation ADC
Unless otherwise specified in the table below, all limits guaranteed for TA = -40ºC to +85ºC, Vdd = 3.0V to
3.6V, Power HIGH, OpAmp bias LOW, output referenced to 1.64V external Analog Ground on P2[4] with
1.25 external Vref on P2[6].
Table 4.
3.3V SAR6 DC and AC Electrical Characteristics
Parameter
Typical
Limit
Units
Conditions2 and Notes
INPUT
Input Range3
--
Vss to Vdd
Vdd/2 ± Vdd/2
Input Capacitance4
0.8
--
pF
Input Impedance5,6
1/(C*clk)1
--
Ω
Resolution
--
6
Bits
2’s Complement
tconvert, Conversion Time
--
20
µs
12 MHz CPU, fclock = 250 kHz
fclock, Internal Update Rate
--
32 to 333
kHz
Column Clock ÷4
Resolution
--
6
Bits
INL
.04
.09
LSB
DNL
.02
.04
LSB
Monotonicity
--
½
Bit
Gain Error
1.0
2.5
%FSR
VOS, Offset Voltage
7
31
mV
Low Power
100
--
µA
Med Power
250
--
µA
High Power
640
900
µA
DC ACCURACY
Operating Current
Electrical Characteristics Notes
1. clk = (column clock)/4 = fclock/4; C = Total capacitance of the input capacitor. For this user module, the
input capacitance of the block is 31*Csc. Csc is the "Capacitor unit value" and is available in the
respective silicon datasheet.
2. fclock = 125 kHz, external AGND 2.50V, external VRef 1.23V, unless otherwise noted.
3.
4.
5.
6.
REFPWR = HIGH, SCPOWER = ON, PSoC block power HIGH, unless otherwise noted.
Typical values represent statistical mean plus 1σ.
Limits guaranteed by testing or statistical analysis.
Two’s complement zero scale offset to external AGND. Does not include analog output buffer offset
error.
7. Limit for Φ1, Φ2 specified for 3 dB increase in broadband noise.
8. PSoC block current requirements exclusive of reference current.
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6-Bit Successive Approximation ADC
Placement
The SA block can be placed in any of the switched capacitor PSoC blocks. However, it will require the
comparator bus for the particular column to which it is connected. Other user modules that require use of
the column comparator cannot be placed in the same column.
Parameters and Resources
The SAR6 maps onto any switched-capacitor PSoC block. The only requirement is that the comparator
bus in that column is not allocated to another user module in the same configuration. The SAR6
symbolically names its switched-capacitor PSoC™ block SA. After placing SA with the Device Editor, its
SignalSource must be set to complete its configuration. Additional tasks include configuring associated
pins, multiplexors and/or other PSoC blocks to deliver the input to SA, and setting up a source clock for
the column in which SA resides.
SignalSource
The Device Editor restricts input selections to the connections possible for the particular PSoC block
onto which SA is mapped. In general, input ports may be directly accessible or that the input must
come from another switched capacitor (SC) or continuous time (CT) PSoC block. Although it may be
possible to connect an input to an unmapped and unconfigured PSoC block, the selection should be
planned for a block that will provide a useful input, such as filters and amplifiers.
A successive approximation register type ADC, requires that the input signal is stable during the
conversion. This implementation of a SAR, does not contain an internal sample and hold circuit to
stabilize the input during conversion. This means that the input voltage should not change more than
50 percent of the LSB during conversion. For example, if the Reference multiplexor is set at (Vdd/2)
+/- BandGap, one LSB is equal to about 1.3V/32 or about 40 mV. With this setting, the input should
not deviate more than 20 mV during the conversion. The actual conversion period is six times the
period of the sample clock (Φ1/Φ2) which is one fourth of the analog column clock. If the analog
column clock is set at 1 MHz, the sample clock will be 250 kHz. So the conversion time will be 6 times
the sample clock period ( 6 * 1/250 kHz) or 24 μS.
Analog Column Clock
The analog column clock multiplexors select the source clock used to generate the phase clocks, Φ1
and Φ2, that control each successive approximation step. The phase clock generator divides the
column clock by four to produce Φ1 and Φ2, so the column clock frequency is four times faster than
the actual analog step approximation rate. Two levels of multiplexing provide choices for the column
clock that include any of the digital blocks and the system clock dividers. The Electrical Characteristics
section, above, specifies lower and upper limits for the column clock frequency.
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6-Bit Successive Approximation ADC
Application Programming Interface
The Application Programming Interface (API) routines are provided as part of the user module to allow the
designer to deal with the module at a higher level. This section specifies the interface to each function
together with related constants provided by the “include" files.
Each time a user module is placed, it is assigned an instance name. By default, PSoC Designer assigns
the SAR6_1 to the first instance of this user module in a given project. It can be changed to any unique
value that follows the syntactic rules for identifiers. The assigned instance name becomes the prefix of
every global function name, variable and constant symbol. In the following descriptions the instance name
has been shortened to SAR6 for simplicity.
Note
In this, as in all user module APIs, the values of the A and X register may be altered by calling an API
function. It is the responsibility of the calling function to preserve the values of A and X prior to the call if
those values are required after the call. This “registers are volatile" policy was selected for efficiency
reasons and has been in force since version 1.0 of PSoC Designer. The C compiler automatically takes
care of this requirement. Assembly language programmers must ensure their code observes the policy,
too. Though some user module API function may leave A and X unchanged, there is no guarantee they
will do so in the future.
For Large Memory Model devices, it is also the caller's responsibility to preserve any value in the
CUR_PP, IDX_PP, MVR_PP, and MVW_PP registers. Even though some of these registers may not be
modified now, there is no guarantee that will remain the case in future releases.
Entry points are provided to initialize the SAR6 User Module, perform and read conversions, and disable
the SAR6 function.
SAR6_Start
Description:
Performs all required initialization for this user module and sets the power level for the switched
capacitor PSoC block.
C Prototype:
void
SAR6_Start(BYTE bPowerSetting)
Assembler:
mov
A, bPowerSetting
lcall SAR6_Start
Parameters:
bPowerSetting: One byte that specifies the power level. Following reset and configuration, the PSoC
block assigned to the SAR is powered down. Symbolic names, provided in C and assembly, and their
associated values, are given in the following table.
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6-Bit Successive Approximation ADC
Symbolic Name
Value
SAR6_OFF
0
SAR6_LOWPOWER
1
SAR6_MEDPOWER
2
SAR6_HIGHPOWER
3
Returns:
None
Side Effects:
The comparator bus will be driven. The A and X registers may be altered by this function.
SAR6_SetPower
Description:
Sets the power level for the switched capacitor PSoC block. May be used to turn the block off and on.
C Prototype:
void
SAR6_SetPower(BYTE bPowerSetting)
Assembler:
mov
A, bPowerSetting
lcall SAR6_SetPower
Parameters:
bPowerSetting: Same as the PowerSetting parameter used for the Start entry point.
Returns:
None
Side Effects:
The comparator bus will be driven. The A and X registers may be altered by this function.
SAR6_cGetSample
Description:
Performs a conversion, returning a 2’s complement value representing the ratio of the input voltage
to the reference voltage, both relative to analog ground.
C Prototypes:
CHAR
SAR6_cGetSample(void)
Assembler:
lcall SAR6_cGetSample
mov
[abResultBuffer], A
Parameters:
None
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6-Bit Successive Approximation ADC
Returns:
Returns the sample value.
Side Effects:
The A and X registers may be altered by this function.
SAR6_Stop
Description:
Powers the user module off.
C Prototype:
void
SAR6_Stop()
Assembler Macro:
lcall
SAR6_Stop
Parameters:
None
Returns:
None
Side Effects:
The A and X registers may be altered by this function.
Sample Firmware Source Code
The sample code given here illustrates the use of a PGA to buffer an input signal that is then converted to
a digital value by the SAR6 User Module. The code drives the result onto Port 2 with a “data valid" strobe
applied to the high-order bit of Port 1.
For proper functionality, all Port 2 pins and P1[7] must be configured for strong drive mode. Additionally, a
PGA User Module must be added to the project that passes an external signal on Port 0 to the input of the
SAR6 ADC.
;;; SAR6 Example Code
;;;
;;; Send a stream of samples to Port 2 with a data-valid
;;; (rising edge) strobe on P1[7].
;;;
;;;
;;;
include "m8c.inc"
; part specific constants and macros
include "memory.inc"
; Constants & macros for SMM/LMM and Compiler
include "PSoCAPI.inc"
; PSoC API definitions for all user modules
export _main
_main:
mov A, PGA_HIGHPOWER
call PGA_Start
Document Number: 001-13587 Rev. *G
; Start PGA with HIGH power setting
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6-Bit Successive Approximation ADC
mov A, SAR6_HIGHPOWER
call SAR6_Start
mov reg[PRT2DR], 00h
mov reg[PRT1DR], 80h
; Start ADC with HIGH power setting
; Set Port 2 initial value
; Initialize data valid strobe on P1[7]
loop:
xor reg[PRT1DR], 80h
call SAR6_cGetSample
mov reg[PRT2DR], A
xor reg[PRT1DR], 80h
jmp loop
;
;
;
;
;
De-assert data valid strobe
Get one ADC sample
Applied sample value to Port 2
Assert strobe for data valid
Repeat the loop
The same Program in C is:
//-------------------------------------------------------------------// C Example
//
// Write data from SAR6 to Port 2 and toggle a strobe pin on P1[7].
//-------------------------------------------------------------------#include <m8c.h>
#include "PSoCAPI.h"
void main(void)
{
char bResult;
// This variable holds the ADC sample
PGA_Start(PGA_HIGHPOWER);
// Start PGA in HIGH power mode
SAR6_Start(SAR6_HIGHPOWER);
// Start ADC in HIGH power mode
PRT2DR = 0x00;
PRT1DR = 0x80;
// Set Port 2 initial value
// Init data valid strobe on P1[7]
while(1)
// Loop forever
{
PRT1DR ^= 0x80;
// De-assert the data valid strobe
bResult = SAR6_cGetSample();
// Get one ADC sample
PRT2DR = bResult;
// Write sample data to Port 2
PRT1DR ^= 0x80;
// Assert data valid strobe
}
}
Configuration Registers
The following registers are used for the SAR6 switched capacitor SA block.
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6-Bit Successive Approximation ADC
Table 5.
Block SA, mapped to a Switched Capacitor Type SCA or SCC PSoC Block
Bit
7
6
5
4
3
2
1
0
CR0
0
0
Sign and Magnitude[5:0]
CR1
0
1
0
1
1
1
1
1
CR2
0
1
0
0
0
0
0
0
CR3
0
0
0
0
Input Select
Table 6.
Power
Block SA, mapped to a Switched Capacitor Type SCB or SCD PSoC Block
Bit
7
6
5
4
3
2
1
0
CR0
0
0
Sign and Magnitude[5:0]
CR1
0
1
0
1
1
1
1
1
CR2
0
1
0
0
0
0
0
0
CR3
0
0
0
0
0
Input
Select
Power
The Sign and Magnitude bit field is manipulated directly by the hardware and the API.
The Input Selector field is initialized by the Device Editor as determined by the InputSource parameter.
The Input Selector field is initialized by the Device Editor as determined by the InputSource parameter.
Power: 0 = Off, 1 = Low, 2 = Medium, 3 = Full. Default is off. To set, use the Start call in the API.
Version History
Version Originator
1.5
Note
DHA
Description
Added Version History
PSoC Designer 5.1 introduces a Version History in all user module datasheets. This section documents high level descriptions of the differences between the current and previous user module versions.
Document Number: 001-13587 Rev. *G
Revised October 8, 2012
Page 12 of 12
Copyright © 2002-2012 Cypress Semiconductor Corporation. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems
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assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.