INTEGRATED CIRCUITS PCK2021 CK00 (100/133 MHz) spread spectrum differential system clock generator Product data File under Integrated Circuits, ICL03 2001 Oct 11 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator FEATURES PCK2021 PIN CONFIGURATION • 3.3 V operation • Six differential CPU clock pairs • Two PCI clocks at 33 MHz and one 3V66 clock • Two 48 MHz clocks at 3.3 V • One 14.318 MHz reference clock • Power management control pins • Host clock jitter less than 200 ps cycle-to-cycle • Host clock skew less than 150 ps pin-to-pin • Spread Spectrum capability • Optimized frequency and spread spectrum performance VDDPCI 1 48 PCI0 VDD48 2 47 PCI1 48M_0/SELA 3 46 VSSPCI 48M_1/SELB 4 45 SEL133/100 VSS48 5 44 NC 3V66 6 43 VDDA VSS3V66 7 42 VSSA VDD3V66 8 41 PWRDWN VDDCPU 9 40 VDDCPU HCLK0 10 HCLKB0 11 VDDCPU 12 HCLK1 13 DESCRIPTION The PCK2021 is a clock synthesizer/driver for a Pentium III and other similar processors. The PCK2021 has six differential pair CPU current source outputs, two 33 MHz outputs, one 3V66 output, and two 48 MHz clocks which can be disabled on power-up, and one 3.3 V reference clock at 14.318 MHz which can also be disabled on power-up. 38 HCLKB3 37 VDDCPU 36 HCLK4 HCLKB1 14 35 HCLKB4 VSSCPU 15 34 VSSCPU HCLK2 16 33 HCLK5 HCLKB2 17 VDDCPU 18 The part possesses a dedicated power-down input pin for power management control. This input is synchronized on chip, and ensures glitch-free output transitions. In addition, the part can be configured to disable the 48 MHz outputs for lower power operation and an increase in the performance of the functioning outputs. The REF and PCI outputs can also be disabled for the highest performance of the Host outputs. 39 HCLK3 32 HCLKB5 31 VDD REF 19 30 MULTSEL0 SPREAD 20 29 MULTSEL1 VSSREF 21 XIN 22 XOUT 23 VDDREF 24 28 VSS 27 VSSIREF 26 IREF 25 VDDIREF SW00960 ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 48-Pin Plastic TSSOP 0 to +70 °C PCK2021DGG SOT362-1 48-Pin Plastic SSOP 0 to +70 °C PCK2021DL SOT370-1 Intel and Pentium III are trademarks of Intel Corporation. 2001 Oct 11 2 853-2301 27233 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 PIN DESCRIPTION PIN(S) SYMBOL FUNCTION 1, 2, 8, 9, 12, 18, 24, 25, 31, 37, 40 VDD 3.3 V power supply Pins 9, 12, and 18 supply host output pairs 0, 1, and 2. Pins 37 and 40 supply host output pairs 3, 4, and 5. 3, 4 48M_0/SELA 48M_1/SELB 3.3 V fixed 48 MHz clock outputs. During power-up pins function as latched inputs that enable SELA and SELB prior to the pins being used for output of 3 V at 48 MHz. Part must be clocked to latch data in. 6 3V66 66 MHz clock: 66 MHZ reference clock 10, 11 HCLK0 HCLKB0 Host output pair 0 13, 14 HCLK1 HCLKB1 Host output pair 1 16, 17 HCLK2 HCLKB2 Host output pair 2 47, 48 PCI0 PCI1 33 MHz clocks: 33 MHz reference clocks 39, 38 HCLK3 HCLKB3 Host output pair 3 36, 35 HCLK4 HCLKB4 Host output pair 4 33, 32 HCLK5 HCLKB5 Host output pair 5 19 REF 3.3 V fixed 14.318 MHz output 20 SPREAD Enables spread spectrum mode when held LOW on differential host outputs, 3V66 and PCI clocks. Asserts LOW. 22 XIN Crystal input 23 XOUT Crystal output 26 IREF This pin controls the reference current for the host pairs. This pin requires a fixed precision resistor tied to ground in order to establish the correct current. 29, 30 MULTSEL0 MULTSEL1 Select input pin used to control the scaling of the HCLK and HCLKB output current. 41 PWRDWN Device enters power-down mode when held LOW. Asserts LOW. 45 SEL133/100 Select input pin for enabling 133 MHz or 100 MHz CPU outputs 5, 7, 15, 21, 27, 28, 34, 46 VSS Ground 43 VDDA 3.3 V power supply for analog circuits 42 VSSA Ground for analog circuits 2001 Oct 11 3 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 BLOCK DIAGRAM REF[0] (14.318 MHz) PWRDWN XIN SELC 14.318 MHz OSC XOUT USB PLL 48MHz[0..1] (3 V) PWRDWN SELA/B HOST[0..5] (100/133 MHz) PWRDWN IREF IBIAS PWRDWN HOST_BAR[0..5] (100/133 MHz) PWRDWN PCI[0..1] (33 MHz) PWRDWN 3V66[0] (66 MHz) SYS PLL PWRDWN SEL133/100 LOGIC SPREAD MULTSEL0 MULTSEL1 SW00961 FUNCTION TABLE SEL100/133 SELA SELB HOST 48MHz PCI33MHz 66MHz REFCLK 0 0 0 0 0 1 100 MHz 48 MHz 33.3 MHz 66.7 MHz 14.3 MHz 100 MHz Disable/Low 33.3 MHz 66.7 MHz 14.3 MHz 0 1 0 1 0 100 MHz Disable/Low Disable/Low 66.7 MHz Disable/Low 1 Hi-Z Hi-Z Hi-Z Hi-Z 1 Hi-Z 0 0 133 MHz 48 MHz 33.3 MHz 66.7 MHz 14.3 MHz 1 0 1 133 MHz Disable/Low 33.3 MHz 66.7 MHz 14.3 MHz 1 1 0 200 MHz 48 MHz 33.3 MHz 66.7 MHz 14.3 MHz 2001 Oct 11 4 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 Table 1. Host swing select functions MULTSEL0 MULTSEL1 BOARD IMPEDANCE IREF IOH VOH @ IREF = 2.32 mA 0 0 60 Ω RREF = 475 1% IREF = 2.32 mA IOH = 5*IREF 0.71 V 0 0 50 Ω RREF = 475 1% IREF = 2.32 mA IOH = 5*IREF 0.59 V 0 1 60 Ω RREF = 475 1% IREF = 2.32 mA IOH = 6*IREF 0.85 V 0 1 50 Ω RREF = 475 1% IREF = 2.32 mA IOH = 6*IREF 0.71 V 1 0 60 Ω RREF = 475 1% IREF = 2.32 mA IOH = 4*IREF 0.56 V 1 0 50 Ω RREF = 475 1% IREF = 2.32 mA IOH = 4*IREF 0.47 V 1 1 60 Ω RREF = 475 1% IREF = 2.32 mA IOH = 7*IREF 0.99 V 1 1 50 Ω RREF = 475 1% IREF = 2.32 mA IOH = 7*IREF 0.82 V 0 0 30 Ω RREF = 221 1% IREF = 5 mA IOH = 5*IREF 0.75 V 0 0 25 Ω RREF = 221 1% IREF = 5 mA IOH = 5*IREF 0.62 V 0 1 30 Ω RREF = 221 1% IREF = 5 mA IOH = 6*IREF 0.90 V 0 1 25 Ω RREF = 221 1% IREF = 5 mA IOH = 6*IREF 0.75 V 1 0 30 Ω RREF = 221 1% IREF = 5 mA IOH = 4*IREF 0.60 V 1 0 25 Ω RREF = 221 1% IREF = 5 mA IOH = 4*IREF 0.50 V 1 1 30 Ω RREF = 221 1% IREF = 5 mA IOH = 7*IREF 1.05 V 1 1 25 Ω RREF = 221 1% IREF = 5 mA IOH = 7*IREF 0.84 V MIN. MAX. NOTE: The outputs are optimized for the configurations shown shaded. CONDITIONS CONFIGURATION LOAD IOUT VDD = 3.3 V All combinations; see Table 1 above Nominal test load for given configuration –7% of IOH see Table 1 above +7% of IOH see Table 1 above IOUT VDD = 3.3 V ±5% All combinations; see Table 1 above Nominal test load for given configuration –12% of IOH see Table 1 above +12% of IOH see Table 1 above POWER-DOWN MODE PWRDWN HCLK/HCLKB 3V66 PCI Asserts LOW Host = 2*IREF LOW LOW 0 = Active Host_bar = undriven NOTE: The differential outputs should have a voltage forced across them when power-down is asserted. 48MHz REFCLK LOW LOW SPREAD SPECTRUM FUNCTION 2001 Oct 11 SPREAD # FUNCTION 48 MHz PLL REFCLK 1 Host, PCI, and 3V66 No Spread No Spread 0 Host, PCI, and 3V66 spread t0.5% No Spread 5 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 ABSOLUTE MAXIMUM RATINGS SYMBOL VDD3 PARAMETER CONDITIONS DC 3.3 V supply IIK DC input diode current VI DC input voltage IOK DC output diode current VO DC output voltage IO DC output source or sink current Tstg Storage temperature range Ptot Power dissipation per package plastic medium-shrink (TSSOP) LIMITS MIN MAX UNIT –0.5 4.6 V VI < 0 — –50 mA Note 2 –0.5 VDD V VO > VDD or VO < 0 — ±50 mA Note 2 –0.5 VDD+0.5 V VO = 0 to VDD — ±50 mA –65 +150 °C — 850 mW For temperature range 0 °C to +70 °C; above +55 °C derate linearly with 11.3 mW/K NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated under “recommended operating condition” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage rating may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS LIMITS MIN MAX UNIT VDD3 DC 3.3 V supply voltage 3.135 3.465 V AVDD DC 3.3 V analog supply voltage 3.135 3.465 V 1 device load, possible 2 10 30 pF Must meet JEDEC PCI 2.1 Spec. Requirements 10 30 pF 48 MHz clock 1 device load 10 20 pF REF 1 device load 10 20 pF 14.31818 14.31818 MHz 0 +70 °C Capacitive load on: 3V666 CL fref Tamb PCI Reference frequency, oscillator normal value Operating ambient temperature range in free air POWER MANAGEMENT CONDITION MAXIMUM 3.3 V SUPPLY CONSUMPTION MAXIMUM DISCRETE CAPACITANCE LOADS VDDL = 3.465 V ALL STATIC INPUTS = VDD3 OR VSS Power-down mode (PWRDWN = 0) 60 mA Full active 100/133 MHz 250 mA 2001 Oct 11 6 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 DC ELECTRICAL CHARACTERISTICS Tamb = 0 to +70 °C SYMBOL PARAMETER CONDITIONS VDD (V) LIMITS OTHER MIN TYP MAX UNIT VIH HIGH level input voltage 3.135 to 3.465 2.0 — VDD+0.3 V VIL LOW level input voltage 3.135 to 3.465 VSS–0.3 — 0.8 V VOH3 3.3 V output HIGH voltage REF, 48M 3.135 to 3.465 IOH = –1 mA 2.0 — — V VOL3 3.3 V output LOW voltage REF, 48M 3.135 to 3.465 IOH = 1 mA — — 0.4 V VOHP 3.3 V output HIGH voltage 3V66/PCI 3.135 to 3.465 IOH = –1 mA 2.4 — — V VOLP 3.3 V output LOW voltage 3V66/PCI 3.135 to 3.465 IOH = 1 mA — — 0.55 V Output HIGH current 3V66/PCI 3.135 VOUT = 1.0 V –33 — — mA 3.465 VOUT = 3.135 V Type y 5 12 – 55 Ω — — –33 mA IOH O Output HIGH current 48 MHz, REF 3.135 VOUT = 1.0 V — — mA 3.465 VOUT = 3.135 V Type y 3 20 – 60 Ω –29 — — –23 mA IOH O Output HIGH current HOST/HOST_BAR 11 — — mA — — 12.7 mA IOL O Output LOW current 3V66/PCI 3.135 VOUT = 1.95 V — — mA VOUT = 0.4 V Type y 5 12 – 55 Ω 30 3.465 — — 38 mA Output LOW current 48 MHz, REF 3.135 VOUT = 1.95 V — — mA 3.465 VOUT = 0.4 V Type y 3 20 – 60 Ω 29 — — 27 mA VSS = 0 V RS = 33.2 Ω RP = 49.9 Ω Type X1 — — 0 05 0.05 V 3.465 0 < VIN < VDD3 –50 — 50 µA 3.465 VOUT = VDD or GND — — 101 µA IOH O IOL O VOL O ±II HOST/HOST BAR HOST/HOST_BAR Input leakage current ±IOZ 3-State output OFF-State current 3 135 to 3 3.135 3.465 465 0.66 V 0.76 V Type X1 IO = 0 Cin Input pin capacitance — — 5 pF Cout Output pin capacitance — — 6 pF Cxtal Crystal input capacitance 13.5 — 22.5 pF NOTE: 1. REF output limit is 100 mA. 2001 Oct 11 7 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 AC ELECTRICAL CHARACTERISTICS VDD3 = 3.3 V ±5%; fcrystal = 14.31818 MHz Host clock outputs Tamb = 0 to +70 °C; see Figure 1 for waveforms and Figure 6 for test setup. LIMITS 133 MHz MODE 100 MHz MODE MIN MAX MIN MAX HOST CLK average period 7.5 7.65 10.0 Absolute minimum host clock period 7.35 N/A 9.85 tRISE HOST CLK rise time 175 700 tFALL HOST CLK fall time 175 700 HOST_CLK cycle-to-cycle jitter — Output duty cycle 45 SYMBOL tPERIOD Abs Min Period tJITTER DUTY CYCLE tSKEW PARAMETER HOST CLK pin-to-pin skew Vcrossover UNITS NOTES 10.2 ns 11, 14, 19 N/A ns 11, 14, 19 175 700 ns 11, 15, 19 175 700 ps 11, 15, 19 150 — 150 ps 11, 12, 14, 19 55 45 55 % 11, 14, 19 — 150 — 110 ps 11, 14, 19 45% VOH 55% VOH 45% VOH 55% VOH V 11, 14, 19 UNITS NOTES MHz 4 REFER TO NOTES ON PAGE 10. USB clock output, 48MHz Tamb = 0 to +70 °C; lump capacitance test load = 20 pF LIMITS SYMBOL 48 MHz MODE PARAMETER MIN MAX f Frequency, actual fD Deviation from 48 MHz –0 +167 ppm 4 tRISE 3V48MHZCLK rise time 1.0 4.0 ns 8, 19 tFALL 3V48MHZCLK fall time 1.0 4.0 ns 8, 19 Cycle-to-cycle jitter — 450 ps 17, 19 Output duty cycle 45 55 % 17, 19 UNITS NOTES tJITTER DUTY CYCLE 48.000 REFER TO NOTES ON PAGE 10. PCI Outputs Tamb = 0 to +70 °C SYMBOL tPERIOD LIMITS PARAMETER MIN MAX Period 30.0 N/A ns 2, 3, 9, 19 tHIGH High time 12.0 N/A ns 5, 10, 19 6, 10, 19 tLOW Low time 12.0 N/A ns tRISE Rise time 0.5 2.0 ns 8, 19 tFALL Fall time 0.5 2.0 ns 17, 19 DUTY CYCLE Duty cycle 45 55 % 17, 19 tJITTER Cycle-to-cycle jitter — 200 ps 17, 19 tSKEW Pin-to-pin skew — 150 ps 2 REFER TO NOTES ON PAGE 10. 2001 Oct 11 8 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 3V66 Outputs Tamb = 0 to +70 °C SYMBOL LIMITS PARAMETER UNITS NOTES 16.0 ns 2, 3, 9, 19 5.25 N/A ns 5, 10, 19 5.05 N/A ns 6, 10, 19 Rise time 0.5 2.0 ns 8, 19 Fall time 0.5 2.0 ns 17, 19 Duty cycle 45 55 % 17, 19 Cycle-to-cycle jitter — 400 ps 17, 19 UNITS NOTES MIN MAX Period 15.0 tHIGH High time tLOW Low time tRISE tFALL tPERIOD DUTY CYCLE tJITTER REFER TO NOTES ON PAGE 10. REF clock output Tamb = 0 to +70 °C; lump capacitance test load = 20 pF LIMITS SYMBOL 48 MHz MODE PARAMETER MIN MAX f Frequency, actual MHz 16, 19 tJITTER Cycle-to-cycle jitter — 300 ps 17, 19 Output duty cycle 45 55 % 17, 19 UNITS NOTES 19 DUTY CYCLE 14.318 REFER TO NOTES ON PAGE 10. All outputs Tamb = 0 to +70 °C LIMITS SYMBOL PARAMETER 133 MHz MODE 100 MHz MODE MIN MAX MIN MAX tPZL, tPZH Output enable delay (all outputs) 1.0 10.0 1.0 10.0 ns tPZL, tPZH Output disable delay (all outputs) 1.0 10.0 1.0 10.0 ns 19 All clock stabilization from power-up — 3 — 3 ms 7, 19 tSTABLE REFER TO NOTES ON PAGE 10. 2001 Oct 11 9 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 Group offset limits GROUP OFFSET MEASUREMENT LOADS (LUMPED) MEASUREMENT POINTS NOTES 3V66 to PCI 0–500 ps, 3V66 leads 30 pF 1.5 V 18, 19 NOTES TO THE AC TABLES: 1. Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels. 2. Period, jitter, offset, and skew measured on rising edge at 1.5 V for 3.3 V clocks. 3. PCI is a fixed 33 MHz and 3V66 is a fixed 66 MHz. 4. Frequency accuracy of 48 MHz must be +167 ppm to match USB default. 5. tHIGH is measured at 2.4 V for 3.3 V outputs, as shown in Figure 7. 6. tLOW is measured at 0.4 V for all outputs as shown in Figure 7. 7. the time is specified from when VDDQ achieves its normal operating level (typical condition VDDQ = 3.3 V) until the frequency output is stable and operating within specification. 8. tRISE and tFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1 mA) JEDEC specification. 9. The average period over any 1 µs period of time must be greater than the minimum specified period. 10. Calculated at minimum edge rate (1 V/ns) to guarantee 45–55% duty cycle. Pulse width is required to be wider at faster edge rate to ensure duty specification is met. 11. Test load is RS = 33.2 Ω, RP = 49.9 Ω. 12. Must be guaranteed in a realistic system environment. 13. Configured for VOH = 0.71 V in a 50 Ω environment. 14. Measured at crossing points. 15. Measured at 20% to 80%. 16. Frequency generated by crystal oscillator 17. Voltage measure point (VM = 1.5 V). 18. All offsets are to be measured at rising edges. 19. Parameters are guaranteed by design. 2001 Oct 11 10 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 AC WAVEFORMS VM = 1.25 V @ VDDL and 1.5 V @ VDD3 VX = VOL + 0.3 V VY = VOH – 0.3 V VOL and VOH are the typical output voltage drop that occur with the output load. VOH HOST CLK 50% VI 50% SEL1, SEL0 VSS VM GND tPERIOD SW00962 tPLZ Figure 1. HOST CLOCK tPZL VDD OUTPUT LOW-to-OFF OFF-to-LOW COMPONENT MEASUREMENT POINTS VM VX VOL VOH = 2.4 V VOL = 0.4 V VDDL tPHZ VIH = 2.0 V 1.5 V VIL = 0.7 V VY OUTPUT HIGH-to-OFF OFF-to-HIGH SYSTEM MEASUREMENT POINTS VSS tPZH VOH VSS VM outputs enabled SW00668 outputs disabled outputs enabled Figure 2. 3.3 V clock waveforms SW00662 Figure 3. State enable and disable times VDD S1 2 VDD Open VSS 500 Ω VI VO PULSE GENERATOR DUT RT CL TEST S1 tPLH/tPHL Open tPLZ/tPZL 2 VDD tPHZ/tPZH VSS 500 Ω VDD = VDD3 SW00963 Figure 4. Load circuitry for switching times 2001 Oct 11 11 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 PWRDWN HOST CLK (INTERNAL) PCICLK (INTERNAL) PWRDWN HOST CLK (EXTERNAL) PCICLK (EXTERNAL) Á Á Á Á OSC & VCO USB (48 MHz) SW00669 Figure 5. Power management VDD CL RS RP = 50 Ω HOST CRYSTAL 14.318 MHz RS = 33.2 Ω DUT HOST_BAR RS CL RP = 50 Ω SW00671 Figure 6. HOST CLOCK measurements tPERIOD DUTY CYCLE tHIGH 3.3V CLOCKING INTERFACE 2.4 V 1.5 V 0.4 V tLOW tRISE tFALL SW00943 Figure 7. 3.3 V clock waveforms 2001 Oct 11 12 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm 2001 Oct 11 13 PCK2021 SOT362-1 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm 2001 Oct 11 14 PCK2021 SOT370-1 Philips Semiconductors Product data CK00 (100/133 MHz) spread spectrum differential system clock generator PCK2021 Data sheet status Data sheet status [1] Product status [2] Definitions Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2001 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 10-01 For sales offices addresses send e-mail to: [email protected]. Document order number: 2001 Oct 11 15 9397 750 08953