CY8C20236A, CY8C20566A ® Automotive CapSense Applications CapSense Applications Features ■ Automotive Electronics Council (AEC) Q100 qualified ■ Versatile analog mux ❐ Common internal analog bus ❐ Simultaneous connection of I/O ❐ High power supply rejection ratio (PSRR) comparator ❐ Low-dropout voltage regulator for all analog resources ■ Additional system resources 2 ❐ I C Slave: • Selectable to 50 kHz, 100 kHz, or 400 kHz • No clock stretching (under most conditions) • Implementation during sleep modes with less than 100 µA • Hardware address validation ❐ SPI master and slave: Configurable 46.9 kHz to 12 MHz ❐ Three 16-bit timers ❐ Watchdog and sleep timers ❐ Internal voltage reference ❐ Integrated supervisory circuit ❐ 8 to 10-bit incremental analog-to-digital converter (ADC) ❐ Two general-purpose high speed, low power analog comparators ■ Complete development tools ❐ Free development tool (PSoC Designer™) ❐ Full-featured, in-circuit emulator (ICE) and programmer ❐ Full-speed emulation ❐ Complex breakpoint structure ❐ 128 KB trace memory ■ Package options ❐ CY8C20x36A:16-Pin 3 × 3 × 0.6 mm QFN ❐ CY8C20x66A: 48-Pin SSOP ■ Operating Range: 1.71 V to 5.5 V Low power CapSense® block ❐ Configurable capacitive sensing elements ❐ Supports SmartSense ❐ Supports a combination of CapSense buttons, sliders, touchpads, touchscreens, and proximity sensors ■ Powerful Harvard-architecture processor ❐ M8C CPU speed can be up to 24 MHz or sourced by an external crystal, resonator, or clock signal ❐ Low power at high speed ❐ Interrupt controller ❐ Temperature range: –40 °C to +85 °C ■ Flexible on-chip memory ❐ Two program/data storage size options: • CY8C20x36A: 8 KB flash/1 KB SRAM • CY8C20x66A: 32 KB flash/2 KB SRAM ❐ 1,000 flash erase/write cycles ❐ Partial flash updates ❐ Flexible protection modes ❐ In-system serial programming (ISSP) ■ ■ Precision, programmable clocking ❐ Internal main oscillator (IMO): 6/12/24 MHz ± 5% ❐ Internal low speed oscillator (ILO) at 32 kHz for watchdog and sleep timers ❐ Precision 32 kHz oscillator for optional external crystal ■ Programmable pin configurations ❐ Up to 36 general-purpose I/Os (GPIOs) (depending on package) ❐ Dual mode GPIO: All GPIOs support digital I/O and analog inputs ❐ 25-mA sink current on each GPIO • 120 mA total sink current on all GPIOs ❐ Pull-up, high Z, open-drain modes on all GPIOs ❐ CMOS drive mode – 5 mA source current on ports 0 and 1 and 1 mA on ports 2, 3, and 4 • 20 mA total source current on all GPIOs ❐ Selectable, regulated digital I/O on port 1 ❐ Configurable input threshold on port 1 ❐ Hot-swap capability on all Port 1 GPIO Cypress Semiconductor Corporation Document Number: 001-63115 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 19, 2011 CY8C20236A, CY8C20566A Logic Block Diagram Port 4 Port 3 Port 2 Port 1 Port 0 1.8/2.5/3V LDO PWRSYS  (Regulator) PSoC CORE SYSTEM BUS Global Analog Interconnect 1K/2K SRAM Supervisory ROM (SROM) Interrupt Controller 8K/32K Flash Nonvolatile Memory Sleep and Watchdog CPU Core (M8C) 6/12/24 MHz Internal Main Oscillator (IMO) Internal Low Speed Oscillator (ILO) Multiple Clock Sources CAPSENSE SYSTEM Analog Reference CapSense Module Two Comparators Analog Mux SYSTEM BUS I2C Slave Internal Voltage References System Resets POR and LVD SPI Master/ Slave Three 16-Bit Programmable Timers Digital Clocks SYSTEM RESOURCES Note 1. Internal voltage regulator for internal circuitry Document Number: 001-63115 Rev. *B Page 2 of 29 CY8C20236A, CY8C20566A Contents PSoC® Functional Overview ............................................ 4 PSoC Core .................................................................. 4 CapSense System ....................................................... 4 Additional System Resources ..................................... 5 Getting Started .................................................................. 5 Application Notes ........................................................ 5 Development Kits ........................................................ 5 Training ....................................................................... 5 CYPros Consultants .................................................... 5 Solutions Library .......................................................... 5 Technical Support ....................................................... 5 Designing with PSoC Designer ....................................... 6 Select Components ..................................................... 6 Configure Components ............................................... 6 Organize and Connect ................................................ 6 Generate, Verify, and Debug ....................................... 6 Pinouts .............................................................................. 7 16-Pin QFN (No E-Pad) ............................................ 7 48-Pin SSOP .............................................................. 8 Electrical Specifications .................................................. 9 Absolute Maximum Ratings ......................................... 9 Operating Temperature ............................................... 9 DC Chip-Level Specifications .................................... 10 DC GPIO Specifications ............................................ 11 DC Analog Mux Bus Specifications ........................... 13 DC Low Power Comparator Specifications ............... 13 Comparator User Module Electrical Specifications ... 14 ADC Electrical Specifications ................................... 14 DC POR and LVD Specifications .............................. 15 Document Number: 001-63115 Rev. *B DC Programming Specifications ............................... 15 AC Chip-Level Specifications .................................... 16 AC General Purpose I/O Specifications .................... 17 AC Comparator Specifications .................................. 17 AC External Clock Specifications .............................. 17 AC Programming Specifications ................................ 18 AC I2C Specifications ................................................ 19 Packaging Information ................................................... 22 Thermal Impedances ................................................ 23 Solder Reflow Specifications ..................................... 23 Development Tool Selection ......................................... 24 Software .................................................................... 24 Development Kits ...................................................... 24 Evaluation Tools ............................................................. 25 Device Programmers ................................................. 25 Accessories (Emulation and Programming) .............. 25 Ordering Information ...................................................... 26 Ordering Code Definitions ............................................ 26 Reference Information ................................................... 27 Acronyms .................................................................. 27 Reference Documents ............................................... 27 Document Conventions ............................................. 27 Glossary .................................................................... 28 Document History Page ................................................. 29 Sales, Solutions, and Legal Information ...................... 29 Worldwide Sales and Design Support ....................... 29 Products .................................................................... 29 PSoC Solutions ......................................................... 29 Page 3 of 29 CY8C20236A, CY8C20566A PSoC® Functional Overview Figure 1. CapSense System Block Diagram The PSoC family consists of on-chip controller devices, which are designed to replace multiple traditional microcontroller unit (MCU)-based components with one, low cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, and programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. CS1 IDAC The Core ■ CapSense Analog System ■ System Resources (including a full-speed USB port). Analog Global Bus CSN Vr The architecture for this device family, as shown in the Logic Block Diagram on page 2, consists of three main areas: ■ CS2 Reference Buffer Cinternal Cexternal (P0 or P0) Comparator Mux A common, versatile bus allows connection between I/O and the analog system. Mux Each CY8C20x36A/66A PSoC device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. Depending on the PSoC package, up to 36 GPIO are also included. The GPIO provides access to the MCU and analog mux. Refs Cap Sense Counters CSCLK PSoC Core The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO and ILO. The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit Harvard-architecture microprocessor. CapSense System The analog system contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. The analog system is composed of the CapSense PSoC block and an internal 1 V or 1.2 V analog reference, which together support capacitive sensing of up to 33 inputs. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins are completed quickly and easily across multiple ports. SmartSense™ SmartSense is an innovative solution from Cypress that removes manual tuning of CapSense applications. This solution is easy to use and provides a robust noise immunity. It is the only autotuning solution that establishes, monitors, and maintains all required tuning parameters. SmartSense allows engineers to go from prototyping to mass production without re-tuning for manufacturing variations in PCB and/or overlay material properties. IMO CapSense Clock Select Oscillator Analog Multiplexer System The Analog Mux Bus can connect to every GPIO pin. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with the CapSense block comparator. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include: ■ Complex capacitive sensing interfaces, such as sliders and touchpads. ■ Chip-wide mux that allows analog input from any I/O pin. ■ Crosspoint connection between any I/O pin combinations. Note 2. 36 GPIOs = 33 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor. Document Number: 001-63115 Rev. *B Page 4 of 29 CY8C20236A, CY8C20566A Additional System Resources System resources provide additional capability, such as I2C slave, SPI master, or SPI slave interfaces, three 16-bit programmable timers, and various system resets supported by the M8C. These system resources provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. The merits of each system resource are listed here: ■ The I2C slave/SPI master-slave module provides 50/100/400 kHz communication over two wires. SPI communication over three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock). ■ The I2C hardware address recognition feature reduces the already low power consumption by eliminating the need for CPU intervention until a packet addressed to the target device is received. ■ ■ The I2C enhanced slave interface appears as a 32-byte RAM buffer to the external I2C master. Using a simple predefined protocol, the master controls the read and write pointers into the RAM. When this method is enabled, the slave does not stall the bus when receiving data bytes in active mode. For usage details, refer to the application note I2C Enhanced Slave Operation - AN56007. Low-voltage detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced poweron-reset (POR) circuit eliminates the need for a system supervisor. ■ An internal reference provides an absolute reference for capacitive sensing. ■ A register-controlled bypass mode allows the user to disable the LDO regulator. Getting Started The quickest way to understand PSoC silicon is to read this datasheet and then use the PSoC Designer Integrated Development Environment (IDE). This datasheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming details, see the Technical Reference Manual for the CY8C20x36A/66A PSoC devices. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web at www.cypress.com/psoc. Application Notes Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located at www.cypress.com/psoc. Select Application Notes under the Documentation tab. Development Kits PSoC Development Kits are available online from Cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include Arrow, Avnet, DigiKey, Farnell, Future Electronics, and Newark. Refer to Development Kits on page 24. Training Free PSoC and CapSense technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs. CYPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros. Solutions Library Visit our growing library of solution focused designs at www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, create a technical support case or call technical support at 1-800-541-4736. Document Number: 001-63115 Rev. *B Page 5 of 29 CY8C20236A, CY8C20566A Designing with PSoC Designer Organize and Connect The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. You build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. You perform the selection, configuration, and routing so that you have complete control over all on-chip resources. The PSoC development process can be summarized in the following four steps: 1. Select User Modules 2. Configure User Modules 3. Organize and Connect 4. Generate, Verify, and Debug Select Components PSoC Designer provides a library of pre-built, pre-tested hardware peripheral components called "user modules." User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure Components Each of the User Modules you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a PWM User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the User Module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. Document Number: 001-63115 Rev. *B Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, you perform the "Generate Configuration Files" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides application programming interfaces (APIs) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's Debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Page 6 of 29 CY8C20236A, CY8C20566A Pinouts The CY8C20x36A/66A PSoC device is available in a variety of packages, which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, VSS, VDD, and XRES are not capable of Digital I/O. 16-Pin QFN (No E-Pad) Table 1. Pin Definitions – CY8C20236A PSoC Device Analog I/O I P2 ECO output (XOut) 2 I/O I P2 ECO input (XIn) 3 I/OHR I P1 I2C SCL, SPI SS 4 I/OHR I P1 I2C SDA, SPI MISO 5 I/OHR I P1 SPI SCLK 6 I/OHR I P1 ISSP CLK, I2C SCL, SPI MOSI 7 Power VSS I/OHR I P1 ISSP DATA, I2C SDA, SPI CLK 9 I/OHR I P1 10 I/OHR I P1 Optional external clock input (EXTCLK) 12 13 Input I/OH P0, AI P0, AI P0, AI VDD 16 15 14 13 XOut, AI, P2 Xin, AI, P2 I2C SCL, SPI SS, AI, P1 I2C SDA, SPI MISO, AI, P1 Ground connection 8 11 Figure 2. CY8C20236A PSoC Device Description XRES Active high external reset with internal pull-down I Power P0 VDD 1 2 3 4 QFN 12 11 10 9 P0, AI XRES P1, AI, EXTCLK P1, AI 5 6 7 8 Digital 1 Name SPI SCLK, AI, P1 I2C SCL, SPI MOSI, AI, P1 VSS I2C SDA, SPI SCLK, AI, P1 Type Pin No. Supply voltage 14 I/OH I P0 15 I/OH I P0 Integrating input 16 I/OH I P0 Integrating input LEGEND A = Analog, I = Input, O = Output, H = 5 mA High Output Drive, R = Regulated Output. Notes 3. On power-up , the SDA(P1) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1)line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1 and P1 may disturb the I2C bus. Use alternate pins if you encounter issues. 4. Alternate SPI clock. Document Number: 001-63115 Rev. *B Page 7 of 29 CY8C20236A, CY8C20566A 48-Pin SSOP Table 2. Pin Definitions – CY8C20566A PSoC Device Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Type Digi- Anatal log I/OH I I/OH I I/OH I I/OH I I/O I I/O I I/O I I/O I I/O I/O I/O I/O I/O I/O I I I I I I I/OHR I/OHR I/OHR I/OHR Power I/OHR I/OHR I/OHR I I I I I/OHR I I I I Figure 3. CY8C20566A PSoC Device Name P0 P0 P0 P0 P2 P2 P2 P2 NC NC P4 P4 NC P3 P3 P3 P3 NC NC P1 P1 P1 P1 VSS P1 P1 P1 P1 NC NC NC NC NC Description AI, P0 AI, P0 AI, P0 Integrating input Integrating input AI, P0 AI, P2 XOut, AI, P2 ECO output (XOut) ECO input (XIn) XIn, AI, P2 AI, P2 No connection No connection NC NC AI, P4 AI, P4 No connection NC AI, P3 AI, P3 No connection No connection I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK ISSP CLK, I2C SCL, SPI MOSI Ground connection ISSP DATA, I2C SDA, SPI CLK AI, P3 AI, P3 NC NC I2C SCL, SPI SS, AI, P1 I2C SDA, SPI MISO, AI, P1 SPI SCLK, AI, P1 I2C SCL, SPI MOSI, AI, P1 VSS Optional external clock input (EXT CLK) No connection No connection No connection No connection No connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SSOP Type Name Dig- Anital alog 34 NC No connection 41 I/O I P2 35 Input XRES Active high external reset with internal pull- 42 I/O I P2 down 43 I/O I P2 36 I/O I P3 44 I/OH I P0 37 I/O I P3 45 I/OH I P0 38 I/O I P3 46 I/OH I P0 39 I/O I P3 47 I/OH I P0 40 I/O I P2 48 Power VDD Supply voltage LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option. Pin No. 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD P0, AI P0, AI P0, AI P0, AI P2, AI P2, AI P2, AI P2, AI P3, AI P3, AI P3, AI P3, AI XRES NC NC NC NC NC NC P1, AI P1, AI, EXTCLK P1, AI P1, AI, SPI SCLK, I2C SDA Description Notes 5. On power-up , the SDA(P1) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1)line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1 and P1 may disturb the I2C bus. Use alternate pins if you encounter issues. 6. Alternate SPI clock. Document Number: 001-63115 Rev. *B Page 8 of 29 CY8C20236A, CY8C20566A Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C20x36A/66A PSoC devices. For the latest electrical specifications, confirm that you have the most recent datasheet by visiting the web at http://www.cypress.com/psoc. Figure 4. Voltage versus CPU Frequency 5.5V Vdd Voltage li d ng Va rati n e io Op Reg 1.71V 750 kHz 3 MHz CPU 24 MHz Frequency Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 3. Absolute Maximum Ratings Symbol Description Conditions Min Typ Max Units TSTG Storage temperature Higher storage temperatures reduce data retention time. Recommended Storage Temperature is +25 °C ± 25 °C. Extended duration storage temperatures above 85 °C degrades reliability. –55 +25 +125 °C VDD Supply voltage relative to VSS – –0.5 – +6.0 V VIO DC input voltage – VSS – 0.5 – VDD + 0.5 V VIOZ DC voltage applied to tristate – VSS – 0.5 – VDD + 0.5 V IMIO Maximum current into any port pin – –25 – +50 mA ESD Electro static discharge voltage Human body model ESD 2000 – – V LU Latch-up current In accordance with JESD78 standard – – 200 mA Min Typ Max Units Operating Temperature Table 4. Operating Temperature Symbol Description Conditions TA Ambient temperature – –40 – +85 °C TJ Operational die temperature The temperature rise from ambient to junction is package specific. Refer the table Thermal Impedances per Package on page 23. The user must limit the power consumption to comply with this requirement. –40 – +100 °C Document Number: 001-63115 Rev. *B Page 9 of 29 CY8C20236A, CY8C20566A DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 5. DC Chip-Level Specifications Symbol VDD [7, 8, 9, 10] Description Supply voltage Conditions Refer the table DC POR and LVD Specifications on page 15 Min Typ Max Units 1.71 – 5.50 V IDD24 Supply current, IMO = 24 MHz Conditions are VDD ≤ 3.0 V, TA = 25 °C, CPU = 24 MHz. CapSense running at 12 MHz, no I/O sourcing current – 3.32 4.00 mA IDD12 Supply current, IMO = 12 MHz Conditions are VDD ≤ 3.0 V, TA = 25 °C, CPU = 12 MHz. CapSense running at 12 MHz, no I/O sourcing current – 1.86 2.60 mA IDD6 Supply current, IMO = 6 MHz Conditions are VDD ≤ 3.0 V, TA = 25 °C, CPU = 6 MHz. CapSense running at 6 MHz, no I/O sourcing current – 1.13 1.80 mA ISB0 Deep sleep current VDD ≤ 3.0 V, TA = 25 °C, I/O regulator turned off – 0.10 0.50 μA ISB1 Standby current with POR, LVD VDD ≤ 3.0 V, TA = 25 °C, I/O regulator turned off and sleep timer – 1.07 1.50 μA Notes 7. When VDD remains in the range from 1.71 V to 1.9 V for more than 50 µsec, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be slower than 1 V/500 µsec to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter. 8. If powering down in standby sleep mode, to properly detect and recover from a VDD brown out condition any of the following actions must be taken: a. Bring the device out of sleep before powering down. b. Assure that VDD falls below 100 mV before powering back up. c. Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep. d. Increase the buzz rate to assure that the falling edge of VDD is captured. The rate is configured through the PSSDC bits in the SLP_CFG register. For the referenced registers, refer to the CY8C20x36 Technical Reference Manual. In deep sleep mode, additional low power voltage monitoring circuitry allows VDD brown out conditions to be detected for edge rates slower than 1V/ms. 9. For USB mode, the VDD supply for bus-powered application should be limited to 4.35V-5.35V. For self-powered application, VDD should be 3.15 V-3.45 V. 10. For proper CapSense block functionality, if the drop in VDD exceeds 5% of the base VDD , the rate at which VDD drops should not exceed 200 mV/s. Base VDD can be between 1.8 V and 5.5 V Document Number: 001-63115 Rev. *B Page 10 of 29 CY8C20236A, CY8C20566A DC GPIO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and –40 °C ≤ TA ≤ 85 °C, 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, or 1.71 V to 2.4 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5V and 3.3 V at 25 C and are for design guidance only. Table 6. 3.0-V to 5.5-V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units RPU Pull-up resistor – 4 5.60 8 kΩ VOH1 High output voltage Port 2 or 3 pins IOH < 10 μA, maximum of 10 mA source current in all I/Os VDD – 0.20 – – V VOH2 High output voltage Port 2 or 3 Pins IOH = 1 mA, maximum of 20 mA source current in all I/Os VDD – 0.90 – – V VOH3 High output voltage Port 0 or 1 pins with LDO regulator Disabled for port 1 IOH < 10 μA, maximum of 10 mA source current in all I/Os VDD – 0.20 – – V VOH4 High output voltage Port 0 or 1 pins with LDO regulator Disabled for port 1 IOH = 5 mA, maximum of 20 mA source current in all I/Os VDD – 0.90 – – V VOH5 High output voltage Port 1 Pins with LDO Regulator Enabled for 3 V out IOH < 10 μA, VDD > 3.1 V, maximum of 4 I/Os all sourcing 5 mA 2.85 3.00 3.30 V VOH6 High output voltage IOH = 5 mA, VDD > 3.1V, maximum of Port 1 pins with LDO regulator enabled 20 mA source current in all I/Os for 3 V out 2.20 – – V VOH7 High output voltage IOH < 10 μA, VDD > 2.7 V, maximum of Port 1 pins with LDO enabled for 2.5 V 20 mA source current in all I/Os out 2.35 2.50 2.75 V VOH8 IOH = 2 mA, VDD > 2.7 V, maximum of High output voltage Port 1 pins with LDO enabled for 2.5 V 20 mA source current in all I/Os out 1.90 – – V VOH9 High output voltage IOH < 10 μA, VDD > 2.7 V, maximum of Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os out 1.60 1.80 2.10 V VOH10 High output voltage IOH = 1 mA, VDD > 2.7 V, maximum of Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os out 1.20 – – V VOL Low output voltage IOL = 25 mA, VDD > 3.3 V, maximum of 60 mA sink current on even port pins (for example, P0 and P1) and 60 mA sink current on odd port pins (for example, P0 and P1) – – 0.75 V VIL Input low voltage – – – 0.80 V VIH Input high voltage – 2.00 – – V VH Input hysteresis voltage – – 80 – mV IIL Input leakage (Absolute Value) – – 0.001 1 μA CPIN Pin capacitance Package and pin dependent Temp = 25 °C 0.50 1.70 7 pF Document Number: 001-63115 Rev. *B Page 11 of 29 CY8C20236A, CY8C20566A Table 7. 2.4-V to 3.0-V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units 4 5.60 8 kΩ IOH < 10 μA, maximum of 10 mA source current in all I/Os VDD - 0.20 – – V High output voltage Port 2 or 3 Pins IOH = 0.2 mA, maximum of 10 mA source current in all I/Os VDD - 0.40 – – V VOH3 High output voltage Port 0 or 1 pins with LDO regulator Disabled for port 1 IOH < 10 μA, maximum of 10 mA source current in all I/Os VDD - 0.20 – – V VOH4 High output voltage Port 0 or 1 pins with LDO regulator Disabled for Port 1 IOH = 2 mA, maximum of 10 mA source VDD - 0.50 current in all I/Os – – V VOH5A High output voltage IOH < 10 μA, VDD > 2.4 V, maximum of Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os out 1.50 1.80 2.10 V VOH6A High output voltage IOH = 1 mA, VDD > 2.4 V, maximum of Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os out 1.20 – – V VOL Low output voltage IOL = 10 mA, maximum of 30 mA sink current on even port pins (for example, P0 and P1) and 30 mA sink current on odd port pins (for example, P0 and P1) – – 0.75 V VIL Input low voltage – – – 0.72 V VIH Input high voltage – 1.40 – VH Input hysteresis voltage – – 80 – mV IIL Input leakage (absolute value) – CPIN Capacitive load on pins Package and pin dependent Temp = 25 °C RPU Pull-up resistor – VOH1 High output voltage Port 2 or 3 pins VOH2 V – 1 1000 nA 0.50 1.70 7 pF Min Typ Max Units Table 8. 1.71-V to 2.4-V DC GPIO Specifications Symbol Description Conditions RPU Pull-up resistor – 4 5.60 8 kΩ VOH1 High output voltage Port 2 or 3 pins IOH = 10 μA, maximum of 10 mA source current in all I/Os VDD – 0.20 – – V VOH2 High output voltage Port 2 or 3 pins IOH = 0.5 mA, maximum of 10 mA source current in all I/Os VDD – 0.50 – – V VOH3 High output voltage Port 0 or 1 pins with LDO regulator Disabled for Port 1 IOH = 100 μA, maximum of 10 mA source current in all I/Os VDD – 0.20 – – V VOH4 High output voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 IOH = 2 mA, maximum of 10 mA source VDD – 0.50 current in all I/Os – – V VOL Low output voltage IOL = 5 mA, maximum of 20 mA sink current on even port pins (for example, P0 and P1) and 30 mA sink current on odd port pins (for example, P0 and P1) – – 0.40 V VIL Input low voltage – – – 0.30 × VDD V VIH Input high voltage – 0.65 × VDD – – V Document Number: 001-63115 Rev. *B Page 12 of 29 CY8C20236A, CY8C20566A Table 8. 1.71-V to 2.4-V DC GPIO Specifications (continued) Symbol Description Conditions Min Typ Max Units VH Input hysteresis voltage – – 80 – mV IIL Input leakage (absolute value) – – 1 1000 nA CPIN Capacitive load on pins Package and pin dependent temp = 25 oC 0.50 1.70 7 pF DC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 9. DC Analog Mux Bus Specifications Symbol Description Conditions Min Typ Max Units RSW Switch resistance to common analog bus – – – 800 Ω RGND Resistance of initialization switch to VSS – – – 800 Ω The maximum pin voltage for measuring RSW and RGND is 1.8 V DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 10. DC Comparator Specifications Symbol Description Conditions Min Typ Max Units 0.0 – 1.8 V VLPC Low power comparator (LPC) common Maximum voltage limited to VDD mode ILPC LPC supply current – – 10 40 μA VOSLPC LPC voltage offset – – 2.5 30 mV Document Number: 001-63115 Rev. *B Page 13 of 29 CY8C20236A, CY8C20566A Comparator User Module Electrical Specifications The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the entire device voltage and temperature operating range: –40°C <= TA <= 85°C, 1.71V <= VDD <= 5.5V. Table 11. Comparator User Module Electrical Specifications Symbol Min Typ Max Units 50 mV overdrive – 70 100 ns Offset Valid from 0.2 V to VDD – 0.2 V – 2.5 30 mV Current Average DC current, 50 mV overdrive – 20 80 µA Supply voltage > 2 V Power supply rejection ratio – 80 – dB Supply voltage < 2 V Power supply rejection ratio – 40 – 0 TCOMP PSRR Description Comparator response time Input range Conditions – dB 1.5 V ADC Electrical Specifications Table 12.ADC User Module Electrical Specifications Symbol Description Conditions Min Typ Max Units 0 – VREFADC V Input VIN Input voltage range CIIN Input capacitance – RIN Input resistance Equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution ADC reference voltage FCLK – – – 5 pF 1/(500fF × data clock) 1/(400fF × data clock) 1/(300fF × data clock) Ω – 1.14 – 1.26 V Data clock Source is chip’s internal main oscillator. See AC Chip-Level Specifications for accuracy 2.25 – 6 MHz S8 8-bit sample rate Data clock set to 6 MHz. sample rate = 0.001/ (2^Resolution/Data Clock) – 23.43 – ksps S10 10-bit sample rate Data clock set to 6 MHz. sample rate = 0.001/ (2^resolution/data clock) – 5.85 – ksps RES Resolution Can be set to 8-, 9-, or 10-bit 8 – 10 bits DNL Differential nonlinearity – –1 – +2 LSB INL Integral nonlinearity – –2 – +2 LSB EOFFSET Offset error 8-bit resolution 0 3.20 19.20 LSB 10-bit resolution 0 12.80 76.80 LSB Gain error For any resolution –5 – +5 %FSR IADC Operating current – – 2.10 2.60 mA PSRR Power supply rejection ratio PSRR (VDD > 3.0 V) – 24 – dB PSRR (VDD < 3.0 V) – 30 – dB Reference VREFADC Conversion Rate DC Accuracy EGAIN Power Document Number: 001-63115 Rev. *B Page 14 of 29 CY8C20236A, CY8C20566A DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 13. DC POR and LVD Specifications Symbol VPOR0 Description Conditions Min Typ Max Units 1.61 – 1.66 1.71 V 2.36 2.41 – 2.60 2.66 – 2.82 2.95 VPOR2 1.66 V selected in PSoC Designer VDD must be greater than or equal to 1.71 V 2.36 V selected in PSoC Designer during startup, reset from the XRES pin, or reset from watchdog. 2.60 V selected in PSoC Designer VPOR3 2.82 V selected in PSoC Designer VLVD0 2.45 V selected in PSoC Designer – 2.40 2.45 2.51 VLVD1 2.71 V selected in PSoC Designer 2.64 2.71 2.78 VLVD2 2.92 V selected in PSoC Designer 2.85 2.92 2.99 VLVD3 3.02 V selected in PSoC Designer 2.95 3.02 3.09 VLVD4 3.13 V selected in PSoC Designer 3.06 3.13 3.20 VLVD5 1.90 V selected in PSoC Designer 1.84 1.90 2.32 VLVD6 1.80 V selected in PSoC Designer 1.75 1.80 1.84 VLVD7 4.73 V selected in PSoC Designer 4.62 4.73 4.83 VPOR1 V DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 14. DC Programming Specifications Symbol Description VDDIWRITE Supply voltage for flash write operations IDDP Supply current during programming or verify VILP Input low voltage during programming or verify VIHP Input high voltage during programming or verify IILP Input current when Applying VILP to P1 or P1 during programming or verify IIHP Input current when applying VIHP to P1 or P1 during programming or verify VOLP Output low voltage during programming or verify VOHP Output high voltage during programming or verify FlashENPB Flash write endurance FlashDR Flash data retention – Conditions Min 1.71 Typ – Max 5.25 Units V – – 5 25 mA See the appropriate DC GPIO Specifications on page 11 See appropriate DC GPIO Specifications on page 11 table on pages 15 or 16 Driving internal pull-down resistor – – VIL V VIH – – V – – 0.2 mA – – 1.5 mA – – VSS + 0.75 V VOH – VDD V 50,000 20 – – – – – Years Driving internal pull-down resistor See appropriate DC GPIO Specifications on page 11 table on page 16. For VDD > 3V use VOH4 in Table 4 on page 9. Erase/write cycles per block Following maximum Flash write cycles; ambient temperature of 55 °C Notes 11. Always greater than 50 mV above VPPOR1 voltage for falling supply. 12. Always greater than 50 mV above VPPOR2 voltage for falling supply. 13. Always greater than 50 mV above VPPOR3 voltage for falling supply. 14. Always greater than 50 mV above VPPOR0 voltage for falling supply. Document Number: 001-63115 Rev. *B Page 15 of 29 CY8C20236A, CY8C20566A AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 15. AC Chip-Level Specifications Min Typ Max Units FIMO24 Symbol Internal main oscillator frequency at 24 MHz Setting Description – Conditions 22.8 24 25.2 MHz FIMO12 Internal main oscillator frequency at 12 MHz setting – 11.4 12 12.6 MHz FIMO6 Internal main oscillator frequency at 6 MHz setting – 5.7 6.0 6.3 MHz FCPU CPU frequency – 0.75 – 25.20 MHz F32K1 Internal low speed oscillator frequency – 19 32 50 kHz F32K_U Internal low speed oscillator (ILO) untrimmed – frequency) 13 32 82 kHz DCIMO Duty cycle of IMO – 40 50 60 % DCILO Internal low speed oscillator duty cycle – 40 50 60 % VDD slew rate during power-up – – 250 V/ms After supply voltage is valid 1 – – ms Applies after part has booted 10 – – μs SRPOWER_UP Power supply slew rate tXRST tXRST2 External reset pulse width at power-up External reset pulse width after power-up Note 15. The minimum required XRES pulse length is longer when programming the device (see Table 19 on page 18). Document Number: 001-63115 Rev. *B Page 16 of 29 CY8C20236A, CY8C20566A AC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 16. AC GPIO Specifications Symbol FGPIO Description GPIO operating frequency Conditions Normal strong mode Port 0, 1 Min 0 0 tRISE23 tRISE23L tRISE01 tRISE01L tFALL tFALLL Rise time, strong mode, Cload = 50 pF Ports 2 or 3 Rise time, strong mode low supply, Cload = 50 pF, Ports 2 or 3 Rise time, strong mode, Cload = 50 pF Ports 0 or 1 Rise time, strong mode low supply, Cload = 50 pF, Ports 0 or 1 Fall time, strong mode, Cload = 50 pF all ports Fall time, strong mode low supply, Cload = 50 pF, all ports Typ Max Units – 6 MHz for MHz 1.71 V <VDD < 2.40 V – 12 MHz for MHz 2.40 V < VDD< 5.50 V – 80 ns VDD = 3.0 to 3.6 V, 10% to 90% 15 VDD = 1.71 to 3.0 V, 10% to 90% 15 – 80 ns VDD = 3.0 to 3.6 V, 10% to 90% LDO enabled or disabled VDD = 1.71 to 3.0 V, 10% to 90% LDO enabled or disabled VDD = 3.0 to 3.6 V, 10% to 90% 10 – 50 ns 10 – 80 ns 10 – 50 ns VDD = 1.71 to 3.0 V, 10% to 90% 10 – 70 ns Figure 5. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRise23 TRise01 TRise23L TRise01L TFall TFallL AC Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 17. AC Low Power Comparator Specifications Symbol tLPC Description Comparator response time, 50 mV overdrive Conditions 50 mV overdrive does not include offset voltage. Min Typ Max Units – – 100 ns AC External Clock Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 18. AC External Clock Specifications Symbol FOSCEXT Description Frequency (external oscillator frequency) Conditions – Min Typ Max Units 0.75 – 25.20 MHz High period – 20.60 – 5300 ns Low period – 20.60 – – ns Power-up IMO to switch – 150 – – μs Document Number: 001-63115 Rev. *B Page 17 of 29 CY8C20236A, CY8C20566A AC Programming Specifications Figure 6. AC Waveform SCLK (P1) T RSCLK T FSCLK SDATA (P1) TSSCLK T HSCLK TDSCLK The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 19. AC Programming Specifications Symbol tRSCLK tFSCLK tSSCLK tHSCLK FSCLK tERASEB tWRITE tDSCLK tDSCLK3 tDSCLK2 tXRST3 Description Rise time of SCLK Fall time of SCLK Data setup time to falling edge of SCLK Data hold time from falling edge of SCLK Frequency of SCLK Flash erase time (block) Flash block write time Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK External reset pulse width after power-up tXRES tVDDWAIT tVDDXRES tPOLL tACQ XRES pulse length VDD stable to wait-and-poll hold off VDD stable to XRES assertion delay SDATA high pulse time “Key window” time after a VDD ramp acquire event, based on 256 ILO clocks. “Key window” time after an XRES event, based on 8 ILO clocks tXRESINI Document Number: 001-63115 Rev. *B Conditions – – – – – – – 3.6 < VDD 3.0 ≤ VDD ≤ 3.6 1.71 ≤ VDD ≤ 3.0 Required to enter programming mode when coming out of sleep – – – – – – Min 1 1 40 40 0 – – – – – 300 Typ – – – – – – – – – – – Max 20 20 – – 8 18 25 60 85 130 – Units ns ns ns ns MHz ms ms ns ns ns μs 300 0.1 14.27 0.01 3.20 – – – – – – 1 – 200 19.60 μs ms ms ms ms 98 – 615 μs Page 18 of 29 CY8C20236A, CY8C20566A AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 20. AC Characteristics of the I2C SDA and SCL Pins Symbol fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF tSP Description SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH Period of the SCL clock Setup time for a repeated START condition Data hold time Data setup time Setup time for STOP condition Bus free time between a STOP and START condition Pulse width of spikes are suppressed by the input filter Standard Mode Min Max 0 100 4.0 – 4.7 4.0 4.7 0 250 4.0 4.7 – – – – 3.45 – – – – Fast Mode Min 0 0.6 Max 400 – 1.3 – 0.6 – 0.6 – 0 0.90 100 – 0.6 – 1.3 – 0 50 Units kHz µs µs µs µs µs ns µs µs ns Figure 7. Definition for Timing for Fast/Standard Mode on the I2C Bus Note 16. A Fast-Mode I2C-bus device can be used in a standard mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-63115 Rev. *B Page 19 of 29 CY8C20236A, CY8C20566A Table 21. SPI Master AC Specifications Min Typ Max Units FSCLK Symbol SCLK clock frequency Description VDD ≥ 2.4 V VDD < 2.4 V Conditions – – – – 6 3 MHz MHz DC SCLK duty cycle – – 50 – % tSETUP MISO to SCLK setup time VDD ≥ 2.4 V VDD < 2.4 V 60 100 – – – – ns ns tHOLD SCLK to MISO hold time – 40 – – ns tOUT_VAL SCLK to MOSI valid time – – – 40 ns tOUT_HIGH MOSI high time – 40 – – ns Figure 8. SPI Master Mode 0 and 2 SPI Master, modes 0 and 2 1/FSCLK THIGH TLOW SCLK (mode 0) SCLK (mode 2) TSETUP MISO (input) THOLD LSB MSB TOUT_SU TOUT_H MOSI (output) Figure 9. SPI Master Mode 1 and 3 SPI Master, modes 1 and 3 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TSETUP MISO (input) THOLD TOUT_SU MOSI (output) Document Number: 001-63115 Rev. *B LSB MSB TOUT_H MSB LSB Page 20 of 29 CY8C20236A, CY8C20566A Table 22. SPI Slave AC Specifications Symbol FSCLK Description SCLK clock frequency tLOW tHIGH tSETUP tHOLD tSS_MISO tSCLK_MISO tSS_HIGH tSS_CLK tCLK_SS SCLK low time SCLK high time MOSI to SCLK setup time SCLK to MOSI hold time SS high to MISO valid SCLK to MISO valid SS high time Time from SS low to first SCLK Time from last SCLK to SS high Conditions VDD ≥ 2.4 V VDD < 2.4 V – – – – – – – – – Min – – 42 42 30 50 – – 50 2/SCLK 2/SCLK Typ – – – – – – – – – – – Max 12 6 – – – – 153 125 – – – Units MHz MHz ns ns ns ns ns ns ns ns ns Figure 10. SPI Slave Mode 0 and 2 SPI Slave, modes 0 and 2 TSS_HIGH TCLK_SS TSS_CLK /SS 1/FSCLK THIGH TLOW SCLK (mode 0) SCLK (mode 2) TOUT_H TSS_MISO MISO (output) TSETUP MOSI (input) THOLD LSB MSB Figure 11. SPI Slave Mode 1 and 3 SPI Slave, modes 1 and 3 TSS_CLK TCLK_SS /SS 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TOUT_H TSCLK_MISO TSS_MISO MISO (output) MSB TSETUP MOSI (input) Document Number: 001-63115 Rev. *B LSB THOLD MSB LSB Page 21 of 29 CY8C20236A, CY8C20566A Packaging Information This section illustrates the packaging specifications for the CY8C20x36A/66A PSoC device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com. Figure 12. 16-pin QFN No E-pad 3x3x0.6 mm Package Outline (Sawn) 2.9 3.1 0.20 min 1 1 2 2.9 3.1 0.20 DIA TYP. 2 1.5 (NOM) 0.45 0.55 PIN #1 ID 0.152 REF. 0.30 0.18 0.05 MAX 0.50 0.60 MAX 1.5 SEATING PLANE TOP VIEW SIDE VIEW BOTTOM VIEW NOTES: PART NO. DESCRIPTION LG16A LEAD-FREE LD16A STANDARD 1. JEDEC # MO-220 2. Package Weight: 0.014g 3. DIMENSIONS IN MM, MIN MAX 001-09116 *E Figure 13. 48-Pin (300-Mil) SSOP 51-85061 *D Important Note For information on the preferred dimensions for mounting QFN packages, refer to Application Note, Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com. Document Number: 001-63115 Rev. *B Page 22 of 29 CY8C20236A, CY8C20566A Thermal Impedances Table 23. Thermal Impedances per Package Package Typical θJA  16-pin QFN 33 °C/W 48-pin SSOP 69 °C/W Solder Reflow Specifications Table 24 shows the solder reflow temperature limits that must not be exceeded. Table 24. Solder Reflow Specifications Package Maximum Peak Temperature (TC) Maximum Time above TC – 5 °C 16-pin QFN 260 °C 30 seconds 48-pin SSOP 260 °C 30 seconds Note 17. TJ = TA + Power × θJA. Document Number: 001-63115 Rev. *B Page 23 of 29 CY8C20236A, CY8C20566A Development Tool Selection Software PSoC Designer At the core of the PSoC development software suite is PSoC Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for years. PSoC Designer is available free of charge at http:// www.cypress.com. PSoC Designer comes with a free C compiler. PSoC Designer Software Subsystems You choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. You configure the user modules for your chosen application and connect them to each other and to the proper pins. Then you generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration allows for changing configurations at run time. Code Generation Tools PSoC Designer supports multiple third-party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers allow assembly code to be merged seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. In-Circuit Emulator capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24MHz) operation. Standard Cypress PSoC IDE tools are available for debugging the CY8C20x36A/66A family of parts. However, the additional trace length and a minimal ground plane in the Flex-Pod can create noise problems that make it difficult to debug the design. A custom bonded On-Chip Debug (OCD) device is available in a 48-pin QFN package. The OCD device is recommended for debugging designs that have high current and/or high analog accuracy requirements. The QFN package is compact and is connected to the ICE through a high density connector. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube in-circuit emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com/psocprogrammer. Development Kits All development kits are sold at the Cypress Online Store. CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. PSoC Designer supports the advance emulation features also. The kit includes: ■ PSoC Designer Software CD ■ ICE-Cube In-Circuit Emulator ■ ICE Flex-Pod for CY8C29x66A Family ■ Cat-5 Adapter ■ Mini-Eval Programming Board ■ 110 ~ 240 V Power Supply, Euro-Plug Adapter ■ iMAGEcraft C Compiler (Registration Required) ■ ISSP Cable ■ USB 2.0 Cable and Blue Cat-5 Cable ■ 2 CY8C29466A-24PXI 28-PDIP Chip Samples A low cost, high functionality In-Circuit Emulator (ICE) is available for development support. This hardware has the Document Number: 001-63115 Rev. *B Page 24 of 29 CY8C20236A, CY8C20566A Evaluation Tools All evaluation tools are sold at the Cypress Online Store. CY3280-20x66 Universal CapSense Controller CY3210-MiniProg1 The CY3280-20X66 CapSense Controller Kit is designed for easy prototyping and debug of CY8C20xx6A CapSense Family designs with pre-defined control circuitry and plug-in hardware. Programming hardware and an I2C-to-USB bridge are included for tuning and data acquisition. The CY3210-MiniProg1 kit enables the user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes: ■ MiniProg Programming Unit ■ MiniEval Socket Programming and Evaluation Board ■ 28-Pin CY8C29466A-24PXI PDIP PSoC Device Sample ■ 28-Pin CY8C27443A-24PXI PDIP PSoC Device Sample ■ PSoC Designer Software CD ■ Getting Started Guide ■ USB 2.0 Cable The kit includes: ■ CY3280-20x66 CapSense Controller Board ■ CY3240-I2USB Bridge ■ CY3210 MiniProg1 Programmer ■ USB 2.0 Retractable Cable ■ CY3280-20x66 Kit CD Device Programmers All device programmers are purchased from the Cypress Online Store. CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: CY3207ISSP In-System Serial Programmer (ISSP) ■ Evaluation Board with LCD Module The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production programming environment. Note that CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: ■ MiniProg Programming Unit ■ CY3207 Programmer Unit ■ 28-Pin CY8C29466A-24PXI PDIP PSoC Device Sample (2) ■ PSoC ISSP Software CD ■ PSoC Designer Software CD ■ 110 ~ 240 V Power Supply, Euro-Plug Adapter ■ Getting Started Guide ■ USB 2.0 Cable ■ USB 2.0 Cable Accessories (Emulation and Programming) Table 25. Emulation and Programming Accessories Part Number Pin Package Flex-Pod Kit Foot Kit Adapter CY8C20236A-24LKXA 16-pin QFN CY3250-20246QFN CY3250-16QFN-FK – CY8C20566A-24PVXA 48-pin SSOP CY3250-20566 CY3250-48SSOP-FK AS-48-48-01SS-6-GANG Notes 18. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 19. Foot kit includes surface mount feet that can be soldered to the target PCB. 20. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. Document Number: 001-63115 Rev. *B Page 25 of 29 CY8C20236A, CY8C20566A Ordering Information The following table lists the CY8C20x36A/66A PSoC devices' key package features and ordering codes.. Table 26. PSoC Device Key Features and Ordering Information Flash (Bytes) SRAM (Bytes) CapSense Blocks 16-Pin (3 × 3 × 0.6 mm) QFN CY8C20236A-24LKXA 8K 1K 1 13 13 Yes No Yes 16-Pin (3 × 3 × 0.6 mm) QFN CY8C20236A-24LKXAT (Tape and Reel) 8K 1K 1 13 13 Yes No Yes 48-Pin SSOP 32 K 2K 1 34 34 Yes No Yes 32 K 2K 1 34 34 Yes No Yes Package Ordering Code CY8C20566A-24PVXA 48-Pin SSOP (Tape and Reel) CY8C20566A-24PVXAT Digital I/O Analog XRES Pins Inputs Pin USB ADC Ordering Code Definitions A = Automotive Note 21. Dual-function Digital I/O Pins also connect to the common analog mux. Document Number: 001-63115 Rev. *B Page 26 of 29 CY8C20236A, CY8C20566A Reference Information Reference Documents Acronyms ■ Technical reference manual for CY8C20xx6 devices The following table lists the acronyms that are used in this document. ■ In-system Serial Programming (ISSP) protocol for 20xx6 (AN2026C) Table 27. Acronyms Used in this Document ■ Host Sourced Serial Programming for 20xx6 devices (AN59389) Acronym AC ADC API CMOS CPU DAC DC EOP FSR GPIO GUI I2C ICE IDAC ILO IMO I/O ISSP LCD LDO LSB LVD MCU MIPS MISO MOSI MSB OCD POR PPOR PSRR PWRSYS PSoC® SLIMO SRAM SNR QFN SCL SDA SDATA SPI SS SSOP TC USB USB D+ USB DWLCSP XTAL Description alternating current analog-to-digital converter application programming interface complementary metal oxide semiconductor central processing unit digital-to-analog converter direct current end of packet full scale range general purpose input/output graphical user interface inter-integrated circuit in-circuit emulator digital analog converter current internal low speed oscillator internal main oscillator input/output in-system serial programming liquid crystal display low dropout (regulator) least-significant bit low voltage detect micro-controller unit mega instructions per second master in slave out master out slave in most-significant bit on-chip debugger power on reset precision power on reset power supply rejection ratio power system Programmable System-on-Chip slow internal main oscillator static random access memory signal to noise ratio quad flat no-lead serial I2C clock serial I2C data serial ISSP data serial peripheral interface slave select shrink small outline package test controller universal serial bus USB Data + USB Datawafer level chip scale package crystal Document Number: 001-63115 Rev. *B Document Conventions Units of Measure Table 28 lists all the abbreviations used to measure the PSoC devices. Table 28. Units of Measure Symbol °C dB fF g Hz KB Kbit KHz Ksps kΩ MHz MΩ μA μF μH μs μW mA ms mV nA ns nV W pA pF pp ppm ps sps s V W Unit of Measure degree Celsius decibels femto farad gram hertz 1024 bytes 1024 bits kilohertz kilo samples per second kilohm megahertz megaohm microampere microfarad microhenry microsecond microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts watt Page 27 of 29 CY8C20236A, CY8C20566A Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal. Glossary Crosspoint connection Connection between any GPIO combination via analog multiplexer bus. Differential non-linearity Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly one LSB apart. Differential non-linearity is a measure of the worst case deviation from the ideal 1 LSB step. Hold time Hold time is the time following a clock event during which the data input to a latch or flipflop must remain stable in order to guarantee that the latched data is correct. I2C It is a serial multi-master bus used to connect low speed peripherals to MCU. Integral nonlinearity It is a term describing the maximum deviation between the ideal output of a DAC/ADC and the actual output level. Latch-up current Current at which the latch-up test is conducted according to JESD78 standard ( at 125 degree celsius) Power supply rejection ratio (PSRR) The PSRR is defined as the ratio of the change in supply voltage to the corresponding change in output voltage of the device. Scan The conversion of all sensor capacitances to digital values. Setup time Period required to prepare a device, machine, process, or system for it to be ready to function. Signal-to-noise ratio The ratio between a capacitive finger signal and system noise. SPI Serial peripheral interface is a synchronous serial data link standard. Document Number: 001-63115 Rev. *B Page 28 of 29 CY8C20236A, CY8C20566A Document History Page Document Title: CY8C20236A, CY8C20566A Automotive CapSense® Applications Document Number: 001-63115 Revision ECN Origin of Change Submission Date Description of Change ** 2989484 BTK 07/21/10 New Datasheet *A 3262255 BTK 05/19/11 Converted from Advance to Preliminary. Added preliminary information to datasheet. *B 3311559 BTK 07/13/11 Changed status from Preliminary to Final. Removed “Capacitance on Crystal Pins” section. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 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Document Number: 001-63115 Rev. *B Revised July 19, 2011 Page 29 of 29 2 PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.